Home

ANALOG DEVICES ADP8860 handbook

1. 7 Typical Performance Characteristics sse 8 Theory of Operation ssseeeeeee tenentes 12 Power SUA GE ise tite HERR THE repperi eet 13 Operating iernii edu red 14 Backlight Operating Levels sse 16 Backlight Maximum and Dim Settings 17 Automated Fade In and Fade Out sss 17 REVISION HISTORY 5 09 Revision 0 Initial Version Backlight Turn On Turn Off Dim see 17 Automatic Dim and Turn Off Timers sss 18 Fade Override synir nde is 19 Ambient Light Sensing sisene 19 Automatic Backlight Adjustment sss 20 Independent Sink Control see 20 Short Circuit Protection Mode sse 21 Overvoltage Protection ertet reti tette 21 Thermal Shutdown Overtemperature Protection 21 ese essersi este d 23 Applications Information eeeeeeneneeenttns 24 Layout Guidelines coL EU 24 Example Circuits ERE bees 25 Programming and Digital Control ss 26 Backlight Register Descriptions sse 30 Independent Sink Register Descriptions 37 Comparator Register Descriptions 45 Outline Dimensions eerte 49 Ordering Gilde reri ort reris 50 Rev 0 Page 2 of 52 SPECIFICATIONS VIN 3
2. PH2LEV_LOW Table 81 Bit Descriptions for the PH2LEVL Register Bit Name Bit No Description PH2LEV_LOW 7 0 13 bit conversion value for the second light sensor low byte Bit 7 to Bit 0 The value is updated every 80 ms when the light sensor is enabled This is a read only register Second Phototransistor Register High Byte PH2LEVH Register 0x24 Table 82 PH2LEVH Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved PH2LEV_HIGH Table 83 Bit Descriptions for the PH2LEVH Register Bit Name Bit No Description N A 7 5 Reserved PH2LEV HIGH 4 0 13 bit conversion value for the second light sensor high byte Bit 12 to Bit 8 The value is updated every 80 ms when the light sensor is enabled This is a read only register Rev 0 Page 48 of 52 ADP8860 0 645 OUTLINE DIMENSIONS 1 995 0 600 1 955 0 555 1 915 SEATING EL PLANE BALL A1 IDENTIFIER 2 395 25 1 60 i 0 287 REF 0 267 0 247 0 40 BOTTOM VIEW TOP VIEW 0 415 Li 0 05 MAX BALL SIDE UP BALL SIDE DOWN 0400 COPLANARITY 0 385 0 230 0 200 0 170 8 Figure 47 20 Ball Wafer Level Chip Scale Package WLCSP CB 20 6 Dimensions shown in millimeters PIN 1 INDICATOR PIN 1 2 65 INDICATOR expose asa BOTTOM VIEW 2 35 4 0 25 MIN 100 12 0 68 FOR PROPER CONNEC
3. Figure 2 Interface Timing Diagram Rev 0 Page 5 of 52 ADP8860 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating VIN VOUT 0 3V to 6 V D1 D2 D3 D4 D5 D6 and D7 0 3V to 6 V CMP IN 0 3V to 6 V nINT nRST SCL and SDA 0 3V to 6 V Output Short Circuit Duration Indefinite Operating Ambient Temperature Range 40 C to 85 Operating Junction Temperature Range 40 C to 125 C Storage Temperature Range 65 C to 150 C Soldering Conditions JEDEC J STD 020 ESD Electrostatic Discharge Human Body Model HBM 2 kV Charged Device Model CDM 2 kV THERMAL RESISTANCE junction to air is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages The junction to board and junction to case are determined according to JESD51 9 on a 4 layer printed circuit board PCB with natural convection cooling For the LFCSP package the exposed pad must be soldered to the GNDI and or GND2 terminal s on the board Table 3 Thermal Resistance Package Bsc Unit WLCSP 48 9 N A C W LFCSP_VQ 49 5 N A 5 3 C W The maximum operating junction temperature supersedes the maximum operating ambient temperature Tax See the Maximum Temperature Ranges section for more information Stresses above those listed under Absolute Maximum Ratings may cause permanent da
4. Diode 4 backlight sink enable 1 selects LED4 as independent sink 0 connects LED4 sink to backlight enable BL EN D3EN Diode 3 backlight sink enable 1 selects LED3 as independent sink 0 connects LED3 sink to backlight enable BL EN D2EN Diode 2 backlight sink enable 1 selects LED2 as independent sink 0 connects LED2 sink to backlight enable BL EN D1EN Diode 1 backlight sink enable 1 selects LED1 as independent sink 0 connects LED1 sink to backlight enable BL EN Backlight Off Timeout BLOFF Register 0x06 Table 20 BLOFF Bit Map Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved OFFT Table 21 Bit Descriptions for the BLOFF Register Bit Name Bit No Description N A 7 Reserved OFFT 6 0 Backlight off timeout After the off timeout OFFT period the backlight turns off If the dim timeout DIMT is enabled the off timeout starts after the dim timeout 0000 timeout disabled 0000001 1 sec 0000010 2 sec 0000011 3 sec 1111111 127 sec Backlight Dim Timeout BLDIM Register 0x07 Table 22 BLDIM Bit Map Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved DIMT Table 23 Bit Descriptions for the BLDIM Register Bit Name Bit No Description N A 7 Reserved DIMT 6 0 Backlight dim timeout After the dim
5. Table 9 MFDVID Manufacturer and Device ID Bit Map Bit 7 Bit6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Manufacture ID Device ID 0 0 0 0 0 1 1 1 Mode Control Register MDCR Register 0x01 Table 10 MDCR Mode Control Bit Map Bit7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 Reserved INT CFG nSTBY DIM EN Reserved SIS EN AUTOEN BL EN Table 11 Bit Descriptions for the MDCR Register Bit Name Bit No Description N A 7 Reserved INT_CFG 6 Interrupt configuration 1 processor interrupt deasserts for 50 us and reasserts with pending events 0 processor interrupt remains asserted if the host tries to clear the interrupt while there is a pending event nSTBY 5 1 device is in active mode 0 device is in standby mode only the interface is enabled DIM EN 4 DIM EN is set by the hardware after a DIM timeout The user may also force the backlight into DIM mode by asserting this bit DIM mode can only be entered if BL EN is also enabled 1 backlight is operating at the DIM current level BL EN must also be asserted 0 backlight is not in DIM mode N A Reserved SIS EN Synchronous independent sinks enable 1 enables all LED current sinks designated as independent sinks All of the ISC enable bits must be cleared if any ofthe SC EN bits in Register Ox10 are set this bit has no effect 0 disables all sinks designated as independent sink
6. V 07967 102 07967 105 Figure 7 Typical Standby lo Figure 10 Typical Diode Matching vs Current Sink Headroom Voltage Vus Rev 0 Page 8 of 52 ADP8860 1 0 lour 100mA 0 9 0 8 0 7 z _ 06 E 5 05 E 0 4 0 3 40 C 4 40 25 25 85 C 0 1 85 105 105 0 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 8 V 2 Vin V Figure 11 Typical Diode Current vs Current Sink Headroom Voltage Vir Figure 14 Typical ROUT G 1x vs Vin Vout 80 OF Vin z lt E z gt 5 9 ni 2 2 40 C 25 C 85 C 105 C d 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 JUNCTION TEMPERATURE C Vin V 8 Figure 12 Typical Change In Diode Current vs Temperature Figure 15 Typical Soft Start Current Iss Vip 425 C 85 C 40 C QT d Vy 25 e 6 Wy 85 C 40 C 8 2 5 3 0 3 5 40 4 5 5 0 55 TEMPERATURE C Vin V 8 Figure 13 Rour vs Temperature Figure 16 Typical Thresholds and Vit Rev 0 Page 9 of 52 ADP8860 laus mA Vout V Vour V 1 4 1 3 1 2 1 1 1 0 0 9 40 C 0 8 25 C 85 C 105 C 0
7. 18 90 5 952 0x54 39 69 26 248 0x29 19 37 6 254 0x55 40 16 26 878 Ox2A 19 84 6 562 0x56 40 63 27 514 Ox2B 20 31 6 878 0x57 41 10 28 156 0 2 20 79 7 202 0x58 41 57 28 808 Ox2D 21 26 7 534 0x59 42 05 29 466 0 2 21 73 7 872 Ox5A 42 52 30 132 Ox2F 22 20 8 218 Ox5B 42 99 30 806 0x30 22 68 8 57 Ox5C 43 46 31 486 0x31 23 15 8 932 0 5 43 94 32 174 0 32 23 62 9 3 Ox5E 44 41 32 87 0 33 24 09 9 676 Ox5F 44 88 33 574 0x34 24 57 10 058 0x60 45 35 34 284 0x35 25 04 10 45 0x61 45 83 35 002 0x36 25 51 10 848 0x62 46 30 35 726 0x37 25 98 11 254 0x63 46 77 36 46 0x38 26 46 11 666 0x64 47 24 37 2 0x39 26 93 12 086 0x65 47 72 37 948 Ox3A 27 40 12 514 0x66 48 19 38 702 Ox3B 27 87 12 95 0x67 48 66 39 466 Ox3C 28 35 13 392 0x68 49 13 40 236 Ox3D 28 82 13 842 0x69 49 61 41 014 Ox3E 29 29 14 3 Ox6A 50 08 41 798 Ox3F 29 76 14 764 Ox6B 50 55 42 59 0x40 30 24 15 238 0 6 51 02 43 39 0 41 30 71 15 718 0 6 51 50 44 198 0 42 31 18 16 204 Ox6E 51 97 45 012 0x43 31 65 16 7 Ox6F 52 44 45 834 0x44 32 13 17 202 0x70 52 91 46 664 0x45 32 60 17 71 0x71 53 39 47 5 0x46 33 07 18 228 0x72 53 86 48 346 0x47 33 54 18 752 0x73 54 33 49 198 0x48 34 02 19 284 0x74 54 80 50 056 0x49 34 49 19 824 0x75 55 28 50 924 Ox4A 34 96 20 37 0x76 55 75 51 798 Ox4B 35 43 20 926 0x77 56 22 52 68 Ox4C 35 91 21 486 0x78 56 69 53 568 Ox4D 36 38 22 056 0x79 57 17 54 464 Ox4E 36 85 22 632 Ox7A 57 64 55 368 Ox4F 37 32 23 216 Ox7B 58 11 56 28 0x50 37 80 23 808 Ox7C 58 58 57 198 0x51 3
8. 6 V SCL 2 7 V SDA 2 7 V nINT open nRST 2 7 V IN 0 V 0 4 V C1 1 uF C2 1 uF Cour 1 uF ADP8860 typical values are at T4 25 C and are not guaranteed minimum and maximum limits are guaranteed from Ta 40 C to 85 C unless otherwise noted Table 1 Parameter Symbol Test Conditions Comments Min Typ Max Unit SUPPLY Input Voltage Operating Range Vin 2 5 5 5 V Startup Level VIN TART Vin increasing 2 05 2 30 V Low Level ViN STOP Vin decreasing 1 75 1 97 V Vinstart Hysteresis VincHys After startup 80 mV UVLO Noise Filter 10 Us Quiescent Current lo Prior to Vinistart lo srART Vin Vinstart 100 mV 10 uA During Standby loisrev Vin 3 6 V Bit nSTBY 0 SCL SDA 0V 0 3 1 0 pA After Startup and Switching Vin 3 6 V Bit nSTBY 1 lout 0 mA 4 5 7 2 mA gain 2x OSCILLATOR Switching Frequency fsw 0 8 1 1 32 MHz Duty Cycle D 50 96 OUPUT CURRENT CONTROL Maximum Drive Current 7 Voip 0 4 V D1 to D7 Bit SCR 0 in the ISC7 register 25 C 26 2 30 341 mA Tj 40 to 85 C 24 4 341 mA D7 Only 60 mA Setting Ipz 60 mA Vp 0 4 V Bit SCR 1 in the ISC7 register 25 C 52 5 60 67 mA Tj 40 C to 85 C 48 8 67 mA LED Current Source Matching All Current Sinks ImatcH7 0 4 V 2 0 D2 to D7 Current Sinks 6 Vo207 0 4 V 1 5 96 Leakage Current on LED Pins Ipipz ko
9. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 MFDVID Manufacture ID Device ID 0x01 MDCR Reserved INT_CFG NSTBY DIM_EN Reserved SIS_EN CMP_AUTOEN BLEN 0x02 MDCR2 Reserved SHORT_INT TSD_INT OVP_INT CMP2_INT CMP_INT 0x03 INTR_EN Reserved SHORT_IEN TSD_IEN OVP_IEN CMP2 IEN CMP IEN 0x04 CFGR Reserved SEL_AB CMP2_SEL BLV Law FOVR 0x05 BLSEN Reserved D7EN D6EN D5EN D4EN D3EN D2EN 0 06 BLOFF Reserved OFFT 0x07 BLDIM Reserved DIMT 0x08 BLFR BL_FO BL FI 0x09 BLMX1 Reserved BL1_MC Ox0A BLDM1 Reserved BL1 DC OxOB BLMX2 Reserved BL2 MC OxOC BLDM2 Reserved BL2 DC OxOD BLMX3 Reserved BL3 MC OxOE BLDM3 Reserved BL3 DC OxOF ISCFR Reserved SC LAW 0x10 ISCC Reserved SC7_EN SC6_EN SC5_EN SCA EN SC3 EN SC2 EN SC1 EN Ox11 ISCT1 SCON SC7OFF SC6OFF SC5OFF 0 12 5 2 5 5 SC2OFF SC1OFF 0x13 ISCF SCFO SCFI 0x14 ISC7 SCR SCD7 0x15 ISC6 Reserved SCD6 0x16 ISC5 Reserved SCD5 0x17 ISC4 Reserved SCD4 0x18 ISC3 Reserved SCD3 0x19 ISC2 Reserved SCD2 Ox1A ISC1 Reserved SCD1 Ox1B CCFG FILT FORCE RD L3 OUT L2 OUT L3 EN 12 EN Ox1C CCFG2 FILT2 FORCE RD2 L3 OUT2 L2 OUT2 L3 EN2 L2 EN2 Ox1D L2 TRP L2 TRP Ox1E L2_HYS L2 HYS Ox1F L3_TRP L3_TRP 0x20 L3_HYS L3_HYS 0x21 PH1LEVL PH1LEV_LOW 0x22 PH1LEVH Reserved PH1LEV_HIGH 0x23 PH2LEVL PH2LEV_LOW 0x24 PH2LEVH Reserved PH2LEV_HIGH Rev 0 Page 27 of 52 ADP8860 Manufacturer and Device ID MFDVID Register 0x00 This is a read only register
10. Cour is too large the device inadvertently enters short circuit protection OVERVOLTAGE PROTECTION Overvoltage protection OVP is implemented on the output There are two types of overvoltage events normal no fault and abnormal from a fault or sudden load change Normal Overvoltage In a normal no fault overvoltage the output voltage approaches 4 9 V typical during normal operation This is not caused by a fault or load change but it is simply a consequence of the input voltage times the gain reaching the same level as the clamped output voltage Voureeo To prevent this type of over ADP8860 voltage the ADP8860 detects when the output voltage rises to Vovureeo It then increases the effective of the gain stage to reduce the voltage that is delivered This effectively regulates Vour to Voutirea however there is a limit to the effect that this system can have on regulating Vour It is designed only for normal operation and it is not intended to protect against faults or sudden load changes When the output voltage is regulated to Vourrc no interrupt is set and the operation is transparent to the LEDs and the overall application Abnormal Overvoltage Because of the open loop behavior of the charge pump as well as how the gain transitions are computed a sudden load change or fault can abnormally force Vour beyond 6 V This causes an abnormal overvoltage situation If the event happens slowly
11. LEDs reduces the input power consumption by allowing the charge pump to operate at lower gain states The equivalent circuit model for a charge pump is shown in Figure 43 Vout 07967 140 Figure 43 Charge Pump Equivalent Circuit Model The input voltage is multiplied by the gain G and delivered to the output through an effective resistance Rour The output current flows through Rour and produces an IR drop to yield Vour G x Vw Iovr x Rovi G 5 The Rour term is a combination of the Roson resistance for the switches used in the charge pump and a small resistance that accounts for the effective dynamic charge pump resistance The Rovr level changes based upon the gain the configuration of the switches Typical Rour values are given in Table 1 and Figure 13 and Figure 14 Vovr is also equal to the largest Vf of the LEDs that are used plus the voltage drop across the regulating current source This gives Vour Vftuax Vox 6 Combining Equation 5 and Equation 6 gives Vm Vfauax Vox Iovr Rour G G 7 This equation is useful for calculating approximate bounds for the charge pump design Determining the Transition Point of the Charge Pump Consider the following design example where Vftuax 3 7 V Tour 140 mA 7 LEDs at 20 mA each G 1 5x 3 Q obtained from Figure 13 At the point of a gain transition Vp Vurup Table 1 gives the typical value of as 0 2 V Therefore t
12. Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 709 0 017 1111111 30 30 Backlight Level 3 Dark Maximum Current Register BLMX3 Register OxOD Table 35 BLMX3 Bit Map Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved BL3 MC Table 36 Bit Descriptions for the BLMX3 Register Bit Name Bit No Description N A 7 Reserved BL3 MC 6 0 Backlight Level 3 dark maximum current See Table 28 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 709 0 017 1111111 30 30 Rev 0 Page 36 of 52 ADP8860 Backlight Level 3 Dark Dim Current Register BLDM3 Register OxOE Table 37 BLDM3 Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved BL3_DC Table 38 Bit Descriptions for the BLDM3 Register Bit Name Bit No Description N A 7 Reserved BL3_DC 6 0 Backlight Level 3 dark dim current See Table 28 for a complete list of values The backlight is set to the dim current value after a dim timeout or if the DIM_EN flag is set by the user DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 709 0 017 1111111 30 30 INDEPENDENT SINK REGISTER DESCRIPTIONS Independent Sink Current Fade Control Regis
13. PIN 1 D3 1 oc INDICATO ADP8860 TOP VIEW Not to Scale NOTES 1 CONNECT THE EXPOSED PADDLE TO GND1 AND OR GND2 16 D7 R ADP8860 15 GND1 B 14 VIN 13 VOUT 12 C2 c 11 C14 07967 003 TOP VIEW BALL SIDE DOWN Not to Scale 07967 004 Figure 3 LFCSP Pin Configuration Figure 4 WLCSP Pin Configuration Table 4 Pin Function Descriptions Pin No LFCSP WLCSP Mnemonic Description 14 A3 VIN Input Voltage 2 5 V to 5 5 V 3 D3 D1 LED Sink 1 2 E3 D2 LED Sink 2 1 E4 D3 LED Sink 3 20 D4 D4 LED Sink 4 19 D5 LED Sink 5 17 B4 D6 CMP IN2 LED Sink 6 Comparator Input for Second Phototransistor When using this pin as a second phototransistor input a capacitor 0 1 uF recommended must be connected from this pin to ground 16 B3 D7 LED Sink 7 18 C3 IN Comparator Input for Phototransistor When using this function a capacitor 0 1 uF recommended must be connected from this pin to ground 13 A2 VOUT Charge Pump Output 11 A1 1 Charge Pump 1 9 C1 C1 Charge Pump C1 12 B1 C24 Charge Pump C24 10 B2 C2 Charge Pump C2 15 A4 GND1 Ground Connect the exposed pad to GND1 and or GND2 8 D1 GND2 Ground Connect the exposed pad to GND1 and or GND2 6 D2 nINT Processor Interrupt Active Low Requires an external pull up resistor If this pin is not used it can be left floating 5 E1 nRST Hardware Reset Active Low This bit resets the device to the default
14. Vin 5 5 V 2 5 V Bit nSTBY 1 0 5 uA Equivalent Output Resistance Rout Gain 1x Vin 3 6 V lour 100 mA 0 5 Q Gain 1 5x Vin 3 1 V lour 100 mA 3 0 Q Gain 2x Vin 2 5 V lour 100 mA 3 8 Q Regulated Output Voltage Vour REG Vin 3V gain 2x lout 10 mA 4 3 4 9 5 5 V AUTOMATIC GAIN SELECTION Minimum Voltage Gain Increases VHRUP Decrease Vp1 p7 until the gain switches up 162 200 276 mV Minimum Current Sink Headroom Varmin X 95 180 mV Voltage Gain Delay The delay after gain has changed and 100 Us before gain is allowed to change again Rev 0 Page 3 of 52 ADP8860 Parameter Symbol Test Conditions Comments Min Typ Max Unit AMBIENT LIGHT SENSING COMPARATORS Ambient Light Sensor Current 5 CMP_IN Vos 2 8 V Bit CMP2_SEL 1 0 70 1 08 1 33 mA DAC Bit Step Threshold L2 Level luzerr 1 15 250 4 3 uA Threshold L3 Level liserr lacs 2000 0 54 FAULT PROTECTION Startup Charging Current Source Iss Vin 3 6 V Vout 0 8 x Vin 2 5 3 75 5 5 mA Output Voltage Threshold Vour Exit Soft Start Vouristart Vourrising 0 92 x VN V Short Circuit Protection Vour falling 0 55 x Vin V Output Overvoltage Protection Vove Activation Level 5 8 V OVP Recovery Hysteresis 500 mV Thermal Shutdown Threshold TSD 150 C Hysteresis 5 20 C Isolation from Input to Output loutLKe Vin 5 5 V Vout O V Bi
15. alternatively charge from the battery and discharge into the output For G 1 5x the capacitors are charged from VIN in series and are discharged to VOUT in parallel For G 2x the capacitors are charged ADP8860 from VIN in parallel and are discharged to VOUT in parallel In certain fault modes the switches are opened and the output is physically isolated from the input Automatic Gain Selection Each LED that is driven requires a current source The voltage on this current source must be greater than a minimum head room voltage 200 mV typical to maintain accurate current regulation The gain is automatically selected based on the minimum voltage Vox at all of the current sources At startup the device is placed into G 1x mode and the output charges to Vm If any Vox level is less than the required headroom 200 mV the gain is increased to the next step G 1 5x A 100 delay is allowed for the output to stabilize prior to the next gain switching decision If there remains insufficient current sink headroom then the gain is increased again to 2x Conversely to optimize efficiency it is not desirable for the output voltage to be too high Therefore the gain reduces when the headroom voltage is great enough This point labeled Vomax in Figure 27 is internally calculated to ensure that the lower gain still results in ample headroom for all the current sinks The entire cycle is illustrated in Figure 27 Note that t
16. conditions If not used this pin must be tied above Viu 7 C2 SDA PC Serial Data Requires an external pull up resistor 4 E2 SCL Clock Requires an external pull up resistor Rev 0 Page 7 of 52 ADP8860 TYPICAL PERFORMANCE CHARACTERISTICS VIN 3 6 V SCL 2 7 V SDA 2 7 V nRST 2 7 V 0 4 V Cx 1 C1 1 uF C2 1 uF Cour 1 Ta 25 C unless otherwise noted Vin 3 6V Ipt p7 30mA lour NO LOAD Iq mA lout mA 40 C 25 85 C 105 C 2 1 0 1 2 V Figure 8 Typical Diode Current vs Current Sink Headroom Voltage Vr 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Vin V 07967 100 07967 103 Figure 5 Typical Operating Current G 1x lour NO LOAD Vp1 p7 0 4V Iq mA lout mA 10 25 C 85 C 105 C 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Vin V 07967 104 Vin V 07967 101 Figure 6 Typical Operating Current G 2x lovactive Figure 9 Typical Diode Matching vs Vin 10 Vin 3 6V Ipt p7 30mA SCL SDA 0V nRST 2 7V 0 1 la HA MISMATCH 0 2 04 06 08 1 0 1 2 1 4 1 6 1 8 2 0 0 001 0 Vu V 1 2 3 4 5 6 Vin
17. enough the system first tries to regulate the output to 4 9 V as in a normal overvoltage scenario However if this is not sufficient or if the event happens too quickly then the ADP8860 enters overvoltage protection OVP mode when Vour exceeds the OVP threshold typically 5 8 V In the OVP mode only the charge pump is disabled to prevent Vour from rising too high The current sources and all other device functionality remain intact When the output voltage falls by about 500 mV to 5 3 V typical the charge pump resumes operation If the fault or load step recurs the process may repeat An interrupt flag is set at each OVP instance THERMAL SHUTDOWN OVERTEMPERATURE PROTECTION If the die temperature of the ADP8860 rises above a safe limit 150 C typical the controllers enter thermal shutdown TSD protection mode In this mode most of the internal functions shut down the part enters standby and the TSD_INT interrupt is set When the die temperature decreases below 130 C the part can be restarted To restart the part simply remove it from standby No interrupt is generated when the die temperature falls below 130 C However if the software clears the pending TSD_INT interrupt and the temperature remains above 130 C another interrupt is generated The complete state machine for these faults SCP OVP and TSD is shown in Figure 42 Rev 0 Page 21 of 52 ADP8860 EXIT STBY 0 ds EXIT sey 1 f STARTUP CHARGE
18. mode The following lists the code settings for photosensor current hysteresis 0000000 0 pA 00000001 4 3 pA 00000010 8 6 HA 00000011 12 9 pA 11111010 1080 pA 11111111 1106 uA Although codes above 1111010 250 are possible they should not be used Furthermore the maximum value of L2_TRP L2_HYS must not exceed 1111010 250 Rev 0 Page 46 of 52 ADP8860 Comparator Level 3 Threshold L3 TRP Register Ox1F Table 72 L3 TRP Bit Map Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit O L3 TRP Table 73 Bit Descriptions for the L3 TRP Register Bit Name Bit No Description L3 TRP 7 0 Comparator Level 3 threshold If the comparator input is below L3 TRP the comparator trips and the backlight enters Level 3 dark mode The following lists the code settings for photosensor current 0000000 0 pA 0000001 0 54 uA 0000010 1 08 uA 0000011 1 62 uA 1111111 137 7 pA Comparator Level 3 Hysteresis L3 HYS Register 0x20 Table 74 L3_HYS Comparator Level 3 Hysteresis Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O L3_HYS Table 75 Bit Descriptions for the L3_HYS Register Bit Name Bit No Description L3_HYS 7 0 Comparator Level 3 hysteresis If the comparator input is above L3_TRP L3_HYS the comparator trips and the backlight enters Level 2 off
19. the interrupt or writing a 0 has no effect Rev 0 Page 23 of 52 ADP8860 APPLICATIONS INFORMATION The ADP8860 allows the charge pump to operate efficiently with a minimum of external components Specifically the user must select an input capacitor Ci output capacitor Cour and two charge pump fly capacitors and C2 Cm should be 1 uF or greater The value must be high enough to produce a stable input voltage signal at the minimum input voltage and maximum output load A 1 capacitor for Cour is recommended Larger values are permissible but care must be exercised to ensure that VOUT charges above 5596 typical of Vin within 4 ms typical See the Short Circuit Protection Mode section for more details For best practice it is recommended that the two charge pump fly capacitors be 1 uF larger values are not recommended and smaller values may reduce the ability of the charge pump to deliver maximum current For optimal efficiency the charge pump fly capacitors should have low equivalent series resistance ESR Low ESR X5R or X7R capacitors are recommended for all four components Use voltage ratings of 10 V or greater for these capacitors If one or both ambient light sensor comparator inputs IN and D6 CMP IN2 are used a small capacitor 0 1 uF is recommended must be connected from the input to ground Any color of LED can be used if the Vf forward voltage is less than 4 1 V However using lower Vf
20. timeout DIMT period the backlight is set to the dim current value The dim timeout starts after backlight reaches the maximum current 0000 timeout disabled 0000001 1 sec 0000010 2 sec 0000011 3 sec 1111111 2 127 sec Rev 0 Page 31 of 52 ADP8860 Backlight Fade BLFR Register 0x08 Table 24 BLFR Backlight Fade Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BL FO BL FI Table 25 Bit Descriptions for the BLFR Register Bit Name Bit No Description BL FO 7 4 Backlight fade out rate If the fade out is disabled BL FO 0000 the backlight changes instantly within 100 ms If the fade out rate is set the backlight fades from its current value to the dim or the off value The times listed for BL FO are for a full scale fade out 30 mA to 0 mA Fades between closer current values reduce the fade time See the Automated Fade In and Fade Out section for more information 0000 0 1 sec fade out disabled 0001 0 3 sec 0010 0 6 sec 0011 0 9 sec 0100 1 2 sec 0101 1 5 sec 0110 1 8 sec 0111 2 1 sec 1000 2 4 sec 1001 2 7 sec 1010 2 3 0 sec 1011 2 3 5 sec 1100 4 0 sec 1101 4 5 sec 1110 2 5 0 sec 1111 5 5 sec BL FI 3 0 Backlight fade in rate If the fade in is disabled BL Fl 0000 the backlight changes instantly within 100 ms If the fade in rate is set the backlight fades from its current value to its maxim
21. to the SCON setting 00 off time disabled 01 0 6 sec 10 1 2 sec 11 1 8 sec SC2OFF 3 2 SC2 off time When the SC off time is disabled the ISC remains on while enabled When the SC off time is set to any other value then the ISC turns off for the off time per the following listed times and then turns on according to the SCON setting 00 off time disabled 01 2 0 6 sec 10 1 2 sec 11 1 8 SC1OFF 1 0 SC1 off time When the SC off time is disabled the ISC remains on while enabled When the SC off time is set to any other value then the ISC turns off for the off time per the following listed times and then turns on according to the SCON setting 00 off time disabled 01 20 6 sec 10 1 2 sec 11 1 8 sec 1 An independent sink remains on continuously when SCx EN 1 and SCx OFF is 00 disabled To enable multiple independent sinks set the appropriate SCx EN bits To create equivalent blinking and fading sequences enable all independent sinks in one write Cycle This causes a preprogrammed sequence to start simultaneously Rev 0 Page 39 of 52 ADP8860 Independent Sink Current Fade ISCF Register 0x13 Table 47 ISCF Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCFO SCFI Table 48 Bit Descriptions for the ISCF Register Bit Name Bit No Description SCFO 7 4 Sink current fade out rate The foll
22. 2 0 007 0000011 0 709 0 017 1111111 30 30 Sink Current Register LED1 ISC1 Register Ox1A Table 62 ISC1 Bit Map Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved SCD1 Table 63 Bit Descriptions for the ISC1 Register Bit Name Bit No Description N A 7 Reserved SCD1 6 0 Sink current Use the following DAC code schedule see Table 28 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 709 0 017 1111111 30 30 Rev 0 Page 44 of 52 COMPARATOR REGISTER DESCRIPTIONS Comparator Configuration CCFG Register 0x1B Table 64 CCFG Bit Map ADP8860 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 FILT FORCE_RD L3_OUT L2 OUT L3 EN L2 EN Table 65 Bit Descriptions for the CCFG Register Bit Name Description FILT 7 5 Filter setting for the CMP IN light sensor 000 80 ms 001 160 ms 010 320 ms 011 640 ms 100 1280 ms 101 2560 ms 110 5120 ms 1112 10 240 ms FORCE RD 4 Force a read of the CMP_IN light sensor while independent sinks are running but the backlight is not Reset by chip after the conversion is complete and L2 OUT and L3 OUT are valid Ignored if the backlight is enabled L3 OUT This bit is the output of the L3 comparator L2 OUT This bit is the output of the L2 comparat
23. 2 comparator controls the office to daylight transition see Figure 38 The currents for the different lighting modes are defined the BLMXx and BLDMx registers see the Backlight Operating Levels section L2 OUT 1 L2 OUT 1 L2 OUT 0 L3 OUT 1 L3 OUT 0 L3 OUT 0 07967 023 BRIGHTNESS Figure 38 Light Sensor Modes Based on the Detected Ambient Light Level Each light sensor comparator uses an external capacitor together with an internal reference current source to form an analog to digital converter ADC that samples the output of the external photosensor The ADC result is fed into two programmable trip comparators The ADC has an input range of 0 uA to 1080 uA typical FILTER SETTINGS L3 TRIP PHOTO SENSOR OUTPUT L3 OUT 07967 024 Figure 39 Ambient Light Sensing and Trip Comparators The L2 CMPR detects when the photosensor output has dropped below the programmable L2 point Register Ox1D If this event occurs then the L2 OUT status signal is set L2 CMPR contains programmable hysteresis meaning that the photo sensor output must rise above L2 TRP L2 HYS before 12 OUT clears L2_CMPR is enabled via the L2 EN bit The L2 TRP and L2 HYS values of L2 CMPR can be set between 0 pA and 1080 typical in steps of 4 3 uA typical The L3 CMPR detects when the photosensor output has dropped below the programmable L3 TRP point Register Ox1F If this event occurs the L3 OUT
24. 42 0x69 24 803 20 507 0x49 17 244 9 912 Ox6A 25 039 20 899 Ox4A 17 480 10 185 Ox6B 25 276 21 295 Ox4B 17 717 10 463 0 6 25 512 21 695 Ox4C 17 953 10 743 0 6 25 748 22 099 Ox4D 18 189 11 028 Ox6E 25 984 22 506 Ox4E 18 425 11 316 Ox6F 26 220 22 917 Ox4F 18 661 11 608 0x70 26 457 23 332 0x50 18 898 11 904 0x71 26 693 23 750 0x51 19 134 12 203 0x72 26 929 24 173 0x52 19 370 12 507 0x73 27 165 24 599 0x53 19 606 12 814 0x74 27 402 25 028 0x54 19 842 13 124 0x75 27 638 25 462 0x55 20 079 13 439 0x76 27 874 25 899 0x56 20 315 13 757 0x77 28 110 26 340 0x57 20 551 14 078 0x78 28 346 26 784 0x58 20 787 14 404 0x79 28 583 27 232 0x59 21 024 14 733 Ox7A 28 819 27 684 Ox5A 21 260 15 066 Ox7B 29 055 28 140 Ox5B 21 496 15 403 Ox7C 29 291 28 599 Ox5C 21 732 15 743 0x7D 29 528 29 063 Ox5D 21 968 16 087 Ox7E 29 764 29 529 Ox5E 22 205 16 435 Ox7F 30 000 30 000 1 Cubic 10 and Cubic 11 laws use the square law DAC setting but vary the time step per DAC code see Figure 31 Rev 0 Page 34 of 52 Backlight Level 1 Daylight Dim Current Register BLDM1 Register OxOA Table 29 BLDMI Bit Map ADP8860 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved BL1_DC Table 30 Bit Descriptions for the BLDMI Register Bit Name Bit No Description N A 7 Reserved BL1 DC 6 0 Backlight Level 1 daylight dim current The backlight is set to the dim current value after
25. 45 0 030 0x23 8 268 2 279 0x05 1 181 0 047 0x24 8 504 2 411 0x06 1 417 0 067 0x25 8 740 2 546 0x07 1 654 0 091 0x26 8 976 2 686 0x08 1 890 0 119 0x27 9 213 2 829 0x09 2 126 0 151 0x28 9 449 2 976 Ox0A 2 362 0 186 0x29 9 685 3 127 OxOB 2 598 0 225 0 2 9 921 3 281 0x0C 2 835 0 268 0x2B 10 157 3 439 0x0D 3 071 0 314 0 2 10 394 3 601 OxOE 3 307 0 365 0x2D 10 630 3 767 OxOF 3 543 0 419 Ox2E 10 866 3 936 0x10 3 780 0 476 Ox2F 11 102 4 109 0x11 4 016 0 538 0x30 11 339 4 285 0x12 4 252 0 603 0x31 11 575 4 466 0x13 4 488 0 671 0x32 11 811 4 650 0x14 4 724 0 744 0x33 12 047 4 838 0x15 4 961 0 820 0x34 12 283 5 029 0x16 5 197 0 900 0x35 12 520 5 225 0x17 5 433 0 984 0x36 12 756 5 424 0x18 5 669 1 071 0x37 12 992 5 627 0x19 5 906 1 163 0x38 13 228 5 833 Ox1A 6 142 1 257 0x39 13 465 6 043 Ox1B 6 378 1 356 0x3A 13 701 6 257 0x1C 6 614 1 458 0x3B 13 937 6 475 0x1D 6 850 1 564 0x3C 14 173 6 696 Ox1E 7 087 1 674 Ox3D 14 409 6 921 Rev 0 Page 33 of 52 ADP8860 DAC Code Linear Law mA Square Law mA DAC Code Linear Law mA Square Law mA Ox3E 14 646 7 150 Ox5F 22 441 16 787 Ox3F 14 882 7 382 0x60 22 677 17 142 0x40 15 118 7 619 0x61 22 913 17 501 0x41 15 354 7 859 0x62 23 150 17 863 0x42 15 591 8 102 0x63 23 386 18 230 0x43 15 827 8 350 0x64 23 622 18 600 0x44 16 063 8 601 0x65 23 858 18 974 0x45 16 299 8 855 0x66 24 094 19 351 0x46 16 535 9 114 0x67 24 331 19 733 0x47 16 772 9 376 0x68 24 567 20 118 0x48 17 008 9 6
26. 7 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Vin V Figure 17 Typical ALS Current las Vin 3V GAIN 2x lout 10mA 40 10 20 50 80 110 JUNCTION TEMPERATURE C Figure 18 Typical Regulated Output Voltage Voutirec 6 0 5 8 OVP THRESHOLD 5 6 5 4 OVP RECOVERY 52 0 10 20 50 80 11 4 0 JUNCTION TEMPERATURE C Figure 19 Typical Overvoltage Protection OVP Threshold EFFICIENCY 07967 112 EFFICIENCY 07967 113 07967 114 Rev 0 Page 10 of 52 lin mA lout 140mA Vf 3 1V lour 210mA Vf 3 2V 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Vin V Figure 20 Typical Efficiency Low Vf Diode liN mA lout 140mA Vf 3 85V lout 210mA Vf 4 25V 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Vin V Figure 21 Typical Efficiency High Vf Diode COUPLED 50mV DIV 1 AC COUPLED 10mA DIV Cin 14F Cour 1pF C1 1pF C2 1pF Vin 3 6V lout 120mA 500ns DIV 07967 117 Figure 22 Typical Operating Waveforms 1x 07967 115 07967 116 ADP8860 Vin 3 7V i Vout 1V DIV EP t I 10mA DIV Ci 1HF 1uF C1 1pF C2 1pF Vin 3 0V d E lour 120mA 5 lout 10mA DIV 100psiDIV E Figure 25
27. 8 27 24 406 0x7D 59 06 58 126 0x52 38 74 25 014 Ox7E 59 53 59 058 0x53 39 21 25 628 Ox7F 60 60 Cubic 10 and Cubic 11 laws use the square law DAC setting but vary the time step per DAC code see Figure 31 Rev 0 Page 42 of 52 Sink Current Register LED6 ISC6 Register 0x15 Table 52 ISC6 Bit Map ADP8860 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved SCD6 Table 53 Bit Descriptions for the ISC6 Register Bit Name Bit No Description N A 7 Reserved SCD6 6 0 Sink current Use the following DAC code schedule see Table 28 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 709 0 017 1111111 30 30 Sink Current Register LED5 ISC5 Register 0x16 Table 54 ISC5 Bit Map Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved SCD5 Table 55 Bit Descriptions for the ISC5 Register Bit Name Bit No Description N A 7 Reserved SCD5 6 0 Sink current Use the following DAC code schedule see Table 28 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 709 0 017 1111111 30 30 Sink Current Register LED4 ISC4 Register 0x17 Table 56 ISC4 Bit Map Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reser
28. ANALOG DEVICES Charge Pump 7 Channel Smart LED Driver with 12 Interface ADP8860 FEATURES Charge pump with automatic gain selection of 1x 1 5x and 2x for maximum efficiency Up to two built in comparator inputs with programmable modes for ambient light sensing Outdoor office and dark modes for maximum backlight power savings 7 independent and programmable LED drivers 6 drivers capable of 30 mA typical 1 driver capable of 60 mA typical Programmable maximum current limit 128 levels Standby mode for lt 1 pA current consumption 16 programmable fade in and fade out times 0 1 sec to 5 5 sec Choose from linear square or cubic rates Fading override PC compatible interface for all programming Dedicated reset pin and built in power on reset POR Short circuit overvoltage and overtemperature protection Internal soft start to limit inrush currents Input to output isolation during faults or shutdown Operation down to Vin 2 5 V with undervoltage lockout UVLO at Vin 2 0 V Small wafer level chip scale package WLCSP or lead frame chip scale package LFCSP APPLICATIONS Mobile display backlighting Mobile phone keypad backlighting Dual RGB backlighting LED indication General backlighting of small format displays GENERAL DESCRIPTION The ADP8860 combines a programmable backlight LED charge pump driver with automatic phototransistor control This combi nation allows for significant power savings because it chang
29. CMPR and L3 CMPR comparators can be enabled independently of each other or can operate simultaneously A single conversion from each ADC takes 80 ms typical When AUTOEN is set for automatic backlight adjustment see the Automatic Backlight Adjustment section the ADC and comparators run continuously If the backlight is disabled and at least one independent sink is enabled it is possible to use the light sensor comparators in a single shot mode A single shot read of the photocomparators is performed by setting the FORCE RD bit After the single shot measurement is completed the internal state machine clears the FORCE RD bit The interrupt flags INT and INT2 be used to notify the system when either L2 or L3 changes state Refer to the Interrupts section for more information AUTOMATIC BACKLIGHT ADJUSTMENT The ambient light sensor comparators can automatically transition the backlight between one of its three operating levels To enable this mode set the AUTOEN bit in Register 0x01 When enabled the internal state machine takes control of the BLV bits and changes them based on the L2 OUT and L3 OUT status bits When L2 OUT is set high it indicates that the ambient light conditions have dropped below the L2 point and the backlight should move to its office L2 level When L3 OUT is set high it indicates that ambient light conditions have dropped below the L3 TRP point and the backlight sh
30. D typically 30 mA The ADP8860 can also implement a nonlinear square approxima tion relationship between input code and backlight current level In this case law 01 the backlight current in milliamperes is determined by the following equation Backlight Current mA Code x TT Figure 30 shows the backlight current level vs input code for both the linear and square law algorithms 30 N a N e BACKLIGHT CURRENT mA a 0 32 64 96 128 SINK CODE 07967 015 Figure 30 Backlight Current vs Input Code AUTOMATED FADE IN AND FADE OUT The LED drivers are easily configured for automated fade in and fade out Sixteen fade in and fade out rates can be selected via the C interface Fade and fade out rates range from 0 1 sec to 5 5 sec per full scale current either 30 mA or 60 mA ADP8860 Table 5 Available Fade In and Fade Out Rates Code Fade Rate in sec per Full Scale Current 0000 0 1 disabled 0001 0 3 0010 0 6 0011 0 9 0100 1 2 0101 1 5 0110 1 8 0111 2 1 1000 24 1001 2 7 1010 3 0 1011 3 5 1100 4 0 1101 4 5 1110 5 0 1111 5 5 Full Scale Current 3 The fade profile is based on the transfer law selected linear square Cubic 10 or Cubic 11 and the delta between the actual current and the target current Smaller changes in current reduce the fade time For linear and square law fades the fade time is given by F
31. Page 24 of 52 ADP8860 The ADP8860 has an integrated noise filter on the nRST bypass capacitor on this pin If the nRST pin is not used it must pin Under normal conditions it is not necessary to filter be pulled well above the Vinay level see Table 1 Do not allow the reset line However if exposed to an unusually noisy the nRST pin to float signal then it is beneficial to add a small RC filter or EXAMPLE CIRCUITS 5 OPTIONAL PHOTOSENSOR _ SET PHOTOSENSOR l Saw Ray SR Raw lt 1 Tour D1 02 D3 04 05 D6 D7 T 0 1uF 03 E3 E4 0 C4 84 03 _ Vout nRST ADP8860 SDA SCL nINT 07967 028 Figure 44 Generic Application Schematic KEYPAD LIGHT UP TO 10 LEDs 6mA EACH 60mA MAX TOTAL CURRENT inm 2 8V ACCESSORY DISPLAY BACKLIGHT LIGHTS OR r E e cc 1 SUB DISPLAY BL 0 1pF D5 D6 CMP_IN2 D7 CMP_IN 1 VDDIO 01 1pF 1 R1 R2 3 R4 ADP8860 C1 nRST 1uF 2C CONTROL SIGNALS c2 1uF 07967 029 nINT Figure 45 Application Schematic with Keypad Light Control Rev 0 Page 25 of 52 ADP8860 2 PROGRAMMING AND DIGITAL CONTROL The ADP8860 provides full software programmability to e All registers are read write unless otherwise specified facilitate its adoption in various product architectures The e Unused bits are read as zero default addre
32. TION OF 0 85 _ THE EXPOSED PAD REFER TO 0 80 0 05 THE PIN CONFIGURATION AND 0 02 NOM FUNCTION DESCRIPTIONS CK d SECTION OF THIS DATA SHEET SEATING 0 30 ia dirt oa PLANE 0 23 0 20 REF 0 18 090408 B COMPLIANT JEDEC STANDARDS MO 220 VGGD 1 Figure 48 20 Lead Lead Frame Chip Scale Package LFCSP VO 4mm x 4 mm Body Very Thin Quad CP 20 4 Dimensions shown in millimeters Rev 0 Page 49 of 52 ADP8860 ORDERING GUIDE Model Temperature Range Package Description Package Option ADP8860ACBZ R7 40 C to 85 C 20 Ball WLCSP Tape and Reel CB 20 6 ADP8860ACPZ R7 40 C to 85 C 20 Lead LFCSP VQ Tape and Reel CP 20 4 17 RoHS Compliant Part 07967 033 Figure 49 Tape and Reel Orientation for WLCSP Units Figure 50 Tape and Reel Orientation for LFCSP Units Rev 0 Page 50 of 52 07967 034 ADP8860 NOTES Rev 0 Page 51 of 52 ADP8860 NOTES 2009 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners Www ana 0 g com xus La DEVICES Rev 0 Page 52 of 52
33. Typical Start Up Waveform lin AC COUPLED 10mA DIV 07967 119 1 Cour 1 C1 1pF C2 1pF Vin 2 5 lour 120mA 500ns DIV Figure 24 Typical Operating Waveforms G 2x Rev 0 Page 11 of 52 ADP8860 THEORY OF OPERATION The ADP8860 combines a programmable backlight LED charge pump driver with automatic phototransistor control This combi nation allows for significant power savings because it is able to change the current intensity based on the lighting conditions It performs this function automatically thereby removing the need for a processor to monitor the phototransistor The light intensity levels are fully programmable via the interface A second phototransistor input with dedicated comparators improves the ambient light detection abilities for various user operating conditions STNDBY 1 1 UVLO 1 I 1 1 1 STNDBY SWITCH CONTROL ILED CONTROL nINT GND2 The ADP8860 allows up to seven LEDs to be independently driven up to 30 mA typical The seventh LED can also be driven to 60 mA typical All LEDs can be individually pro grammed or combined into a group to operate backlight LEDs A full set of safety features including short circuit overvoltage and overtemperature protection with input to output isolation allow for a robust and safe design The integrated soft start limits inrush currents at startu
34. Vin TO Vout SCP FAULT DIE TEMP lt TSD TSD uys MIN Vp1 D7 100us TYP lt VHR UP 0 WAIT MIN Vp4 p7 MIN Vp4 p7 100us lt VHR UP gt Vpmax Vout gt Vour REG TRY TO REGULATE 1 VOUT TO VoUuT REG WAIT MIN Vp1 p7 100ps gt Vomax REGULATE VOUT TO NOTES Vour REG 1 5 THE CALCULATED GAIN DOWN TRANSITION POINT 07967 027 Figure 42 Fault State Machine Rev 0 Page 22 of 52 INTERRUPTS There are five interrupt sources available on the ADP8860 Main light sensor comparator CMP_INT sets every time the main light sensor comparator detects a threshold L2 or L3 transition rising or falling conditions Sensor Comparator 2 CMP2_INT interrupt works the same way as CMP_INT except the sensing input derives from the second light sensor The programmable thresholds are the same as the main light sensor comparator ADP8860 e Overvoltage protection is generated when the output voltage exceeds 5 8 V typical e Thermal shutdown circuit An interrupt TSD_INT is generated when entering overtemperature protection e Short circuit detection SHORT INT is generated when the device enters short circuit protection mode The interrupt if any that appears on the nINT pin is deter mined by the bits mapped in Register INTR EN To clear an interrupt write a 1 to the interrupt in the MDCR2 register or reset the part Reading
35. a dim timeout or if the DIM EN flag is set by the user see Table 28 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 709 0 017 1111111 30 30 Backlight Level 2 Office Maximum Current Register BLMX2 Register OxOB Table 31 BLMX2 Bit Map Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Reserved BL2_MC Table 32 Bit Descriptions for the BLMX2 Register Bit Name Bit No Description N A 7 Reserved BL2 MC 6 0 Backlight Level 2 office maximum current see Table 28 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 709 0 017 1111111 30 30 Rev 0 Page 35 of 52 ADP8860 Backlight Level 2 Office Dim Current Register BLDM2 Register 0 0 Table 33 BLDM2 Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved BL2_DC Table 34 Bit Descriptions for the BLDM2 Register Bit Name Bit No Description N A 7 Reserved BL2_DC 6 0 Backlight Level 2 office dim current See Table 28 for a complete list of values The backlight is set to the dim current value after a dim timeout or if the DIM_EN flag is set by the user DAC Linear Law mA Square
36. ade Time Fade Rate x Code 127 4 where the Fade Rate is shown in Table 5 The Cubic 10 and Cubic 11 laws also use the square backlight currents in Equation 3 however the time between each step is varied to produce a steeper slope at higher currents and a shallower slope at lighter currents see Figure 31 30 25 20 CURRENT mA a CUBIC 11 CUBIC 10 0 0 25 0 50 0 75 1 00 UNIT FADE TIME 07967 016 Figure 31 Comparison of the Dimming Transfers Laws BACKLIGHT TURN ON TURN OFF DIM With the device in active mode nSTBY 1 the backlight can be turned on using the BL_EN bit in Register 0x01 Before turning on the backlight the user chooses which level daylight L1 office L2 or dark L3 in which to operate and ensures that maximum and dim settings are programmed for that level Rev 0 Page 17 of 52 ADP8860 The backlight turns on when BL_EN 1 The backlight turns off when BL_EN 0 BACKLIGHT CURRENT MAX BL EN 1 BL EN 0 Figure 32 Backlight Turn On Off 07967 017 While the backlight is on EN 1 the user can change to the dim setting by programming DIM EN 1 in Register 0x01 If DIM EN 0 the backlight reverts to its maximum setting BACKLIGHT CURRENT MAX DIM MER BL EN 1 DIM EN 1 DIM EN 0 BL 0 Figure 33 Backlight Turn On Dim Turn Off 07967 018 The maximum and dim settings can be set between 0 mA and 30 mA t
37. agram in Figure 28 Rev 0 Page 14 of 52 ADP8860 SHUTDOWN lt gt 1 Vin 24 Vin CROSSES 2 05V AND TRIGGERS POWER ON RESET nRST MUST BE HIGH FOR 20 MAX BEFORE SENDING 2 COMMANDS BIT nSTBY IN REGISTER NC GOES HIGH lt 7100 5 DELAY BETWEEN POWER UP AND WHEN 12 COMMANDS CAN BE RECEIVED tot 25us TO 100s NOISE nRST l 3 75mA CHARGES 4 5x Vout TO Vin LEVEL GAIN CHANGES ONLY OCCUR WHEN NECESSARY nSTBY nRST IS LOW WHICH FORCES nSTBY LOW AND RESETS ALL I2C REGISTERS Vout 4 SOFT START gt gt 1 SOFT START 10ps 1100ps 07967 013 Figure 28 Typical Timing Diagram Rev 0 Page 15 of 52 ADP8860 BACKLIGHT OPERATING LEVELS By default the backlight operates at daylight level BLV 00 where the maximum brightness is set using Register 0x09 BLMX1 A daylight dim setting can also be set using Register 0x0A BLDM1 When operating at office level BLV 01 the backlight maximum and dim brightness settings are set by Register 0x0B BLMX2 and Register 0x0C BLDM2 When operating at the dark level BLV 10 the backlight maximum and dim brightness settings are set by Register 0 0 BLMX3 and Register BLDM3 Backlight brightness control operates in three distinct levels daylight L1 of
38. ame Bit No Description L2_EN2 0 Note that the L3 comparator has priority over L2 1 the L2 comparator is enabled for the CMP_IN2 comparator 0 the L2 comparator is disabled for the CMP_IN2 comparator Comparator Level 2 Threshold L2 TRP Register 0x1D Table 68 L2 TRP Bit Map Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 L2_TRP Table 69 Bit Descriptions for the L2_TRP Register Bit Name Bit No Description L2_TRP 7 0 Comparator Level 2 threshold If the comparator input is below L2_TRP then the comparator trips and the backlight enters Level 2 office mode The following lists the code settings for photosensor current 00000000 0 pA 00000001 4 3 pA 00000010 8 6 uA 00000011 12 9 pA 11111010 1080 pA 11111111 1106 Although codes above 1111010 250 are possible they should not be used Furthermore the maximum value of L2_TRP L2_HYS must not exceed 1111010 250 Comparator Level 2 Hysteresis 12 HYS Register Ox1E Table 70 L2 HYS Bit Map Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O L2_HYS Table 71 Bit Descriptions for the L2_HYS Register Bit Name Bit No Description L2_HYS 7 0 Comparator Level 2 hysteresis If the comparator input is above L2_TRP L2_HYS the comparator trips and the backlight enters Level 1 daylight
39. de in out Driving this entire configuration is a two capacitor charge pump with gains of 1x 1 5x and 2x This setup is capable of driving a maximum lovr of 240 mA from a supply of 2 5 V to 5 5 V The device includes a variety of safety features including short circuit overvoltage and overtemperature protection These features allow easy implementation of a safe and robust design Addi tionally input inrush currents are limited via an integrated soft start combined with controlled input to output isolation ADP8860 is available in two package types either a compact 2mm x 24 mm x 0 6 mm WLCSP wafer level chip scale package or a small LFCSP lead frame chip scale package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2009 Analog Devices Inc All rights reserved ADP8860 TABLE OF CONTENTS Features cose RR RITE REESE RR 1 Applications tee tenent etes et etre Ea 1 General D scriptionu enter IRR 1 Typical Operating Circuit seen 1 R vision HiStOEy oec rS EEEE e 2 Specificato Sei eed terit Merle dilatio tete 3 PC Timing Diagrami escineinsenincineninnininnsniiie 5 Absolute Maximum Ratings seen 6 Maximum Temperature Ranges sse 6 Thermal Resistance oe tere temone tete 6 ESDCautioniz RENE 6 Pin Configurations and Function Descriptions
40. e may force the backlight to operate at one of the three brightness levels Setting CMP_AUTOEN high Register 0x01 sets these values automatically and overwrites any previously written values 00 Level 1 daylight 01 Level 2 office 10 Level 3 dark 11 off backlight set to 0 mA Law 2 1 Backlight transfer law 00 linear law DAC linear time steps 01 square law DAC linear time steps 10 square law DAC nonlinear time steps Cubic 10 11 square law DAC nonlinear time steps Cubic 11 FOVR 0 Backlight fade override 1 the backlight fade override is enabled 0 the backlight fade override is disabled Backlight Sink Enable BLSEN Register 0x05 Table 18 BLSEN Bit Map Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved D7EN D6EN D5EN D4EN D3EN D2EN D1EN Table 19 Bit Descriptions for the BLSEN Register Bit Name Bit No Description N A 7 Reserved D7EN 6 Diode 7 backlight sink enable 1 selects LED7 as an independent sink 0 connects LED7 sink to backlight enable BL EN D6EN 5 Diode 6 backlight sink enable 1 selects LED6 as an independent sink 0 connects LED6 sink to backlight enable BL EN Rev 0 Page 30 of 52 ADP8860 Bit Name Bit No Description D5EN Diode 5 backlight sink enable 1 selects LED5 as an independent sink 0 connects LEDS sink to backlight enable BL EN D4EN
41. ent settings disabled 0 6 sec 1 2 sec and 1 8 sec Blink mode is activated by setting the off timers to any setting other than disabled Rev 0 Page 20 of 52 Program all fade on and off timers before enabling any of the LED current sinks If ISCx is on during a blink cycle and SCx_EN is cleared it turns off or fades to off if fade out is enabled If ISCx is off during a blink cycle and SCx_EN is cleared it stays off SCx CURRENT ON TIME ON TIME Ha FADE IN FADE OUT FADE IN FADE OUT HL MAX OFF OFF TIME TIME Ht gt Ht n gt SCx EN SET BY USER Figure 41 Independent Sink Blink Mode with Fading SHORT CIRCUIT PROTECTION MODE The ADP8860 can protect against short circuits on the output VOUT Short circuit protection SCP is activated at the point when VOUT 55 of Vin Note that this SCP sensing is disabled during both start up and restart attempts fault recovery SCP 07967 026 sensing reenables 4 ms typical after activation During a short circuit fault the device enters a low current consumption state and an interrupt flag is set The device can be restarted at any time after receiving a short circuit fault by simply rewriting nSTBY 1 It then repeats another complete soft start sequence Note that the value of the output capacitance Cour should be small enough to allow VOUT to reach approximately 55 typical of V within the 4 ms typical time If
42. er OFFT before turning on the backlight If BL EN 1 the backlight turns on to its maximum setting and the off timer starts counting When the off timer expires the internal state machine clears the EN bit and the backlight turns off BACKLIGHT CURRENT OFF TIMER RUNNING i 1t i MAX BL 1 BL 0 SET BY USER 5 SET BY INTERNAL STATE MACHINE Figure 35 Off Timer 07967 020 The backlight can be turned off at any point during the off timer countdown by clearing BL_EN The dim timer and off timer can be used together for sequential maximum to dim to off functionality With both the dim and off timers programmed if BL_EN is asserted the backlight turns on to its maximum setting and when the dim timer expires the backlight changes to its dim setting When the off timer expires the backlight turns off Rev 0 Page 18 of 52 BACKLIGHT CURRENT DIM TIMER RUNNING 1i a MAX OFF TIMER RUNNING DIM 1 BL_EN 1 DIM_EN 1 BLEN 0 SET BY USER 4 SET BY INTERNAL STATE MACHINE 07967 021 Figure 36 Dim and Off Timers Used Together FADE OVERRIDE A fade override feature FOVR in Register CFGR 0x04 enables the host to override the preprogrammed fade in or fade out settings If FOVR is set and the backlight is enabled in the middle of a fade out process the backlight instantly within approximately 100 ms returns to its max
43. es the current intensity in office and dark ambient light conditions By performing this function automatically it eliminates the need for a processor to monitor the phototransistor The light intensity thresholds are fully programmable via the interface A second phototransistor input with dedicated comparators improves the ambient light detection levels for various user operating conditions Rev 0 Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners TYPICAL OPERATING CIRCUIT Vals OPTIONAL PHOTOSENSOR Vout PHOTOSENSOR D1 D2 D3 D4 D5 0 1pF D6 CMP_IN2 ADP8860 C1 gt 1 SDA lt gt C2 SCL E2 1uF nINT 07967 001 Figure 1 The ADP8860 allows as many as six LEDs to be independently driven up to 30 mA typical A seventh LED can be driven to 60 mA typical All LEDs are programmable for minimum max imum current and fade in out times via the interface These LEDs can also be combined into groups to reduce the processor instructions during fa
44. fice L2 and dark L3 The BLV bits in Register 0x04 control the specific level in which the backlight operates These bits can be changed manually or if in automatic mode CMP_AUTOEN is set high in Register 0x01 by the ambient light sensor see the Ambient Light Sensing section 30mA DAYLIGHT L1 OFFICE L2 DARK L3 SJ AYLIGHT_MA X 1 YLIGHT_DI BACKLIGHT CURRENT 07967 014 BACKLIGHT OPERATING LEVELS Figure 29 Backlight Operating Levels Rev 0 Page 16 of 52 BACKLIGHT MAXIMUM AND DIM SETTINGS The backlight maximum and dim current settings are deter mined by a 7 bit code programmed by the user into the registers previously listed in the Backlight Operating Levels section The 7 bit resolution allows the user to set the backlight to one of 128 different levels between 0 mA and 30 mA The ADP8860 can implement two distinct algorithms to achieve a linear and a nonlinear relationship between input code and backlight current The law bits in Register 0x04 are used to change between these algorithms By default the ADP8860 uses a linear algorithm law 00 where the backlight current increases linearly for a corresponding increase of input code Backlight current in millamperes is determined by the following equation Backlight Current mA Code x Full Scale Current 127 2 where Code is the input code programmed by the user Full Scale Current is the maximum sink current allowed per LE
45. he gain selection criteria apply only to active current sources If current sources have been deactivated through an command for example only five LEDs are used then the voltages on the deactivated current sources are ignored Rev 0 Page 13 of 52 ADP8860 EXIT STARTUP WAIT 100us TYP WAIT 100 EXIT STBY STATUP CHARGE Vin TO Vout WAIT 100 NOTES 1 IS THE CALCULATED GAIN DOWN TRANSITION POINT MIN Vp1 p7 lt VHR UP MIN Vp1 p7 lt Vomax MIN Vp4 p7 gt Vomax 07967 012 Figure 27 State Diagram for Automatic Gain Selection Soft Start Feature At startup either from UVLO activation or fault standby recovery the output is first charged by Iss 3 75 mA typical until it reaches about 92 of Vix This soft start feature reduces the inrush current that is otherwise present when the output capacitance is initially charged to Vi When this point is reached the controller enters 1x mode If the output voltage is not sufficient then the automatic gain selection determines the optimal point as defined in the Automatic Gain Selection section OPERATING MODES There are four different operating modes active standby shutdown and reset Active Mode In active mode all circuits are powered up and in a fully operational state This mode is entered when nSTBY in Register MDCR is set to 1 Standby Mode Standby mode disables all circui
46. he input voltage level when the gain transitions from 1 5x to 2x is Vin 3 7 V 0 2 V 140 mA x 3 Q 1 5 2 88 V LAYOUT GUIDELINES e For optimal noise immunity place the C and Cour capacitors as close as possible to their respective pins These capacitors should share a short ground trace If the LEDs are a significant distance from the VOUT pin another capacitor on VOUT placed closer to the LEDs is advisable e For optimal efficiency place the charge pump fly capacitors as close to the part as possible e ADP8860 does not distinguish between power ground and analog ground Therefore both ground pins can be connected directly together It is recommended that these ground pins be connected at the ground for the input and output capacitors e Ifusing the LFCSP package the exposed pad must be soldered at the board to the GND1 and or GND2 pin s e Unused diode pins Pin D1 to Pin D7 can be connected to ground VOUT or remain floating However the unused diode current sinks must be disabled by setting them as independent sinks in Register 0x05 and then disabling them in Register 0x10 If they are not disabled the charge pump efficiency may suffer e Ifthe CMP IN phototransistor input is not used it can be connected to ground or remain floating e Ifthe interrupt pin nINT is not used connect it to ground or leave it floating Never connect it to a voltage supply except through a 21 series resistor Rev 0
47. herefore it is possible to program a dim setting that is greater than a maximum setting For normal expected opera tion ensure that the dim setting is programmed to be less than the maximum setting AUTOMATIC DIM AND TURN OFF TIMERS The user can program the backlight to dim automatically by using the DIMT timer in Register 0x07 The dim timer has 127 settings ranging from 1 sec to 127 sec Program the dim timer DIMT before turning on the backlight If BL EN 1 the backlight turns on to its maximum setting and the dim timer starts counting When the dim timer expires the internal state machine sets DIM EN 1 and the backlight enters its dim setting BACKLIGHT CURRENT TIMER DIM TIMER RUNNING RUNNING 2 1 I 1 1 1 DIM f 1 DIM EN21 0 DIM 1 BL 0 4 SET BY USER 4 SET BY INTERNAL STATEMACHINE 07967 019 Figure 34 Dim Timer Ifthe user clears the DIM EN bit the backlight reverts to its maximum setting and the dim timer begins counting again When the dim timer expires the internal state machine again sets DIM EN 1 and the backlight enters its dim setting The backlight can be turned off at any point during the dim timer countdown by clearing BL EN The user can also program the backlight to turn off automati cally by using the OFFT timer in Register 0x06 The off timer has 127 settings ranging from 1 sec to 127 sec Program the off tim
48. ice mode The following lists the code settings for photosensor current hysteresis 0000000 0 pA 0000001 0 54 uA 0000010 1 08 pA 0000011 1 62 uA 1111111 137 7 pA First Phototransistor Register Low Byte PH1LEVL Register 0x21 Table 76 PHILEVL Bit Map Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit O LOW Table 77 Bit Descriptions for the PHILEVL Register Bit Name Bit No Description LOW 7 0 13 bit conversion value for the first light sensor low byte Bit 7 to Bit 0 The value is updated every 80 ms when the light sensor is enabled This is a read only register Rev 0 Page 47 of 52 ADP8860 First Phototransistor Register High Byte PH1LEVH Register 0x22 Table 78 PHILEVH Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Reserved PH1LEV_HIGH Table 79 Bit Descriptions for the PHILEVH Register Bit Name Bit No Description N A 7 5 Reserved HIGH 4 0 13 bit conversion value for the first light sensor high byte Bit 12 to Bit 8 The value is updated every 80 ms when the light sensor is enabled This is a read only register Second Phototransistor Register Low Byte PH2LEVL Register 0x23 Table 80 PH2LEVL Bit Map Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
49. imum setting Alter natively if the backlight is fading in reasserting BL EN overrides the programmed fade in time and the backlight instantly goes to its final fade value This is useful for situations where a key is pressed during a fade sequence However if FOVR is cleared and the backlight is enabled in the middle of a fade process the backlight gradually brightens from where it was interrupted it does not go down to 0 and then come back on BACKLIGHT CURRENT FADE IN FADE OUT OVER RIDDEN OVER RIDDEN MAX 11 ME 07967 022 BL_EN 1 BL_EN 1 BL EN 0 BL EN 1 BL EN 0 RE ASSERTED Figure 37 Fade Override Function FOVR is High AMBIENT LIGHT SENSING The ADP8860 integrates two ambient light sensing comparators One of the ambient light sensing comparator pins CMP IN is always available The second pin D6 CMP IN2 can be activated rather than connecting an LED to D6 Activating the CMP IN2 function of the pin is accomplished through Bit CMP2_SEL in Register CFGR Therefore when Bit CMP2 SEL is set to 0 Pin D6 CMP IN is programmed as a current sink When Bit CMP2 SEL is set to 1 Pin D6 CMP IN2 becomes the input for a second phototransistor ADP8860 These comparators have two programmable trip points L2 and L3 that select among three of the backlight operation modes daylight office and dark based on the ambient lighting conditions The L3 comparator controls the dark to office mode transition The L
50. lue the ISC turns off for the off time per the following listed times and then turns on according to the SCON setting 00 off time disabled 01 0 6 sec 10 1 2 sec 11 1 8 sec independent sink remains on continuously when SCx EN 1 and SCx OFF is 00 disabled To enable multiple independent sinks set the appropriate SCx EN bits To create equivalent blinking and fading sequences enable all independent sinks in one write cycle to cause a preprogrammed sequence to start simultaneously Rev 0 Page 38 of 52 ADP8860 Independent Sink Current Time ISCT2 Register 0x12 Table 45 ISCT2 Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O SCAOFF 5 SC2OFF SC1OFF Table 46 Bit Descriptions for the ISCT2 Register Designation Bit Description SC4OFF 7 6 SC4 off time When the SC off time is disabled the ISC remains on while enabled When the SC off time is set to any other value then the ISC turns off for the off time per the following listed times and then turns on according to the SCON setting 00 off time disabled 01 0 6 sec 10 1 2 sec 11 1 8 sec 5 5 4 SC3 off time When the SC off time is disabled the ISC remains on while enabled When the SC off time is set to any other value then the ISC turns off for the off time per the following listed times and then turns on according
51. mage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Absolute maximum ratings apply individually only not in combination Unless otherwise specified all voltages are referenced to GND MAXIMUM TEMPERATURE RANGES The maximum operating junction temperature supersedes the maximum operating ambient temperature Therefore in situations where the ADP8860 is exposed to poor thermal resistance and a high power dissipation Pp the maximum ambient temperature may need to be derated In these cases the ambient temperature maximum can be calculated with the following equation Oya X 1 N A means not applicable ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 6 of 52 ADP8860 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 18 CMP_IN 17 D6 CMP IN2 aa Ne
52. nd SC7_EN 0 SCD7 6 0 For Sink Current 0 use the following DAC code schedule see Table 28 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 709 0 017 1111111 30 30 For Sink Current 1 use the following DAC code schedule see Table 51 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 472 0 004 0000010 0 945 0 014 0000011 01 417 0 034 1111111 60 60 Table 51 Linear and Square Law Currents for LED7 SCR 1 DAC Code Linear Law mA Square Law mA DAC Code Linear Law mA Square Law mA 0x00 0 000 0 0x14 9 45 1 488 0x01 0 472 0 004 0x15 9 92 1 64 0x02 0 945 0 014 0x16 10 39 1 8 0x03 1 42 0 034 0x17 10 87 1 968 0x04 1 89 0 06 0x18 11 34 2 142 0x05 2 36 0 094 0x19 11 81 2 326 0x06 2 83 0 134 Ox1A 12 28 2 514 0x07 3 31 0 182 Ox1B 12 76 2 712 0x08 3 78 0 238 0x1C 13 23 2 916 0x09 4 25 0 302 0x1D 13 70 3 128 Ox0A 4 72 0 372 Ox1E 14 17 3 348 OxOB 5 20 0 45 Ox1F 14 65 3 574 0x0C 5 67 0 536 0x20 15 12 3 81 0x0D 6 14 0 628 0x21 15 59 4 052 OxOE 6 61 0 73 0x22 16 06 4 3 OxOF 7 09 0 838 0x23 16 54 4 558 0x10 7 56 0 952 0x24 17 01 4 822 0x11 8 03 1 076 0x25 17 48 5 092 0x12 8 50 1 206 0x26 17 95 5 372 0x13 8 98 1 342 0x27 18 43 5 658 Rev 0 Page 41 of 52 ADP8860 DAC Code Linear Law mA Square Law mA DAC Code Linear Law mA Square Law mA 0x28
53. or L3 EN 1 the L3 comparator is enabled for the CMP IN comparator 0 the L3 comparator is disabled for the IN comparator 2 EN 0 Note that the L3 comparator has priority over L2 1 the L2 comparator is enabled for the CMP IN comparator 0 the L2 comparator is disabled for the IN comparator Second Comparator Configuration CCFG2 Register 0x 1C Table 66 CCFG2 Bit Map Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FILT2 FORCE_RD2 L3_OUT2 L2_OUT2 L3_EN2 L2_EN2 Table 67 Bit Descriptions for the CCFG2 Register Bit Name Bit No Description FILT2 7 5 Filter setting for the CMP_IN2 light sensor 000 80 ms 001 160 ms 010 320 ms 011 640 ms 100 1280 ms 101 2560 ms 110 5120 ms 1112 10 240 ms FORCE RD2 Force a read of the CMP_IN2 light sensor while independent sinks are running but the backlight is not Reset by chip after the conversion is complete and 12 OUT and L3 OUT are valid Ignored if the backlight is enabled L3 OUT2 This bit is the output of the L3 comparator for the second light sensor L2 OUT2 This bit is the output of the L2 comparator for the second light sensor L3 EN2 1 the L3 comparator is enabled for the CMP IN2 comparator 0 the L3 comparator is disabled for the IN2 comparator Rev 0 Page 45 of 52 ADP8860 Bit N
54. ould move to its dark L3 level Table 6 shows the relationship between backlight operation and the ambient light sensor comparator outputs The L3 OUT status bit has greater priority therefore the backlight operates at L3 dark even if L2 OUT is set Filter times of between 80 ms and 10 sec can be programmed for the comparators Register Ox1B and Register 0x1C before they change state Table 6 Comparator Output Truth Table CMP AUTOEN L3 OUT L2 OUT Backlight Operation 0 x x BLV can be manually set by the user 1 0 0 BLV 00 backlight operates at L1 daylight 1 0 1 BLV 01 backlight operates at L2 office 1 1 x BLV 10 backlight operates at L3 dark 1X is the don t care bit INDEPENDENT SINK CONTROL Each of the seven LEDs can be configured in Register 0x05 to operate as either part of the backlight or to operate as an indepen dent sink current ISC Each ISC can be enabled independently and has its own current level All ISCs share the same fade in rates fade out rates and fade law The ISCs have additional timers to facilitate blinking functions A shared on timer SCON used in conjunction with the off timers of each ISC SCIOFE SC2OFF SC3OFF SCAOFE SC5OFF SC6OFF and SC7OFF allow the LED current sinks to be configured in various blinking modes The on timer can be set to four different settings 0 2 sec 0 6 sec 0 8 sec and 1 2 sec The off timers have four differ
55. owing times listed are for a full scale fade out 30 mA to 0 mA Fades between closer current values reduce the fade time See the Automated Fade In and Fade Out section for more information 0000 disabled 0001 0 30 sec 0010 0 60 sec 0011 0 90 sec 0100 1 2 sec 0101 1 5 sec 0110 1 8 sec 0111 2 1 sec 1000 2 4 sec 1001 2 7 sec 1010 3 0 sec 1011 3 5 sec 1100 4 0 sec 1101 4 5 sec 1110 5 0 sec 1111 5 5 sec SCFI 3 0 Sink current fade in rate The following times listed are for a full scale fade in 0 mA to 30 mA Fades between closer current values reduce the fade time See the Automated Fade In and Fade Out section for more information 0000 disabled 0001 0 30 sec 0010 0 60 sec 0011 0 90 sec 0100 1 2 sec 0101 1 5 sec 0110 1 8 sec 0111 2 1 sec 1000 2 4 sec 1001 2 7 sec 1010 3 0 sec 1011 3 5 sec 1100 4 0 sec 1101 4 5 sec 1110 5 0 sec 1111 5 5 sec Rev 0 Page 40 of 52 Sink Current Register LED7 ISC7 Register 0x14 Table 49 ISC7 Bit Map ADP8860 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O SCR SCD7 Table 50 Bit Descriptions for the ISC7 Register Bit Name Bit No Description SCR 7 1 Sink Current 1 0 Sink Current 0 For the lowest input current consumption and optimal efficiency set SCR to 0 when D7 is set to ISC in Register 0x05 a
56. p restart attempts and gain transitions PHOTOSENSOR OPTIONAL PHOTOSENSOR CONVERSION SOFT START CHARGE PUMP LOGIC VOUT C1 1 CHARGE PUMP 1x 1 5 2x C2 1 07967 011 Figure 26 Detailed Block Diagram Rev 0 Page 12 of 52 POWER STAGE Because typical white LEDs require up to 4 V to drive them some form of boosting is required over the typical variation in battery voltage The ADP8860 accomplishes this with a high efficiency charge pump capable of producing a maximum Iour of 240 mA over the entire input voltage range 2 5 V to 5 5 V Charge pumps use the basic principle that a capacitor stores charge based on the voltage applied to it as shown in the following equation Q CxV 1 By charging the capacitors in different configurations the charge and therefore the gain can be optimized to deliver the voltage required to power the LEDs Because a fixed charging and discharging combination must be used only certain multiples of gain are available The ADP8860 is capable of automatically optimizing the gain G from 1x 1 5x and 2x These gains are accomplished with two capacitors labeled C1 and C2 in Figure 26 and an internal switching network In G 1x mode the switches are configured to pass VIN directly to VOUT In this mode several switches are connected in parallel to minimize the resistive drop from input to output In G 1 5x and 2x modes the switches
57. r has not triggered CMP INT 0 1 indicates that the main ALS comparator IN has changed state 0 the main sensor comparator has not triggered Interrupt bits are cleared by writing a 1 to the flag writing a 0 or reading the flag has no effect Interrupt Enable INTR EN Register 0x03 Table 14 INTR EN Bit Map Bit7 Bit 6 Bit 5 Bit4 Bit3 Bit2 Bit 1 Bit O Reserved SHORT_IEN TSD_IEN OVP_IEN CMP2_IEN CMP_IEN Table 15 Bit Descriptions for the INTR_EN Register Bit Name Bit No Description N A 7 5 Reserved SHORT IEN 4 Short circuit interrupt is enabled When the SHORT INT status bit is set after an error condition an interrupt is raised to the host if the SHORT IEN flag is enabled 1 the short circuit interrupt is enabled 0 the short circuit interrupt is disabled the SHORT INT flag continues to assert TSD IEN 3 Thermal shutdown interrupt is enabled When the TSD_INT status bit is set after an error condition an interrupt is raised to the host if the TSD flag is enabled 1 the thermal shutdown interrupt is enabled 0 the thermal shutdown interrupt is disabled the TSD INT flag continues to assert OVP_IEN 2 Overvoltage interrupt enabled When the OVP_INT status bit is set after an error condition an interrupt is raised to the host if the OVP_IEN flag is enabled 1 the overvoltage interrupt is enabled 0 the overvoltage interrupt is disabled the INT flag continue
58. rent OxOE BLDM3 Backlight Brightness Level 3 dark dim current OxOF ISCFR Independent sink current fade control register 0x10 ISCC Independent sink current control register 0x11 ISCT1 Independent Sink Current Timer Register LED 7 5 0x12 ISCT2 Independent Sink Current Timer Register LED 4 1 0x13 ISCF Independent sink current fade register 0x14 ISC7 Independent Sink Current LED7 0x15 ISC6 Independent Sink Current LED6 0x16 ISC5 Independent Sink Current LED5 0x17 ISC4 Independent Sink Current LED4 0x18 ISC3 Independent Sink Current LED3 0x19 ISC2 Independent Sink Current LED2 Ox1A ISC1 Independent Sink Current LED1 Ox1B CCFG Comparator configuration Ox1C CCFG2 Second comparator configuration 0x1D L2_TRP L2 comparator reference Ox1E L2_HYS L2 hysteresis Ox1F L3_TRP L3 comparator reference Rev 0 Page 26 of 52 ADP8860 Address Register Name Description 0x20 L3_HYS L3 hysteresis 0x21 PH1LEVL First phototransistor ambient light level low byte register 0x22 PH1LEVH First phototransistor ambient light level high byte register 0x23 PH2LEVL Second phototransistor ambient light level low byte register 0x24 PH2LEVH Second phototransistor ambient light level high byte register Table 8 Register Map Addr Reg Name Bit 7 Bit 6
59. rned off SC1_EN 0 This enable acts upon the LED1 1 SC1 is turned on 0 SC1 is turned off Independent Sink Current Time ISCT1 Register 0x11 Table 43 ISCT1 Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O SCON SC7OFF SC6OFF SCSOFF Table 44 Bit Descriptions for the ISCT1 Register Bit Name Bit No Description 2 SCON 7 6 SC on time If the SCxOFF time is not disabled then when the independent current sink is enabled Register 0x10 it remains on for the on time selected per the following list and then turns off 00 0 2 sec 01 0 6 sec 10 0 8 sec 11 1 2 sec SC7OFF 5 4 SC7 off time When the SC off time is disabled the ISC remains on while enabled When the SC off time is set to any other value the ISC turns off for the off time per the following listed times and then turns on according to the SCON setting 00 off time disabled 01 0 6 sec 10 1 2 sec 11 1 8 sec SC6OFF 3 2 SC6 off time When the SC off time is disabled the ISC remains on while enabled When the SC off time is set to any other value the ISC turns off for the off time per the following listed times and then turns on according to the SCON setting 00 off time disabled 01 0 6 sec 10 1 2 sec 11 1 8 sec SC5OFF 1 0 SC5 off time When the SC off time is disabled the ISC remains on while enabled When the SC off time is set to any other va
60. s All of the ISC enable bits must be cleared if any of the SC EN bits are set in Register 0x10 this bit has no effect CMP AUTOEN 1 1 backlight automatically responds to the comparator outputs 12 OUT and L3 OUT L2 EN and or L3 EN must be set for this to function BLV values in Register Ox04 are overridden 0 backlight does not autorespond to comparator level changes The user can manually select backlight operating levels using Bit BLV in Register 0x04 BL EN 0 1 backlight is enabled nSTBY must also be asserted 0 backlight is disabled Rev 0 Page 28 of 52 ADP8860 Mode Control Register 2 MDCR2 Register 0x02 Table 12 MDCR2 Bit Map Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved SHORT INT TSD INT OVP INT CMP2 INT INT Table 13 Bit Descriptions for the MDCR2 Register Bit Name Bit No Description N A 7 5 Reserved SHORT INT 4 Short circuit error 1 a short circuit or overload condition on VOUT was detected 0 no short circuit or overload condition has been detected TSD INT 3 Thermal shutdown 1 the device temperature has exceeded 150 C typical 0 2 no overtemperature condition has been detected OVP INT 2 Overvoltage interrupt 1 VOUT has exceeded 0 VOUT has not exceeded CMP2 INT 1 1 indicates that the second ALS comparator CMP_IN2 has changed state 0 the second sensor comparato
61. s to assert CMP2 1 When the CMP2 INT status bit is set after an enabled comparator trips an interrupt is raised if the CMP2_IEN flag is enabled 1 the second phototransistor comparator interrupt is enabled 0 the second phototransistor comparator interrupt is disabled the CMP2 INT flag continues to assert Rev 0 Page 29 of 52 ADP8860 Bit Name Bit No Description CMP_IEN When the CMP_INT status bit is set after an enabled comparator trips an interrupt is raised if the CMP_IEN flag is enabled 1 the main comparator interrupt is enabled 0 the main comparator interrupt is disabled the INT flag continues to assert BACKLIGHT REGISTER DESCRIPTIONS Configuration Register CFGR Register 0x04 Table 16 CFGR Bit Map Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Reserved SEL_AB CMP2_SEL BLV Law FOVR Table 17 Bit Descriptions for the CFGR Register Bit Name No Description N A 7 Reserved SEL AB 6 1 selects the second phototransistor CMP_IN2 to control the backlight 0 selects the main phototransistor CMP IN to control the backlight CMP2 SEL 5 1 the second phototransistor is enabled the current sink on D6 is disabled 0 the second phototransistor is disabled BLV 4 3 Brightness level This field indicates the brightness level at which the device is operating The softwar
62. ss is 0101010x 0 during write x 1 during read Therefore the default write address is 0x54 and the read address is 0x55 The following tables provide register and bit descriptions The reset value for all bits in the bit map tables is all Os except in Table 9 see Table 9 for its unique reset value Wherever the Note the following general behavior of registers acronym N A appears in the tables it means not applicable e All registers are set to their default values during reset or after a UVLO event 0 WRITE 1 READ ST SP BO GODODOZOERESSESSEREDOETSEEREROE CHIP ADDRESS 5 REG ADDRESS 5 DATA 5 07967 030 Figure 46 Command Sequence Table 7 Register Set Definitions Address Register Name Description 0x00 MFDVID Manufacturer and device ID 0x01 MDCR Device mode and status 0x02 MDCR2 Device mode and Status Register 2 0x03 INTR EN Interrupts enable 0x04 CFGR Configuration register 0x05 BLSEN Sink enable backlight or independent 0x06 BLOFF Backlight off timeout 0x07 BLDIM Backlight dim timeout 0x08 BLFR Backlight fade in and out rates 0x09 BLMX1 Backlight Brightness Level 1 daylight maximum current BLDM1 Backlight Brightness Level 1 daylight dim current OxOB BLMX2 Backlight Brightness Level 2 office maximum current OxOC BLDM2 Backlight Brightness Level 2 office dim current OxOD BLMX3 Backlight Brightness Level 3 dark maximum cur
63. status signal is set L3 CMPR Rev 0 Page 19 of 52 ADP8860 contains programmable hysteresis meaning that the photo sensor output must rise above L3_TRP L3_HYS before L3_OUT clears L3_CMPR is enabled via the L3_EN bit The L3_TRP and L3_HYS values of L3_CMPR can be set between 0 pA and 137 7 uA typical in steps of 0 54 uA typical 1 L2_TRP l L2_HYS 1 L3 HYS 1 10 100 1000 ADC RANGE pA 07967 025 Figure 40 Comparator Ranges Note that the full scale value of the L2 TRP and L2 HYS registers is 250 decimal Therefore if the value of L2 L2 HYS exceeds 250 the comparator output is unable to deassert For example if L2 is set at 204 80 of the full scale value or approximately 0 80 x 1080 uA 864 uA then L2 HYS must be set at less than 46 250 204 46 If it is not then the L2 HYS L2_TRP exceeds 250 and the L2 CMPR comparator is never allowed to go low When both phototransistors are enabled and programmed in automatic mode through Bit L3 EN and Bit L2 EN in Register Ox1B and Register Ox1C the user application needs to determine which of the comparator outputs to use selecting Bit SEL AB in Register 0x04 for automatic light sensing transitions For example the user s software may select the comparator of the phototransistor exposed to higher light intensity to control the transition between the programmed backlight intensity levels The L2
64. t nSTBY 0 1 5 uA During Fault Time to Validate a Fault trAULT 2 us INTERFACE Vono Voltage Operating Range Vopio 5 5 V Logic Low Input Vi Vin 3 6V 06 V Logic High Input Vin 3 6V 1 30 V 12 TIMING SPECIFICATIONS Guaranteed by design Delay from Reset Deassertion to tneseT 20 Hs access SCL Clock Frequency 400 2 SCL High Time 0 6 Us SCL Low Time tiow 1 3 us Setup Time Data tsu DAT 100 ns Repeated Start tsu 5 0 6 Hs Stop Condition tsu sro 0 6 us Hold Time Data tup DAT 0 0 9 us Start Repeated Start tup STA 0 6 us Bus Free Time Stop and Start tBuF 1 3 us Conditions Rise Time SCL and SDA tr 20 0 1 300 ns Fall Time SCL and SDA tr 20 0 1 300 ns Pulse Width of Suppressed Spike tsp 0 50 ns Capacitive Load Per Bus Line 400 Current source matching is calculated by dividing the difference between the maximum and minimum current from the sum of the maximum and minimum Vi is a function of the input voltage See Figure 16 in the Typical Performance Characteristics section for typical values over operating ranges 3 Vu is a function of the input voltage See Figure 16 in the Typical Performance Characteristics section for typical values over operating ranges Rev 0 Page 4 of 52 ADP8860 PC TIMING DIAGRAM 1 SDA SCL tup DAT S S START CONDITION Sr REPEATED START CONDITION P STOP CONDITION 07967 002
65. ter ISCFR Register OxOF Table 39 ISCFR Bit Map Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Reserved SC LAW Table 40 Bit Descriptions for the ISCFR Bit Name Bit No Description N A 7 2 Reserved SC LAW 1 0 Independent sink current fade transfer law 00 linear law DAC linear time steps 01 square law DAC linear time steps 10 2 square law DAC nonlinear time steps Cubic 10 11 2 square law DAC nonlinear time steps Cubic 11 Independent Sink Current Control ISCC Register 0x10 Table 41 ISCC Bit Map Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved SC7 EN SC6 EN SC5 EN 5 4 EN SC3 EN SC2 EN SC1 EN Table 42 Bit Descriptions for the ISCC Register Bit Name Bit No Description N A 7 Reserved SC7 EN 6 This enable acts upon the LED7 1 SC7 is turned on 0 SC7 is turned off SC6 EN 5 This enable acts upon the LED6 1 SC6 is turned on 0 SC6 is turned off SC5_EN 4 This enable acts upon the LEDS 1 SC5 is turned on 0 SC5 is turned off Rev 0 Page 37 of 52 ADP8860 Bit Name Bit No Description SCA EN 3 This enable acts upon the LED4 1 SC4 is turned on 0 SCA is turned off SC3 EN 2 This enable acts upon the LED3 1 SC3 is turned on 0 SC3 is turned off SC2 EN 1 This enable acts upon the LED2 1 SC2 is turned on 0 5 2 is tu
66. try except for the receivers Current consumption is reduced to less than 1 uA This mode is entered when nSTBY is set to 0 or when the nRST pin is held low for more than 100 us maximum When standby is exited a soft start sequence is performed Shutdown Mode Shutdown mode disables all circuitry including the IC receivers Shutdown occurs when Vw is below the undervoltage thresholds When Vw rises above 2 05 V typical all registers reset and the part is placed into standby mode Reset Mode In reset mode all registers are set to their default values and the part is placed into standby There are two ways to reset the part power on reset POR and the nRST pin POR is activated any time that the part exits shutdown mode After a POR sequence is complete the part automatically enters standby mode After startup the part can be reset by pulling the nRST pin low As long as the nRST pin is low the part is held in a standby state but no commands are acknowledged all registers kept at their default values After releasing the nRST pin all registers remain at their default values and the part remains in standby however the part does accept commands The nRST pin has a 50 us typical noise filter to prevent inad vertent activation of the reset function The nRST pin must be held low for this entire time to activate reset The operating modes function according to the timing di
67. um when the backlight is turned on The times listed for BL Fl are for a full scale fade 0 mA to 30 mA Fades between closer current values reduce the fade time See the Automated Fade In and Fade Out section for more information 0000 0 1 sec fade in disabled 0001 0 3 sec 0010 0 6 sec 0011 0 9 sec 1111 5 5 sec 1 When fade in and fade out are disabled the backlight does not instantaneously fade but instead fades rapidly within about 100 ms Rev 0 Page 32 of 52 ADP8860 Backlight Level 1 Daylight Maximum Current Register BLMX1 Register 0x09 Table 26 BLMX1 Bit Map Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved BL1_MC Table 27 Bit Descriptions for the BLMX1 Register Bit Name Bit No Description N A 7 Reserved BL1_MC 6 0 Backlight maximum Level 1 daylight current The backlight maximum current can be set according to the linear or square law function as follows see Table 28 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 708 0 017 1111111 30 30 Table 28 Linear and Square Law Currents Per DAC Code DAC Code Linear Law mA Square Law mA DAC Code Linear Law mA Square Law mA 0x00 0 0 000 Ox1F 7 323 1 787 0x01 0 236 0 002 0x20 7 559 1 905 0x02 0 472 0 007 0x21 7 795 2 026 0x03 0 709 0 017 0x22 8 031 2 150 0x04 0 9
68. ved SCD4 Table 57 Bit Descriptions for the ISC4 Register Bit Name Bit No Description N A 7 Reserved SCD4 6 0 Sink current Use the following DAC code schedule see Table 28 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 709 0 017 1111111 30 30 Rev 0 Page 43 of 52 ADP8860 Sink Current Register LED3 ISC3 Register 0x18 Table 58 ISC3 Bit Map Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Reserved SCD3 Table 59 Bit Descriptions for the ISC3 Register Bit Name Bit No Description N A 7 Reserved SCD3 6 0 Sink current Use the following DAC code schedule see Table 28 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 472 0 007 0000011 0 709 0 017 1111111 30 30 Sink Current Register LED2 ISC2 Register 0x19 Table 60 ISC2 Bit Map Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved SCD2 Table 61 Bit Descriptions for the ISC2 Register Bit Name Bit No Description N A 7 Reserved SCD2 6 0 Sink current Use the following DAC code schedule see Table 28 for a complete list of values DAC Linear Law mA Square Law mA 0000000 0 0 0000001 0 236 0 002 0000010 0 47

ANALOG DEVICES ADP8860 handbook

Contents

Download Pdf Manuals

Related Search

Related Contents