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ANALOG DEVICES AD5263 handbook

1. 128 160 CODE Decimal Figure 10 DNL vs Code Vpp 5 V 7 40 20 0 20 40 60 80 100 120 TEMPERATURE C Figure 11 Full Scale Error vs Temperature 03142 009 Rev A Page 9 of 28 ZSE LSB SHUTDOWN CURRENT pA Vpp Vss 4 5 0V Vpp Vss 5V Vpp Vss 16 5 0V Ipp lss SUPPLY CURRENT uA 10 0 20 0 20 40 60 80 100 TEMPERATURE C Figure 12 Zero Scale Error vs Temperature 120 03142 010 10 VLocic 5V Vin 5V ViL OV 1 Iss Vpp Vss 5V 0 1 Ipp Vpp Vss 15 0V 01 lbo Vpp Vss 5V 40 0 40 80 120 TEMPERATURE C Figure 13 Supply Current vs Temperature 0 1 0 01 0 001 TEMPERATURE C Figure 14 Shutdown Current vs Temperature 03142 012 03142 011 ILoGic HA WIPER RESISTANCE 0 RHEOSTAT MODE TEMPCO ppmf C 40 0 40 80 120 TEMPERATURE C Figure 15 losic vs Temperature V di Vpp Vss 5 0V Ron Vpp Vss 5V Ron Vpp Vss 15 0V Vaias V Figure 16 Wiper On Resistance vs Bias Voltage ES CODE Decimal Figure 17 Rheostat Mode Tempco ARws AT vs Code POTENTIOMETER MODE TEMPCO ppmf
2. tette 28 Ordering Guide 2 ete et 28 Rev A Page 2 of 28 ELECTRICAL CHARACTERISTICS 20 KO 50 kQ 200 kO VERSIONS Vpp 5 V Vss 5 V Vr 5 V Va Vpp Vp 0 V 40 C lt Ta lt 125 C unless otherwise noted Table 1 Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs Resistor Differential NL R DNL Rwe Va NC 1 1 4 1 LSB Resistor Nonlinearity2 R INL Rwe Va NC 1 1 2 1 LSB Nominal Resistor Tolerance ARAB Ta 25 C 30 30 Resistance Mode Temperature ARwe AT 30 ppm C Coefficient ARwa AT 30 ppm C Wiper Resistance Rw lw 1 V Ras 60 150 Q DC CHARACTERISTICS POTENTIOMETER Specifications apply to all VRs DIVIDER MODE Resolution N 8 Bits Differential Nonlinearity DNL 1 1 4 1 LSB Integral Nonlinearity INL 1 1 2 1 LSB Voltage Divider Temperature Coefficient AVw AT Code 0x80 5 ppm C Full Scale Error Vwese Code OxFF 2 1 0 LSB Zero Scale Error Vwzse Code 0x00 0 1 2 LSB RESISTOR TERMINALS Voltage Range VABW Vss Vop V Capacitance Ax Bx CAB f 1 MHz measured to GND 25 pF ode Capacitamce 1 z measure 5 pF ode 30x80 WAN A Va CO nA Shutdown Current Ishon 0 02 5 uA DIGITAL INPUTS Input Logic High Vin 2 4 V Input Logic Low Vit 0 8 V Input Logic High SDA and SCL Vin Vss OV 0 7 xV V 0 V Input Logic Low SDA and SCL Vit Vss 0 V 0 5 03xM V Input Current l
3. Nanao _ BT BBY ps Y p Y ps oz 91 Xs 7 ACK BY NO ACK AD5263 BY MASTER 03142 043 MASTER Figure 44 Reading Data from a Previously Selected RDAC Register in Write Mode Rev A Page 16 of 28 03142 041 03142 042 OPERATION The AD5263 is a quad channel 256 position digitally controlled variable resistor VR device To program the VR settings refer to the SPI Compatible Digital Interface DIS 0 section and the PC Compatible Digital Interface DIS 1 section The part has an internal power on preset that places the wiper at midscale during power on simplifying the fault condition recovery at power up In addition the shutdown SHDN pin of AD5263 places the RDAC in an almost zero power consumption state where Terminal A is open circuited and the wiper W is connected to Terminal B resulting in only leakage current consumption in the VR structure During shutdown the VR latch settings are maintained or new settings can be programmed When the part is returned from shutdown the corresponding VR setting is applied to the RDAC 03142 044 Figure 45 AD5263 Equivalent RDAC Circuit PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminal A and Terminal B is available in 20 kO 50 kO and 200 kO The final two or three digits of the part number determine the nominal resistance value for example 20 kO 20 50 kO 50 200 kQ 200 The nominal res
4. Page 18 of 28 of data is required The first 10 bits complying with the format 2 In write mode the second byte is the instruction byte The shown in the Serial Data Word Format section and bit map go first bit MSB of the instruction byte is a don t care The to U2 and the second 10 bits with the same format go to U1 following two bits labeled A1 and A0 are the RDAC CS should be kept low until all 20 bits are clocked into their subaddress select bits respective serial registers After this CS is pulled high to The fourth MSB RS is the midscale reset A logic high on complete the operation and load the RDAC latch Note that data this bit moves the wiper of the selected channel to the appears on SDO on the negative edge of the clock thus making center tap where RWA RWB This feature effectively it available to the input of the daisy chained device on the rising writes over the contents of the register so that when taken edge of the next clock out of reset mode the RDAC remains at midscale L The fifth MSB SD is the shutdown bit A logic high causes the selected channel to open circuit at Terminal A while shorting the wiper to Terminal B This operation OS o ax O yields almost 0 O in rheostat mode or 0 V in potentiometer mode This SD bit serves the same function as the SHDN pin except that the SHDN pin reacts to active low In AD5263 U2 03142 046 addition the SHDN pin affects all channels as opposed to the SD
5. as a potentiometer divider the 3 dB bandwidth of the AD5263 20 kQ resistor measures 300 kHz at half scale Figure 22 CA A 0 25E 12 uy RWA A W 1 D 256 RDAC 60 provides the large signal BODE plot characteristics of the CW W 0 S5E 12 three available resistor versions 20 kO 50 kO and 200 kO A RWB W B D 256 RDAC 60 parasitic simulation model is shown in Figure 56 The following CB B 2 pan LA code provides a macro model net list for the 20 kO RDAC ENDS DPOT RDAC 20kQ A B N a o a 8 o s nal N e a 03142 069 Figure 56 RDAC Circuit Simulation Model for RDAC 20 kQ ww BDI C com ALI Rev A Page 22 of 28 APPLICATIONS BIPOLAR DC OR AC OPERATION FROM DUAL SUPPLIES The AD5263 can be operated from dual supplies enabling control of ground referenced ac signals or bipolar operation The ac signal as high as Vpp Vss can be applied directly across Terminal A to Terminal B with the output taken from Terminal W 5 0V X5V p p 03142 056 5 0V Figure 57 Bipolar Operation from Dual Supplies GAIN CONTROL COMPENSATION A digital potentiometer is commonly used in gain control such as the noninverting gain amplifier shown in Figure 58 C2 4 7pl 4 R2 200kO 03142 057 Figure 58 Typical Noninverting Gain Amplifier Notice the RDAC B terminal parasitic capacitance is connected to the op amp noninverting node It introduces a zero for the 1 B term with 20 dB dec whereas a ty
6. Vin OVor 5V 1 uA Input Capacitance Ci 5 pF DIGITAL OUTPUTS SDA Vo Isink 3 mA 0 4 V Vo Isink 6 mA 0 6 V 01 02 Von Isource 40 pA 4 V 01 02 VoL Isink 1 6 mA 0 4 V SDO Vou Ri 2 2 kQ to Voo Voo 0 1 V SDO Vo Isink 3 mA 0 4 V Three State Leakage Current loz Vin OVor 5V 1 yA Output Capacitance Coz 3 8 pF Rev A Page 3 of 28 Parameter Symbol Conditions Min Typ Max Unit POWER SUPPLIES Logic Supply V 2 7 5 5 V Power Single Supply Range VDD RANGE Vss 0V V 16 5 V Power Dual Supply Range VDD SS RANGE 4 5 7 5 V Logic Supply Current I V 5V 25 60 pA Positive Supply Current lbo Viu 2 5 V or Vu 0V 1 HA Negative Supply Current Iss Vss 5 V 1 yA Power Dissipation Poiss Vu 5 V or Vii OV Voo 5 0 6 mW V Vs 5V Power Supply Sensitivity PSS AVpp 5 V 10 0 002 0 01 DYNAMIC CHARACTERISTICS Bandwidth 3 dB BW Ras 20 kQ 50 kQ 200 kO 300 150 35 kHz Total Harmonic Distortion THDw Va 1 V rms Vs OV f 1 kHz 0 05 Ras 20 kO Vw Settling Time ts Va 10V Vs OV 1 LSB error 2 Us band Resistor Noise Voltage eN ws Rws 10 kO f 1 kHz RS 0 9 nv 4Hz Typicals represent average readings at 25 C and Voo 5 V Vss 5 V Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions R DNL measures the relative step change from ideal bet
7. bit which affects only the channel being written to Figure 47 Daisy Chain Configuration It is important to note that the shutdown operation does not disturb the contents of the register When brought out l C COMPATIBLE 2 WIRE SERIAL BUS DIS 1 x of shutdown the previous setting is applied to the RDAC In the PC compatible mode the RDACs are connected to the bus as slave devices The next two bits are O2 and O1 They are extra programmable logic outputs that can be used to drive other Referring to the bit maps in the C Compatible Digital digital loads logic gates LED drivers analog switches etc Interface DIS 1 section the first b XS p in the PC Write slave addre i f a 7 bit S IW bit The five the fi the last byte in write mode is the data byte Data is transmitted over the serial bus in sequences of nine clock pulses eight data bits followed by an acknowledge bit The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL see Figure 43 ADO and ADI allow the user to place up to four of the PC compatible devices on one bus The 2 wire PC serial bus protocol operates as follows l The master initiates a data transfer by establishing a START condition which is when a high to low transition on the SDA line occurs while SCL is high see Figure 43 The following byte is the slave address byte which consists of the 7 bit slave address foll
8. db Bandwidth 100 1k 10k FREQUENCY Hz 100k Figure 23 PSRR vs Frequency 03142 021 Rev A Page 11 of 28 CODE 0x80 Vpp Vss 5 5V VglVa7 55V 50 0mV V M100ns A CH2 2 70V Figure 24 Digital Feedthrough A CH2 2 00V Figure 25 Midscale Glitch Code 0x80 to Ox7F 4 7 nF Capacitor Used from Wiper to Ground 5 00V CH2 5 00V M400ns A CH1_ 2 70V Figure 26 Large Signal Settling Time Code 0x00 to OxFF 03142 022 03142 023 03142 024 INL LSB 03142 025 IVpp Vssl V Figure 27 INL vs Supply Voltage ww BDI C com AD R INL LSB Rev A Page 12 of 28 IVpp Vssl V Figure 28 R INL vs Supply Voltage 03142 026 TEST CIRCUITS Figure 29 to Figure 39 define the test conditions used in the product specification table V Vpp 1LSB V 2N 03142 028 Figure 29 Test Circuit for Potentiometer Divider Nonlinearity Error INL DNL NO CONNECT O DUT g g V 3 8 8 DUT lw Vpp RNowiNAL Rw Vms1 Vus2l w CO Vus 03142 030 Figure 31 Test Circuit for Wiper Resistance V Vpp 10 PSRR dB 20 log A AVpp AVus AVpp PSS 03142 031 Figure 32 Test Circuit for Power Supply Sensitivity PSS PS
9. operation over temperature Unlike the rheostat mode the output voltage is dependent mainly on the ratio of the internal resistances Rwa and Rws and not their absolute values therefore the temperature drift reduces to 5 ppm C PIN SELECTABLE DIGITAL INTERFACE The AD5263 provides the flexibility of a selectable interface When the digital interface select DIS pin is tied low the SPI mode is engaged When the DIS pin is tied high to the Vi supply the PC mode is engaged SPI COMPATIBLE 3 WIRE SERIAL BUS DIS 0 The AD5263 contains a 3 wire SPI compatible digital interface SDI CS and CLK The 10 bit serial word must be loaded with address bits Al and AO followed by the data byte MSB first The format of the word is shown in the Serial Data Word Format section and bit map The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register Standard logic families work well If mechanical switches are used for product evaluation they should be debounced by a flip flop or other suitable means When CS is low the clock loads data into the serial register on each positive clock edge see Figure 40 Table 7 AD5263 Address Decode Table A1 AO Latch Loaded 0 0 RDAC 1 0 1 RDAC 2 1 0 RDAC 3 1 1 RDAC 4 The data setup and data hold times in the specification table determine the valid timing requirements The AD5263 uses a 10 bit serial i
10. the Wien network R R C C provides positive feedback while R1 and R2 provide negative feedback At the resonant frequency fo the overall phase shift is zero and the positive feedback causes the circuit to oscillate With R R C C and R2 R2A R2B Rnionr the oscillation frequency is 1 1 O or 14 0 RE fo mc a4 where R is equal to Rwa such that 256 D R R 15 256 48 MS At resonance setting R2 16 RI balances the bridge In practice R2 R1 should be set slightly greater than 2 to ensure that the oscillation can start On the other hand the alternating turn on of the diodes D1 and D2 ensures that R2 R1 is momentarily less than 2 thereby stabilizing the oscillation Once the frequency is set the oscillation amplitude can be tuned by R2B because 2 3o Ip XR2B Vp 17 Vo Ip and Vp are interdependent variables With proper selection of R2B an equilibrium is reached such that Vo converges R2B can be in series with a discrete resistor to increase the amplitude but the total resistance should not be so large that it saturates the output FREQUENCY LLL LLL ADJUSTMENT c R K Pvp 22nF 10kQ y R1 R1 R2B AD5263 D1 D2 1N4148 AMPLITUDE ADJUSTMENT 03142 065 Figure 66 Programmable Oscillator with Amplitude Control Rev A Page 26 of 28 RESISTANCE SCALING The AD5263 offers 20 kO 50 kO and 200 kO nominal resistances Users who
11. their ADO and ADI pins are different This allows each RDAC within each device to be written to or read from independently The master device output bus line drivers are open drain pull downs in a fully PC compatible interface 03142 048 Figure 49 Multiple AD5263 Devices on One PC Bus LEVEL SHIFT FOR NEGATIVE VOLTAGE OPERATION The digital potentiometer is popular in laser diode driver and certain telecommunication equipment level setting applications These applications are sometimes operated between ground and some negative supply voltage so that the systems can be biased at ground to avoid large bypass capacitors that may significantly impede the ac performance Like most digital potentiometers the AD5263 can be configured with a negative supply see Figure 50 AD5263 LEVEL SHIFTED 4 SDA LEVEL SHIFTED SCL 03142 050 Figure 50 Biased at Negative Voltage Rev A Page 20 of 28 Vi However the digital inputs must also be level shifted to allow u proper operation because the ground is referenced to the negative potential As a result Figure 51 shows one implement A tation with a couple of transistors and a few resistors When Vin is high Q1 is turned on and its emitter is clamped at one threshold above ground This threshold appears at the base of Q2 which causes Q2 to turn off In this state Vour approaches 5 V When Vm is low Q1 is turned off and the base of Q2 is Vss p
12. with a selectable digital interface This device performs the same electronic adjustment function as mechanical potentiometers or variable resistors with enhanced resolution solid state reliability and superior low temperature coefficient performance The AD5263 is available in a narrow body 24 lead TSSOP All parts are guaranteed to operate over the automotive temperature range of 40 C to 125 C Each channel of the AD5263 offers a completely programmable value of resistance between the A terminal and the wiper or between the B terminal and the wiper The fixed A to B terminal resistance of 20 kO 50 kO or 200 kQ has a nominal For single or dual channel applications refer to the temperature coefficient of 30 ppm C and a 1 channel to AD5260 AD5280 or AD5262 AD5282 data sheets channel matching tolerance Another key feature of this part is sq The terms digital potentiometer VR and RDAC are used interchangeably the ability to operate from 4 5 V to 15 V or at 5 V SP qe Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Anal
13. 0 MA CURRENT SOURCE A programmable 4 20 mA current source can be implemented with the circuit shown in Figure 63 The REF191 is a unique low supply headroom and high current handling precision reference that can deliver 20 mA at 2 048 V The load current is simply the voltage across Terminal B to Terminal W ofthe digital potentiometer divided by Rs Vaer x D Rs x2N 8 0 TO 2 048V V 2 048V TO V 03142 062 potentiometer setting supply the programmable resolution of the system is reduced For applications that demand higher current capabilities a few changes to the circuit in Figure 63 produce an adjustable current in the range of hundreds of mA First the voltage reference needs to be replaced with a high current low dropout regulator such as the ADP3333 and the op amp needs to be swapped with a high current dual supply model such as the AD8532 Depending on the desired range of current an appropriate value for Rs must be calculated Because of the high current flowing to the load the user must pay attention to the load impedance so as not to drive the op amp past the positive rail PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE For applications that require bidirectional current control or higher voltage compliance a Howland current pump can be a solution see Figure 64 If the resistors are matched the load current is R2A R2B RI x V 9 R2B W 0 L R2A 14 95kO 03142 0
14. 16 spo o1 Viocic 19 15 SHDN SDI SDA 11 14 RES AD1 y CLK SCL 2 a Cs Apo Figure 2 24 Lead TSSOP Table 4 Pin Function Descriptions Pin Name Description B1 A1 W1 O OO 40U Q N w 11 SDI SDA 12 CLK SCL 13 CS AD0 14 RES AD1 15 SHDN 16 SDO O1 17 NC O2 19 W4 20 A4 21 B4 22 w2 23 A2 24 B2 Resistor Terminal B1 Resistor Terminal A1 ADDR 00 Wiper Terminal W1 Resistor Terminal B3 Resistor Terminal A3 Wiper Terminal W3 ADDR 10 Positive Power Supply specified for 5 V to 15 V operation Ground Digital Interface Sel In addition logic Serial Clock Input Chip Select in SPI Mode Device Address Bit 0 in I C Mode RESET in SPI Mode Device Address Bit 1 in PC Mode Shutdown Shorts wiper to Terminal B opens Terminal A Tie to 5 V supply if not used Do not tie to Vo if Voo gt 5 V Serial Data Output in SPI Mode Open drain transistor requires pull up resistor Digital Output O1 in PC Mode Can be used to drive external logic No Connection in SPI Mode Digital Output O2 in PC Mode Can be used to drive external logic Negative Power Supply Specified for operation from 0 V to 5 V Wiper Terminal W4 ADDR 11 Resistor Terminal A4 Resistor Terminal B4 Wiper Terminal W2 ADDR 01 Resistor Terminal A2 Resistor Terminal B2 Rev A Page 7 of 28 TYPICAL PERFORMANCE CHARACTERISTICS Ras 20 kO
15. 196 Device to device matching is process lot dependent and it is possible to have 30 variation Because the resistance element is processed in thin film technology the change in Ras with temperature has a very low temperature coefficient of 30 ppm C PROGRAMMING THE POTENTIOMETER DIVIDER VOLTAGE OUTPUT OPERATION The digital potentiometer easily generates a voltage divider at wiper to B and wiper to A proportional to the input voltage from Terminal A and Terminal B Unlike the polarity from Von to Vss which must be positive the voltage across A to B W to A and W to B can be at either polarity if Vss is powered by a negative supply If the effect of the wiper resistance for approximation is ignored connecting the A terminal to 5 V and the B terminal to ground produces an output voltage from the wiper to B starting at 0 V up to 1 LSB below 5 V Each LSB step of voltage is equal to the voltage applied across Terminal A to Terminal B divided by the 256 positions of the potentiometer divider Because the AD5263 can be powered by dual supplies the general equation defining the output voltage Vw with respect to ground for any valid input voltages applied to Terminal A and Terminal B is Vw D For a more accurate calculation which includes the effect of wiper resistance Vw can be found as Ryp D Ry D wal Ral y 256 256 Vw D 4 Operation of the digital potentiometer in the divider mode results in a more accurate
16. 63 Figure 64 Programmable Bidirectional Current Source R2B in theory can be made as small as needed to achieve the current needed within th ent driving capability Int either direction andithe vo celap It can be shown that th outptt i _ RI x R2B RI amp R2A RIxR2 RI R2A R2B 10 This output impedance can be infinite if resistors R1 and R2 match precisely with R1 and R2A R2B respectively On the other hand it can be negative if the resistors are not matched Asa result C1 in the range of 1 pF to 10 pF is needed to prevent oscillation Rev A Page 25 of 28 PROGRAMMABLE LOW PASS FILTER In analog to digital conversion applications it is common to include an antialiasing filter to band limit the sampling signal Dual channel digital potentiometers can be used to construct a second order Sallen Key low pass filter see Figure 65 The design equations are 2 Vo _ Qo 11 Viu T 00 1 QQ 12 O NRIXxR2xCIxC2 me 1 1 e RIxCI R2xC2 Q 13 Users can first select some convenient values for the capacitors To achieve maximally flat bandwidth where Q 0 707 let C1 be twice the size of C2 and let R1 R2 Asa result the user can adjust R1 and R2 to the same settings to achieve the desired bandwidth C1 03142 064 ADJUSTED TO SAME SETTING Figure 65 Sallen Key Low Pass Filter PROGRAMMABLE OSCILLATOR In a classic Wien bridge oscillator Figure 66
17. ANALOQ Quad 15 V 256 Position Digital DEVICES Potentiometer with Pin Selectable SPI I2C FEATURES FUNCTIONAL BLOCK DIAGRAM 256 position 4 channel A1 W B1 A2 W B2 A3 W B A4 W B4 End to end resistance 20 kO 50 kO 200 kO Vpp O Pin selectable SPI or I C compatible interface Vss O Power on preset to midscale SHDN Two package address decode pins ADO and AD1 RES AD1 O Rheostat mode temperature coefficient 30 ppm C Voltage divider temperature coefficient 5 ppm C V O AD5263 Wide operating temperature range 40 C to 125 C CLKISCL Q SDI SDA SERIAL INPUT 5V to 15V single supply 5 V dual supply CS ADO SPINE REGISTER SELECT GND LOGIC APPLICATIONS O Mechanical potentiometer replacement DIS NC O2 SDO O1 8 Optical network adjustment Figure 1 Instrumentation gain offset adjustment Stereo channel audio level control Automotive electronics adjustment Programmable power supply Programmable filters delays time constants Line impedance matching Low resolutio r plac Base station po Sensor calibration GENERAL DESCRIPTION Wiper position programming presets to midscale upon power on Once powered the VR wiper position is programmed by either the 3 wire SPI or 2 wire PC compatible interface In the PC mode additional programmable logic outputs enable users to drive digital loads logic gates and analog switches in their systems The AD5263 is the industry5 first quad channel 256 position digital potentiometer
18. C 03142 013 GAIN dB 03142 014 GAIN dB 03142 015 Rev A Page 10 of 28 32 64 96 128 160 CODE Decimal 192 224 25 Figure 18 Potentiometer Mode Tempco ARws AT vs Code 0 0x80 6 0x40 12 0x20 18 0x10 24 0x08 30 0x04 k 0x02 42 0x0 4 TA 25 C Va 50mV rms 5V a ss 1k 1 100k 1M FREQUENCY Hz Figure 19 Gain vs Frequency vs Code Ras 20 kQ 0 0x80 6 0x40 12 0x20 18 0x10 24 0x08 30 0x04 36 0x02 Ec 0x01 48 TA 25 C 54 Va 50mV rms Vpp Vss 5V 60 1k 10k 100k 1M FREQUENCY Hz Figure 20 Gain vs Frequency vs Code Ras 50 kQ 03142 017 03142 016 eo 03142 018 GAIN dB PSRR dB GAIN dB 0 0x80 6 0x40 12 E 0x20 ET 0x10 xa 0x08 X 0x04 4 0x02 er 0x01 Ta 25 C 2 Va 50mV rmsT VpplVss 5V z 1k 10k 100k FREQUENCY Hz Figure 21 Gain vs Frequency vs Code Ras 200 kQ R 20kO 300kHz 6 12 18 R 50kO 150kHz 24 R 200kO 30 35kHz 36 42 48 A72 54 pp Vs sv JH S AT ms i 60 3 1k 10k 100k 1M FREQUENCY Hz Figure 22 Gain vs Frequency at 3
19. C Storage Temperature Range 65 C to 150 C Reflow Soldering Peak Temperature 260 C Time at Peak Temperature Thermal Resistance Oja TSSOP 24 20 sec to 40 sec 143 C W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features y Y patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD 4 A Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality 1 Maximum terminal current is bounded by the maximum current handling of the switches maximum power dissipation of the package and maximum applied voltage across any two of the A B and W terminals at a given resistance TES WY C com AL Rev A Page 6 of 28 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS B1 1 24 B2 A1 2 23 A2 wi 3 22 w2 B3 a AD5263 21 B4 TOP VIEW A3 5 Not to Scale 20 A4 w3 19 w4 Vpp 18 Vss GND 5 NC O2 pis
20. DAC latch codes in Table 5 result in the corresponding output resistance Rws Table 5 Codes and Corresponding Rws Resistances D Dec Rw Q Output State 255 19 982 Full scale Ras 1 LSB Rw 128 10 120 Midscale 1 0 O act resistance Note that in the zero scale condition a finite wiper resistance of 120 Q is present Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA Otherwise degradation or possible destruction of the internal switch contact can occur Similar to the mechanical potentiometer the resistance of the RDAC between the W wiper and Terminal A also produces a digitally controlled complementary resistance Rwa When these terminals are used the B terminal can be opened Setting the resistance value for Rwa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value The general equation for this operation is 256 D Rwa D 57 Rap 2 Ry Q For Ras 20 kO and the B terminal is open circuited the RDAC latch codes in Table 6 result in the corresponding output resistance Rwa Table 6 Codes and Corresponding Rwa Resistances D Dec Rwa Q Output State 255 198 Full scale 128 10 120 Midscale 1 19 982 1LSB 0 20 060 Zero scale Rev A Page 17 of 28 The typical distribution of the end to end resistance Ras from channel to channel matches within
21. EVISION HISTORY 11 06 Rev 0 to Rev A Updated Foftmata l qasashina sta ayara Universal Changes to Absolute Maximum Ratings 6 Changes to Ordering Guide a 28 6 03 Revision 0 Initial Version Self Contained Shutdown Function sss 20 Multiple Devices on One BUS serene 20 Level Shift for Negative Voltage Operation 20 ESD Protectionz aaa aq wasa 21 Terminal Voltage Operating Range s 21 Power Up Sequence sese 21 Viocic Power Supply e tp e 21 Layout and Power Supply Bypassing 21 RDAC Circuit Simulation Model s 22 Applicationsz a eene nene ete dus 23 Bipolar DC or AC Operation from Dual Supplies 23 Gain Control Compensation serene 23 Programmable Voltage Reference sss 23 8 Bit Bipolar DAC essendo eue en eee bre Bipol g CO ge Sonr Programmable 4 to 20 mA Current Source 25 Programmable Bidirectional Current Source 25 Programmable Low Pass Filter 1 26 Programmable Oscillator ees 26 Resistance Scaling eerte 27 Resistance Tolerance Drift and Temperature Coefficient Mismatch Considerations sese 27 Outline Dimensions
22. NG GUIDE Model Ras kO Temperature Package Description Package Option Ordering Quantity AD5263BRU20 20 40 C to 125 C 24 Lead TSSOP RU 24 AD5263BRU20 REEL7 20 24 SSOP RU 24 AD5263BRUZ20 24 Lead TSSOP AD5263BRUZ20 REEL 24 Lead TSSOP 24 AD5263BRU50 50 40 C to 125 C 24 Lead TSSOP RU 24 AD5263BRU50 REEL7 50 40 C to 125 C 24 Lead TSSOP RU 24 AD5263BRUZ50 50 40 C to 125 C 24 Lead TSSOP RU 24 AD5263BRUZ50 REEL7 50 40 C to 125 C 24 Lead TSSOP RU 24 AD5263BRU200 200 40 C to 125 C 24 Lead TSSOP RU 24 AD5263BRU200 REEL7 200 40 C to 125 C 24 Lead TSSOP RU 24 AD5263BRUZ200 200 40 C to 125 C 24 Lead TSSOP RU 24 AD5263BRUZ200 R7 200 40 C to 125 C 24 Lead TSSOP RU 24 AD5263EVAL Evaluation Board 1 The AD5263 contains 5 184 transistors Die size 108 mil x 198 mil 21 384 sq mil 2 Package branding Line 1 contains the model number Line 2 contains the end to end resistance and Line 3 contains the date code YYWW 37 Pb free part 4 The evaluation board is shipped with the 20 kO Ras resistor option however the board is compatible with all available resistor value options Purchase of licensed C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips PC Patent Rights to use these components in an lC system provided that the system conforms to the I C Standard Specification as defined by Philips 2006 Anal
23. RR Rev A Page 13 of 28 OFFSET s BIAS 03142 033 Figure 35 Test Circuit for Gain vs Frequency 0 1V Isw CODE 0x00 Rsw 03142 035 03142 032 Figure 36 Test Circuit for Incremental On Resistance 03142 034 DUT Vss GND s z o 03142 036 03142 038 CTA 20 log Vour Vin Figure 37 Test Circuit for Common Mode Leakage Current Figure 39 Test Circuit for Analog Crosstalk lLocic VLocic SCL SCA 03142 037 Figure 38 Test Circuit for Viocic Current vs Digital Input Voltage ww BDI C comi AD Rev A Page 14 of 28 SPI COMPATIBLE DIGITAL INTERFACE DIS 0 SERIAL DATA WORD FORMAT MSB LSB Addr Data B9 B8 B7 B6 B5 B4 B3 B2 B1 BO A1 AO D7 D6 D5 D4 D3 D2 D1 DO 2 2 2 lt c a 03142 039 Figure 40 AD5263 Timing Diagram Va 5 V Ve 0 V Vw Vout 1 SDI DATA IN 0 _ SENSIT ps I tcu gt csi te e WA BUI 7 ON AER 4 ts 03142 040 LSB Figure 41 Detailed SPI Timing Diagram VA 5 V Vs 0 V Vw Vour Rev A Page 15 of 28 l C COMPATIBLE DIGITAL INTERFACE DIS 1 The word format maps in this section use the following abbreviations Description Abbreviation S P A AD1 ADO A1 AO RS SD 01 02 Ww R D7 D6 D5 D4 D3 D2 D1 DO X Start condition Stop
24. circuit of Figure 70 the tolerance mismatch between the digital potent iometer and the discrete resistor can cause repeatability issues among various systems Because of the inherent matching of the silicon process it is practical to apply the multichannel device in this type of application As such R1 should be replaced by one of the channels of the digital potentiometer R1 should be programmed to a specific value while R2 can be used for the adjustable gain Although it adds cost this approach minimizes the tolerance and temperature coefficient mismatch between R1 and R2 In addition this approach also tracks the resistance drift over time As a result these nonideal parameters become less sensitive to system variations 03142 070 n x o gt o Notice that the circuit in Figure 71 can also be used to track the tolerance temperature coefficient and drift in this particular application However the characteristics of the transfer function change from a linear to a pseudologarithmic gain function Figure 71 Nonlinear Gain Control with Tracking Resistance Tolerance and Drift Rev A Page 27 of 28 OUTLINE DIMENSIONS 0 6 40 BSC vy 8 0 75 Pus Tis SEATING 0 20 559 PLANE 0 09 0 45 0 10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO 153 AD Figure 72 24 Lead Thin Shrink Small Outline Package TSSOP RU 24 Dimensions shown in millimeters ORDERI
25. condition Acknowledge IC device address bits Must match with the logic states at Pin AD1 and Pin ADO Refer to Figure 49 RDAC channel select Software reset wiper A1 AO to midscale position Shutdown active high ties wiper A1 AO to Terminal A opens Terminal B RDAC register contents are not disturbed To exit shutdown the command SD 0 must be executed for each RDAC A1 AO Data to digital output pins Pin O1 and Pin O2 in PC mode used to drive external logic The logic high level is determined by V and the logic low level is GND Write 0 Read 1 Data bits Don t care PC WRITE MODE DATA WORD FORMAT 0 1 0 1 1 AD1 ADO W A X Al AO RS SD O1 O2 X A D7 D6 DS D4 D3 D2 D1 DOJA Slave Address Byte Instruction Byte Data Byte PC READ MODE DATA WORD FORD S 0 Figure 42 Detailed PC Timing Diagram 1 9 1 9 1 9 sc LI l LTI UUU sa 0 1 0 1 1 VorfaoNuw x XAtXA0 XRsXsp Kor Xo2 Ax N 07 Ape jos Apa pos Ap2 X 01 X Do ACK BY ACK BY ACK BY AD5263 AD5263 AD5263 START BY RAME 1 STOP BY MASTER START BY lt FRAME 1 MJ ERAME2 x SIOPBY MASTER SLAVE ADDRESS BYTE RDAC REGISTER Figure 43 Writing to the RDAC Register s LP LPL LL LL LLL Li soa No sf o
26. e with a minimum conductor length Ground paths should have low resistance and low inductance Q1 Q2 2N3906 2N3906 Hp V 5V Figure 51 Level Shift for Bipolar Potential Operation 03142 051 03142 052 Similarly it is also a good practice to bypass the power supplies with quality capacitors for optimum stability Supply leads to the device should be bypassed with 0 01 uF to 0 1 uF ceramic disc or chip capacitors Low ESR 1 uF to 10 uF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple TERMINAL VOLTAGE OPERATING RANGE see Figure 55 Notice the digital ground should also be joined remotely to the analog ground at one point to minimize the A B W 03142 053 Vss Figure 53 ESD Protection of Resistor Terminals The AD5263 positive Vpp and negative Vss power supply defines the boundary conditions for proper 3 terminal digital ground bounce potentiometer operation Supply signals present on the A B and W terminals that exceed Vpp or Vss are clamped by the internal forward biased diodes shown in Figure 54 03142 055 Figure 55 Power Supply Bypassing Rev A Page 21 of 28 RDAC CIRCUIT SIMULATION MODEL Listing 1 Macro Model Net List for RDAC PARAM D 256 RDAC 20E3 The internal parasitic capacitances and the external capacitive d loads dominate the ac characteristics of the RDACs Configured SUBCKT DPOT A W B
27. equent readback operation Refer to Figure 44 for the programming format Rev A Page 19 of 28 4 After all data bits have been read or written a STOP condition is established by the master A STOP condition is defined as a low to high transition on the SDA line while SCL is high In write mode the master pulls the SDA line high during the tenth clock pulse to establish a STOP condition see Figure 43 In read mode the master issues a no acknowledge for the ninth clock pulse that is the SDA line remains high The master then brings the SDA line low before the tenth clock pulse which goes high to establish a STOP condition see Figure 44 A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once For example after the RDAC has acknowledged its slave address and instruction bytes in the write mode the RDAC output updates on each successive byte If different instructions are needed the write read mode has to start again with a new slave address instruction and data byte Similarly a repeated read function of the RDAC is also allowed ADDITIONAL PROGRAMMABLE LOGIC OUTPUT The AD5263 features additional programmable logic outputs O1 and O2 which can be used to drive a digital load analog switches and logic gates O1 and O2 default to Logic 0 The voltage level can swing from GND to V1 The logic states of O1 and O2 can be programmed i
28. in most cases PROGRAMMAB LTAG Forlyoltag aiv m er 9 itis common to buf Outputlof thedigita Sr unless the load is much larger than Rws Not only does the buffer serve the purpose of impedance conversion but it also allows a heavier load to be driven 03142 058 Figure 59 Programmable Voltage Reference Rev A Page 23 of 28 8 BIT BIPOLAR DAC Figure 60 shows a low cost 8 bit bipolar DAC It offers the same number of adjustable steps but not the precision as compared to conventional DACs The linearity and temperature coefficient especially at low values codes are skewed by the effects of the digital potentiometer wiper resistance The output of this circuit is 2D Va 1 xV 5 b E T 5 03142 059 BIPOLAR PR For applications requiring bipolar gain Figure 61 shows one implementation similar to the previous circuit The digital potentiometer U1 sets the adjustment range The wiper voltage at W2 can therefore be programmed between V and KV at a given U2 setting Configuring A2 in the noninverting mode allows linear gain and attenuation The transfer function is Va Ry D2 S Vi 2 oe K 6 where K is the ratio of Rwai Rwa set by U1 U2 AD5263 w2 U1 AD5263 03142 060 O Vss Figure 61 Bipolar Programmable Gain Amplifier Similar to the previous example in the simpler and much more usual case where K 1 a single channel is used and U1 is replaced by a matched
29. istance Ras of the VR has 256 contact points accessed by the wiper terminal plus the B terminal contact The 8 bit data in the RDAC latch is decoded to select one of the 256 possible settings Assuming a 20 kQ part is used the wipers first connection starts at the B terminal for data 0x00 Because there is a 60 Q wiper contact resistance such a connection yields a minimum of 2 x 60 Q resistance between the W and B terminals The second connection is the first tap point and corresponds to 198 Q Rws Ras 256 Rw 78 O 2 x 60 Q for Data 0x01 The third connection is the next tap point representing 216 Q Rws 78 Q x 2 2 x 60 Q for Data 0x02 and so on Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 19 982 O Ras 1 LSB 2 x Rw Figure 45 shows a simplified diagram of the equivalent RDAC circuit where the last resistor string is not accessed therefore there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance The general equation determining the digitally programmed output resistance between the W and B terminals is D D x Ry 2 Ry 1 Rys D m where Dis the decimal equivalent of the binary code loaded in the 8 bit RDAC register Raz is the end to end resistance Rwis the wiper resistance contributed by the on resistance of one internal switch In summary if Ras 20 kO and the A terminal is open circuited the R
30. n Frame 2 un Figure 43 These e adequ capability to sink s6u illi Users can also activate O1 and O2 in three different ways without affecting the wiper settings They may do the following e START slave address byte acknowledge instruction byte with O1 and O2 specified acknowledge STOP e Complete the write cycle with STOP then START slave address byte acknowledge instruction byte with O1 and O2 specified acknowledge STOP e Do not complete the write cycle by not issuing the STOP then START slave address byte acknowledge instruction byte with O1 and O2 specified acknowledge STOP SELF CONTAINED SHUTDOWN FUNCTION Shutdown can be activated by strobing the SHDN pin or programming the SD bit in the write mode instruction byte In addition shutdown can even be implemented with the devices digital output as shown in Figure 48 In this configuration the device is shut down during power up but users are allowed to program the device Thus when O1 is programmed high the device exits from the shutdown mode and responds to the new setting This self contained shutdown function allows absolute shutdown during power up which is crucial in hazardous environments without adding extra components RPULL DOWN 03142 047 Figure 48 Shutdown by Internal Logic Output MULTIPLE DEVICES ON ONE BUS Figure 49 shows four AD5263 devices on the same serial bus Each has a different slave address because the states of
31. need a lower resistance and the same number of step adjustments can place multiple devices in parallel For example Figure 67 shows a simple scheme of using two channels in parallel To adjust half of the resistance linearly per step users need to program both channels to the same settings Vpp O A1 W2 B1 YA LEDY 03142 066 Figure 67 Reduce Resistance by Half with Linear Adjustment Characteristics Applicable only to the voltage divider mode by connecting a discrete resistor in parallel as shown in Figure 68 a propor tionately lower voltage appears at Terminal A This translates into a finer degree of precision because the step size at Terminal W is smaller The voltage can be found as 18 03142 067 R1 lt lt Rag Figure 68 Decreasing Step Size by Lowering the Nominal Resistance Figure 67 and Figure 68 show applications in which the digital potentiometers change steps linearly On the other hand log taper adjustment is usually preferred in applications such as volume control Figure 69 shows another method of resistance scaling which produces a pseudolog taper output In this circuit the smaller the value of R2 with respect to Ras the more the output approaches log type behavior a a w O 03142 068 Figure 69 Resistor Scaling with Log Adjustment Characteristics RESISTANCE TOLERANCE DRIFT AND TEMPERATURE COEFFICIENT MISMATCH CONSIDERATIONS In rheostat mode operation such as the gain control
32. nput data register word that is transferred to the internal RDAC register when the CS line returns to logic high Note that only the last 10 bits that are clocked into the register are latched into the decoder As CS goes high it activates the address decoder and updates the corresponding channel according to Table 7 During shutdown SHDN the serial data output SDO pin is ighai void r F quivale SERIAL REGISTER 03142 045 Figure 46 Detailed SDO Output Schematic of the AD5263 During reset RES the wiper is set to midscale Note that unlike SHDN when the part is taken out of reset the wiper remains at midscale and does not revert to its pre reset setting Daisy Chain Operation The serial data output SDO pin contains an open drain N channel FET This output requires a pull up resistor in order to transfer data to the SDI pin of the next package This allows for daisy chaining several RDACs from a single processor serial data line The pull up resistor termination voltage can be greater than the Vp supply voltage It is recommended to increase the clock period when using a pull up resistor to the SDI pin of the following device because capacitive loading at the daisy chain node SDO to SDI between devices may induce time delay to subsequent devices Users should be aware of this potential problem to achieve data transfer successfully see Figure 47 If two AD5263s are daisy chained a total of 20 bits Rev A
33. og Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners C03142 0 11 06 A DEVICES www analog com Rev A Page 28 of 28
34. og Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2006 Analog Devices Inc All rights reserved TABLE OF CONTENTS Features ga atas aka RNE uo IUD OOS 1 Applications nns na ai e DD E EIE etd I s 1 Functional Block Diagram eren 1 General Description uuu usss 1 Revision History uu 2 Electrical Characteristics 20 kO 50 kO 200 kO Versions 3 Timing Characteristics 20 kQ 50 kO 200 kQ Versions 5 Absolute Maximum Ratings nasa 6 ESD CautiOn eere rer te tte tee sis saqsa 6 Pin Configuration and Pin Function Descriptions 7 Typical Performance Characteristics se 8 Test Cit Cuts iis 13 SPI Compatible Digital Interface DIS 0 15 Serial Data Word Format seen 15 PCT Atl OM ee no eR OO E UR a ss 17 Programming the Variable Resistor sss 17 Programming the Potentiometer Divider Voltage Output OperatiOTL eerte rir ERO DEDE HH THEMES PATRIE 18 Pin Selectable Digital Interface sss 18 SPI Compatible 3 Wire Serial Bus DIS 0 18 PC Compatible 2 Wire Serial Bus DIS 1 19 Additional Programmable Logic Output 20 R
35. owed by an R W bit This R W bit determines whether data will be read from or written to the slave device 3 Inread mode the data byte follows immediately after the acknowledgment of the slave address byte Data is transmitted over the serial bus in sequences of nine clock pulses a slight difference with the write mode where there are eight data bits followed by an acknowledge bit Similarly the transitions on the SDA line must occur during the low period of SCL and remain stable during the The slave whose address corresponds to the transmitted high period of SCL see Figure 44 address responds by pulling the SDA line low during the ninth clock pulse this is termed the acknowledge bit At this stage all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register If the R W bit is high the master reads from the slave device If the R W bit is low the master writes to the slave device Note that the channel of interest is the one that was previously selected in write mode In cases where users need to read the RDAC values of both channels they must program the first channel in write mode and then change to read mode to read the first channel value After that they must change back to write mode with the second channel selected and read the second channel value in read mode again It is not necessary for users to issue the Frame 3 data byte in the write mode for subs
36. pair of resistors to apply Vi and V1 at the ends of the digital potentiometer The relationship becomes R2 2xD2 Va 14 x 1 xV 7 J 256 J f 0 If R2 is large a compensation capacitor of a few pF may be needed to avoid any gain peaking Table 8 shows the result of adjusting D with A2 configured with unity gain gain of 2 and gain of 10 The result is a bipolar amplifier with linearly programmable gain and 256 step resolution Table 8 Result of Bipolar Gain Amplifier D R1 gt R2 0 R1 R2 R2 9xR1 0 1 2 10 64 0 5 1 5 128 0 0 0 192 0 5 1 5 255 0 968 1 937 9 680 PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT For appli a nt ad ent such as a laser diode dri ror ab r boosted voltflee source can onsi igure U3 2N7002 Vin Vout U1 R AD5263 BIAS A 03142 061 Figure 62 Programmable Booster Voltage Source In this circuit the inverting input of the op amp forces the Vour to be equal to the wiper voltage set by the digital potentiometer The load current is then delivered by the supply via the N channel FET N1 N1 power handling must be adequate to dissipate power equal to Vin Vour x Ix This circuit can source a maximum of 100 mA with a 5 V supply For precision applications a voltage reference such as ADR421 ADRO3 or ADR370 can be applied at the A terminal of the digital potentiometer Rev A Page 24 of 28 PROGRAMMABLE 4 TO 2
37. pical op amp GBP has 20 dB dec characteristics A large R2 and finite C1 can cause this zeros frequency to fall well below the crossover frequency Thus the rate of closure becomes 40 dB dec and the system has 0 phase margin at the crossover frequency The output may ring or oscillate if the input is a rectangular pulse or step function Similarly it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input Depending on the op amp GBP reducing the feedback resistor may extend the zero s frequency far enough to overcome the problem A better approach is to include a compensation capacitor C2 to cancel the effect caused by C1 Optimum compensation occurs when R1 x C1 R2 x C2 This is not an option because of the variation of R2 As a result one may use the relationship described and scale C2 as if R2 is at its maximum value Doing so may overcompensate and compromise the performance slightly when R2 is set at low values However it avoids the gain peaking ringing or oscillation in the worst case For critical applications C2 should be found empirically to suit the need In general C2 in the range of a few pF to no more than a few tenths of pF is usually adequate for the compensation Similarly there are W and A terminal capacitances connected to the output not shown fortunately their effect at this node is less significant and the compensation can be disregarded
38. se Setup tcsi 10 ns Reset Pulse Width tns 5 ns PC INTERFACE TIMING CHARACTERISTICS Specifications apply to all parts 3 SCL Clock Frequency fsa 400 kHz tsur Bus Free Time Between Stop and Start ti 1 3 Us tupsra Hold Time Repeated Start t After this period the first clock 0 6 Us pulse is generated tiow Low Period of SCL Clock ts 1 3 Us tuich High Period of SCL Clock ta 0 6 50 Us tsusrA Setup Time for Start Condition ts 0 6 Us tup pAr D 0 9 Us tsu par Da C O 100 ns te Fall Time lof S d S L Sig 300 ns tr Rise Time of Both SDA and SCL Signals to 300 ns tsusro Setup Time for Stop Condition tio 0 6 Us 1 Typicals represent average readings at 25 C and Voo 5 V Vss 5 V Guaranteed by design and not subject to production test 3 See timing diagrams for location of measured values All input control voltages are specified with ta tr 2 ns 10 to 90 of 3 V and timed from a voltage level of 1 5 V Switching characteristics are measured using V 5 V Rev A Page 5 of 28 ABSOLUTE MAXIMUM RATINGS T4 25 C unless otherwise noted Table 3 Parameter Value Vop to GND 0 3V to 16 5 V Vss to GND 7 5V to 0V Vo to Vss 16 5 V V to GND 0 3 V to 6 5 V Va Vs Vw to GND Vss to Vop Terminal Current Ax to Bx Ax to Wx Bx to Wx Pulsed 20 mA Continuous 3 mA Digital Inputs and Output Voltage to GND OVto 7V Operating Temperature Range 40 C to 85 C Maximum Junction Temperature Timax 150
39. ulled low which in turn causes Q2 to turn on In this state Vovr approaches 0 V Beware that proper time shifting is also needed for successful communication with the device POWER UP SEQUENCE 5V VIN ov 03142 054 Figure 54 Maximum Terminal Voltages Set by Vpp and Vss Because the ESD protection diodes limit the voltage compliance at the A B and W terminals see Figure 54 it is important to power Vpp and Vss before applying any voltage to the A B and W terminals otherwise the diodes are forward biased such that Von and Vss are powered unintentionally and may affect the rest of the circuit The ideal power up sequence is in the following order GND Von Vss Vr digital inputs and V asw The relative order of powering Va Vs Vw and digital inputs is not important as long as they are powered after Vpp and V ss Vioac POWER SUPPLY ESD PROTECTION The AD5263 is capable of operating at high voltages beyond the All digital inputs are protected with a series input resistor and internal logic levels which are limited to operation at 5 V Asa parallel Zener howni igu n resul always e ti e 2 7 V to 5 5 V This protec igital Mput ie 5 soufce to oper digital CS ADO RES A n be lifai tegardles JKogic levels must n Vi should LAYOUT AND POWER SUPPLY BYPASSING Itis a good practice to employ compact minimum lead length layout design The leads to the input should be as direct as Figure 52 ESD Protection of Digital Pins possibl
40. unless otherwise noted RHEOSTAT MODE DNL LSB RHEOSTAT MODE INL LSB RHEOSTAT MODE DNL LSB 0 8 5V 15 0V 03142 073 0 32 64 96 128 160 192 224 25 CODE Decimal eo Figure 3 R DNL vs Code vs Supply Voltage CODE Decimal Figure 4 R INL vs Code vs Supply Voltage CODE Decimal Figure 5 R DNL vs Code Vpp 5 V 03142 002 03142 003 Rev A Page 8 of 28 POTENTIOMETER MODE INL LSB RHEOSTAT MODE INL LSB POTENTIOMETER MODE INL LSB 40 C 0 8 25 C 85 C 0 6 125 C 0 2 0 6 0 8 03142 004 0 32 64 96 128 160 192 224 256 CODE Decimal Figure 6 R INL vs Code Voo 5 V 03142 005 0 32 64 96 128 160 192 224 2 CODE Decimal a Figure 7 INL vs Code vs Supply Voltage 03142 007 0 32 64 96 128 160 192 224 25 CODE Decimal o Figure 8 INL vs Code vs Supply Voltage POTENTIOMETER MODE INL LSB o o N POTENTIOMETER MODE DNL LSB FSE LSB Fr LJ F 1 0 03142 007 0 32 64 96 128 160 192 224 256 CODE Decimal Figure 9 INL vs Code Vop 5 V
41. ween successive tap positions Parts are guaranteed monotonic lw Voo R for both Voo 5 V and Vss 5 V 3 Vas Von Wiper Vw no connect INL and DNL are measured at Vw with the RDAC configured as a potentiometer divider similar to a voltage output DAC Va Voo and Vs 0 V DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions gt The A B and W resistor terminals have no limitations on polarity with respect to each other Measured at the inals are q eng shutdown mo 8 V is limited to Vop i i Worst case supply Il logic at 2 4 V standard characteristigof CMG B 10 Poss is calculated fri level inp n power dissipation All dynamic characteristics use Vop 5 V Vss 5 V V 5 V 12 Settling time depends on value of Von Ri and C Rev A Page 4 of 28 TIMING CHARACTERISTICS 20 KQ 50 kQ 200 kO VERSIONS Vpp 5 V Vss 5 V Vy 5 V Va Vpp Vs 0 V 40 C lt Ta lt 125 C unless otherwise noted Table 2 Parameter Symbol Conditions Min Typ Max Unit SPI INTERFACE TIMING CHARACTERISTICS Specifications apply to all parts Clock Frequency fax 25 MHz Input Clock Pulse Width tcu tc Clock level high or low 20 ns Data Setup Time tps 10 ns Data Hold Time tou 10 ns CS Setup Time tess 15 ns CS High Pulse Width tcsw 20 ns CLK Fall to CS Fall Hold Time tcsuo 0 ns CLK Fall to CS Rise Hold Time tcsui 0 ns CS Rise to Clock Ri

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