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ANALOG DEVICES AD5231 handbook

1. 0 CODE 0x200 10 0x100 0x80 20 0x40 0x20 30 0x10 40 50 0 0 01 60 1 10k 100k 1M FREQUENCY Hz Figure 19 Gain vs Frequency vs Code Ras 100 Figure 32 80 Rag 7 100kO 70 Rag 50kQ 60 Rag 10 m AB 40 30 20 5 0V 100mV AC Vss OV 5V Vg MEASURED AT Vw WITH CODE 0x200 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 20 PSRR vs Frequency 02739 018 02739 019 02739 020 Figure 21 Power On Reset Va Vout V SDI IDD 20mA DIV Rev C Page 11 of 28 100us DIV 2 25 V Va 0 V Code Vpp Vss 5 CODE 0x200 TO Ox1FF TIME us Rag 10 Rag 50 Rag 100kO 0 5V DIV 02739 021 10101010108 02739 022 Figure 22 Midscale Glitch Energy Code 0x200 to Ox 1FF 5VIDIV 5VIDIV 5VIDIV 4ms DIV Figure 23 loo vs Time when Storing Data to EEMEM 02739 023 SDI Ipp A sd 4ms DIV SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION IF INSTRUCTION 0 NOP IS EXECUTED IMMEDIATELY AFTER INSTRUCTION 1 READ EEMEM Figure 24 loo vs Time when Restoring Data from EEMEM 5VIDIV 5VIDIV 5VIDIV THEORETICAL Iwg max 02739 024 VA Vg OPEN 0 128 256 384 512 640 768 896 1024 CODE Decimal Figure 25
2. 16 Power Up Sequence eerie u tib 16 REVISION HISTORY 1 07 Rev B to Rev Updated Format Universal Changes to Dynamic Characteristics Specifications 4 Changes to Table 2 Footnote Changes to Table 3 Changes to Ordering Guide sene 27 9 04 Rev to Rev B Updated Format eet eet Universal Chaneesto Table 205 t PHONES ds 23 Changes to Resistance Scaling Section sss 25 Changes to Ordering Guide eene 27 Digital Outputs eR 16 Advanced Control Modes sse 18 Structures 19 Programming the Variable Resistor ss 19 Programming the Potentiometer Divider 20 Programming Examples serene 21 Flash EEMEM Reliability s 22 Applications 23 Bipolar Operation from Dual 23 High Voltage Operation 23 Bipolar Programmable Gain 23 10 Bit Bipolar DAC iseyin 23 10 Bit Unipolar DAC 24 Programmable Voltage Source with Boosted Output 24 Programmable Current Source sss 24 Programmable Bidirectional Current Source 25 Resistance Scaling edite sente Hee ene 25 AC Ci
3. ti 20 ns CS Setup Time t 10 ns CLK Shutdown Time to CS Rise t 1 tcvc Input Clock Pulse Width ta ts Clock level high or low 10 ns Data Setup Time te From positive CLK transition 5 ns Data Hold Time t From positive CLK transition 5 ns CS to SDO SPI Line Acquire te 40 ns CS to SDO SPI Line Release to 50 ns CLK to SDO Propagation tio 2 2 C lt 20 pF 50 ns CLK to SDO Data Hold Time Rp 2 2 lt 20 pF 0 ns CS High Pulse Width tie 10 ns CS High to CS High tia 4 terc RDY Rise to CS Fall 0 CS Rise to RDY Fall Time tis 01 0415 ms Store Read EEMEM Time 16 Applies to instructions 0x2 0 3 and 0 9 25 ms Power On EEMEM Restore Time 1 10 140 us Dynamic EEMEM Restore Time 2 Ras 10 140 us CS Rise to Clock Rise Fall Setup 10 ns Preset Pulse Wi 5 ongus shown in timing di vA ns Preset Re Setti pulsed low to eden 70 us FLASH EE Endurance 100 kCycles Data Retention 100 Years Typical values represent average readings at 25 C and 5 V Guaranteed by design and not subject to production test 3 See timing diagrams Figure and Figure 4 for location of measured values All input control voltages are specified with tr tr 2 5 ns 10 to 90 of V and timed from a voltage level of 1 5 V Switching characteristics are measured using both V and 35 V 4 Propagation delay depends on the value of Vo
4. 25 unless otherwise noted Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress Table 3 Parameters Ratings to GND 0 3V 7V Vss to GND 0 3V 7V to Vss 7V Va Vs Vw to GND Vss 0 3 0 3 V A W B W Intermittent 20 mA Continuous 2 mA Digital Input and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature max Storage Temperature Reflow Soldering Peak Temperature Time at Peak Temperature Thermal Resistance Junction to Ambient 0 4 TSSOP 16 Junction to Case TSSOP 16 Package Power Dissipati 0 3 V Vpp 0 3 V 40 to 85 150 65 to 150 260 20 sec to 40 sec 150 C W 28 C W rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Atas Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functiona
5. 0 10 ZERO SCALE 0 05 0 2 4 6 8 10 12 CLOCK FREQUENCY MHz Figure 14 lon vs Clock Frequency Ras 10 02739 012 02739 013 GAIN dB THD NOISE GAIN dB 02739 014 Rev C Page 10 of 28 f 37kHz Rag 10 0 2 A 44kHz Rag 100 8 85kHz Rag 10 12 14 VA 1 rms A Vpp Vss 2 5V D MIDSCALE 16 1k 10k 100k 1M FREQUENCY Hz Figure 15 3 dB Bandwidth vs Resistance Figure 32 Vpp Vss 2 5V VA 1V rms FREQUENCY kHz Figure 16 Total Harmonic Distortion vs Frequency 0 CODE 0x200 5 10 0 100 15 0 80 20 0 40 25 0 20 30 0x10 35 0x08 40 45 0x04 0x02 00 50 1 10 100 1 10M FREQUENCY Hz Figure 17 Gain vs Frequency vs Code Ras 10 Figure 32 02739 015 02739 016 02739 017 GAIN dB GAIN dB PSRR dB CODE 0x200 100k FREQUENCY Hz Figure 18 Gain vs Frequency vs Code Ras 50 Figure 32
6. 1 1 0 0 0 0 X 09 D8 D7 DO Write contents of Data Bytes 0 and 1 total 10 bits to RDAC See Table 13 125 1 1 0 0 0 0 0 X X X X X Increment RDAC by 6 dB See Table 16 135 1 1 0 1 X X X X X X X X X Same as Instruction 12 14 1 1 1 0 0 0 0 X X X X X Increment RDAC by 1 position See Table 14 155 1 1 1 1 X X X X X X X X X Same as Instruction 14 1 The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy chain operation Exception for any instruction following Instruction 9 or Instruction 10 the selected internal register data is present in Data Byte 0 and Data Byte 1 The instruction following 9 and 10 must also be a full 24 bit data word to completely clock out the contents of the serial register The RDAC register is a volatile scratchpad register that is refreshed at power on from the corresponding nonvolatile EEMEM register Execution of these operations takes place when the CS strobe returns to logic high Instruction writes two data bytes 16 bits of data to EEMEM In the case of 0 addresses only the last 10 bits are valid for wiper position setting 5 increment decrement and shift instructions ignore the contents of the shift register Data Byte 0 and Data Byte 1 Rev C Page 17 of 28 ADVANCED CONTROL MODES The AD5231 digital potentiometer includes a set of user programming features to address the wide number
7. EEMEM O value to the RDAC register Ox00XXXX Ox10XXXX NOP Recommended step to minimize power consumption Table 16 Using Left Shift by One to Increment 6 dB Step SDI SDO Action OxCOXXXX OxXXXXXX Moves the wiper to double the present data contained in the RDAC register Rev C Page 21 of 28 FLASH EEMEM RELIABILITY The Flash EE memory array on the AD5231 is fully qualified for two key Flash EE memory characteristics namely Flash EE memory cycling endurance and Flash EE memory data retention Endurance quantifies the ability of the Flash EE memory to be cycled through many program read and erase cycles In real terms a single endurance cycle is composed of four independent sequential events These events are defined as e Initial page erase sequence e Read verify sequence e Byte program sequence e Second read verify sequence During reliability qualification Flash EE memory is cycled from 0x000 to 0x3FF until a first fail is recorded signifying the endurance limit of the on chip Flash EE memory As indicated in the Specifications section the AD5231 Flash EE memory endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of 40 to 85 C The results allow the specification of a minimum endurance figure over supply and temperature of 100 000 cycles with an endi 700 000 cycles atibn at Rete
8. Figure 43 for a simplified diagram of the equivalent RDAC circuit When Rws is used Terminal A can be left floating or tied to the wiper ofthe Terminal A and Rev C Page 19 of 28 75 50 25 Rwa 0 Rws D of Nominal Rag 0 256 512 768 1023 CODE Decimal Figure 44 Rwa D and vs Decimal Code 02739 043 The general equation that determines the programmed output resistance between W and B is D Rwg D 3002 x Rag Ry 1 where Dis the decimal equivalent of the data contained in the RDAC register Ras is the nominal resistance between Terminal and Terminal B Rwis the wiper For example the for the given RDAC latch codes wit Ras 10 digital potentiometers Table 11 Rws D at Selected Codes for Ras 10 kQ The general transfer equation for this operation is 1024 D D jer d 122 2 For example the output resistance values in Table 12 set for the latch codes with Vpp 5 V applies to Ras 10 digital potentiometers Table 12 Rwa D at Selected Codes for Ras 10 D DEC Rwa D Output State 1023 24 7 Full scale 512 5015 Midscale 1 10005 1 LSB 0 10 015 Zero scale D DEC 0 O Output State 1023 10 005 Full scale 512 50 015 Midscale 1 24 7 115 0 15 Zero scale wiper contact resistor Note that in the zero scale condition a finite wiper resis
9. Figure 46 Bipolar Operation from Dual Supplies HIGH VOLTAGE OPERATION The digital potentiometer can be placed directly in the feedback or input path of an op amp for gain control provided that the voltage across Terminals Terminals W A or Terminals W B does not exceed 5 V When high voltage gain is needed users should set a fixed gain in an op voltage andilet nti met O adjustable input Figur 6 pler 2R O Vo AD5231 OV TO15V 02739 046 Figure 47 15 V Voltage Span Control BIPOLAR PROGRAMMABLE GAIN AMPLIFIER There are several ways to achieve bipolar gain Figure 48 shows one versatile implementation Digital potentiometer U1 sets the adjustment range the wiper voltage Vw can therefore be programmed between Vi and KViat a given U2 setting For linear adjustment configure A2 as a noninverting amplifier and the transfer function becomes 1 4 V RI 1024 where Kis the ratio of Rws Rwa that is set by U1 Dis the decimal equivalent of the input code U1 AD5231 02739 047 Figure 48 Bipolar Programmable Gain Amplifier In the simpler and much more usual case where K 1 a pair of matched resistors can replace U1 Equation 4 be simplified to 2 Vo R2 2D V 1024 Table 20 shows the result of adjusting D with A2 configured asa unity gain a gain of 2 and a gain of 10 The result is a bipolar amplifi
10. components look up table or system identification information In scratchpad programming mode a specific setting can be programmed directly to the RDAC register that sets the 1 terms nonvolatile memory and EEMEM are used interchangeably The terms digital potentiometer and RDAC are used interchangeably Rev Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property their respective owners Nonvolatile Memory 1024 Position Digital Potentiometer FUNCTIONAL BLOCK DIAGRAM SERIAL INTERFACE r V EEMEM 1 28 BYTES USER EEMEM 02739 001 Figure 1 of Nominal Rag Rwa D R 02739 002 CODE Decimal Figure 2 Rwa D and Rws D vs Decimal Code resistance between Terminals W A and Terminals W B This setting can be stored into the EEMEM and is transferred automatically to the RDAC register during system power on The EEMEM content can be restored dynamically or through external PR strobing and a WP function protects EEMEM contents To simplify the programming the linear step increment o
11. equation defining the output voltage at Vw with respect to ground for any given input voltages applied to Terminal A and Terminal B is Vw D 3 Equation 3 assumes that Vw is buffered so that the effect of wiper resistance is minimized Operation of the digital potentiometer in divider mode results in more accurate operation over temperature Here the output voltage is dependent on the ratio of the internal resistors and not the absolute value therefore the drift improves to 15 ppm C There is no voltage polarity restriction between Terminal A Terminal B and Terminal W as long as the terminal voltage stays within Vss lt lt Voo Rev C Page 20 of 28 PROGRAMMING EXAMPLES The following programming examples illustrate a typical sequence of events for various features of the AD5231 See Table 7 for the instructions and data word format The instruction numbers addresses and data appearing at SDI and SDO pins are in hexadecimal format Table 13 Scratchpad Programming Table 17 Storing Additional User Data in EEMEM SDI SDO Action 0xB00100 OxXXXXXX Writes data 0x100 into RDAC register Wiper W moves to 1 4 full scale position SDI SDO Action 0 32 OxXXXXXX Stores data OxAAAA in the extra EEMEM location 95 1 Allowable to address in 14 locations with a maximum of 16 bits of data 0x335555 Ox32AAAA Stores data 0x5555 in the ex
12. lwa vs Code ww comi Rev C Page 12 of 28 02739 025 TEST CIRCUITS Figure 26 to Figure 35 define the test conditions used in the specifications T OFFSET BIAS Figure 26 Resistor Position Nonlinearity Error Figure 31 Noninverting Gain Rheostat Operation R INL R DNL 02739 026 02739 031 NC NO CONNECT V Vpp 1LSB V 2N 02739 027 02739 032 CODE 0x000 LA 02739 033 Figure 28 Wiper Resistance Figure 33 Incremental On Resistance VA V Vpp 310 AVus PSRR dB 20 log sy 5 22 o jo AVMs 8 PSS 9 3 B NC NOCONNECT Figure 29 Power Supply Sensitivity PSS PSRR Figure 34 Common Mode Leakage Current A DUT B MIN O Vour TO OUTPUT OR PIN VoL x OFFSET BIAS 2 Figure 30 Inverting Gain Figure 35 Load Circuit for Measuring Von and The diode bridge test circuit is equivalent to the application circuit with of 2 2 Rev C Page 13 of 28 THEORY OF OPERATION The AD5231 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of Vss lt Vrerm lt Voo The basic voltage range is limited to Vss lt 5 5 V The digital potentiometer wiper position is determined by the RDAC register contents The RDAC register acts a
13. not used No internal pull up resistors are present on any digital input pins The SDO and RDY pins are open drain digital outputs that need pull up resistors only if these functions are used A resistor value in the range of 1 kO to 10 kO is a proper choice that balances the dissipation and switching speed The equivalent serial data input and output logic is shown in Figure 36 The open drain output SDO is disabled whenever chip select CS is in logic high ESD protection of the digital inputs is shown in Figure 37 and Figure 38 PR WB VALID COMMAND COMMAND PROCESSOR AND ADDRESS DECODE 5V RpuLL uP SERIAL REGISTER o 02739 035 o e GND Figure 37 Equivalent ESD Digital Input Protection Vpp Q INPUT 3000 2 GND 5 38 Equivalent WP Input Protection SERIAL DATA INTERFACE The AD5231 contains a 4 wire SPI compatible digital interface SDI SDO CS and CLK It uses a 24 bit serial data word loaded MSB first The format of the SPI compatible word is shown in Table 6 The chip select CS pin must be held low until the complete data word is loaded into the SDI pin When CS returns high the serial data word is decoded according to the instructions in Table 7 The command bits Cx control the operation of the digital potentiometer The address bits Ax determine which register is activated The data bits Dx are the values that ar
14. provides a macro model net list for the 10 kO RDAC PARAM D 1024 RDAC 10E3 SUBCKT DPOT A W B CA A 0 50E 12 RWA W 1 D 1024 RDAC 15 CW W 0 50E 12 RWB W B D 1024 RDAC 15 CB B 0 50E 12 ENDS DPOT ww C com Rev C Page 26 of 28 OUTLINE DIMENSIONS 0 30 0 19 COPLANARITY 0 10 COMPLIANT TO JEDEC STANDARDS MO 153 AB Figure 58 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 Dimensions shown in millimeters ORDERING GUIDE Model Ras kQ Temperature Range Package Description Package Option Ordering Quantity AD5231BRU10 10 40 to 85 16 Lead TSSOP RU 16 96 AD5231BRU10 REEL7 10 40 C to 85 C 16 Lead TSSOP RU 16 1 000 AD5231BRUZ10J 16 6 AD5231 sd AA 6 000 AD5231BRU 0 0 46 6 AD5231BRU50 REEL7 50 40 C 85 16 Lead TSSOP RU 16 1 000 AD5231BRUZ50 50 40 C to 85 C 16 Lead TSSOP RU 16 96 AD5231BRUZ50 REEL7 50 40 to 85 C 16 Lead TSSOP RU 16 1 000 AD5231BRU100 100 40 C to 85 C 16 Lead TSSOP RU 16 96 AD5231BRU100 RL7 100 40 C to 85 C 16 Lead TSSOP RU 16 1 000 AD5231BRUZ100 100 40 to 85 16 Lead TSSOP RU 16 96 AD5231BRUZ100 RL7 100 40 C to 85 C 16 Lead TSSOP RU 16 1 000 17 Pb free part Rev C Page 27 of 28 NOTES ww C com Purchase of licensed components of Analog Devices or one of its su
15. s A terminal This limits the potentiometer s current and increases the current adjustment resolution Rev C Page 24 of 28 PROGRAMMABLE BIDIRECTIONAL CURRENT RESISTANCE SCALING SOURCE The AD5231 offers 10 50 and 100 kO nominal For applications that require bidirectional current control or resistance For users who need lower resistance but want to higher voltage compliance a Howland current pump can be a maintain the number of adjustment steps they can parallel solution If the resistors are matched the load current is multiple devices For example Figure 54 shows a simple scheme R2A R2B of paralleling two AD5231s To adjust half the resistance RH linearly per step users need to program both devices coherently W 8 with the same settings and tie the terminals as shown Rt R2 150kQ 15kQ A1 A2 LD Y Z Figure 54 Reduce Resistance by Half with Linear Adjustment Characteristics 02739 053 In voltage diver mode by paralleling a discrete resistor as shown in Figure 55 a proportionately lower voltage appears at Terminals This translates into a finer degree of precision because the step size at Terminal W is smaller The voltage can be found as follows R R2 D V D Bax x Vpp 10 02739 052 Figure 53 Programmable Bidirectional Current Source R3 R R2 1024 R2B in theory be made as small as necessary to achieve the current needed within the A2 output current
16. AC register can also be refreshed with the EEMEM register data under hardware control by pulsing the PR pin The PR pulse first sets the wiper at midscale when brought to logic zero and then on the positive transition to logic high it reloads the RDAC wiper register with the contents of EEMEM Many additional advanced programming commands are available to simplify the variable resistor adjustment process see Table 7 For example the wiper position can be changed one step at a time using the increment decrement instruction or by 6 dB with the shift left right instruction Once an increment decrement or shift instruction has been loaded into the shift register subsequent CS strobes can repeat this command A serial data output SDO pin is available for daisy chaining and for readout of the internal register contents EEMEM PROTECTION The write protect WP pin disables any changes to the scratchpad register contents except for the EEMEM setting which can still be restored using Instruction 1 Instruction 8 and the PR pulse Therefore WP can be used to provide a hardware EEMEM protection feature To disable WP it is recommended to execute a NOP instruction before returning WP to logic high Rev C Page 14 of 28 DIGITAL INPUT OUTPUT CONFIGURATION digital inputs are ESD protected high input impedance that can be driven directly from most digital sources Active at logic low PR and WP must be tied to Vpn if they are
17. ANALOG DEVICES FEATURES 1024 position resolution Nonvolatile memory maintains wiper setting Power on refresh with EEMEM setting EEMEM restore time 140 ps typ Full monotonic operation 10 kO 50 kO and 100 kO terminal resistance Permanent memory write protection Wiper setting readback Predefined linear increment decrement instructions Predefined 6 dB step log taper increment decrement instructions SPI compatible serial interface 3V to 5V single supply or 2 5 V dual supply operation 28 bytes extra nonvolatile memory for user defined data 100 year typical data retention 55 APPLICATIONS Mechanical potentiometer replacement Instrumentation gain offset adjustme Programmabl rrent co ver Programm sta Programmable r Low resolution DAC replacement Sensor calibration GENERAL DESCRIPTION The AD5231 is a nonvolatile memory digitally controlled potentiometer with 1024 step resolution The device performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution solid state reliability and remote controllability The AD5231 has versatile programming that uses a standard 3 wire serial interface for 16 modes of operation and adjustment including scratchpad programming memory storing and restoring increment decrement 6 dB step log taper adjustment wiper setting readback and extra EEMEM for user defined information such as memory data for other
18. E Resolution N 10 Bits Differential Nonlinearity DNL Monotonic Ta 25 C 1 1 2 1 LSB Monotonic Ta 40 C or 85 C 1 1 25 LSB Integral Nonlinearity INL 0 4 0 4 LSB Voltage Divider Temperature AVw Vw AT x 106 Code half scale 15 ppm C Coefficient Full Scale Error full sc 3 0 96 FS Zero Sca Code zerofscale 1 5 FS RESISTOR TERMI Terminal Voltage Range Vss V Capacitance A B CAB f 1 MHz measured to GND 50 pF code half scale Capacitance W Cw f 1 MHz measured to GND 50 pF code half scale Common Mode Leakage Current 6 Vw 2 0 01 1 DIGITAL INPUTS AND OUTPUTS Input Logic High Vin With respect to GND Voo 5 2 4 Input Logic Low With respect to GND Voo 5 V 0 8 V Input Logic High Vin With respect to GND Voo 3 V 2 1 Input Logic Low Vit With respect to GND Voo 3 V 0 6 V Input Logic High Vin With respect to GND Voo 2 5 2 0 Vss 2 5 V Input Logic Low Vit With respect to GND Voo 2 5 V 0 5 V Vss 2 5 V Output Logic High SDO RDY 2 2 to 5 V 4 9 V see Figure 26 Output Logic Low Vo lo 1 6 mA 5 V 0 4 V see Figure 26 Input Current l Vin OV or Voo 2 5 Input Capacitance Ci 4 pF Output Current loi loz 5 Vss OV TA 25 50 mA 2 5 V Vss OV Ta 25 7 mA Rev C Page 3 of 28 Parameter Symbol Con
19. Q 0 5 TA 85 25 1 0 1 5 2 0 2 0 128 256 384 512 640 768 896 1024 8 0 128 256 384 512 640 768 896 1024 CODE Decimal 5 CODE Decimal Figure 6 INL vs Code Ta 40 C 25 85 Overlay Ras 10 Figure 9 R DNL vs Code Ta 40 C 25 85 C Overlay Ras 10 2 0 Vpp 5V Vss 0V Vpp 5 5V Vss m 40 TO 85 1 0 40 E m 0 5 x ul 05 8 25 o 1 0 amp 1 5 2 0 d 0 128 256 384 512 640 768 896 1024 8 CODE Decimal 5 CODE Decimal 5 Figure 7 DNL vs Code Ta 40 C 25 C 85 C Overlay Ras 10 Figure 10 ARws Rws AT x 10 100 ve 5 5V Vss 0V p lt 40 TO 85 so Vg 0 2 60 ul T 40 gt 25 li 20 0 20 0 128 256 384 512 640 768 896 1024 8 E CODE Decimal CODE Decimal Figure 8 R INL vs Code 40 C 25 C 85 C Overlay Ras 10 Figure 11 AVw Vw AT x 10 Rev C Page 9 of 28 Rw CURRENT uA Ipp mA Vpp 27V Vss 0V 25 Figure 12 Wiper On Resistance vs Code Iss Q Vpp Vss 2 7V 0 40 20 0 20 40 60 80 100 TEMPERATURE Figure 13 loo vs Temperature Ras 10 0 25 0 20 0 15
20. ad register is a standard logic register with no restriction on the number of changes allowed but the EEMEM registers have a program erase write cycle limitation see the Flash EEMEM Reliability section BASIC OPERATION The basic mode of setting the variable resistor wiper position programming the scratchpad register is accomplished by loading the serial data input register with Instruction 11 0xB Address 0 and the desired wiper position data When the proper wiper position is determined the user can load the serial data input register with Instruction 2 0x2 which stores the wiper position data in the EEMEM register After 25 ms the wiper position is permanently stored in the nonvolatile memory Table 5 provides a programming example listing the sequence of serial data input SDI words with the serial data output appearing at the SDO pin in hexadecimal format Table 5 Set and Store RDAC Data to EEMEM Register SDI SDO Action 0xB00100 Writes data 0x100 to the RDAC register Wiper W moves to 1 4 full scale position 0x20XXXX 0xB00100 Stores RDAC register content into the EEMEM register At system power on the scratchpad register is automatically refreshed with the value previously stored in the EEMEM register The factory preset EEMEM value is midscale but the user tliereafi During perati shed with t EMifegiste 0x1 or Instruction 8 0x8 The RD
21. blicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components an system provided that the system conforms to the Standard Specification as defined by Philips 2007 Analog Devices Inc All rights reserved Trademarks and AN ALOG registered trademarks are the property of their respective owners C02739 0 1 07 C DEVICES www analog com Rev C Page 28 of 28
22. ditions Min Max Unit POWER SUPPLIES Single Supply Power Range Vop Vss 0V 2 7 5 5 Dual Supply Power Range Vop Vss 2 25 2 75 V Positive Supply Current Vin Voo or Vi GND 2 7 10 Negative Supply Current 155 Vin Voo Vi GND 0 5 10 42 5 V Vss 2 5 V Store Mode Current loo store or GND 40 mA Vss GND Iss 0 Iss store 42 5 V Vss 2 5 V 40 mA EEMEM Restore Mode Current loo restore or GND 0 3 3 9 mA Vss GND Iss 0 Iss restore 42 5 V Vss 2 5 V 0 3 3 9 Power Dissipation Poiss or Vi GND 0 018 0 05 mW Power Supply Sensitivity Pss AVpp 5 V 10 0 002 0 01 DYNAMIC CHARACTERISTICS 9 Bandwidth BW 3 dB Ras 10 kO 50 370 85 44 kHz 100 kO Total Harmonic Distortion THDw 1 V rms Vs OV f 1 kHz 0 045 Ras 10 1 V rms Vs OV f 1 kHz 0 022 Ras 50 kO 100 kO Vw Settling Time ts Va Ve OV 1 2 3 7 7 Hs Vw 0 5096 error band Code 0x000 to 0x200 for Ras 10 kO 50 kO 100 Resistor Noise Vol Rw 5 1 9 nV 4Hz Typical values repr 2 Resistor position i valie meas een th i esistanceandtheminim ce wiper positions R DNL measures the relative step change from ideal between successive tap positions 50 2 7 V and lw 400 HA 5 V for the Ra
23. driving In this circuit ivers 5 m Ain both dire the voltage the output i R2B R1 R2A RIR2 RI R2A R2B Zo 9 Figure 55 Lowering the Nominal Resistance Figure 54 and Figure 55 show that the digital potentiometers change steps linearly On the other hand pseudo log taper adjustment is usually preferred in applications such as audio control Figure 56 shows another type of resistance scaling In this configuration the smaller the R2 with respect to R1 the more the pseudo log taper characteristic of the circuit behaves Zo be infinite if resistors R1 and R2 match precisely with and R2A R2B respectively On the other hand Zo can be negative if the resistors are not matched As a result C1 in the range of 1 pF to 10 15 needed to prevent oscillation from the negative impedance 02739 055 Figure 56 Resistor Scaling with Pseudo Log Adjustment Characteristics Rev C Page 25 of 28 RDAC CIRCUIT SIMULATION MODEL The internal parasitic capacitances and the external load dominates the ac characteristics of the The 3 dB bandwidth of the AD5231BRU10 10 resistor measures 370 kHz at half scale when configured as a potentiometer divider Figure 15 provides the large signal BODE plot charac teristics A parasitic simulation mode is shown in Figure 57 RDAC 02739 056 Figure 57 RDAC Circuit Simulation Model for RDAC 10 The following code
24. e loaded into the decoded register The AD5231 has an internal counter that counts a multiple of 24 bits a frame for proper operation For example AD5231 works with a 48 bit word but it cannot work properly with a 23 bit or 25 bit word In addition AD5231 has a subtle feature that if CS is pulsed without CLK and SDI the part repeats the previous command except during power up As a result care must be taken to ensure that no excessive noise exists in the CLK or CS line that might alter the effective number of bits ENOB pattern Also to prevent data from mislocking due to noise for example the counter resets if the count is not a multiple of four when CS goes high The SPI interface can be used in two slave modes CPHA 1 CPOL 1 and CPHA 0 CPOL 0 CPHA and CPOL refer to the control bits that dictate SPI timing in the following MicroConverters and microprocessors ADuC812 ADuC824 M68HC11 MC68HC16R1 916R1 DAISY CHAIN OPERATION The serial data output pin SDO serves two purposes It can be and EEMEM respectively The alid for daisy chaining multiple devi es in simultaneous operations Daisy chaining minimizes the number of port pins required from the controlling IC see Figure 39 The SDO pin contains an open drain N Ch FET that requires a pull up resistor if this function is used As shown in Figure 39 users need to tie the SDO pin of one package to the SDI pin of the next package Users might
25. elivered by the supply via the N Ch FET Ni power handling must be adequate to dissipate Vi Vo x power This circuit can source a maximum of 100 mA with a 5 V supply For precision applications a voltage reference such as ADR421 ADR03 or ADR370 can be applied at Terminal A of the digital potentiometer PROGRAMMABLE CURRENT SOURCE programmable current source be implemented with the circuit shown in Figure 52 5V Vi 6 SLEEP REF 191 GND AD5231 2 048V TOV 02739 051 Figure 52 Programmable Current Source REF191 is a unique low supply headroom precision reference that can deliver the 20 mA needed at 2 048 V The load current is simply the voltage across Terminals B W of the digital potentiometer divided by Rs _ XD RQx1024 The circuitsis sin First dual sup ntia at full scale of the potentiometer setting Although the circuit works under single supply the programmable resolution of the system is reduced Second the voltage compliance at V1 is limited to 2 5 V or equivalently 125 Q load Should higher voltage compliance be needed users can consider digital potentiometers AD5260 AD5280 and AD7376 Figure 53 shows an alternate circuit for high voltage compliance 7 L To achieve higher current such as when driving a high power LED the user can replace the UI with an reduce Rs and add a resistor in series with the digital potentiometer
26. ent and Decrement Left Shift 6 dB step Actual the contents Left Shift Right Shift 0000000000 1111111111 00 00000001 0111111111 00 00000010 001111 1111 0000000100 000111 1111 00 0000 1000 00 0001 0000 00 0010 0000 00 0100 0000 00 1000 0000 01 0000 0000 10 0000 0000 11 1111 1111 11 1111 1111 00 0011 1111 00 0001 1111 00 0000 1111 00 0000 0111 00 0000 0011 00 0000 0001 00 0000 0000 00 0000 0000 r Right Shift 6 dB step right shift 4 and 5 command execution contains an error only for odd numbers of bits Even numbers of bits are ideal The graph in Figure 42 shows plots of Log Error 20 x logio error code for the AD5231 For example Code 3 Log Error 20 x logio 0 5 3 15 56 dB which is the worst case The plot of Log Error is more significant at the lower codes 0 dB 40 60 80 0 0 1 02 03 04 05 0 6 07 08 CODE From 1 to 1023 by 2 0 x 103 0 9 10 1 1 8 ge 8 Figure 42 Plot of Log_Error Conformance for Odd Numbers of Bits Only Even Numbers of Bits Are Ideal Rev C Page 18 of 28 Using Additional Internal Nonvolatile EEMEM The AD5231 contains additional user EEMEM registers for storing any 16 bit data such as memory data for other compo nents look up tables or system identification information Table 9 provides an address map of the internal storage registers shown in the
27. er with linearly programmable gain and 1024 step resolution Table 20 Result of Bipolar Gai D 2 9 1 0 10 256 5 512 0 0 768 0 5 5 1023 0 992 9 92 10 BIT BIPOLAR DAC If the circuit in Figure 48 is changed with the input taken from a voltage reference and A2 configured as a buffer a 10 bit bipolar DAC can be realized Compared to the conventional DAC this circuit offers comparable resolution but not the precision because of the wiper resistance effects Degradation of the nonlinearity and temperature coefficient is prominent near both ends of the adjustment range On the other hand this circuit offers a unique nonvolatile memory feature that in some cases outweighs any shortfall in precision The output of this circuit is y 6 E REF 6 Rev C Page 23 of 28 02739 048 Figure 49 10 Bit Bipolar DAC 10 BIT UNIPOLAR DAC Figure 50 shows a unipolar 10 bit DAC using AD5231 The buffer is needed to drive various leads 5V PROGRAMM BOOSTED OU For applications that require high current adjustment such as a laser diode driver or tunable laser a boosted voltage source can be considered see Figure 51 VNO Vour AD5231 2N7002 02739 058 Figure 51 Programmable Booster Voltage Source In this circuit the inverting input of the op amp forces the Vour to be equal to the wiper voltage set by the digital potentiometer The load current is then d
28. functional block diagram as EEMEMI EEMEM2 and 28 bytes 14 addresses x 2 bytes each of user EEMEM Table 9 EEMEM Address Map Address EEMEM for 0000 0001 O1 O2 0010 USER1 0011 USER2 1110 USER13 1111 USER14 RDAC data stored EEMEM location is transferred to the RDAC register at power on or when Instruction 1 Instruction 8 or PR are executed 2 Execution of Instruction 1 leaves the device the read mode power consumption state After the last Instruction 1 is executed the user should perform a Instruction 0 to return the device to the low power idling state 301 and O2 data stored in EEMEM locations is transferred to the corresponding digital register at power on or when Instruction 1 and Instruction 8 are executed resistor segments with an array of analog switches that act as the wiper connection The number of positions is the resolution of the device The AD5231 has 1024 connection points allowing it to provide better than 0 196 settability resolution Figure 43 shows an equivalent structure of the connections among the three terminals of the The SWa and SW are always on while the switches SW 0 to SW 2 1 are on one at a time depending on the resistance position decoded from the data bits Because the switch is not ideal there is a 15 O wiper resistance Rw Wiper resistance is a function of supply voltage and temperature The lower the supply vo
29. it is important to power Vpp Vss first before applying any voltage to Terminal Terminal B and Terminal W Otherwise the diode is forward biased such that Vpp Vss are powered unintentionally and might affect the rest of the user s circuit The ideal power up sequence is GND Vpp Vss digital inputs and VA Vs Vw The order of powering Va Vp Vw and digital inputs is not important as long as they are powered after Vpp Vss Regardless of the power up sequence and the ramp rates of the power supplies once Vpp Vss are powered the power on preset remains effective which restores the EEMEM value to the RDAC register LATCHED DIGITAL OUTPUTS pair of digital outputs O1 and O2 is available on the AD5231 These outputs provide a nonvolatile Logic 0 or Logic 1 setting O1 and O2 are standard CMOS logic outputs shown in Figure 41 These outputs are ideal to replace the functions often provided by DIP switches In addition they can be used to drive other standard CMOS logic controlled parts that need an occasional setting change Pin O1 and Pin O2 default to Logic 1 and they can drive up to 50 mA of load at 5 V 25 C 02739 040 GND Figure 41 Logic Outputs O1 and O2 Rev C Page 16 of 28 In Table 6 command bits CO to C3 address bits are to 0 Data Bit DO Data Bit D9 are applicable to RDAC and D0 to D15 are applicable to EEMEM Table 6 AD5231 24 Bit Serial Data Word MSB Command Byte 0 Data Byte 1 Da
30. lity voltage across any two of the A B and W terminals at a given resistance Includes programming of nonvolatile memory Rev C Page 7 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS o1 1 e 16 02 2 15 RDY 14 cs spo 4 AD5231 13 PR TOP VIEW GND 5 Not to Scale 12 WP Vss 6 11 T 10 A 02739 005 Figure 5 Pin Configuration Table 4 Pin Function Descriptions Pin No Mnemonic Description 1 01 Nonvolatile Digital Output 1 ADDR 0x1 data bit position DO For example to store O1 high the data bit format is 0x310001 2 CLK Serial Input Register Clock Pin Shifts in one bit at a time on positive clock edges 3 SDI Serial Data Input Pin Shifts in one bit at a time on positive clock CLK edges MSB loaded first 4 SDO Serial Data Output Pin Serves readback and daisy chain functions Command 9 and Command 10 activate the SDO output for the readback function delayed by 24 or 25 clock pulses depending on the clock polarity before and after the data word see Figure 3 Figure 4 and Table 7 In other commands the SDO shifts out the C loaded SDI bit pattern delayed by 24 or 25 clock pulses d ing ure COL out 5 GND Ground Pin Logic ground reference Vss Negative Supply Connect to 0 V for single supply applications If Vss is used in dual supply applications it must be able to sink 40 mA for 25 ms when storing data t
31. ltage or the higher the temperature the higher the resulting wiper resistance Users should be aware of the wiper resistance dynamics if accurate prediction of the output resistance is needed Rg Rap 2N DIGITAL CIRCUITRY OMITTED FOR CLARITY 02739 042 Figure 43 Equivalent RDAC Structure Patent Pending Table 10 Nominal Individual Segment Resistor Rs Device 10 kO 50 100 Resolution Version Version Version 10 Bit 9 80 48 80 9760 PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation wi and 100 ina Teil wit inal digit s of the part number determine the nominal resistance value for example 10 kO 10 50 50 100 The 10 bit data word in the RDAC latch is decoded to select one of the 1024 possible settings The following discussion describes the calculation of resistance Rws at different codes of a 10 part For Vpp 5 V the wiper s first connection starts at Terminal for data 0x000 Rws 0 is 15 because of the wiper resistance and because it is independent of the nominal resistance The second connection is the first tap point where Rws 1 becomes 9 7 15 24 7 for data 0x001 The third connection is the next tap point representing Rws 2 19 4 Q 15 Q 34 4 for data 0x002 and so on Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at Rws 1023 10 005 See
32. m setting the last 6 dB increment instruction causes the wiper to go to the full scale 1023 code position Further 6 dB per increment instructions do not change the wiper position beyond its full scale Logarithmic Ta The 6 dB step increments and 6 dB step decrements are achieved by shifting the bit internally to the left or right respectively The following information explains the nonideal 6 dB step adjustment under certain conditions Table 8 illustrates the operation of the shifting function on the RDAC register data bits Each table row represents a successive shift operation Note that the left shift 12 and 13 instructions were modified such that if the data in the RDAC register is equal to zero and the data is shifted left the RDAC register is then set to Code 1 Similarly if the data in the RDAC register is greater than or equal to midscale and the data is shifted left then the data in the RDAC register is automatically set to full scale This makes the left shift function as ideal a logarithmic adjustment as possible The right shift 4 and 5 instructions are ideal only if the LSB is 0 ideal logarithmic no error If the LSB is 1 the right shift function generates a linear half LSB error which translates to a number of bits dependent logarithmic error as shown in Figure 42 The plot shows the error of the odd numbers of bits for the AD5231 Table 8 Detail Left Shift and Right Shift Functions for 6 dB Step Increm
33. need to increase the clock period because the pull up resistor and the capacitive loading at the SDO to SDI interface might require additional time delay between sub sequent packages When two AD5231s are daisy chained 48 bits of data are required The first 24 bits go to U2 and the second 24 bits go to U1 The CS should be kept low until all 48 bits are clocked into their respective serial registers The CS is then pulled high to complete the operation 02739 038 Figure 39 Daisy Chain Configuration Using SDO Rev C Page 15 of 28 TERMINAL VOLTAGE OPERATION RANGE The AD52315 positive Vpp and negative Vss power supplies define the boundary conditions for proper 3 terminal digital potentiometer operation Supply signals present on the A B and W terminals that exceed Vpp or Vss are clamped by the internal forward biased diodes see Figure 40 The ground pin of the AD5231 device is primarily used as a digital ground reference which needs to be tied to the common ground of the PCB The digital input control signals to the AD5231 must be referenced to the device ground pin GND and satisfy the logic level defined in the Specifications section An internal level shift circuit ensures that the common mode voltage range of the three terminals extends from Vss to regardless of the digital input level POWER UP SEQUENCE Because there are diodes to limit the voltage compliance at the A B and W terminals Figure 40
34. ntion quanti i the Flas retain its programmed data over time Again the AD5231 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification A117 at a specific junction temperature T 55 C As part of this qualification procedure the Flash EE memory is cycled to its specified endurance limit described previously before data retention is characterized This means that the Flash EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash EE memory is reprogrammed It should also be noted that retention lifetime based on an activation energy of 0 6 eV derates with as shown in Figure 45 For example the data is retained for 100 years at 55 C operation but reduces to 15 years at 85 C operation Beyond these limits the part must be reprogrammed so that the data can be restored DEVICES PERFORMANCE 5 C RETENTION Years 02739 044 Figure 45 Flash EE Memory Data Retention Rev C Page 22 of 28 APPLICATIONS BIPOLAR OPERATION FROM DUAL SUPPLIES The AD5231 can be operated from dual supplies 2 5 V which enables control of ground referenced ac signals or bipolar operation AC signals as high as Vpp Vss can be applied directly across Terminal A to Terminal B with output taken from Terminal W See Figure 46 for a typical circuit connection 2 5V AD5231 D MIDSCALE 02739 045 2 5V
35. o EEMEM T Reserved for factory testing Connect to or Vss B Terminal B of RDAC Wiper Terminal of RDAC ADDR RDAC 0x0 A Terminal A of RDAC 11 Positive Power Supply Pin Optional Write Protect Pin When active low WP prevents any changes to the present contents except PR and Instruction 1 and Instruction 8 and refreshes the RDAC register from EEMEM Execute a NOP instruction before returning to WP high Tie WP to Von if not used 13 PR Optional Hardware Override Preset Pin Refreshes the scratchpad register with current contents of the EEMEM register Factory default loads midscale 51210 until EEMEM is loaded with a new value by the user PR is activated at the logic high transition Tie PR to if not used 14 CS Serial Register Chip Select Active Low Serial register operation takes place when CS returns to logic high 15 RDY Ready Active high open drain output Identifies completion of Instructions 2 3 8 9 10 and PR 16 O2 Nonvolatile Digital Output 2 ADDR 0 1 data bit position D1 For example to store O2 high the data bit format is 0x310002 Rev C Page 8 of 28 TYPICAL PERFORMANCE CHARACTERISTICS 2 0 5V Vss 85 1 5 1 0 TA 40C T 0 5 o 0 z ui
36. of applications for these universal adjustment devices Key programming features include Scratchpad programming to any desirable values Nonvolatile memory storage of the scratchpad RDAC register value in the EEMEM register e Increment and decrement instructions for the RDAC wiper register e Left and right bit shift of the wiper register to achieve 6 dB level changes 28 extra bytes of user addressable nonvolatile memory Linear Increment and Decrement Instructions The increment and decrement instructions 14 15 6 and 7 are useful for linear step adjustment applications These commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the device For an increment command executing Instruction 14 with the proper address automatically moves the wiper to the next resistance segment position Instruction 15 ns the same function except D be Four programming instructions produce logarithmic taper increment and decrement of the wiper These settings are activated by the 6 dB increment and 6 dB decrement instructions 12 13 4 and 5 For example starting at zero scale executing the increment Instruction 12 eleven times moves the wiper in 6 dB per step from 0 to full scale Ras The 6 dB increment instruction doubles the value of the RDAC register contents each time the command is executed When the wiper position is near the maximu
37. r and Ci 5 Valid for commands that do not activate the RDY __ RDY pin low only for Instructions 2 3 8 9 10 and the PR hardware pulse 2 3 20 ms 8 1 ms 9 10 0 12 ms Device operation at TA 40 C lt 3 extends the EEMEM store time to 35 ms 7 Endurance is qualified to 100 000 cycles per JEDEC Standard 22 Method A117 and measured at 40 C 25 C and 85 C typical endurance at 25 C is 700 000 cycles 8 Retention lifetime equivalent at junction temperature T 55 C per JEDEC Standard 22 Method A117 Retention lifetime based an activation energy of 0 6 eV derates with junction temperature as shown in Figure 45 in the Flash EEMEM Reliability section Rev C Page 5 of 28 Timing Diagrams CLK CPOL 1 SDI SDO tie RDY NOT DEFINED BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED THE CPOL 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK 02739 003 Figure 3 CPHA 1 Timing Diagram 0 B23 7 ty gt HIGH OR LOW SDI B23 MSB IN SDO tie RDY DEFINED BUT NORMALLY MSB OF CHARACTER PREVIOUSLY RECEIVED THE CPOL 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK 02739 004 Figure 4 CPHA 0 Timing Diagram Rev C Page 6 of 28 ABSOLUTE MAXIMUM RATINGS T4
38. r decrement commands can be used to move the RDAC wiper up or down one step at a time The 6 dB step commands can be used to double or half the RDAC wiper setting The AD5231 is available 16 lead TSSOP The part is guaranteed to operate over the extended industrial temperature range of 40 C to 85 C One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2007 Analog Devices Inc All rights reserved TABLE OF CONTENTS Features LU LE Mer 1 Applications ien itte Ue REP RR 1 Functional Block Diagram eerte 1 General Description sissies 1 Revision History senes 2 SPECIEIGALIONS eL ELT 3 Electrical Characteristics 10 50 100 Versions 3 Timing Characteristics 10 50 100 Versions 5 Absolute Maximum Ratings eerte 7 ESD Caution ior ERR 7 Pin Configuration and Function Descriptions 8 Typical Performance Characteristics see 9 Test 13 Theory of Operation es 14 Scratchpad and EEMEM 14 Basic Operation eet tton rei rne inus 14 EEMEM 14 Daisy Chain Terminal Voltage Operation Range
39. rcuit Simulation Outline 0 5 04 0 to Rev Updated formatting eene Universal Edits to Features General Description and Block Diagram 1 Changes to Specifications tentent 3 Replaced Timing Diagrams 6 Changes to Pin Function Descriptions 8 Changes to Typical Performance Characteristics 9 Changes to Test Circuits 13 Edits to Theory of Operation see 14 Edits to Applications 23 Updated Outline 2 27 12 01 Revision 0 Initial Version Rev C Page 2 of 28 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 10 50 100 VERSIONS Vpp 3 V 1096 or 5 1096 Vss 0 V Va Vs 0 V 40 C lt lt 85 C unless otherwise noted Table 1 Parameter Symbol Conditions Min Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity R DNL Rwe Va NC monotonic 1 1 2 1 8 LSB Resistor Integral Nonlinearity R INL Rwe Va NC 0 2 402 LSB Nominal Resistor Tolerance ARas Ras D 0x3FF 40 20 Resistance Temperature Coefficient ARwe Rwe AT x 105 600 ppm C Wiper Resistance Rw 100 pA 5 5 V 15 100 Q code half scale 100 pA Voo 3 V 50 Q code half scale DC CHARACTERISTICS POTENTIOMETER DIVIDER MOD
40. s 10 version lw 50 pA for the Ras 50 and lw 25 pA for the Ras 100 version see Figure 26 and DNL are measured at Vw with the RDAC configured as a potentiometer divider similar to a voltage output DAC V4 and Vs Vss DNL specification limits of 1 LSB minimum are guaranteed monotonic operating condition see Figure 27 Resistor Terminal A Resistor Terminal B and Resistor Terminal W have no limitations on polarity with respect to each other Dual supply operation enables ground referenced bipolar signal adjustment 5 Guaranteed by design and not subject to production test Common mode leakage current is a measure of the dc leakage from any Terminal B W to a common mode bias level 2 7 EEMEM restore mode current is not continuous Current consumed while EEMEM locations are read and transferred to the RDAC register see Figure 23 To minimize power dissipation a Instruction 0 0x0 should be issued immediately after Instruction 1 0x1 8 Ppiss is calculated from lop Iss Vss All dynamic characteristics use Voo 2 5 V and Vss 2 5 V Rev C Page 4 of 28 TIMING CHARACTERISTICS 10 50 100 VERSIONS 3 V to 5 5 Vss 0 V and 40 C lt lt 85 C unless otherwise noted Table 2 Parameter Symbol Conditions Min Unit INTERFACE TIMING CHARACTERISTICS 3 Clock Cycle Time
41. s a scratchpad register allowing as many value changes as necessary to place the potentiometer wiper in the correct position The scratchpad register can be programmed with any position value using the standard SPI serial interface mode by loading the complete representative data word Once a desirable position is found this value can be stored in an EEMEM register Thereafter the wiper position is always restored to that position for subsequent power up The storing of EEMEM data takes approximately 25 ms during this time the shift register is locked preventing any changes from taking place The RDY pin pulses low to indicate the completion of this EEMEM storage The following instructions facilitate the user s programming needs see Table 7 for details 0 Do nothing Restore EEMEM content to RDAC Store RDAC Setting or user data to EE Decrement 6 dB Decrement 6 dB Decrement one step Decrement one step Reset EEMEM content to RDAC Read EEMEM content from SDO 10 Read RDAC wiper setting from SDO 11 Write data to RDAC 12 Increment 6 dB OEE 13 Increment 6 dB 14 Increment one step 15 Increment one step SCRATCHPAD AND EEMEM PROGRAMMING The scratchpad RDAC register directly controls the position of the digital potentiometer wiper For example when the scratchpad register is loaded with all zeros the wiper is connected to Terminal B of the variable resistor The scratchp
42. ta Byte 0 LSB RDAC C2 CO 0 0 0 0 X X X X X X 09 08 07 06 05 D4 D 02 DI DO C2 CO 2 015 014 013 012 011 010 DI 08 07 06 05 D4 D 02 D1 DO Command instruction codes are defined in Table 7 Table 7 Command Operation Truth Table Command Byte 0 Data Byte 1 Data Byte 0 Instruction B23 B16 B15 B8 B7 BO Number C3 2 1 2 1 X 09 D8 D7 00 Operation 0 0 0 0 0 X X X X X X X X X NOP Do nothing See Table 15 1 0 0 0 1 0 0 0 0 X ade 1X X X tea X Restore 0 contents to RDAC register This command leaves the device in the read program power state To return the part to the idle state perform NOP instruction 0 See Table 15 2 0 0 1 0 0 0 0 0 X X X X X Store Wiper Setting Store RDAC setting to EEMEM 0 See Table 14 34 0 0 1 1 2 A1 AO D15 08 D7 00 Store contents of Data Bytes 0 1 total 16 bits to EEMEM ADDR 1to ADDR 15 See Table 17 4 0 1 0 0 X X X a X Decrement RDAC by 6 dB 5 0 1 0 X X X X Same as Instruction 4 65 0 1 0 X X X X cremen position 7 X ea 8 x X X t f h EEMEM 0 value 9 1 0 X X Read WDR Oo ADDR 15 from SDO output in the next frame See Table 18 10 1 0 1 0 0 0 0 0 X X X X Read RDAC wiper setting from SDO output in the next frame See Table 19 11 1 0
43. tance of 15 Q is present Care should be taken to limit the current flow between W and B in this state to no more than 20 mA to avoid degradation or possible destruction of the internal switches Like the mechanical potentiometer that the RDAC replaces the AD5231 part is totally symmetrical The resistance between Wiper W and Terminal A also produces a digitally controlled complementary resistance Rwa Figure 44 shows the symmetrical programmability of the various terminal connections When Rwa is used Terminal B can be left floating or tied to the wiper Setting the resistance value for Rwa starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value The typical distribution of Ras from device to device matches tightly when they are processed in the same batch When devices are processed at a different time device to device matching becomes process lot dependent and exhibits a 4096 to 20 variation The change in Ras with temperature has a 600 ppm C temperature coefficient PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer can be configured to generate an output voltage at the wiper terminal that is proportional to the ti 0 v to 5 V Each SB of giis is to the voltage applied across Terminals A B divided by the 2 position resolution of the potentiometer divider Because AD5231 can also be supplied by dual supplies the general
44. tra EEMEM location USER2 Allowable to address in 14 locations with a maximum of 16 bits of data Table 14 Incrementing RDAC Followed by Storing the Table 18 Reading Back Data from Memory Locations Wiper Setting to EEMEM SDI SDO Action 0xB00100 OxXXXXXX Writes data 0x100 into RDAC register OxEOXXXX OxEOXXXX Ox20XXXX 0xB00100 OxEOXXXX OxXXXXXX Wiper W moves to 1 4 full scale position Increments RDAC register by one to 0 101 Increments RDAC register by one to 0x102 Continue until desired wiper position is reached Stores RDAC register data into 0 Optionally tie WP to GND to protect EEMEM value SDI SDO Action 0x92XXXX OxXXXXXX Prepares data read from EEMEM 2 location 0x00XXXX Ox92AAAA NOP Instruction 0 sends 24 bit word out of SDO where the last 16 bits contain the contents in the EEMEM 2 location The NOP command ensures that the device returns to the idle power dissipation state The EEME can by strobing ram Table 15 Table 15 Restoring the EEMEM Value to the RDAC Register Table 19 Reading Back Wiper Settings SDI SDO Action 0 00200 OxXXXXXX Writes RDAC to midscale OxCOXXXX 0 00200 oubl midscale to full EG OxXXXXXX 00 uction ep i iper setting from Reads back full scale value from SDO SDI SDO Action Ox10XXXX OxXXXXXX Restores the

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