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ANALOG DEVICES ADN2850 handbook

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1. Transfer contents of EEMEM ADDR to Serial Register Data Bytes 0 and 1 and previously stored data can be read out from the SDO pin See Table XIV 10 1 0 0 0 AO Transfer contents of RDAC 0 to Serial Register Data Bytes 0 and 1 and wiper setting can be read from the SDO pin See Table XV 11 1 0 0 0 9 8 7 Write contents of Serial Register Data Bytes 0 and 1 total 11 bit to RDAC A0 See Table IX 12 1 0 0 0 Increment 6 dB Left shift contents of RDAC A0 stops at all See Table XII 135 1 X X X X Xs XX X Increment 6 dB Left shift contents of all RDAC Registers stops at all Ones 145 1 0 0 0 X Increment contents of RDAC A0 by One stops at all See Table X 15 1 X X X X X XX Increment contents of all RDAC Registers by One stops at all Ones NOTES SDO output shifts out the last 24 bits of data clocked into the serial register for daisy chain operation Exception for any instruction following Instruction 9 or 10 the selected internal register data will be present in data byte 0 and 1 The instructions following 9 and 10 must also be a full 24 bit data word to completely clock out the contents of the serial register
2. ADN2850 positive and negative power supply defines the boundary conditions for proper two terminal program mable resistance operation Supply signals present on terminals W and B that exceed Vpp or Vss will be clamped by the internal forward biased diodes see Figure 7 Vpp Vss Figure 7 Maximum Terminal Voltages Set by Vpp Vss The ground pin of the ADN2850 device is primarily used as a digital ground reference that needs to be tied to the PCB s common ground The digital input control signals to the ADN2850 must be referenced to the device ground pin GND and satisfy the logic level defined in the Specifications table of this data sheet An internal level shift circuit ensures that the common mode voltage range of the two terminals extends from Vss to Vpp regardless of the digital input level In addition there is no polarity constraint on voltage across terminals magnitude of is by Power Up Sequence r Since diodes limit the voltage compliance at terminals B and W see Figure 7 it is important to power Vpp Vss first before apply ing any voltage to terminals B and W Otherwise the diode will be forward biased such that Vpp Vss will be powered unintentionally For example applying 5 V across Vpp will cause the Vpp terminal to exhibit 4 3 V Although it is not destructive to the device it may affect the rest of the user s system As a result the ideal power
3. 18 I REV 19 8 20 6 0 099202 ww com V S T1 NI GALNIYd 20
4. 8 1 ms CMD 9 10 0 1 ms 2 3 20 ms Device operation at T4 40 C and Vpp lt 3 V extends the save time to 35 ms 15 Endurance is qualified to 100 000 cycles per Std 22 method A117 and measured at 40 C 25 C and 85 C typical endurance at 25 C is 700 000 cycles 16 Retention lifetime equivalent at junction temperature 55 C as per Std 22 Method A117 Retention lifetime based on an activation energy of 0 6 V will derate with junction temperature Specifications subject to change without notice The ADN2850 contains 16 000 transistors Die size 93 mil X 103 mil 10 197 sq mil REV B 3 ADN2850 TIMING DIAGRAMS cs 1 CLK CPOL 1 Spo SDI RDY NOT DEFINED BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED THE CPOL 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK CLK CPOL 0 Spo SDI ta RDY NOT DEFINED BUT NORMALLY MSB OF CHARACTER JUST RECEIVED Figure 2a CPHA 1 Timing Diagram THE CPOL 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK Figure 2b 0 Timing Diagram REV B ADN2850 ABSOLUTE MAXIMUM RATINGS Thermal Resistance Junction to Ambient 25 C unless otherwise noted EPCSP L6 5 2 mcer ataw wiy eos woah en bs 35 C W Vpp tO
5. EEMEM for saving constants and other 16 bit data Table V provides an address map of the internal storage registers shown in the functional block diagram as EEMEM1 EEMEM2 and and 26 bytes 13 addresses X 2 bytes each of USER EEMEM Table V EEMEM Address Map EEMEM Number Address EEMEM Content For 1 0000 RDAC1 2 2 0001 RDAC2 3 0010 USER1 4 0011 USER2 15 1110 USERI3 16 1111 Tolerance NOTES RDAC data stored in EEMEM locations are transferred to their corresponding RDAC REGISTER at power on or when instructions 1 8 and PR are executed Execution of instruction 1 leaves the device in the read mode power consumption state After the last instruction 1 is executed the user should perform a NOP instruction 0 to return the device to the low power idling state 3USER data are internal nonvolatile EEMEM registers available to store and retrieve constants and other 16 bit information using instructions 2 and 9 respectively Read only Calculating Actual Full Scale Resistance The actual tolerance of the rated full scale resistance Ry is stored in EEMEME register 15 during factory testing The actual re be calculated which will be valuable for tolerance matching or calibration Notice this value is read only and the full scale resistance of Ryp gs matches rs of typically 0 1 The tolerance in is stored in the last 16 bits of data in EEMEM register 15 The format is sign magnitude b
6. Figure 12 shows such a conceptual circuit I 11 VT COMPENSATION 1 100k Rg x V4 T LOG AVERAGE POWER 1 1 1 1 1 1 1 1 1 1 1 1 c 1 THERMISTOR 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 12 Conceptual Incoming Optical Power Monitoring Circuit 16 REV B ADN2850 The output voltage represents the average incoming optical power The output voltage of the log stage does not have to be accurate from device to device as the responsivity of the photodiode will change between devices An op amp stage is shown after the log amp stage which compensates for Vr variation over temperature Equation 4 is ideal If the reference current is 1 mA at room temperature characterization shows that there is an additional 30 mV offset between V2 and V A curve fit approximation yields 01 V V 0 026 5 PD Such offset is believed to be caused by the transistors self heating and the thermal gradient effect As seen in Figure 13 the error between an approximation and the actual performance ranges is less than 0 to 4 from 0 1 mA to 0 1 pA ERROR 1 E 06 1 E 05 1 E 04 Ipp A Figure 13 Typical V V vs lpp at 1 mA and TA 25 C Resistance Scaling The ADN2850 offers either 25 or 250 full scale resistance Users who need lower resistance and st
7. Operation Number 823 BlS B8 7 BO C2 CO A2 Al A0 X 0908 7 0 0 0 0 0 X X X X IX XX X Do nothing See Table XI for Programming example 1 0 0 0 0 AO X Retrieve contents of EEMEM A0 to RDAC A0 Register This command leaves device in the Read Program power state To return part to the idle state perform NOP instruction 0 See Table XI 2 0 0 00 AO SAVE WIPER SETTING Write contents of RDAC AO to EEMEM AO See Table X 34 0 A3 2 Al AO D15 D8 D7 D0 Write contents of Serial Register Data Bytes 0 and 1 total 16 bit to EEMEM ADDR See Table XIII 4 0 0 0 0 0 X Decrement 6 dB Right shift contents of RDAC A0 Register stops at all Zeros 55 0 X X X X as M X Decrement 6 dB Right shift contents of all RDAC Registefs stops at J Zeros 6 0 0 1 IT AO Xr X Decrement contents of RDAC A0 by One stops at all Zeros 1 0 X X X X X XX XKeeeee X Decrement contents of all Registers by One stops at all Zeros 8 1 X X X X X XX RESET Load all RDACSs with their corresponding EEMEM previously saved values 9 1 A2 Al AO X XX
8. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding nonvolatile EEMEM register Execution of the above operations takes place when the CS strobe returns to logic high Instruction 3 writes 2 data bytes total 16 bit to EEMEM But in the cases of addresses 0 and 1 only the last 10 bits are valid for wiper position setting gt The increment decrement and shift commands ignore the contents of the shift register data bytes 0 and 1 REV n ADN2850 OPERATIONAL OVERVIEW The ADN2850 programmable resistor is designed to operate as a true variable resistor The resistor wiper position is determined by the RDAC register contents The RDAC register acts as a scratch pad register which allows unlimited changes of resistance settings The scratch pad register can be programmed with any position setting using the standard SPI serial interface by loading the 24 bit data word The format of the data word is that the first 4 bits are instructions the following 4 bits are addresses and the last 16 bits are data Once a specific value is set this value can be saved into a corresponding EEMEM register During subsequent power ups the wiper setting will automatically be loaded at that value Saving data to the EEMEM takes about 25 ms and con sumes approximately 20 mA During this time the shift register is locked preventing any changes from taking place The RDY pin indicates the completion of
9. Bx 1 MHz measured to GND Code Half scale 11 pF Capacitance Wx Cw f 1 MHz measured to GND Code Half scale 80 pF Common Mode Leakage Current Vw Vpp 2 0 01 t2 uA DIGITAL INPUTS AND OUTPUTS Input Logic High Vin With respect to GND Vpp 5 V 2 4 V Input Logic Low With respect to GND Vpp 5 V 0 8 V Input Logic High With respect to GND Vpp 3 V 24 V Input Logic Low With respect to GND Vpp 3 V 0 6 V Input Logic High With respect to GND 2 5 V Vss 52 5 V a 240 V Input Logic Low Vir Whth respect to GND 742 5 VN os 22 5 05 Output Logic High SDO RDY 2 2 to 5 V 4 9 V Output Logic Low VoL 1 6 mA Vrogic 5 V 0 4 V Input Current Ig Vin 0 V or 2 25 uA Input Capacitance Cm 5 pF POWER SUPPLIES Single Supply Power Range Vss 0 V 3 0 5 5 V Dual Supply Power Range Vpp Vss 2 25 2 75 V Positive Supply Current Ipp or GND 25 2 4 5 uA Positive Supply Current Ipp Vpp GND 3 5 6 0 uA Programming Mode Current Vpp GND 35 mA Read Mode Current Ippxrg Vin Vpp or Vir GND 0 3 3 9 mA Negative Supply Current Iss Vig Vpp or Vy GND Vpp 2 5 V Vss 2 5 V 3 5 6 0 uA Power Dissipation Ppiss Vpp or Vy GND 18 50 Power Supply Sensitivity Pss AVpp 5 V 10 0 002 0 01 CURRENT MONITOR TERMINALS
10. Vpp Vss 5V 0V Ran 25 FULL SCALE TPC 5 Ipp vs Temperature Rag 25 MIDSCALE XL ZERO SCALE 0 0 0 00 2 0 06 4 0 06 6 0E 06 8 0E 06 1 0 07 1 2 07 FREQUENCY Hz TPC 6 vs Clock Frequency Rag 25 ADN2850 nA 100 25 Ta 25 O 5V DIV lt to 10 o z 5 T sa 5 VALUE 2 Rws fs 7 504S DIV B Rwg rs 250 0 7 Memory Restore During Power On Reset 0 01 0 128 256 384 512 640 76 896 1024 CODE Decimal TPC 10 MAX vs Code TEST CIRCUITS E Test Circuits 1 to 3 show some of the test conditions used in the Specifications table 4ms DIV TPC 8 lpp vs Time Save Program Mode NC T fest Circuit 1 Resistor Position Nonlinearity Error Rheostat Operation R INL R DNL HI 4ms DIV SUPPLY CURRENT RETURNSTO MINIMUM POWER CONSUMPTION IF INSTRUCTION 0 NOP IS EXECUTED IMMEDIATELY AFTER INSTRUCTION 1 READ EEMEM TPC 9 vs Time Read Program Mode O Vpp DUT NC NO CONNECT Test Circuit 3 Common Mode Leakage Current 14 REV B ADN2850 Table XII Using Left Shift by One to Increm
11. 1 74 4 1 LSB 0 50 Zero Scale Wiper contact resistance Note that in the zero scale condition a finite wiper resistance of 50 Q is present In this state care should be taken to limit the current flow between W and B to no more than 20 mA to avoid degradation or possible destruction of the internal switches Channel to channel matching is well within 1 at full scale The change in with temperature has a 35 ppm C temperature coefficient NAL REV Typical Performance Characteristics ADN2850 10 25 40 0 8 85 0 6 m o m 0 4 t 0 2 tr E z 0 0 2 0 4 0 6 200 400 600 800 1000 DIGITAL CODE TPC 1 R INL vs Code TA 40 C 25 85 C Overlay Rag 25 kQ R DNL ERROR LSB DIGITAL CODE 2 R DNL vs Code TA 40 25 85 C Overlay Rag 25 Vpp Vss 5 0V 0V 25 RHEOSTAT MODE TEMPCO ppm C 0 128 256 384 512 640 768 896 1023 CODE Decimal TPC 3 Rheostat Mode Tempco REV 13 CURRENT pA mA 0 200 400 600 800 1000 1200 CODE TPC 4 Wiper On Resistance vs Code V pp Vss 5V 0V Iss V pp Vss 5V 0V 40 20 0 20 40 60 80 100 TEMPERATURE
12. PROCESSOR AND ADDRESS DECODE COUNTER A RpuLLUP Figure 5 Equivalent Digital Input Output Logic Vpp Figure 6b Equivalent WP Input Protection SERIAL DATA INTERFACE The ADN2850 contains a 4 wire SPI compatible digital inter face SDI SDO CS and CLK The 24 bit serial word must be loaded with MSB first and the format of the word is shown in Table I The Command to C3 control the operation of the programmable resistor according to the instruction shown in Table II AO to A3 are assigned for address bits AO is used to address RDACI or RDAC2 Addresses 2 to 14 are accessible by users Address 15 is reserved for the factory Table V provides an address map of the EEMEM locations The data bits DO to D9 are the values that are loaded into the RDAC registers at instruc tion 11 The data bits DO to D15 are the values that are loaded into the EEMEM registers at instruction 2 The last instruction prior to a period of no programming activity should be applied with the No Operation NOD instruction 0 It is recommended to do so to ensure minimum power consumption in the internal logic circuitry The SPI interface can be used in two slave modes CPHA 1 CPOL 1 and CPHA 0 CPOL 0 CPHA and CPOL refer to the control bits that dictate SPI timing in these microconverters and microprocessors ADuC812 ADuC824 M68HC11 and 68 16 1 916 1 REV B ADN2850 TERMINAL VOLTAGE OPERATING RANGE
13. WP command Table III provides a programming example listing the sequence of serial data input SDI words and the corresponding serial data output SDO in hexadecimal format Table III Set and Save RDAC with Independent Data to EEMEM Registers SDI SDO Action 00100 Loads data 100 into RDACI register Wiper W1 moves to 1 4 full scale position 20 00100 Saves of RDACI register content into corresponding EEMEM I register 10200 20 Loads 200 data into RDAC2 register Wiper W2 moves to 1 2 full scale position 21 10200 Saves copy of RDAC2 register contents into corresponding EEMEM2 register At system power the scratch pad register is automatically refreshed with the value previously saved in the corresponding register The factory preset EEMEM value is midscale During operations the scratch pad register can also be refreshed with the current contents of the EEMEM registers in three different ways First executing instruction 1 retrieves the corresponding EEMEM value Second executing instruction 8 resets the EEMEM values of both channels Finally pulsing the PR pin also refreshes both EEMEM settings Operating the hardware control PR function however requires a complete pulse signal When PR goes low the internal logic sets the wiper at midscale The EEMEM value will not be loaded until PR returns to high EEMEM Pro
14. each time the command is executed When the wiper position is near the maximum setting the last 6 dB increment instruction will cause the wiper to go to the full scale 1023 code position Further 6 dB per increment instruction will no longer change the wiper position beyond its full scale Table IV 6 dB step increment and decrement are achieved by shifting the bit internally to the left and right respectively The following infor mation explains the nonideal 6 dB step adjustment at certain 8 REV B ADN2850 conditions Table IV illustrates the operation of the shifting function on the individual RDAC register data bits Each line going down the table represents a successive shift operation Note that the left shift 12 and 13 commands were modified such that if the data in the RDAC register is equal to zero and the data is left shifted the RDAC register is then set to code 1 Similarly if the data in the RDAC register is greater than or equal to midscale and the data is left shifted then the data in the RDAC register is automatically set to full scale This makes the left shift function as ideal a logarithmic adjustment as possible The right shift 4 and 5 commands will be ideal only if the LSB is zero i e ideal logarithmic no error If the LSB is a one then the right shift function generates a linear half LSB error which translates to a number of bits dependent logarithmic error as shown in Figure 3 The plot shows the
15. error of the odd numbers of bits for ADN2850 Table IV Detail Left and Right Shift Functions for 6 dB Step Increment and Decrement Left Shift Right Shift 00 0000 0000 00 0000 0001 00 0000 0010 00 0000 0100 00 0000 1000 11 1111 1111 01 1111 1111 00 1111 1111 00 0111 1111 00 0011 1111 Left Shit 000001 0000 000001 1111 Right Shift 6 dB step 00 0010 0000 000000 1111 6 dB step 00 0100 0000 1000000 0111 1000 0000 000000 0011 01 0000 0000 10 0000 0000 11 1111 1111 11 1111 1111 00 0000 0001 00 0000 0000 00 0000 0000 00 0000 0000 full scale resistance can there Actual conformance to a logarithmic curve between the data con tents in the RDAC register and the wiper position for each right shift 4 and 5 command execution contains an error only for odd numbers of bits Even numbers of bits are ideal The graph in Figure 3 shows plots of Log Error 20 X logy error code ADN2850 For example code 3 Log Error 20 X logio 0 5 3 15 56 dB which is the worst case The plot of Log Error is more significant at the lower codes 0 dB 80 0 01 02 03 04 05 06 07 08 09 10 1 1 CODE From 1 to 1023 2 0 x 103 Figure 3 Plot of Log_Error Conformance for Odd Numbers of Bits Only Even Numbers of Bits Are Ideal REV Using Additional Internal Nonvolatile ADN2850 contains additional internal user storage registers
16. 023 CODE Decimal Figure 1 vs Decimal Code The linear step increment and decrement commands enable the setting in the RDAC register to be moved UP or DOWN one step at a time For logarithmic changes in wiper setting a left right bit shift command adjusts the level in 6 dB steps The ADN2850 is available in the 5 mm X 5 mm 16 lead frame chip scale LFCSP and thin 16 lead TSSOP packages All parts are guaranteed to operate over the extended industrial temperature range of 40 C to 85 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2002 ADN2850 SPECIFICATIONS Voo 3 V to 5 5 V and 40 lt T lt 85 C ELECTRICAL CHARACTERISTICS 25 250 VERSIONS otherwise noted Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all RDACs Resistor Differential Nonlinearity R DNL 2 2 LSB Resistor Integral Nonlinearity R INL 4 4 LSB Resistance Temperature Coefficient 35 ppm C Wiper Resistance Rw Vpp 5 V Iw 100 uA Code Half scale 50 100 Q Vpp 3 V 100 Code Half scale 200 Q Channel Resistance Matching ARws Rwg 1 and 2 Dx 0 1 Nominal Resistor Tolerance ARwg 30 30 RESISTOR TERMINALS Terminal Voltage Range Vw Vss Vpp V Capacitance
17. ANALOG DEVICES Nonvolatile Memory Dual 1024 Position Programmable Resistors ADN2850 FEATURES Dual 1024 Position Resolution 25 250 Full Scale Resistance Low Temperature Coefficient 35 ppm C Nonvolatile Memory Preset Maintains Wiper Settings Permanent Memory Write Protection Wiper Settings Read Back Actual Tolerance Stored Linear Increment Decrement Log Taper Increment Decrement SPI Compatible Serial Interface 3 V to 5 V Single Supply or 2 5 V Dual Supply 26 Bytes User Nonvolatile Memory for Constant Storage Current Monitoring Configurable Function 100 Year Typical Data Retention T4 55 APPLICATIONS SONET SDH ATM Gigabit Ethernet DWDM Laser Diode Driver Optical Supervisory Systems GENERAL DESCRIPTION The ADN2850 provides dual channel digitally controlled program mable resistors with resolution of 1024 positions These devices perform the same electronic adjustment function as a mechanical rheostat with enhanced resolu NA reliability and superior low temperature coefficient performance The ADN2850 s versatile programming via a standard serial interface allows 16 modes of operation and adjustment including scratch pad pro gramming memory storing and retrieving increment decrement log taper adjustment wiper setting readback and extra user defined EEMEM Another key feature of the ADN2850 is that the actual tolerance is stored in the EEMEM The actual full s
18. Current Sink at Vj L 0 0001 10 mA Current Sink at V L 10 mA DYNAMIC CHARACTERISTICS 10 Resistor Noise Spectral Density WB Ryp rs 25 250 f 1 kHz 20 64 nV VHz Analog Crosstalk Cw Cw2 Cr Vg Vg 0 V Measured with Vw2 100 mV p p f 100 kHz Code 1 Code 2 200g 65 2 REV ADN2850 Parameter Symbol Conditions Min Typ Unit INTERFACE TIMING CHARACTERISTICS apply to all parts 1 Clock Cycle Time tcyc ti 20 ns CS Setup Time ty 10 ns CLK Shutdown Time to CS Rise t 1 Input Clock Pulsewidth ty ts Clock Level High or Low 10 ns Data Setup Time 16 From Positive CLK Transition 5 ns Data Hold Time t From Positive CLK Transition 5 ns CS to SDO SPI Line Acquire ts 40 ns CS to SDO SPI Line Release to 50 ns CLK to SDO Propagation Delay tio Rp 2 2 kQ Cr lt 20 pF 50 ns CS High Pulsewidth ti2 10 ns CS High to CS High 4 tcyc RDY Rise to CS Fall 14 0 ns CS Rise to RDY Fall Time 55 0 15 0 3 ms Read Store to Nonvolatile EEMEM Applies to Command 2 9 35 ms CS Rise to Clock Edge Setup 017 10 ns Preset Pulsewidth Asynchronous tprw Not Shown in Timing Diagram 50 ns Preset Response Time to Wiper Setting tprgsp PR Pulsed Low to Refresh 140 us Wiper Positions FLASH EE MEMORY RELIABILITY Endurance 100 K Cycles Data Retention 100 Years NOTES 1 Parts can be operated at 2 7 V single supply except from 08C to 408C where minimu
19. DAC1 and RDAC2 registers respectively REV Analog Devices offers a user friendly ADN2850EVAL evaluation kit that can be controlled by a personal computer through the printer port The driving program is self contained so no programming languages or skills are needed 15 ADN2850 APPLICATIONS Optical Transmitter Calibration with ADN2841 Together with the multirate 2 7 Gbps Laser Diode Driver ADN2841 the ADN2850 forms an optical supervisory system where the dual programmable resistors are used to set the laser average optical power and extinction ratio see Figure 11 The ADN2850 is particularly ideal for the optical parameter settings because of its high resolution compact footprint and superior temperature coefficient characteristics The ADN2841 is a 2 7 Gbps laser diode driver that uses a unique control algorithm to manage both the laser average power and extinction ratio after the laser initial factory calibration It stabilizes the laser data transmission by continuously monitoring its optical power and correcting the variations caused by temperature and the laser degradation over time In the ADN2841 the Iypp monitors the laser diode current Through its dual loop power and extinction ratio control calibrated by the ADN2850 the internal driver controls the bias current and consequently the average power It also regulates the modulation current Iyopp by changing the modulation current linearly with slope eff
20. GND s ice eerie es REIR NOE s 0 3 V 7 V 155 16 p aot ed 150 C W Ves tO GND anes Bole Za yapukuy Pe 0 3 7 V Thermal Resistance Junction to Case Vip tO iV ss ccs Za raw Satan ed Te aN Mote ee ieee e oct m AL dom 28 C W to GND u a Vss 0 3 V Vpp 0 3 V Package Power Dissipation Ty MAX NOTES Intermittent BRACE EORUM SOT TEM NER BLS 20 mA Stresses above those listed under Absolute Maximum Ratings may cause perma COtitinUOUS uqa as CHR REUS RAE ES dua 2mA nent damage to the device This is a stress rating functional operation of the device Digital Inputs and Output Voltage at these or any other conditions above those listed in the operational sections of this to GND oder 0 3 V Vpp 0 3 V specification is not implied Exposure to absolute maximum rating conditions for 3 extended periods may affect device reliability Op erating Temperature Range 40 to T Maximum terminal current is bounded by the maximum current handling of the Maximum Junction Temperature max 150 switches maximum power dissipation of the package and maximum applied Storage Temperature 65 to 150 voltage across any two of the and W terminals at a given resistance Lead Temperature Soldering Includes programming of nonvolatile memory Va
21. Negative Supply Connect to zero volts for 6 Bl B terminal of RDAC1 single supply applications 7 B2 B terminal of RDAC2 6 Log Output Voltage 1 generated from internal 8 W2 Wiper terminal of RDAC2 ADDR diode configured transistor RDAC2 7 Wi Wiper terminal of RDAC1 ADDR 9 Log Output Voltage 2 generated from internal RDACI Og diode configured transistor 8 Bl B terminal of RDACI 10 Vpp Positive Power Supply Pin 9 B2 B terminal of RDAC2 11 WP Write Protect Pin When active low WP 10 W2 Wiper terminal of RDAC2 ADDR prevents any changes to the present register RDAC2 1 contents except PR and CMD 1 and CMD 8 11 V Log Output Voltage 2 generated from internal will refresh the RDAC register from EEMEM diode configured transistor Execute a NOP instruction before returning 12 Vpp Positive Power Supply Pin n to WP high 13 WP Write Protect Pin When active low WP prevents 12 PR Hardware Override Preset Pin Refreshes the any changes to the present contents except PR scratch pad register with current contents of and CMD 1 and CMD 8 will refresh the the EEMEM register Factory default loads RDAC register from EEMEM Execute a NOP midscale 51210 until EEMEM loaded with instruction before returning to WP high new value by the user PR is activated at 14 PR Hardware Override Preset Pin Refreshes the NE the logic high transition scratch pad register with current contents of 13 CS Serial Register chip s
22. as 1024 connection points allowing it to provide better than 0 1 setability resolution Figure 9 shows an equivalent structure of the connections between the two terminals that make up one channel of the RDAC The Syg will always be ON while one of the switches SW 0 to SW 2 1 will be ON one at a time depending on the resistance position decoded from the data bits Since the switch is not ideal there is a 50 Q wiper resistance Ry Wiper resistance is a function of supply voltage and temperature The lower the supply voltage or the higher the temperature the higher the resulting wiper resistance Users should be aware of the wiper resistance dynamics if accurate prediction of the output resistance is needed SW 2N 1 RDAC WIPERL REGISTER AND DECODER Rs Rwg 2N DIGITAL CIRCUITRY OMITTED FOR CLARITY Figure 9 Equivalent RDAC Structure Table VII Nominal Individual Segment Resistor Values Device Resolution 25 250 1024 Step 24 4 244 CALCULATING THE PROGRAMMABLE RESISTANCE The nominal full scale resistance of the RDAC between terminals W and B is available with 25 and 250 with 1024 positions 10 bit resolution The final digits of the part number determine the nominal resistance value e g 25 25 and 250 kQ 250 The 10 bit data word in the RDAC latch is decoded to select one of the 1024 possible settings The following discussion describes the calculation of
23. cale resistance can therefore be known which is valuable for tolerance matching and calibration In the scratch pad programming mode a specific setting can be programmed directly to the RDAC register which sets the resis tance between terminals W and B The RDAC register can also be loaded with a value previously stored in the EEMEM register The value in the EEMEM can be changed or protected When changes are made to the RDAC register the value of the new setting can be saved into the EEMEM Thereafter such value will be transferred automatically to the RDAC register during system power ON which is enabled by the internal preset strobe EEMEM can also be retrieved through direct programming and external preset pin control Patent pending NOTES The term nonvolatile memory and EEMEM are used interchangeably The term programmable resistor and RDAC are used interchangeably REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM ADN2850 SERIAL INTERFACE h CURRENT MONITOR 26 BYTES USER EEMEM 100 RwB D 96 of Full Scale RwB a m 0 256 512 768 1
24. eer ESD SENSITIVE DEVICE REV B ADN2850 PIN CONFIGURATIONS Spo GND ADN2850BCP Vss CHIP SCALE Vi PACKAGE ADN2850BCP PIN FUNCTION DESCRIPTIONS TOP VIEW Not To Scale ADN2850BRU PIN FUNCTION DESCRIPTIONS Pin Pin No Mnemonic Description No Mnemonic Description 1 SDO Serial Data Output Pin Open Drain output 1 CLK Serial Input Register Clock Pin Shifts in requires external pull up resistor CMD_9 and one bit at a time on positive clock edges CMD_10 activate SDO output See 2 SDI Serial Data Input Pin Shifts in one bit at Instruction Operation Truth Table Table ID a time on positive clock CLK edges Other commands shift out the previously MSB loaded first loaded SDI bit pattern delayed by 24 clock 3 SDO Serial Data Output Pin Open drain out put pulses This allows daisy chain operation of requires external pull up resistor CMD_9 multiple packages and CMD_10 activate the SDO output See 2 GND Ground Pin logic ground reference Instruction Operation Truth Table Table ID 3 Vss Negative Supply Connect to zero volts for Other commands shift out the previously single supply applications loaded SDI bit pattern delayed by 24 clock 4 Vi Log Output Voltage 1 generated from internal pulses This allows daisy chain operation of diode configured transistor T multiple packages 5 Wl Wiper terminal RDAG1 ADDR 4 GND Ground Pin ground reference RDACI 7 Vss
25. elect active low the EEMEM register Factory default loads Serial register operation takes place when midscale 51210 until EEMEM loaded with a CS returns to logic high new value by the user PR is activated at the 14 Ready Active high open drain output Identifies logic high transition completion of commands 2 3 8 9 10 and PR 15 CS Serial Register chip select active low Serial 15 Serial Input Register Clock Pin Shifts register operation takes place when CS returns one bit at a time on positive clock edges to logic high 16 SDI Serial Data Input Pin Shifts in one bit at a time 16 RDY Ready Active high open drain output Identifies on positive clock CLK edges MSB loaded first completion of commands 2 3 8 9 10 and PR REV ADN2850 Table I 24 Bit Serial Data Word MSB Instruction Byte 0 Data Byte 1 Data Byte 0 LSB RDAC C2 Cl CO 0 0 0 0 X X X X X D6 05 D4 D3 D2 D1 DO EEMEM C3 C2 CO A2 0 1015 014 013 012 010 D9 07 D6 05 04 D3 D2 D1 DO Command bits are CO to C3 Address bits are 0 Data bits DO to D9 are applicable to RDAC wiper register whereas DO to 015 are applicable to EEMEM Register Command instruction codes are defined in Table II Table II Instruction Operation Truth Table Inst Instruction Byte 0 Data Byte 1 Data Byte 0
26. ent 6 dB Steps PROGRAMMING EXAMPLES The following programming examples illustrate the typical sequence of events for various features of the ADN2850 Users should refer to Table II for the instructions and data word format The instruc tion numbers addresses and data appearing at SDI and SDO pins are displayed in hexadecimal format in the following examples Table IX Scratch Pad Programming SDI SDO Action 00100 Loads data 100 into RDACI register Wiper W1 moves to 1 4 full scale position 10200 00100 Loads data 200 into RDAC2 register Wiper 2 moves to 1 2 full scale position Table X Incrementing RDAC Followed by Storing the Wiper Setting to EEMEM SDI SDO Action 00100 Loads data 100 into register Wiper W1 moves to 1 4 full scale position EOXXXXg B00100g Increments RDACI register by one to 101g Increments RDACI register by one to 1026 Repeat the increment command until desired wiper position is reached 20XXXXy NAT Adata into KEMEM WP GND_t0 protect EEMEM values Table XI Restoring EEMEM Values to RDAC Registers EEMEM values for RDACs can be restored by Power On Strobing PR pin or Programming shown below SDI SDO Action Moves wiper 1 to double the present data con
27. iciency Any changes in the laser threshold current or slope efficiency are therefore com pensated As a result this optical supervisory system minimizes the laser characterization efforts and enables designers to apply com parable lasers from multiple sources Incoming Optical Power Monitoring The ADN2850 comes with a pair of matched diode connected PNPs Q and that can be used to configure an incoming optical power monitoring function With a reference current source an instrumentation amplifier and 41994 antplifier this feature be used to monitor the optical VAS by knowing the dc average photodiode current from the following relationships I V 2 V 3 15 ADN2850 LOG AMP Vcc Vcc ADN2850 IMPD ADN2841 DIN DINQ IDTONE Figure 11 Optical Supervisory System Knowing Ic a X Ico a X and Q are matched therefore a and Is are matched Combining Equations 2 and 3 theoretically yields V V V In e 4 Ipp Where Is and Is are saturation current Vi V are Vgg base emitted voltages of the diode connector transistors Vr is thesthermalgvoltage which 15 I to k x T q Vr 26 mV at25 k Boltzmann s constant 1 38E 23 Joules Kelvin q electron charge 1 6E 19 coulomb T temperature in Kelvin photodiode current Iger reference current
28. ill maintain the numbers of step adjustment can parallel two or more devices Figure 14 shows a simple scheme of paralleling both channels of the pro grammable resistors In order to adjust half of the resistance linearly per step users need to program both devices coherently with the same settings Note that since the devices will be pro grammed one after another an intermediate state will occur and this method may not be suitable for certain applications REV B Figure 14 Reduce Resistance by Half with Linear Adjustment Characteristics Much lower resistance can also be achieved by paralleling a discrete resistor as shown in Figure 15 B1 Figure 15 Resistor Scaling with Pseudo Log Taper Adjustment Characteristics The equivalent resistance at a given setting is approximated as Dx ps 51200 Dx rs 51200 1024 R 6 In this approach the adjustment is not linear but pseudo logarithmic Users should be aware of the need for tolerance matching as well as temperature coefficient matching of the components BASIC RDACSPICE MODEL RDAC 25 B 11pF Cw 80 w Figure 16 RDAC Circuit Simulation Model RDAC 25 The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RADCs A general parasitic simulation model is shown in Figure 16 Listing I provides a macro model net list for the 25 Listing I Macro Mode
29. inary format with the MSB designates for sign 0 positive and 1 negative the next 7 MSB designate for the integer number and the 8 LSB designate for the decimal number See Table VI Table VI Tolerance in from Rated Full Scale Resistance D7 06 05 D4 03 D2 01 DO 271 2 2 23 2 4 2 5 2 6 2 7 28 Bit 15 14 13 012 011 010 09 08 sign magkign 26 25 24 23 22 21 20 Sign 7 Bits for Integer Number Decimal Point _ 8 Bits Decimal Number For example if rs 250 and the data is 0001 1100 0000 1111 rs AcTUAL can be calculated as follows MSB 0 Positive Next 7 MSB 001 1100 28 8 LSB 0000 1111 15 x 2 0 06 Tolerance 28 06 Thus rs ACTUAL 320 15 ADN2850 Daisy Chain Operation The serial data output pin SDO serves two purposes It can be used to read out the contents of the wiper settings or EEMEM values using instructions 10 and 9 respectively If these instruc tions are not used SDO can be used for daisy chaining multiple devices in simultaneous operations see Figure 4 The SDO pin contains an open drain N Ch FET and requires a pull up resis tor if SDO function is used Users need to tie the SDO pin of one package to the SDI pin of the next package Users may need to increase the clock period because the pull up resistor and the capacitive loading at the SDO SDI interface may induce time delay
30. l Net List for RDAC PARAM D 1024 25E3 SSUBCKT W B RWB W B 0 1024 50 CW W 0 80E 12 CB B 0 11E 12 ENDS RDAC 17 ADN2850 OUTLINE DIMENSIONS 16 Lead Frame Chip Scale Package LFCSP 5 5 Body 16 5 5 Dimensions shown in millimeters PIN1 INDICATOR 3 25 3 10 i nf 2 95 0 70 MAX e F 2 40 BSC 12 MAX ACE je 0 65 NOM 0 05 MAX 0 01 NOM 0 90 0 85 540 0 33 0 20REF COPLANARITY SEATING 028 PLANE COMPLIANT JEDEC STANDARDS MO 220VHHB 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 Dimensions shown in millimeters oss m BSC 0 19 SEATING COPLANARITY PLANE 0 10 COMPLIANT TO JEDEC STANDARDS MO 153AB 18 0 60 PIN 1 0 60 MAX INDICATOR 13 4 REV ADN2850 Revision History Location Page 9 02 Data sheet changed from REV A to REV Changes GENERAL DESCRIPTION C an e RR ex SRE Y 1 Changes to ELECTRICAL CHARACTERISTICS 2 Changes to Calculating Actual Full Scale Resistance section 9 Changes to Fable VI v Re Rer Re ata oe a eg ao ec Planar eoa Seng 9 Updated OUTLINE DIMENSIONS oe RC RE CET RC aed ICA EROR
31. m 3 V is needed Typicals represent average readings at 258C and Vpp 5 V Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions R DNL measures the relative step change from ideal between suecessivejtap positions Iy 50 for 572 7 Wandriwssq400 for Vpp 5 V Resistor terminals W and limitations polarity with r spect to each other gt Guaranteed by design and not subject to pfoduction test i Common mode leakage current is a measure of A dc leakage from any terminal B find W to a common mode bias level of V pp 2 1 Transfer XFR mode current is not continuous Current consumed while EEMEM locations are read and transferred to the RDAC register See TPC 9 8 Pprss is calculated from Ipp X Vpp Iss X Vss 9 Applies to photodiode of optical receiver 10 All dynamic characteristics use 2 5 V and Vss 2 5 V 11 See timing diagram for location of measured values All input control voltages are specified with tg tp 2 5 ns 10 to 90 of 3 V and timed from a voltage level of 1 5 V Switching characteristics are measured using both Vpp 3 V and 5 V 12 Propagation delay depends on value of Vpp Rpurr and See Applications section 13 Valid for commands that do not activate the RDY pin RDY pin low only for commands 2 3 8 9 10 and PR hardware pulse
32. por Phase 60 sec 215 Applicable to TSSOP 16 only For LFCSP 16 please consult factory for details Infrared 15 seC iem p ale dase 220 C ORDERING GUIDE Rws Temperature Package Package Ordering Model LSB LSB Range Description Option Quantity Top Mark ADN2850BCP25 25 2 4 40 85 LFCSP 16 CP 16 96 BCP25 ADN2850BCP25 RL7 25 2 4 40 85 LFCSP 16 CP 16 1 000 25 7 Reel ADN2850BCP250 250 2 4 40 85 LFCSP 16 CP 16 96 BCP250 ADN2850BCP250 RL7 250 2 4 40 t k85 LFCSP 16 16 1 000 250 i V7 ADN2850BRU25 E 4 40 to 85 TSSOP 16 16 96 2850 25 ADN2850BRU25 RL7 25 2 4 40 to 85 TSSOP 16 RU 16 1 000 2850B25 7 Reel Line 1 contains product number ADN2850 line 2 Top Mark branding contains differentiating detail by part type line 3 contains lot number line 4 contains product date code YYWW CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the ADN2850 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING
33. resistance Rwp D at different codes of a 25 part The wiper s first connection starts at the B terminal for data 000 0 is 50 Q because of the wiper resistance and it is independent of the full scale resistance The second connection is the first tap point where Ryg 1 becomes 24 4 Q 50 74 4 Q 11 ADN2850 for data 001g The third connection is the next tap point represent ing 2 48 8 50 98 8 Q for data 002 and so on Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 1023 25026 Q See Figure 9 for a simplified diagram of the equivalent RDAC circuit 25 20 a D kO 0 256 512 768 1023 CODE Decimal Figure 10 Ryp D vs Code UM 12 The general equation that determines the programmed output resistance between Wx and Bx 15 D D 1024 X 1 where D 15 decimal equivalent of the contained in register Ryg rs is the full scale resistance between terminals W and B and Ry is the wiper resistance For example the following output resistance values will be set for the following RDAC latch codes with 5 V applies to Rws rs 25 programmable resistors Table Ryg at Selected Codes rs 25 D DEC 0 Output State 1023 25026 Full Scale 512 12550 Mid Scale
34. tained RDACI register CIXXXXg COXXXXg Moves wiper 2 to double the present data contained in RDAC2 register Table XIII Storing Additional User Data in EEMEM SDI SDO Action 32AAAAg 335555 XOGODOU 32AAAAg Stores data AAAAy into spare EEMEM location USERI Allowable to address in 13 locations with maximum 16 bits of data Stores data 5555 into spare EEMEM location USER2 Allowable to address in 13 locations with maximum 16 bits of data Table XIV Reading Back Data From Various Memory Locations SDI SDO Action 92 Prepares data read from USERI location O0XXXXg 92 NOP instruction 0 sends 24 bit word out of SDO where the last 16 bits contgin the contents of USERI location command ensures device returns to idle power dissipation state Table XV Reading Back Wiper Setting SDI SDO Action 00200 Sets RDACI to midscale COXXXXg 00200 Doubles RDACI from midscale to full scale AOXXXXy COXXXXg Prepares reading wiper setting from RDACI register A003FFg Readback full scale value from RDAC1 register SDI SDO Action 10 Restores EEMEMI value to RDAC1 register 00 1001004 NOP Recommended step to minimize power consumption 8 Reset EEMEMI and EEMEM2 values to R
35. tection The write protect AVP disdbl s any changes of the scratch pad register contents regardless of the software commands except iat the EEMEM setting Can De fefreshed and can overwrite the WP by using commands 1 8 and PR pulse To disable WP it is recommended to execute a NOP command before returning WP to logic high Linear Increment and Decrement Commands The increment and decrement commands 14 15 6 7 are useful for linear step adjustment applications These commands simplify microcontroller software coding by allowing the controller to just send an increment or decrement command to the device The adjustment can be individually or gang controlled For incre ment command executing instruction 14 will automatically move the wiper to the next resistance segment position The master increment instruction 15 will move all resistor wipers up by one position Logarithmic Taper Mode Adjustment 6 dB step There are four programming instructions which provide the logarithmic taper increment and decrement wiper position con trol by either individual or gang control 6 dB increment is activated by instructions 12 and 13 and 6 dB decrement is acti vated by instructions 4 and 5 For example starting at zero scale executing 11 times the increment instruction 12 will move the wiper in 6 dB per step from the 0 of the full scale Ryg to the full scale The 6 dB increment instruction doubles the value of the RDAC register contents
36. this EEMEM saving process There are also 13 two bytes addresses of user defined data that can be stored in EEMEM OPERATION DETAIL There are 16 instructions that facilitate users programming needs Referring to Table II the instructions are 0 Do Nothing 1 Restore EEMEM setting to RDAC 2 Save RDAC setting to EEMEM 3 Save user data or RDAC setting to EEMEM 4 Decrement 6 dB 5 Decrement all 6 dB 6 Decrement one step 7 Decrement all one step 8 Reset all EEMEM settings to 9 Read EEMEM to SDO Read Wiper Setting to SDO Write data to RDAC Increment 6 dB Increment all 6 dB gt P Increment step 15 Increment all one step Tables VIII to XIV provide a few programming examples by using some of these instructions Scratch Pad and EEMEM Programming basic mode of setting the programmable resistor wiper position programming the scratch pad register is done by loading the serial data Input register with the instruction 11 the corresponding address and the data Since the scratch pad register is a standard logic register there is no restriction on the number of changes allowed When the desired wiper position is determined the user can load the serial data input register with the instruction 2 which stores the setting into the corresponding EEMEM register The EEMEM value can be changed at any time or permanently protected by activating the
37. to the subsequent devices see Figure 4 If two ADN2850s are daisy chained a total 48 bits of data is required The first 24 bits formatted 4 bit instruction 4 bit address and 16 bit data go to U2 and the second 24 bits with the same format go to U1 The CS should be kept low until all 48 bits are clocked into their respective serial registers The CS is then pulled high to complete the operation Figure 4 Daisy Chain Configuration DIGITAL INPUTIOUTPUT All digital inputs are ESD protected Digital inputs are high impedance and can be driven directly from most digital sources Active at logic low PR and WP should be biased to Vpp if they are not used There are no internal pull up resistors present on any digital input pins To avoid floating digital pins that may cause false triggering in a nolsy environment pull up resistors should be added to these pins However this only applies to the case where the device will be detached from the driving source once it is programmed The SDO and RDY pins are open drain digital outputs Similarly pull up resistors are needed if these functions are used To optimize the speed and power trade off use 2 2 pull up resistors The equivalent serial data input and output logic is shown in Figure 5 The open drain output SDO is disabled whenever chip select CS is logic high ESD protection of the digital inputs is shown in Figures 6a and 6b 10 VALID COMMAND COMMAND x
38. up sequence is in the following order GND Vpp Vss Digital Inputs and The order of powering Vg Vw and Digital Inputs is not important as long as they are powered after Vpp Vss Regardless of the power up sequence and the ramp rates of the power supplies once Vpp Vss are powered the power on reset remains effective which retrieves EEMEM saved values to the RDAC registers see TPC 7 Layout and Power Supply Bypassing It is a good practice to employ compact minimum lead length layout design The leads to the input should be as direct as pos sible with a minimum of conductor length Ground paths should have low resistance and low inductance To minimize the digital ground bounce the digital signal ground reference can be joined remotely to the analog ground terminal of the ADN2850 Similarly it is also a good practice to bypass the power supplies with quality capacitors for optimum stability Supply leads to the device should be bypassed with 0 01 uF to 0 1 uF disc or chip ceramics capacitors Low ESR 1 uF to 10 uF tantalum or electro lytic capacitors should also be applied at the supplies to minimize any transient disturbance see Figure 8 REV B ADN2850 Figure 8 Power Supply Bypassing RDAC STRUCTURE The patent pending RDAC contains a string of equal resistor segments with an array of analog switches that act as the wiper connection The number of positions is the resolution of the device The ADN2850 h

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