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ANALOG DEVICES AD5165 handbook

1. 2004 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners WWW ana 0 g com DEVICES Rev 0 Page 16 of 16
2. 40 25 0 3 85 C 125 0 2 0 1 0 0 1 N 0 2 0 3 0 4 0 5 0 32 64 96 128 160 192 224 256 E 40 20 0 20 40 60 80 100 120 CODE Decimal TEMPERATURE C Figure 11 R INL vs Code vs Temperature 5 V Figure 14 Zero Scale Error vs Temperature E z 2 o amp 0 2 0 3 13 AM 3L 0 4 1 PATI 0 32 alia 256 3 CODE Decimal TEMPERATURE Figure 12 R DNL vs Code vs Temperature Voo 5 V Figure 15 Supply Current vs Temperature 10000 FSE Q Vpp 5 mers SNR a Q 20 0 20 40 60 80 100 120 TEMPERATURE 04749 0 023 Figure 13 Full Scale Error vs Temperature Rev 0 Page 8 of 16 Vin 0 V Figure 16 Supply Current vs Digital Input Voltage 04749 0 022 04749 0 020 04749 0 025 Ipp RHEOSTAT MODE POTENTIOMETER MODE TEMPCO ppm C 1000 100 10 0 1 0 01 Vin 1MHz V Figure 17 Supply Current vs Digital Input Voltage CODE Decimal Figure 18 Rheostat Mode Tempco ARws AT vs Code CODE Decimal Figure 19 Potentiometer Mode Tempco AVws AT vs Code 04749 0 026 04749 0 015 P
3. 100 VETON 3 3 Wire Serial Bus Digital Interface 14 Absolute Maximum Ratings ninien 5 ESD Protectioti 14 Pin Configuration and Functional Descriptions 6 Terminal Voltage Operating 14 Typical Performance Characteristics 7 Power Up SEQUENCE ee eee EE 14 Mest Circuits 11 Layout and Power Supply Bypassing 15 3 Wire Digital Interface usns 12 Evaluation Board eene 15 Theory of 13 Outline Dimensions eret ne 16 Programming the Variable Resistor 13 Ordering Guide eerte 16 Programming the Potentiometer 1 14 cona 4 04 Revision 0 Initial Version Rev 0 Page 2 of 16 ELECTRICAL CHARACTERISTICS 100 VERSION Vpp 5 V 1096 or V 1096 Va Vs 0 V 40 C lt Ta lt 125 unless otherwise noted Table 1 Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity R DNL Va no connect 1 0 1 1 LSB Resistor Integral Nonlinearity R INL Rws Va no connect 2 0 25 2 LSB Nominal Resistor Tolerance ARas Ras Ta 25 C
4. 20 20 Resistance Temperature Coefficient ARas Ras ATX10 Vas wiper no connect 35 ppm C Wiper Resistance Rw Vpp 2 7 V 5 5 V 85 50 150 120 DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Resolution N 8 Bits Differential Nonlinearity DNL 1 0 1 1 LSB Integral Nonlinearity INL 1 0 3 1 LSB Voltage Divider Temperature AVw Vw 106 Code 0x80 15 ppm C Coefficient Full Scale Error Vwese Code OxFF 0 5 0 3 0 LSB Zero Scale Error Vwzse Code 0x00 0 0 1 0 5 LSB RESISTOR TERMINALS Voltage Range GND Capacitance A f 1 MHz measured to GND 90 pF Code 0x80 Capacitance W Cw f 1 MHz measured to GND 95 pF Common M 1 nA DIGITAL INP Input LogiC Hi Sv 1 V Input Logic Low Vit Voo 2 7 to 5 5 V 0 6 V Input Capacitance 5 pF POWER SUPPLIES Power Supply Range VDD RANGE 27 5 5 Supply Current Ipp Digital inputs 0 V or Voo 0 05 1 Voo 2 7 V digital inputs 1 8 V 10 uA Voo 5 V digital inputs 1 8 V 500 uA Power Dissipation Poiss Digital inputs 0 V or Voo 5 5 uW Power Supply Sensitivity PSS Voo 5 V 10 0 001 0 005 Code Midscale DYNAMIC CHARACTERISTICS Bandwidth 3 dB BW Code 0x80 55 kHz Total Harmonic Distortion THDw Va 1 rms Ve OV f 1 kHz 0 05 96 Vw Settling Time ts 5 0 2 Us 1 LSB error band Resistor Noise Voltage Density Rws 50 28 nV JHz 1 Typical specif
5. MODE DNL LSB POTENTIOMETER MODE INL LSB 0 5 0 4 5 5V 2 7N 0 3 0 2 0 1 0 32 64 96 128 160 192 224 256 CODE Decimal Figure 5 R INL vs Code vs Supply Voltages ror CODE Decimal Figure 6 R DNL vs Code vs Supply Voltages CODE Decimal Figure 7 INL vs Code vs Temperature Voo 5 V POTENTIOMETER MODE DNL LSB 04749 0 011 POTENTIOMETER MODE INL LSB 04749 0 013 POTENTIOMETER MODE DNL LSB 04749 0 006 Rev 0 Page 7 of 16 0 32 64 96 128 160 192 224 256 CODE Decimal Figure 8 DNL vs Code vs Temperature Vpp 5 V 70 32 64 96 128 160 192 224 256 CODE Decimal Figure 9 INL vs Code vs Supply Voltages b bb wo b b 0 32 64 96 128 160 192 224 256 CODE Decimal Figure 10 DNL vs Code vs Supply Voltages 04749 0 008 04749 0 007 04749 0 009 RHEOSTAT MODE DNL LSB RHEOSTAT MODE INL LSB FSE LSB 0 4
6. ANALOG DEVICES FEATURES Ultralow standby power Ipp 50 nA typical 256 position End to end resistance 100 Logic high voltage 1 8 V Power supply 2 7 V to 5 5 V Low temperature coefficient 35 ppm C Compact thin 8 lead TSOT 8 2 9 mm x 2 8 mm package Simple 3 wire digital interface Wide operating temperature 40 C to 125 C Pin to pin compatible to AD5160 with CS inverted APPLICATIONS Battery operated electronics adjustment Remote utilities meter adjustment Mechanical potentiometer replacement Transducer circuit adjustment Automotive electronics adjustment Gain control and offset adjustment System calibration GENERAL OV The AD5165 provides a compact 2 9 mm x 2 8 mm packaged solution for 256 position adjustment applications These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors with enhanced resolution solid state reliability and superior low temperature coefficient performance The AD5165 s supply voltage requirement is 2 7 V to 5 5 but its logic voltage requirement is 1 8 V to The AD5165 consumes very low quiescent power during standby mode and is ideal for battery operated applications Wiper settings are controlled through a simple 3 wire interface The interface is similar to the SPI digital interface except for the inverted chip select function that minimizes logic power con sumption in the idling state The resistance betwe
7. DI CS and CLK The 8 bit serial word must be loaded MSB first The format of the word is shown in Table 5 The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register Standard logic families work well If mechanical switches are used for product evaluation they should be debounced by a flip flop or other suitable means When CS is high the clock loads data into the serial register on each positive clock edge as shown in Figure 34 The data setup and data hold times in the specifications table determine the valid timing requirements The AD5165 uses an 8 bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic low Extra MSB bits are ignored ESD PROTECTION digital inputs are protected with a series of input resistors and parallel Zener ESD structures shown in Figure 39 and Figure 40 This applies to the digital input pins SDI CLK and CS 04749 0 041 04749 0 042 GND Figure 40 ESD Protection of Resistor Terminals TERMI AD NIB power conditions for proper 3 terminal digital potentiometer oper ation Supply signals present on terminals A B and W that exceed Vp or GND are clamped by the internal forward biased diodes as shown in Figure 41 Vpp 04749 0 043 GND Figure 41 Maximum Terminal Voltages Set Voo and GND POWER UP SEQUENCE Because the ESD protect
8. EORY OF OPERATION The AD5165 is a 256 position digitally controlled variable resistor VR device PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between terminals A and B is available in 100 kO The nominal resistance Ras of the VR has 256 contact points accessed by the wiper terminal plus the B terminal contact The 8 bit data in the RDAC latch is decoded to select one of the 256 possible settings 24 Figure 36 Rheostat Mode Configuration 04749 0 038 Assuming that a 100 part is used the wiper s first connec tion starts at the B terminal for data 0x00 Because there is a 50 wiper contact resistance such a connection yields a mini mum of 100 2 x 50 resistance between terminals W and B The second connection is the first tap point which corres ponds to 490 Ris Rap 256 F2 x 2 390 04 2 x 50 resistor ladder until the last tap point is reached at 100 100 Ras 2 x Ry DECODER 04749 0 039 Figure 37 AD5165 Equivalent RDAC Circuit The general equation determining the digitally programmed output resistance between W and B is Ryg D Ra 2 Ry 1 where Dis the decimal equivalent of the binary code loaded in the 8 bit RDAC register Raz is the end to end resistance Rwis the wiper resistance contributed by the on resistance of the internal switch In summary if Ras 100 kO and the A terminal is open circuited the fo
9. Fall to Clock Rise Setup tcsi 10 ns 1 Typical specifications represent average readings at 25 C and 5 V Guaranteed by design and not subject to production test 3 All dynamic characteristics use Voo 5 V 4 See Figure 34 and Figure 35 for location of measured values All input control voltages are specified with tr tc 2 ns 10 to 90 of V and timed from a voltage ww BDI com level of 1 5 V Rev 0 Pa ge4of 16 ABSOLUTE MAXIMUM RATINGS Ta 25 unless otherwise noted Table 3 Parameter Value Voo to GND 0 3Vto 47V Va Ve Vw to GND Maximum Current lws lwa Pulsed 20 mA lws Continuous lt 1 A open 5 mA lwa Continuous Rwa lt 1 B open 5 mA Digital Inputs and Output Voltage to GND OVto 7V Operating Temperature Range 40 C to 125 C Maximum Junction Temperature Timax 150 C Storage Temperature 65 C to 150 C Lead Temperature Soldering 10 30 sec 245 C Thermal Resistance TSOT 8 200 C W Maximum terminal current is bounded by the maximum current handling of the switches maximum power dissipation of the package and maximum applied voltage across any two of the A B and W terminals at a given resistance 2 Package power dissipation Tmax ww ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the hu
10. SRR dB 04749 0 014 Rev 0 Page 9 of 16 REF LEVEL DIV MARKER 54 089 173Hz 0 000dB 6 000dB MAG 9 052dB 0 6 0 80 12 x40 18 0x20 24 0x10 30 0x08 36 0x04 42 0x02 0 01 54 60 1k 10k 100k 1M START 1 000 000Hz STOP 1 000 000 000Hz Figure 20 Gain vs Frequency vs Code Ras 100 REF LEVEL DIV 5 000dB 0 500dB 10k 10M START 1 000 000Hz STOP 1 000 000 000Hz Figure 21 3 dB Bandwidth Code 0x80 100 1k 10k 100k 1M FREQUENCY Hz Figure 22 PSRR vs Frequency 04749 0 048 04749 0 047 04749 0 019 lbp HA Ch 1 100 Bw Ch 2 5 00 V4ByM 200ns CH1 152mV Figure 26 Midscale Glitch Code 0 80 0 7 04749 0 018 FREQUENCY Hz Figure 23 vs Frequency C com AL PENES QU NE ae 04749 0 030 Ch1 200mV Bw Ch 2 5 00 100 5 CH2 3 00 V Figure 25 Digital Feedthrough Rev 0 Page 10 of 16 cs 04749 0 028 TEST CIRCUITS Figure 27 to Figure 33 illustrate the test circuits that define the test conditions u
11. en the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the wiper register Operating from a 2 7 V to 5 5 V power supply and consuming less than 50 nA typical standby power allows use in battery operated portable or remote utility device applications Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 256 Position Ultralow Power 1 8 V Logic Level Digital Potentiometer FUNCTIONAL BLOCK DIAGRAM Vpp 3 WIRE INTERFACE 04749 0 001 GND Figure 1 PIN CONFIGURATION 3 3V WIDE TERMINAL WC VOLTAGE RANGE DIGITAL CONTROL OV lt Va Vp Vw lt 5V LOGIC OR MICRO 04749 0 003 Figure 3 Note The terms digital potentiometer RDAC and VR are used interchangeably One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved TABLE OF CONTENTS
12. from any PC running Windows 98 2000 XP The graphical user interface as shown in Figure 43 is straightforward and easy to use More detailed information is available in the user manual which comes with the board 4 HF Fer 0 0 F Caen Bre A Slave Byte 327 vasvas m SDA Road Bit indicator Hit Read 1615 09 a 76 Y m 04749 0 046 Figure 43 AD5165 Evaluation Board Software The AD5165 starts at midscale upon power up To increment or decrement the resistance the user may move the scroll bars on the left To write any specific value the user should use the bit pattern in the upper screen and click the Run button The format of writing data to ANY Figure 32 Rev 0 Page 15 of 16 OUTLINE DIMENSIONS 2 80 BSC 0 65 BSC 1 0 90 asc n T 1 00 020 008 y 0 60 038 x F gt 045 0 22 SEATING 0 30 PLANE COMPLIANT TO JEDEC STANDARDS MO 193BA Figure 44 8 Lead Thin Small Outline Transistor Package Thin SOT 23 UJ 8 Dimensions shown in millimeters ORDERING GUI Model Branding AD5165BUJZ100 R2 0 D3N AD5165BUJZ100 R7 100 k 40 C to 125 C Thin SOT 23 D3N AD5165EVAL Evaluation Board 17 Pb free part
13. ications represent average readings at 25 C and 5 V Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions R DNL measures the relative step change from ideal between successive tap positions Parts are guaranteed monotonic 3 Vas Von wiper Vw no connect INL and DNL are measured at Vw with the RDAC configured as a potentiometer divider similar to a voltage output D A converter Va and Vs OV 5 Resistor terminals A B and W have no limitations on polarity with respect to each other Guaranteed by design and not subject to production test 7 Poss is calculated from lbo CMOS logic level inputs result in minimum power dissipation 8 All dynamic characteristics use Vpp 5 V Rev 0 Page of 16 TIMING CHARACTERISTICS 100 VERSION Vpp 5 V 1096 or 3 V 10 Va Von Vs 0 V 409 lt Ta lt 125 unless otherwise noted Table 2 Parameter Symbol Conditions Min Unit 3 WIRE INTERFACE TIMING CHARACTERISTICS 4 specifications apply to all parts Clock Frequency ta 25 MHz Input Clock Pulse Width tcu tc Clock level high or low 20 ns Data Setup Time tps 5 ns Data Hold Time toH 5 ns CS Setup Time tcss 15 ns CS Low Pulse Width tcsw 40 ns CLK Fall to CS Rise Hold Time tcsHo 0 ns CLK Fall to CS Fall Hold Time tcsui 0 ns CS
14. ion diodes limit the voltage compliance at terminals A B and W see Figure 41 it is important to power Vpp GND before applying any voltage to terminals B W otherwise the diode is forward biased such that Vp is powered unintentionally and may affect the rest of the user s circuit The ideal power up sequence is in the following order GND digital inputs and then Va and Vw The relative order of powering Va Vs Vw and the digital inputs is not important as long as they are powered after Vop GND Rev 0 Page 14 of 16 LAYOUT AND POWER SUPPLY BYPASSING Itis good practice to employ compact minimum lead length layout design The leads to the inputs should be as direct as possible with a minimum conductor length Ground paths should have low resistance and low inductance Similarly it is also good practice to bypass the power supplies with quality capacitors for optimum stability Supply leads to the device should be bypassed with disk or chip ceramic capacitors of 0 01 uF to 0 1 uF Low ESR 1 pF to 10 tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple see Figure 42 Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce AD5165 EVALUATION BOARD An evaluation board along with all necessary software is available to program the AD5165
15. llowing output resistance Rwz is set for the indicated RDAC latch codes Table 6 Codes and Corresponding Rws Resistance D Dec Rws Q Output State 255 99 710 Full scale Ras 1 LSB Rw 128 50 100 Midscale 1 490 1 LSB 0 100 Zero scale wiper contact resistance Note that in the zero scale condition a finite wiper resistance of 100 is present Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA Otherwise degradation or possible destruction of the internal switch contact can occur mechanica also produces a d e ia e Rwa When these terminals are used the B terminal can be opened Setting the resistance value for Rwa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value The general equation for this operation is 256 D Bia 2 For Ras 100 with the B terminal open circuited the following output resistance Rwa is set for the indicated RDAC latch codes Table 7 Codes and Corresponding Rwa Resistance D Dec Rwa Q Output State 255 490 Full scale 128 50 100 Midscale 1 99 710 1 LSB 0 100 100 Zero scale Typical device to device matching is process lot dependent and may vary by up to 20 Because the resistance element is processed in thin film technology the change in Ras with temperature has a very low 35 ppm C te
16. man body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability C com AL cya ESD SENSITIVE DEVICE Rev 0 Page 5 of 16 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS AD5165 VIEW Not to Scale o e 04749 0 002 Figure 4 Table 4 Pin Name Description 1 Wiper terminal GND lt Va lt 2 Positive Power Supply 3 GND Digital Ground 4 CLK Serial Clock Input Positive edge triggered 5 SDI Serial Data Input data loads MSB first 6 CS Chip Select Input active high When CS returns low data is loaded into the wiper register 7 B B terminal GND lt Va x Vpp 8 A A terminal GND lt Va lt ww BDI com Rev 0 Page 6 of 16 TYPICAL PERFORMANCE CHARACTERISTICS RHEOSTAT MODE INL LSB REHOSTAT
17. mperature coefficient Rev 0 Page 13 of 16 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper to B and wiper to A proportional to the input voltage at A to B Unlike the polarity of Von to GND which must be positive voltage across A to B W to A and W to B can be at either polarity 04749 0 040 Figure 38 Potentiometer Mode Configuration If ignoring the effect of the wiper resistance for approximation connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper to B starting at 0 V up to 1 LSB less than 5 V Each LSB of voltage is equal to the voltage applied across terminals A and B divided by the 256 positions of the potentiometer divider The general equation defining the output voltage at Vw with respect to ground for any valid input voltage applied to terminals A and B is D 256 D WG V 6 more s AM e resistance Vw is Ry C V RwalD y Vw D B 4 AB Ras Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature Unlike the rheostat mode the output voltage is dependent mainly on the ratio of the internal resistors and Rws and not the absolute values Therefore the temperature drift reduces to 15 ppm C 3 WIRE SERIAL BUS DIGITAL INTERFACE The AD5165 contains a 3 wire digital interface S
18. sed in the product specification tables V Vpp 1LSB V 2N lt eo 04749 0 031 04749 0 035 Figure 27 Test Circuit for Potentiometer Divider Nonlinearity Error Figure 31 Test Circuit for Gain vs Frequency INL DNL NO CONNECT 0 1V 04749 0 032 GND TO Vpp 04749 0 036 Figure 28 Test Circuit for Resistor Position Nonlinearity Error Figure 32 Test Circuit for Incremental ON Resistance Rheostat Operation R l C j A NC Rw Vms1 Vms2l lw Vusi 04749 0 033 04749 0 037 NC CONNECT Figure 29 Test Circuit for Wiper Resistance Figure 33 Test Circuit for Common Mode Leakage Current V Vpp 10 AVms PSRR dB 20 LOG 55 AVpp AVms PSS 04749 0 034 Figure 30 Test Circuit for Power Supply Sensitivity PSS PSSR Rev 0 Page 11 of 16 3 WIRE DIGITAL INTERFACE Note that in the AD5165 data is loaded MSB first Table 5 AD5165 Serial Data Word Format B7 B6 B5 B4 B3 B2 B1 BO D7 D6 D5 D4 D3 D2 D1 DO MSB LSB 2 29 5 6 26 po o x ado xeu o 04749 0 004 cs RDAC REGISTER LOAD VOUT Figure 34 3 Wire Digital Interface Timing Diagram Va 5 V 0 V Vw VOUT 1LSB 04749 0 005 Figure 35 3 Wire Digital Interface Detailed Timing Diagram 5 V Vs 0 V Vw Rev 0 Page 12 of 16 TH

ANALOG DEVICES AD5165 handbook

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