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ANALOG DEVICES AD5542A handbook

1. a o a d d 5 tc S fi E LI 2 8 3 id ra LI N 40 25 85 E 40 25 85 E TEMPERATURE C TEMPERATURE C z Figure 13 AD5512A AD5542A Gain Error vs Temperature Figure 16 AD5512A AD5542A Zero Code Error vs Temperature 132 130 128 z REFERENCE VOLTAGE el 3 s Vpp 5V E 126 z i LI tc Fi 424 r1 SUPPLY VOLTAGE a o Vrer 2 5V gt a a 122 a Q 2 2 o B 120 118 116 m 40 25 85 5 i TEMPERATURE C 2 VOLTAGE V E Figure 14 AD5512A AD5542A Supply Current vs Temperature Figure 17 AD5512A AD5542A Supply Current vs Reference Voltage or Supply Voltage 200 200 180 160 zx 150 E 140 E z E 120 ui u 4 i 3 S 100 o 100 gt 80 S W amp tc a gt 60 ra bi ui 50 40 20 0 se 0 1234567 8 9101112131415 16 17 18 19 2021 amp O 10 000 20 000 30 000 40 000 50 000 60 000 70 000 5 DIGITAL INPUT VOLTAGE V Z CODE Decimal Figure 15 AD5512A AD5542A Supply Current vs Digital Input Voltage Figure 18 AD5512A AD5542A Reference Current vs Code Rev A Page 11 of 24 AD5512A AD5542A Vout 1V DIV Vour 50mV DIV GAIN 216 1LSB Vgge 2N 1 09199 018 09199 021 Figure 19 AD5512A AD5542A Digital Feedthrough Figure 22 AD5512A AD5542A Smal
2. NOISE SPECTRAL DENSITY nV rms VHz 0 9600 9700 9800 9900 10 000 10 100 10 200 10 300 10 400 FREQUENCY Hz 2 S a a o Figure 27 AD5512A AD5542A Noise Spectral Density vs Frequency 10 kHz Rev A Page 13 of 24 AD5512A AD5542A TERMINOLOGY Relative Accuracy or Integral Nonlinearity INL For the DAC relative accuracy or INL is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function A typical INL vs code plot is shown in Figure 7 Differential Nonlinearity DNL DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB maximum ensures mono tonicity A typical DNL vs code plot is shown in Figure 10 Gain Error Gain error is the difference between the actual and ideal analog output range expressed as a percent of the full scale range It is the deviation in slope of the DAC transfer characteristic from ideal Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with changes in temperature It is expressed in ppm C Zero Code Error Zero code error is a measure of the output error when zero code is loaded to the DAC register Zero Code Temperature Coefficient This is a measure of the change in zero code error with a change in te
3. FORCE SENSE AMPLIFIER SELECTION Use single supply low noise amplifiers A low output impedance at high frequencies is preferred because the amplifiers must be able to handle dynamic currents of up to 20 mA REFERENCE AND GROUND Because the input impedance is code dependent the refer ence pin should be driven from a low impedance source The AD5512A AD55424 operate with a voltage reference ranging from 2 V to Vpp References below 2 V result in reduced accuracy The full scale output voltage of the DAC is determined by the reference Table 9 and Table 10 outline the analog output voltage or particular digital codes For optimum performance Kelvin sense connections are provided on the AD5512A AD5542A If the application doesn t require separate force and sense lines tie the lines close to the package to minimize voltage drops between the package leads and the internal die POWER ON RESET The AD5512A A D5542A have a power on reset function to ensure that the output is at a known state on power up On power up the DAC register contains all 0s until the data is loaded from the serial register However the serial register is not cleared on power up therefore its contents are undefined When loading data initially to the DAC 16 bits or more should be loaded to prevent erroneous data appearing on the output If more than 16 bits are loaded the last 16 are kept and if less than 16 bits are loaded bits remain from the previous wor
4. ANALOG DEVICES FEATURES 12 16 bit resolution 1 LSB INL 11 8 nV VHz noise spectral density 1 us settling time 1 1 nV sec glitch energy 0 05 ppm C temperature drift 5 kV HBM ESD classification 0 375 mW power consumption at 3 V 2 7 V to 5 5 V single supply operation Hardware CLR and LDAC functions 50 MHz SPI QSPI MICROWIRE DSP compatible interface Power on reset clears DAC output to midscale Available in 3 mm x 3 mm 10 16 lead LFCSP and 16 lead TSSOP APPLICATIONS Automatic test equipment Precision source measure instruments Data acquisition systems Medical and aerospace instrumentation Communication equipment GENERAL DESCRIPTION The AD5512A AD5542A are single 12 16 bit serial input unbuffered voltage output digital to analog converters DAC that operate from a single 2 7 V to 5 5 V supply The DAC output range extends from 0 V to Vrer and is guaranteed monotonic providing 1 LSB INL accuracy at 16 bits without adjustment over the full specified temperature range of 40 C to 85 C AD5542A or 40 C to 125 C AD5512A Offering unbuffered outputs the AD5512A AD5542A achieve a 1 us settling time with low offset errors ideal for high speed open loop control The AD5512A A D5542A incorporate a bipolar mode of operation that generates a V rer output swing The AD5512A AD5542A also include Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity The
5. Figure 32 Bipolar Output Rev A Page 16 of 24 AD5512A AD5542A OUTPUT AMPLIFIER SELECTION For bipolar mode a precision amplifier should be used and supplied from a dual power supply This provides the V per output In a single supply application selection of a suitable op amp may be more difficult because the output swing of the ampli fier does not usually include the negative rail in this case AGND This can result in some degradation of the specified performance unless the application does not use codes near zero The selected op amp must have a very low offset voltage the DAC LSB is 38 uV for the AD5542A with a 2 5 V reference to eliminate the need for output offset trims Input bias current should also be very low because the bias current multiplied by the DAC output impedance approximately 6 kQ adds to the zero code error Rail to rail input and output performance is required For fast settling the slew rate of the op amp should not impede the settling time of the DAC Output impedance of the DAC is constant and code independent but to minimize gain errors the input impedance of the output amplifier should be as high as possible The amplifier should also have a 3 dB bandwidth of 1 MHz or greater The amplifier adds another time constant to the system thus increasing the settling time of the output A higher 3 dB amplifier bandwidth results in a shorter effective settling time of the combined DAC and amplifier
6. Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality TSSOP RU 16 113 C W LFCSP CP 16 22 73 C W LFCSP CP 10 9 74 C W Lead Temperature Soldering Peak Temperature 260 C ESD 5 kV 1 As per JEDEC Standard 20 HBM classification Rev A Page 7 of 24 AD5512A AD5542A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4 AD5512A AD5542A 16 Lead LFCSP Pin Configuration NC NO CONNECT Not to Scale li 14 Vioaic 13 INV on o o oz R REF 1 i cs 2 i 12 DGND L AD5542A 1 11 LDAC SCLK 3 Top VIEW HN ra Not to Scale 10 CLR DIMES 9 DIN CLR 5f NOTES 1 THE EXPOSED PADDLE SHOULD BE TIED TO THE POINT OF LOWEST POTENTIAL IN THIS CASE GND Figure 5 AD5542A 1 10 Lead LFCSP Pin Configuration 09199 036 09199 034 Table 7 AD5512A AD5542A Pin Function Descriptions Pin No 16 Lead 10 Lead LFCSP LFCSP Mnemonic Description 1 6 Vour Analog Output Voltage from the DAC 2 AGNDF Ground Reference Point for Analog Circuitry Force 3 AGNDS Ground Reference Point for Analog Circuitry Sense 4 REFS Voltage Reference Input Sense for the DAC Connect to an external 2 5 V reference Reference can range from 2 V to Vy 5 REFF Voltage Reference Input Force for the DAC Connect to an external 2 5 V reference Reference can range from 2 V to V 6 2 CS Logic Input Signal The chip select signal is used to frame the
7. 08 16 2010 E AD5512A AD5542A 3 10 3 00 SQ gt 2 90 0 50 BSC PIN 1 INDEX 1 74 AREA 1 64 0 50 1 49 0 40 0 30 PIN 1 TOP VIEW 4 BOTTOM VIEW INDICATOR R 0 15 0 80 FOR PROPER CONNECTION OF 0 75 0 05 MAX THE EXPOSED PAD REFER TO 0 02 NOM THE PIN CONFIGURATION AND 0 70 i EXE FUNCTION DESCRIPTIONS HHH SECTION OF THIS DATA SHEET SEATING 0 30 ie PLAN 0 25 0 20 REF s 0 20 S Figure 42 10 Lead Lead Frame Chip Scale Package LFCSP_WD 3 mm x 3 mm Body Very Very Thin Dual Lead CP 10 9 Dimensions shown in millimeters ORDERING GUIDE Power On Temperature Model INL DNL Reset to Code Range Package Description Package Option Branding AD5512AACPZ REEL7 1 LSB 1 LSB Midscale 40 C to 125 C 16 Lead LFCSP CP 16 22 DFQ AD5512AACPZ 500RL7 1 LSB 1 LSB Midscale 40 C to 125 C 16 Lead LFCSP CP 16 22 DFQ AD5542ABRUZ 1 LSB 1 LSB Midscale 40 C to 85 C 16 Lead TSSOP RU 16 AD5542ABRUZ REEL7 1 LSB 1 LSB Midscale 40 C to 85 C 16 Lead TSSOP RU 16 AD5542AARUZ 2 LSB 1 LSB Midscale 40 C to 85 C 16 Lead TSSOP RU 16 AD5542AARUZ REEL7 2 LSB 1 LSB Midscale 40 C to 85 C 16 Lead TSSOP RU 16 AD5542ABCPZ REEL7 1 LSB 1 LSB Midscale 40 C to 85 C 16 Lead LFCSP_WQ CP 16 22 DFL AD5542AACPZ REEL7 2 LSB 1 LSB Midscale 40 C to 85 C 16 Lead LFCSP_WQ CP 16 22 DFK AD5442ABCPZ 1 RL7 1 LSB 1 LSB Midscale 40 C to 85 C 10 Lead LFCSP
8. Unipolar Zero Code Temperature Coefficient 0 05 ppm C Bipolar Resistor Matching 1 O Q Ra Ryy typically R Ry 28 kO 0 02 0 08 Ratio error Bipolar Zero Offset Error 0 07 2 LSB Bipolar Zero Temperature Coefficient 0 2 ppm C Bipolar Zero Code Offset Error 0 02 0 5 LSB Bipolar Gain Error 0 07 2 LSB Bipolar Gain Temperature Coefficient 0 1 ppm C OUTPUT CHARACTERISTICS Output Voltage Range 0 Veer 1 LSB V Unipolar operation V REF dVper 1 LSB V Bipolar operation DAC Output Impedance 6 25 ko Tolerance typically 20 Power Supply Rejection Ratio 1 0 LSB AVpp 10 Output Noise Spectral Density 11 8 nV VHz DAC code 0x840 AD5512A or 0x8400 AD5542A frequency 1 kHz unipolar mode Output Noise 0 134 uV p p 0 1 Hz to 10 Hz unipolar mode DAC REFERENCE INPUT Reference Input Range 2 0 Vbp V Reference Input Resistance 9 kQ Unipolar operation 7 5 kQ Bipolar operation Reference Input Capacitance 26 pF Code 0x0000 26 pF Code 0x3FFF LOGIC INPUTS Input Current 1 uA Input Low Voltage Vy 0 8 V Vpp 2 7 V to 5 5 V Input High Voltage Vy 24 V Vpp 2 7 V to 5 5 V Input Capacitance 10 pF Hysteresis Voltage 0 15 V POWER REQUIREMENTS Vpp 2 7 5 5 V All digital inputs at OV Vioc OF Vpop lop 125 150 HA Vin Viogic OF Vpop and V GND Moss 1 8 5 5 V lioac 15 24 pA All digital inputs at 0 V Viogic OF Vpop Power Dissipation 1 5 6 05 mW 1 Temperatures are as follows A version 4
9. AD5512A AD5542A are available in a 16 lead LFCSP with the AD5542A also available in a 10 lead LFCSP and a 16 lead TSSOP The AD5512A AD5542A use a versatile 3 wire interface that is compatible with 50 MHz SPI OSPI MICROWIRE and DSP interface standards Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 2 1 V to 5 5 V Serial Input Voltage Output 12 16 Bit DAC AD5512A AD5542A FUNCTIONAL BLOCK DIAGRAM AD5512A AD5542A 5 CLR DGND 8 Figure 1 16 Lead TSSOP and 16 Lead LFCSP GND 09199 002 Figure 2 10 Lead LFCSP Table 1 Related Devices Part No Description AD5040 AD5060 2 7V to 5 5 V 14 16 bit buffed output DACs AD5541 AD5542 2 7 V to 5 5 V 16 bit voltage output DACs AD5781 AD5791 18 20 bit voltage output DACs AD5570 16 bit 12 V 15 V bipolar output DAC AD5024 AD5064 4 5 V to 5 5 V 12 16 bit quad channel DAC AD5764 16 bit bipolar voltage output DAC PRODUCT HIGHLIGHTS 1 16 bit performance without adjustment 2 7 V to 5 5 V single supply operatio
10. Ta lt 125 C SCLK LDAC CLR NOTES 1 FOR AD5542A DB15 2 FOR AD5512A DB11 Figure 3 Timing Diagram Rev A Page 6 of 24 09199 003 AD5512A AD5542A ABSOLUTE MAXIMUM RATINGS T 25 C unless otherwise noted Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress Table 6 Parameter Rating Vpp to AGND 0 3V to 6 V Digital Input Voltage to DGND 0 3V to Vy 0 3 V Vou to AGND 0 3V to Vbo 0 3 V AGNDF AGNDS to DGND 0 3V to 0 3 V Input Current to Any Pin Except Supplies 10 mA Operating Temperature Range AD5512A Industrial A Version 40 C to 125 C AD5542A Industrial A B Versions 40 C to 85 C Storage Temperature Range 65 C to 150 C Maximum Junction Temperature T max 150 C Package Power Dissipation Thermal Impedance 0 4 T max T 9 rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION A Atos ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD
11. equation V Veer x D OUT 3N where D is the decimal data word loaded to the DAC register N is the resolution of the DAC For a reference of 2 5 V the equation simplifies to the following 2 5xD O 65 536 This gives a Voy of 1 25 V with midscale loaded and 2 5 V with full scale loaded to the DAC The LSB size is V4 65 536 Vo UT SERIAL INTERFACE The AD5512A A D5542A are controlled by a versatile 3 or 4 wire serial interface that operates at clock rates of up to 50 MHz and is compatible with SPI QSPI MICROWIRE and DSP interface standards The timing diagram is shown in Figure 3 Input data is framed by the chip select input CS Aftera high to low transition on CS data is shifted synchronously and latched into the input register on the rising edge of the serial clock SCLK Data is loaded MSB first in 12 bit AD5512A or 16 bit AD5542A words After 12 AD5512A or 16 AD5542A data bits have been loaded into the serial input register a low to high transition on CS transfers the contents of the shift register to the DAC Data can be loaded to the part only while CS is low The AD5512A AD5542A have an LDAC function that allows the DAC latch to be updated asynchronously by bringing LDAC low after CS goes high LDAC should be maintained high while data is written to the shift register Alternatively LDAC can be tied permanently low to update the DAC synchronously With LDAC tied permanently low the
12. has been enabled As the data is clocked out on each rising edge of the serial clock an inverter is required between the DSP and the DAC because the AD5512A AD5542A clock data in on the falling edge of the SCLK LDAC ADSP 2101 C AD5512A DIN AD5542A SCLK SCLK 09199 025 ADDITIONAL PINS OMITTED FOR CLARITY Figure 36 AD5512A AD5542A to ADSP 2101 Interface AD5512A AD5542A TO MICROWIRE INTERFACE Figure 37 shows an interface between the AD5512A AD5542A and any MICROWIRE compatible device Serial data is shifted out on the falling edge of the serial clock and into the AD5512A AD5542A on the rising edge of the serial clock No glue logic is required because the DAC clocks data into the input shift register on the rising edge cs MICROWIRE so DIN SCLK SCLK AD5512A AD5542A 09199 027 ADDITIONAL PINS OMITTED FOR CLARITY Figure 37 AD5512A AD5542A to MICROWIRE Interface Rev A Page 18 of 24 AD5512A AD5542A LAYOUT GUIDELINES In any circuit where accuracy is important careful consider ation of the power supply and ground return layout helps to ensure the rated performance Design the printed circuit board PCB on which the AD5512A AD5542A is mounted so that the analog and digital sections are separated and confined to certain areas of the board If the AD5512A AD5542A are in a system where multiple devices require an analog ground to digital ground connection make the connection at one point on
13. rising edge of CS loads the data to the DAC UNIPOLAR OUTPUT OPERATION These DACs are capable of driving unbuffered loads of 60 kO Unbuffered operation results in low supply current typically 300 uA and a low offset error The AD5512A AD5542A provide a unipolar output swing ranging from 0 V to V prr The AD5512A A D5542A can be configured to output both unipolar and bipolar voltages Figure 31 shows a typical unipolar output voltage circuit The code table for this mode of operation is shown in Table 9 5V 2 5V O o SERIAL AD820 s INTERFACE REFF REFS DIN AD5512A UNIPOLAR AD5542A Vout OUTPUT SCLK LDAC EXTERNAL DGND AGNDF AGNDS OP AMP 09199 023 Figure 31 Unipolar Output Table 9 AD5542A Unipolar Code Table DAC Latch Contents MSB LSB Analog Output 111111111111 1111 Veer X 65 535 65 536 1000 0000 0000 0000 Veer X 32 768 65 536 Y2 Veer 0000 0000 0000 0001 Veer X 1 65 536 0000 0000 0000 0000 oV Rev A Page 15 of 24 AD5512A AD5542A Assuming a perfect reference the unipolar worst case output voltage can be calculated from the following equation D Vour unt 2N Uae Var Vzsg INL where Vour unr is the unipolar mode worst case output Dis the code loaded to DAC Nis the resolution of the DAC Vig is the reference voltage applied to the part V is the gain error in volts V is the zero scale error in volts INL is the integral
14. 0 C to 125 C Guaranteed by design not subject to production test 3 Reference input resistance is code dependent minimum at 0x855 Rev A Page 3 of 24 AD5512A AD5542A AD5542A Vbp 2 7 V to 5 5 V Vigac 2 7 V to 5 5 V Vy 2 5 V AGND DGND 0 V 40 C lt T lt 85 C unless otherwise noted Table 3 Parameter Min Typ Max Unit Test Condition STATIC PERFORMANCE Resolution 16 Bits Relative Accuracy INL 0 5 1 0 LSB B grade 2 0 A grade Differential Nonlinearity DNL 0 5 1 0 LSB Guaranteed monotonic Gain Error 0 5 2 LSB T 25 C 3 LSB Gain Error Temperature Coefficient 0 1 ppm C Unipolar Zero Code Error 0 3 0 7 LSB T 25 C 41 5 LSB Unipolar Zero Code Temperature Coefficient 0 05 ppm C Bipolar Resistor Matching 1 000 0 0 Rep Rinvy typically Reg Ry 28 kO 0 0015 0 0076 Ratio error Bipolar Zero Offset Error 1 5 LSB T 25 C 6 LSB Bipolar Zero Temperature Coefficient 0 2 ppm C Bipolar Zero Code Offset Error 1 5 LSB T 25 C 6 LSB Bipolar Gain Error 1 5 LSB T 25 C 6 LSB Bipolar Gain Temperature Coefficient 0 1 ppm C OUTPUT CHARACTERISTICS Output Voltage Range 0 Veer 1 LSB V Unipolar operation V REF Vrer 1 LSB V Bipolar operation DAC Output Impedance 6 25 ko Tolerance typically 20 Power Supply Rejection Ratio 1 0 LSB AVpp 10 Output Noise Spectral Density 11 8 nV VHz DAC code 0x840 AD5512A or 0x8400 AD5542A frequency 1
15. Y OF OPERATION The AD5512A AD55424 are single 12 16 bit serial input voltage output DACs They operate from a single supply ranging from 2 7 V to 5 V and consume typically 125 uA with a supply of 5 V Data is written to these devices in a 12 bit AD5512A or 16 bit AD5542A word format via a 3 or 4 wire serial interface To ensure a known power up state these parts are designed with a power on reset function In unipolar mode the output is reset to midscale in bipolar mode the output is set to 0 V Kelvin sense connections for the reference and analog ground are included on the AD5512A AD5542A DIGITAL TO ANALOG SECTION The DAC architecture consists of two matched DAC sections A simplified circuit diagram is shown in Figure 30 The DAC architecture of the AD5512A AD5542A is segmented The four MSBs of the 16 bit AD5542A 12 bit AD5512A data word are decoded to drive 15 switches El to E15 Each switch connects one of 15 matched resistors to either AGND or V The remaining 12 bits of the data word drive the SO to S11 switches of a 12 bit voltage mode R 2R ladder network Vout FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS 12 BIT R 2R LADDER 09199 022 Figure 30 DAC Architecture With this type of DAC configuration the output impedance is independent of code while the input impedance seen by the reference is heavily code dependent The output voltage is dependent on the reference voltage as shown in the following
16. _WQ CP 10 9 DFM AD5542ABCPZ 500RL7 1 LSB 1 LSB Midscale 40 C to 125 C 16 Lead LFCSP CP 16 22 DFL EVAL AD5542ASDZ AD5541A Evaluation Board 1 Z RoHS Compliant Part Rev A Page 21 of 24 AD5512A AD5542A NOTES Rev A Page 22 of 24 AD5512A AD5542A NOTES Rev A Page 23 of 24 AD5512A AD5542A NOTES 2010 2011 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D09199 0 5 11 A DEVICES www analo g com Rev A Page 24 of 24
17. ce AD5512A AD5542A TO SPORT INTERFACE The Analog Devices ADSP BF527 has one SPORT serial port Figure 34 shows how one SPORT interface can be used to control the AD5512A AD5542A AD5512A Ocs AD5542A SPORT TFS SPORT TSCK Q Q BLACK 2 ADSP BF527 GPIOO 09919 045 Figure 34 AD5512A AD5542A to ADSP BF527 Interface AD5512A AD5542A TO 68HC11 68L11 INTERFACE Figure 35 shows a serial interface between the AD5512A AD5542A and the 68HC11 68L11 microcontroller SCK of the 68HC11 68L11 drives the SCLK of the DAC and the MOSI output drives the serial data line serial DIN The CS signal is driven from one of the port lines The 68HC11 68L11 is configured for master mode MSTR 1 CPOL 0 and CPHA 0 Data appearing on the MOSI output is valid on the rising edge of SCK PC6 LDAC 68HC11 PC7 CS AD5512A DIN AD5542A SCLK 68L11 09199 026 ADDITIONAL PINS OMITTED FOR CLARITY Figure 35 AD5512A AD5542A to 68HC1 1 68L11 Interface AD5512A AD5542A TO ADSP 2101 INTERFACE Figure 36 shows a serial interface between the AD5512A AD5542A and the ADSP 2101 The ADSP 2101 should be set to operate in the SPORT transmit alternate framing mode The ADSP 2101 is programmed through the SPORT control register and should be configured as follows internal clock operation active low framing 16 bit word length Transmission is initiated by writing a word to the Tx register after the SPORT
18. d If the AD5512A AD5542A must be interfaced with data shorter than 16 bits the data should be padded with 0s at the LSBs POWER SUPPLY AND REFERENCE BYPASSING For accurate high resolution performance it is recommended that the reference and supply pins be bypassed with a 10 uF tantalum capacitor in parallel with a 0 1 uF ceramic capacitor Rev A Page 17 of 24 AD5512A AD5542A APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5512A AD55424 is via a serial bus that uses standard protocol that is compatible with DSP processors and microcontrollers The communications channel requires a 3 or 4 wire interface consisting of a clock signal a data signal and a synchronization signal The AD5512A AD5542A require a 16 bit data word with data valid on the rising edge of SCLK The DAC update can be done automatically when all the data is clocked in or it can be done under the control of the LDAC AD5512A AD5542A TO ADSP BF531 INTERFACE The SPI interface of the AD5512A AD5542A is designed to be easily connected to industry standard DSPs and micro controllers Figure 33 shows how the AD5512A AD5542A can be connected to the Analog Devices Inc Blackfin DSP The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5512A AD5542A AD5512A AD5542A SPISELx MR ADSP BF531 09199 044 Figure 33 AD5512A AD5542A to ADSP BF531 Interfa
19. de 15 Vioac Logic Power Supply 16 Vop Analog Supply Voltage 5 V 1096 Rev A Page 9 of 24 AD5512A AD5542A TYPICAL PERFORMANCE CHARACTERISTICS 0 50 0 50 Vpp 5V VREF 2 5V ZS a amp 0 25 a a 0 25 E E T T 9 i Z S z o z 2 0 25 3 a 6 H ff 0 25 z 0 50 u a 0 75 0 50 2 0 8192 16 384 24 576 32 768 40 960 49 152 57 344 65 536 O 8192 16 384 24 576 32 768 40 960 49 152 57 344 65 536 CODE B CODE E Figure 7 AD5542A Integral Nonlinearity vs Code Figure 10 AD5542A Differential Nonlinearity vs Code 0 25 0 75 0 25 0 50 0 75 INTEGRAL NONLINEARITY LSB DIFFERENTIAL NONLINEARITY LSB 1 00 K 0 50 o 60 40 20 0 20 40 60 80 100 120 1408 60 40 20 0 20 40 60 80 100 120 1408 TEMPERATURE C E TEMPERATURE C E Figure 8 AD5542A Integral Nonlinearity vs Temperature Figure 11 AD5542A Differential Nonlinearity vs Temperature 0 50 0 75 0 25 0 50 m T o o g a tc o 0 25 tc tc a tc LI LI E z 025 z 0 lt lt Ww LI z z a a 0 50 0 25 0 75 z 0 50 na 8 0 1 2 3 4 5 6 5 SUPPLY VOLTAGE V REFERENCE VOLTAGE V E Figure 9 AD5542A Linearity Error vs Supply Voltage Figure 12 AD5542A Linearity Error vs Reference Voltage Rev A Page 10 of 24 AD5512A AD5542A
20. kHz unipolar mode Output Noise 0 134 uV p p 0 1 Hz to 10 Hz DAC REFERENCE INPUT Reference Input Range 2 0 Vso V Reference Input Resistance 9 ko Unipolar operation 7 5 ko Bipolar operation Reference Input Capacitance 26 pF Code 0x0000 26 pF Code OxFFFF LOGIC INPUTS Input Current 1 yA Input Low Voltage Vix 0 8 V Vbo 2 7 V to 5 5 V Input High Voltage Vy 24 V Vbo 2 7 V to 5 5 V Input Capacitance 10 pF Hysteresis Voltage 0 15 V POWER REQUIREMENTS Vop 2 7 5 5 V All digital inputs at 0 V Vioac OF Vpop lop 125 150 uA Vin Viogic Or Vpop and V GND Viocic 1 8 5 5 V lioac 15 24 UA All digital inputs at 0 V Viae or Vpop Power Dissipation 0 625 0 825 mW 1 For 27 V lt Viggic S 5 5 V temperatures are as follows A B versions 40 C to 85 C Guaranteed by design not subject to production test 3 Reference input resistance is code dependent minimum at 0x8555 Rev A Page 4 of 24 AD5512A AD5542A AC CHARACTERISTICS Vbp 2 7 V to 5 5 V Vigac 2 7 V to 5 5 V 2 5 V Vy Voo AGND DGND 0 V 40 C lt T lt 125 C unless otherwise noted Table 4 Parameter Min Typ Max Unit Test Condition Output Voltage Settling Time 1 us To 1 2 LSB of FS C 10 pF Slew Rate 17 V us C 10 pF measured from 0 to 6396 Digital to Analog Glitch Impulse 1 1 nV sec 1LSB change around major carry Reference 3 dB Bandwidth 22 MHz All 1s loaded Reference Feedthrough 1 mV p p Al
21. l Os loaded V er 1 V p p at 100 kHz Digital Feedthrough 0 2 nV sec Signal to Noise Ratio 92 dB Spurious Free Dynamic Range 80 dB Digitally generated sine wave at 1 kHz Total Harmonic Distortion 74 dB DAC code Ox3FFF AD5512A or OxFFFF AD5542A frequency 10 kHz Vggp 2 5 V 1 V p p Rev A Page 5 of 24 AD5512A AD5542A TIMING CHARACTERISTICS Vpp 5 V 2 5 V Vre Vpp Vir 90 of Vioaic Vint 10 of Vioaic AGND DGND 0 V unless otherwise noted Table 5 Parameter Limit 1 8 lt Viocic lt 2 7 V Limit 2 7 V Vioac lt 5 5 V Unit Description fsck 14 50 MHz max SCLK cycle frequency ti 70 20 ns min SCLK cycle time t 35 10 ns min SCLK high time ts 35 10 ns min SCLK low time t 5 ns min CS low to SCLK high setup ts 5 ns min CS high to SCLK high setup te 5 ns min SCLK high to CS low hold time t 10 5 ns min SCLK high to CS high hold time tg 35 10 ns min Data setup time to 4 ns min Data hold time Viuu 90 of Von Vin 10 of Von to 5 ns min Data hold time Viu 3 V Vin O V tio 20 20 ns min LDAC pulsewidth tu 10 10 ns min CS high to LDAC low setup tio 15 15 ns min CS high time between active periods tia 15 15 ns CLR pulsewidth 1 Guaranteed by design and characterization not production tested All input signals are specified with ta te 1 ns V and timed from a voltage level of Vi Vin 2 3 40C lt Ta lt 105 C 4 40 C lt
22. l Signal Settling Time 1 236 5 cs 1 234 j 9 5 1 232 E u 10 2 1 2 K 30 d 15 gt 1 228 Vout 20 1 226 255 1 224 30 90 100 110 120 3 0 5 0 0 5 1 0 1 5 2 0 3 Ipp SUPPLY pA E TIME ns E 3 Figure 20 AD5512A AD5542A Digital to Analog Glitch Impulse Figure 23 AD5512A AD5542A Analog Supply Current Histogram 125 C 25 C 55 C e CS 5V DIV o E Vout 0 5V DIV s 15 16 18 19 E 8 TE x RAILS pA 8 Figure 21 AD5512A AD5542A Large Signal Settling Time Figure 24 AD5512A AD5542A Digital Supply Current Histogram Rev A Page 12 of 24 AD5512A AD5542A 40 Vpp 5V VREF 2 5V 20 Ta 25 C DATA 0x0000 E 0 gi ur E 20 E z o z 5 5 2 40 n E a 60 80 k 100 m 0 20 40 60 80 100 120 8 O 10 000 20 000 30 000 40 000 50 000 60 000 70 000 FREQUENCY Hz Ed FREQUENCY Hz E Figure 25 AD5512A AD5542A 0 1 Hz to 10 Hz Output Noise Figure 28 AD5512A AD5542A Total Harmonic Distortion R I a E gt gt E nd a 5 kJ 4 amp 5 5 E LI n o LI o S 600 700 800 900 1000 1100 1200 1300 1400 E 1k 10k 100k 1M 10M 100M 3 FREQUENCY Hz B FREQUENCY Hz H Figure 26 AD5512A AD5542A Noise Spectral Density vs Frequency 1 kHz Figure 29 AD5512A AD5542A Multiplying Bandwidth zA N e
23. ly Establish the star ground point as close as possible to the device The AD5512A AD5542A should have ample supply bypassing of 10 uF in parallel with 0 1 uF on each supply located as close to the package as possible ideally right up against the device The 10 uF capacitors are the tantalum bead type The 0 1 uF capacitor should have low effective series resistance ESR and low effective series inductance ESI such as the common ceramic types which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching GALVANICALLY ISOLATED INTERFACE In many process control applications it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common mode voltages that may occur iCoupler products from Analog Devices provide voltage isolation in excess of 2 5 kV The serial loading structure ofthe AD5512A AD5542A makes the parts ideal for isolated interfaces because the number of interface lines is kept to a minimum Figure 38 shows a 4 channel isolated interface to the AD5512A AD5542A using an ADuM1400 For further information visit http www analog com icouplers CONTROLLER ADuM1400 ADDITIONAL PINS OMITTED FOR CLARITY 09199 046 Figure 38 Isolated Interface DECODING MULTIPLE DACS The CS pin of the AD5512A AD5542A can be used to select one of a number
24. mperature It is expressed in mV C Digital to Analog Glitch Impulse Digital to analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state It is normally specified as the area of the glitch in nV sec and is measured when the digital input code is changed by 1 LSB at the major carry transition A digital to analog glitch impulse plot is shown in Figure 20 Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but it is measured when the DAC output is not updated CS is held high while the SCLK and DIN signals are toggled It is specified in nV sec and is measured with a full scale code change on the data bus that is from all 0s to all 1s and vice versa A typical digital feedthrough plot is shown in Figure 19 Power Supply Rejection Ratio PSRR PSRR indicates how the output of the DAC is affected by changes in the power supply voltage The power supply rejection ratio is quoted in terms of percent change in output per percent change in Vpp for full scale output of the DAC V is varied by 10 Reference Feedthrough Reference feedthrough is a measure of the feedthrough from the V xer input to the DAC output when the DAC is loaded with all Os A 100 kHz 1 V p p is applied to Vr Reference feedthrough is expressed in mV p p Rev A Page 14 of 24 AD5512A AD5542A THEOR
25. n 3 Low 11 8 nV VHz noise spectral density Low 0 05 ppm C temperature drift 3 mm x 3 mm LFCSP and TSSOP packaging gus One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2010 2011 Analog Devices Inc All rights reserved AD5512A AD5542A TABLE OF CONTENTS Features corr EEUU ERREUR EARS RETE 1 Applicaton Sanesi n R 1 General Description isisisi rasaae aasa ttd eH der 1 Functional Block Diagram seen 1 Product Highlights iioi ti EV s 1 REVISION HIStory i os eei a Ox EGER ERAT REA ANE 2 Specifications dioe b HO ob endete 3 PDS OV DIAG ecu op NU Iu ned 3 ADEL PA qe 4 AG Characteristics cc ee ERIT TREE E 5 Timing Characteristics sisien ire 6 Absolute Maximum Ratings seen 7 ESD Ca tion i uarie de eti ee ue 7 Pin Configuration and Function Descriptions 8 Typical Performance Characteristics sss 10 Terminology nina Senja 14 Theory of Operation ccceeesseessesesseesessessesessessessessessesseesees 15 Digital to Analog Section eee 15 Serial Interface iacere itp ij anni 15 REVISION HISTORY 5 11 Rev 0 to Rev A Changes to Table 3 Power Dissipation Value and Endnote 1 4 Changes to Table 5 Changes to Ordering Guide 10 10 Revision 0 Initial Version Unipolar Output Operation eerte 15 Bipolar Ou
26. nonlinearity in volts BIPOLAR OUTPUT OPERATION With the aid of an external op amp the AD5512A AD5542A can be configured to provide a bipolar voltage output A typical circuit is shown in Figure 32 The matched bipolar offset resistors Ry and Ry are connected to an external op amp to achieve this bipolar output swing typically R Ry 28 kO Table 10 shows the transfer function for this output operating mode Also provided on the AD55424 are a set of Kelvin connections to the analog ground inputs The example includes the ADR421 45V 42 5V Q Q 10pF j SERIAL INTERFACE 2 5 V reference and the AD8628 low offset and zero drift reference buffer Table 10 AD5542A Bipolar Code Table DAC Latch Contents MSB LSB Analog Output 111111111111 1111 AV per X 32 767 32 768 1000 0000 0000 0001 Vg X 1 32 768 1000 0000 0000 0000 OV 011111111111 1111 Vy X 1 32 768 0000 0000 0000 0000 Vger X 32 768 32 768 V per 0 1uF Assuming a perfect reference the worst case bipolar output voltage can be calculated from the following eguation Vour_unr Vos 2 RD V rer Q RD 1 G RD A V OUT BIP where Vour_gp is the bipolar mode worst case output Vour unr is the unipolar mode worst case output Vos is the external op amp input offset voltage RD is the R and Ry resistor matching error A is the op amp open loop gain O BIPOLAR OUTPUT O 5V EXTERNAL OP AMP 09199 024
27. of DACs All devices receive the same serial clock and serial data but only one device receives the CS signal at any one time The DAC addressed is determined by the decoder There is some digital feedthrough from the digital input lines Using a burst clock minimizes the effects of digital feedthrough on the analog signal channels Figure 39 shows a typical circuit AD5512A Serko cs AD5542A DINO ENABLEO AD5512A es AD5542A CODED ADDRESS AD5512A cg AD5542A Vour 09199 030 Figure 39 Addressing Multiple DACs Rev A Page 19 of 24 AD5512A AD5542A OUTLINE DIMENSIONS 0 30 zu PIN 1 0 18 PIN 1 INDICATOR INDICATOR 1 75 1 60 SQ 1 45 0 0 25 MIN 040 A BOTTOM VIEW 0 30 0 80 FOR PROPER CONNECTION OF 0 75 THE EXPOSED PAD REFER TO 0 70 a cem E 0 05 MAX THE PIN CONFIGURATION AND M 0 02 FUNCTION DESCRIPTIONS A mai ARity SECTION OF THIS DATA SHEET SEATING DA 0 08 PLANE 0 20 REF COMPLIANT TO JEDEC STANDARDS MO 220 WEED 6 Figure 40 16 Lead Lead Frame Chip Scale Package LFCSP_WQ 3 mm x 3 mm Body Very Very Thin Quad CP 16 22 Dimensions shown in millimeters 0 20 0 09 yj 0 75 Ei l 0 60 4 L 0 30 A 0 65 049 SEATING 9 0 45 BSC PLANE COPLANARITY 0 10 COMPLIANT TO JEDEC STANDARDS MO 153 AB Figure 41 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 Dimensions shown in millimeters Rev A Page 20 of 24
28. ons Pin No Mnemonic Description 1 Reg Feedback Resistor Pin In bipolar mode connect this pin to the external op amp output 2 Vour Analog Output Voltage from the DAC 3 AGNDF Ground Reference Point for Analog Circuitry Force 4 AGNDS Ground Reference Point for Analog Circuitry Sense 5 REFS Voltage Reference Input Sense for the DAC Connect to an external 2 5 V reference Reference can range from 2V to V 6 REFF Voltage Reference Input Force for the DAC Connect to an external 2 5 V reference Reference can range from 2V to V 7 NC No Connect 8 CS Logic Input Signal The chip select signal is used to frame the serial data input 9 SCLK Clock Input Data is clocked into the input register on the rising edge of SCLK Duty cycle must be between 4096 and 6096 10 DIN Serial Data Input This device accepts 16 bit words Data is clocked into the input register on the rising edge of SCLK 11 CLR Asynchronous Clear Input The CLR input is falling edge sensitive When CLR is low all LDAC pulses are ignored When CLR is activated the DAC register is cleared to the model selectable midscale 12 LDAC LDAC Input When this input is taken low the DAC register is simultaneously updated with the contents of the input register 13 DGND Digital Ground Ground reference for digital circuitry 14 INV Connection to the Internal Scaling Resistors of the DAC Connect the INV pin to the external op amps inverting input in bipolar mo
29. serial data input 7 NC No Connect 8 3 SCLK Clock Input Data is clocked into the input register on the rising edge of SCLK Duty cycle must be between 4096 and 6096 9 4 DIN Serial Data Input This device accepts 16 bit words Data is clocked into the input register on the rising edge of SCLK 10 5 CLR Asynchronous Clear Input The CLR input is falling edge sensitive When CLR is low all LDAC pulses are ignored When CLR is activated the DAC register is cleared to the model selectable midscale 11 LDAC LDAC Input When this input is taken low the DAC register is simultaneously updated with the contents of the input register 12 DGND Digital Ground Ground reference for digital circuitry 13 7 INV Connection to the Internal Scaling Resistors of the DAC Connect the INV pin to the external op amps inverting input in bipolar mode 14 Vioaic Logic Power Supply 15 9 Vso Analog Supply Voltage 5 V 10 16 8 Reg Feedback Resistor Pin In bipolar mode connect this pin to the external op amp output 1 REF Voltage Reference Input for the DAC Connect this pin to an external 2 5 V reference Reference can range from 2 V to Vpp 10 GND Ground EPAD Exposed Pad The exposed pad should be tied to the point of lowest potential in this case GND Rev A Page 8 of 24 AD5512A AD5542A AD5542A TOP VIEW Not to Scale 09199 035 NC NO CONNECT Figure 6 AD5542A 16 Lead TSSOP Pin Configuration Table 8 AD5542A Pin Function Descripti
30. tput Operation seen 16 Output Amplifier Selection see 17 Force Sense Amplifier Selection sss 17 Reference and Ground reete 17 Power On R6setz eee RENE 17 Power Supply and Reference Bypassing sss 17 Applications Information 18 Microprocessor Interfacing eerte 18 AD5512A AD5542A to ADSP BF531 Interface 18 AD5512A AD5542A to SPORT Interface 18 AD5512A AD5542A to 68HC11 68L11 Interface 18 AD5512A AD5542A to ADSP 2101 Interface 18 AD5512A AD5542A to MICROWIRE Interface Layout Guidelines isis spaja eiit og REESE 19 Galvanically Isolated Interface sss 19 Decoding Multiple DACs sse 19 Outline Dimensioni isteria iR sS ESS 20 Ordering Guides oia optet REDE 21 Rev A Page 2 of 24 AD5512A AD5542A SPECIFICATIONS AD5512A V pp 2 7 V to 5 5 V Viggo 2 7 V to 5 5 V Vy 2 5 V AGND DGND 0 V 40 C lt T lt 125 C unless otherwise noted Table 2 Parameter Min Typ Max Unit Test Condition STATIC PERFORMANCE Resolution 12 Bits Relative Accuracy INL 0 5 1 0 LSB Differential Nonlinearity DNL 0 5 1 0 LSB Guaranteed monotonic Gain Error 0 5 2 LSB Gain Error Temperature Coefficient 0 1 ppm C Unipolar Zero Code Error 0 03 0 5 LSB

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