Home

ANALOG DEVICES AD9125 handbook

1. Register Name Hex Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit Oo Default FTW 1 LSB 0x30 FTWI7 0 0x00 FTW 2 0x31 FTW 15 8 0x00 FTW 3 0x32 FTW 23 16 0x00 FTW 4 MSB 0x33 FTW 31 24 0x00 NCO Phase Offset 0x34 NCO phase offset 7 0 0x00 LSB NCO Phase Offset 0x35 NCO phase offset 15 8 0x00 MSB NCO FTW Update 0x36 Frame Frame FTW Update Update 0x00 FTW ack request FTW ack FTW request Phase Adj LSB 0x38 phase adjust 7 0 0x00 Phase Adj MSB 0x39 phase adjust 9 8 0x00 Phase Adj LSB Ox3A Q phase adjust 7 0 0x00 Phase Adj MSB 0x3B phase adjust 9 8 0x00 DAC Offset LSB Ox3C I DAC offset 7 0 0x00 I DAC Offset MSB 0x3D DAC offset 15 8 0x00 QDAC Offset LSB Ox3E DAC offset 7 0 0x00 DAC Offset MSB Ox3F DAC offset 15 8 0x00 DAC FS Adjust 0x40 I DAC FS adjust 7 0 OxF9 I DAC Control 0x41 IDAC DAC FS adjust 9 8 0x01 sleep Aux DAC Data 0x42 aux DAC 7 0 0x00 Aux DAC 0x43 Aux Aux DAC aux DAC aux DAC 9 8 0x00 Control DAC sign current sleep direction QDACFS Adjust 0x44 Q DAC FS adjust 7 0 OxF9 Q DAC Control 0x45 QDAC Q DAC FS adjust 9 8 0x01 sleep Aux DAC Q Data 0x46 Q aux DAC 7 0 0x00 Q Aux DAC 0x47 Q Aux Q Aux DAC Qaux Q aux DAC 9 8 0x00 Control DAC sign current DAC direction sleep Die Temperature 0x48 FS current 2 0 Reference current 2 0 Capacitor 0x02 Range Control value Die Temperature 0x49 Die temperature 7 0 N A LSB Die Tempe
2. 250 MSPS e 4x interpolation e 140 MHz e fonter 175 MHz As shown in Figure 58 the value at 0 7 x is 0 6 This is calculated as 0 8 2 0 7 0 6 0 6 Therefore the AD9125 supports a bandwidth of 60 of which exceeds the required 5696 The signal center frequency is 0 7 x foara and assuming the input signal is at baseband the frequency shift required is also 0 7 Using the settings detailed in the second row in the IF column in the 4x interpolation section in Table 21 selects the filter modes that give a center frequency of fpara 2 and no frequency translation The selected modes for the three half band filters are HB1 Mode 1 HB2 Mode 1 and HB3 bypassed Because Mode 1 of HB1 was selected the premodulation block should be enabled This provides fpara 2 modulation which centers the baseband input data at the center frequency of HB1 The digital modulator can be used to provide the final frequency translation of 0 2 to place the output signal at 0 7 x as desired The formula for calculating the FTW of the NCO is FTW JCARBIER x2 32 NCO where fcarrier 0 2 fuco 2 fata Therefore FTW 222 10 15 20 fine 2 0 x fing 09016 030 Figure 60 Signal Propagation for 8x Interpolation foara Modulation Rev 0 Page 37 of 56 DATA RATES VS INTERPOLATION MODES Table 23 summarizes the maximum bus speed
3. i t e 32 Interpolation Filters 32 REVISION HISTORY 6 10 Revision 0 Initial Version NCO Modulatioti tee Ree 35 Datapath Configuration seen 35 Determining Interpolation Filter 36 Datapath Configuration Example sss 37 Data Rates vs Interpolation 38 Coarse Modulation Mixing 38 Quadrature Phase Correction sse 39 DG Offset COrFeCtlOIL bee 39 Inverse Sinc Filt r ADR RR TRAE 39 DAC Input Clock Configurations seen 40 DAC Input Clock Configurations eee 40 Analog tide tetto e etas 42 Transmit DAC Operation seen 42 Auxiliary DAC Operation s 43 Baseband Filter Implementation sse 44 Driving the ADE5375 15 ette tete 44 Reducing LO Leakage and Unwanted Sidebands 44 Device Power Dissipation cccccessssssecessssesesssessssseesessesenees 45 Temperature Sensor nodiri ii 46 Multichip Synchronization see 47 Synchronization with Clock Multiplication 47 Synchronization with Direct Clocking 49 Data Rate Mode Synchronization sss 49 FIFO Rate Mode Synchronization
4. EE 1 Applications e ten 1 General DescriptioMs 1 Product Highlights ette 1 Typical Signal Chain sees 1 REVISION 2 Functional Block Diagram sete 3 5 RR 4 DG Specifications ete OD RI irs 4 Digital Specifications seen 5 Latency and Power Up Timing Specifications 5 AC Specifications c i reete tiere deerit 6 Absolute Maximum Ratings eerte 7 Thermal Resistance siiis aia ai 7 ESD Caution ice N 7 Pin Configuration and Function 8 Typical Performance Characteristics sess 10 Mosi s 16 Theory of Operation tete tte tete ente n dere neci 17 Serial Port Operation cie Re TER 17 Data Format a eterne E 17 Serial Port Pin Descriptions 17 Serial Port Options a aspras eet etnies eae ene tele 18 Device Configuration Register Map sse 19 Device Configuration Register Descriptions 21 CMOS Input Data Ports irrien 29 Dials Word Mode ettet tere tier itid 29 Word eae 29 Byte 29 Interface Timing cicer p Uia 30 oet abet sets 30 Digital 32
5. Rev 0 Page 51 of 56 INTERRUPT REQUEST OPERATION The AD9125 provides an interrupt request output signal on Pin 7 IRQ that can be used to notify an external host processor of significant device events Upon assertion of the interrupt the device should be queried to determine the precise event that occurred The IRQ pin is an open drain active low output Pull the IRQ pin high external to the device This pin can be tied to the interrupt pins of other devices with open drain outputs to wire OR these pins together Sixteen event flags provide visibility into the device These 16 flags are located in the two event flag registers Register 0x06 and Register 0x07 The behavior of each of the event flags is independently selected in the interrupt enable registers Register 0x04 and Register 0x05 When the flag interrupt enable is active the event flag latches and triggers an external interrupt When the flag interrupt is disabled the event flag simply monitors the source signal and the external IRQ remains inactive Figure 86 shows the IRQ related circuitry This diagram shows how event flag signals propagate to the IRQ output The INTERRUPT_ ENABLE signal represents one bit from the interrupt enable registers The EVENT FLAG SOURCE signal represents one bit from the event flag registers The EVENT FLAG SOURCE signal represents one of the device signals that can be monitored such as the PLL LOCKED signal from the PLL ph
6. the supported input data rates and the signal bandwidths for various combinations of bus width modes and interpolation rates The maximum bus speed in any mode is 250 MHz The maximum DAC update rate fnac in any mode is 1000 MHz The real signal bandwidth supported is a fraction of the input data rate which depends on the interpolation filter HB1 HB2 or HB3 selected The complex signal bandwidth supported is twice the real signal bandwidth In general 2x interpolation is best supported by enabling HB1 and 4x interpolation is best supported enabling HB1 and HB2 In some cases power dissipation can be lowered by avoiding HB1 If the bandwidth required is low enough 2x interpolation can be supported by using HB2 and 4x interpolation can be supported by using HB2 and HB3 COARSE MODULATION MIXING SEQUENCES The coarse digital quadrature modulation occurs within the interpolation filters The modulation shifts the frequency spectrum of the incoming data by the frequency offset selected The frequency offsets available are multiples of the input data rate The modulation is equivalent to multiplying the quadrature input signal by a complex carrier signal C t of the form C t cos wt j sin we In practice this modulation results in mixing functions as shown in Table 22 Table 22 Modulation Mixing Sequences Modulation Mixing Sequence fs 2 I 14 2 1H Hl Q Q 9 Q Q fs 4 1
7. REFCLK input Rev 0 Page 22 of 56 Register Address Name Hex Bits Name Description Default PLL Control 1 Ox0A 7 PLL enable 1 enables the PLL clock multiplier REFCLK input is 0 used as the PLL reference clock signal 6 PLL manual enable Enables the manual selection of the VCO band 1 1 2 manual mode the correct VCO band must be determined by the user 5 0 Manual VCO band Selects the VCO band to be used 0 PLL Control 2 OxOC 7 5 PLL loop Selects the PLL loop filter bandwidth 110 bandwidth 2 0 000 loop bandwidth is nominally 200 kHz 010 loop bandwidth is nominally 450 kHz 100 loop bandwidth is nominally 950 kHz 110 loop bandwidth is nominally 2 MHz 4 0 PLL charge pump Sets the nominal PLL charge pump current 10001 current 4 0 00000 lowest current setting 11111 highest current setting PLL Control 3 0x0D 7 6 N2 1 0 PLL control clock divider These bits determine the ratio 3 of the DACCLK rate to the PLL controller clock rate fec ax must always be less than 80 MHz 00 foacak fec 2 01 foacak fec 4 10 fpacak fec 8 11 fpacak fec 16 4 PLL cross control enable Enables PLL cross point controller 1 3 2 NO 1 0 PLL VCO divider These bits determine the ratio of the 10 VCO output to the DACCLK frequencies 00 fvco foaccik 1 01 fvco foaccik 2 10 fvco foaccik 4 11 fvco foaccik 4 1 0 N1
8. 1 X 2xR R AD9125 ADL537x IOUTIP IBBP IOUTIN O IBBN IOUT2N Q QBBN IOUT2P O QBBP 09016 041 Figure 73 Typical Interface Circuitry Between the AD9125 and the ADL537x Family of Modulators BASEBAND FILTER IMPLEMENTATION Most applications require a baseband anti imaging filter between the DAC and the modulator to filter out Nyquist images and broadband DAC noise The filter can be inserted between the I V resistors at the DAC output and the signal level setting resistor across the modulator input This configuration establishes the input and output impedances for the filter Figure 75 shows a fifth order low pass filter A common mode choke is used between the I V resistors and the remainder of the filter This removes the common mode signal produced by the DAC and prevents the common mode signal from being converted to a differential signal which can appear as unwanted spurious signals in the output spectrum Splitting the first filter capacitor into two and grounding the center point creates a common mode low pass filter providing additional common mode rejection of high frequency signals A purely differential filter can pass common mode signals DRIVING THE ADL5375 15 The ADL5375 15 is the version of the ADL5375 that offers an input baseband bias levels of 1500 mV Because the ADL5375 15 requires a 1500 mV dc bias it requires a slightly more complex interface than most other Analog Devices Inc mod
9. Figure 39 Serial Register Interface Timing LSB First 1 t 1 1 ILa DS 1 Es 3 tsek gt SDIO r tpwH a ipw 1 INSTRUCTION 7 X INSTRUCTION 6 Figure 40 Timing Diagram for Serial Port Register Write tps to tots Rev 0 Page 18 of 56 tye 4 1 1 DATA BIT n DATA BITn 1 Figure 41 Timing Diagram for Serial Port Register Read 09016 011 09016 012 09016 013 09016 014 DEVICE CONFIGURATION REGISTER MAP Table 10 Device Configuration Register Map Addr Register Name Hex Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit O0 Default Comm 0x00 SDIO LSB FIRST Reset 0x00 Power Control 0x01 Power Power Power Power PLL lock 0x10 down down downdata down status DACI DACQ receiver aux ADC Data Format 0x03 Binary Q data MSB swap Data bus width 1 0 0x00 data first format Interrupt Enable 1 0x04 Enable Enable Enable Enable Enable Enable Enable Enable 0x00 PLL lock PLL sync sync sync soft FIFO FIFO lost lock signal signal phase FIFO Waming 1 Warning 2 lost lock lock sync Interrupt Enable2 0x05 0 0 0 Enable Enable Enable 0 0 0x00 AED AED SED compare compare compare pass fail fail Event Flag 1 0x06 PLL PLL Sync Sync Sync Soft FIFO FIFO N A lock locked signal signal phase FIFO Waming1 Warning 2 lost lost locked locked sync Event Flag 2 0x07 AED AED SED N A compare comp
10. Temperature Drift Temperature drift is specified as the maximum change from the ambient 25 C value to the value at either Tmn or Tmax For offset and gain drift the drift is reported in ppm of full scale range FSR per degree Celsius For reference drift the drift is reported in ppm per degree Celsius Power Supply Rejection PSR The maximum change in the full scale output as the supplies are varied from minimum to maximum specified voltages DATA FORMAT LN finTERFACE 1 1 Settling Time The time required for the output to reach and remain within a specified error band around its final value measured from the start of the output transition Spurious Free Dynamic Range SFDR The difference in decibels between the peak amplitude of the output signal and the peak spurious signal within the dc to the Nyquist frequency of the DAC Typically energy in this band is rejected by the interpolation filters This specification therefore defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output Signal to Noise Ratio SNR SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency excluding the first six harmonics and dc The value for SNR is expressed in decibels Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fpara interpolati
11. 09016 019 Figure 48 FRAME Input vs Write Pointer Value Data Rate Mode Write Pointer Initialization via FRAME Signal In FIFO rate synchronization mode the REFCLK SYNC signal is used to reset the FIFO read pointer to 0 The edge of the DAC clock used to sample the SYNC signal is selected by Bit 3 of Register 0x10 The FRAME signal is used to reset the FIFO write pointer In the FIFO rate synchronization mode the FIFO write pointer is reset immediately after the FRAME signal is asserted high for at least the time interval needed to load complete data to the I and DACs The FIFO write pointer is initialized to the value of the FIFO phase offset 2 0 Register 0x17 FIFO rate synchronization is selected by setting Bit 6 of Register 0x10 to 0 FIFO WRITE RESET FIFO PHASE OFFSET 2 0 FRAME REGISTER 0x17 BITS 2 0 0b101 WRITE POINTER Figure 49 FRAME Input vs Write Pointer Value FIFO Rate Mode 09016 148 Monitoring the FIFO Status The FIFO initialization and status can be read from Register 0x18 This register provides information on the FIFO initialization method and whether the initialization was successful The MSB of Register 0x18 is a FIFO warning flag that can optionally trigger a device interrupt IRQ This flag is an indication that the FIFO is close to emptying FIFO level is 1 or overflowing FIFO level is 7 This is an indication that data may soon be corrupted and action should be taken The FIFO da
12. 50 SDO Serial Port Data Output CMOS levels with respect to IOVDD 51 SDIO Serial Port Data Input Output CMOS levels with respect to IOVDD 52 SCLK Serial Port Clock Input CMOS levels with respect to IOVDD 53 CS Serial Port Chip Select Active Low CMOS levels with respect to IOVDD 54 RESET Reset Active Low CMOS levels with respect to IOVDD 55 NC No Connect 56 AVSS Analog Supply Common 57 AVDD33 3 3V Analog Supply 58 IOUT2P DAC Positive Current Output 59 IOUT2N Q DAC Negative Current Output 60 AVDD33 3 3V Analog Supply 61 AVSS Analog Supply Common 62 REFIO Voltage Reference Nominally 1 2 V output Should be decoupled to analog common 63 FSADJ Full Scale Current Output Adjust Place a 10 resistor on the analog common 64 AVSS Analog Common 65 AVDD33 3 3V Analog Supply 66 IOUTIN DAC Negative Current Output 67 IOUT1P DAC Positive Current Output 68 AVDD33 3 3 V Analog Supply 69 REFCLKN PLL Reference Clock Input Negative This pin has a secondary function as the SYNC input 70 REFCLKP PLL Reference Clock Input Positive This pin has a secondary function as the SYNC input 71 CVDD18 1 8 V Clock Supply Supplies clock receivers clock distribution and PLL circuitry 72 CVDD18 1 8 V Clock Supply Supplies clock receivers clock distribution and PLL circuitry EPAD Exposed pad must be connected to AVSS This provides an electrical thermal and mechanical connection to the PCB Rev
13. Figure 46 Timing Diagram for Frame input 09016 147 Table 14 FRAME Setup and Hold Times Minimum Setup Time ts rrame Minimum Hold Time tu Frame ns ns 0 04 1 05 32 BITS INPUT DATA DATA LATCH ASSEMBLER TAN WRITE POINTER DCI 32 BITS The data interface timing can be verified by using the sample error detection SED circuitry See the Interface Timing Validation section for details FIFO OPERATION The AD9125 contains a 2 channel 16 bit wide eight word deep FIFO designed to relax the timing relationship between the data arriving at the DAC input ports and the internal DAC data rate clock The FIFO acts as a buffer that absorbs timing variations between the data source and DAC such as the clock to data variation of an FPGA or ASIC which significantly increases the timing budget of the interface Figure 47 shows the block diagram of the datapath through the FIFO The data is latched into the device and is formatted and then it is written into the FIFO register determined by the FIFO write pointer The value of the write pointer is incremented every time a new word is loaded into the FIFO Meanwhile data is read from the FIFO register determined by the read pointer and fed into the digital datapath The value of the read pointer is updated every time data is read into the datapath from the FIFO This happens at the data rate that is the DACCLK rate divided by the interpolation ratio V
14. For multibyte transfers A6 is the starting byte address The remaining register addresses are generated by the device based on the LSB FIRST bit Register 0x00 Bit 6 SERIAL PORT PIN DESCRIPTIONS Serial Clock SCLK The serial clock pin synchronizes data to and from the device and runs the internal state machines The maximum frequency of SCLK is 40 MHz data input is registered on the rising edge of SCLK AII data is driven out on the falling edge of SCLK Chip Select CS An active low input starts and gates a communication cycle It allows more than one device to be used on the same serial communication lines The SDO and SDIO pins go to a high impedance state when this input is high During the communication cycle the CS pin should stay low Serial Data I O SDIO Data is always written into the device on this pin However this pin can be used as a bidirectional data line The configuration of this pin is controlled by Register 0x00 Bit 7 The default is Logic 0 configuring the SDIO pin as unidirectional Serial Data Out SDO Data is read from this pin for protocols that use separate lines for transmitting and receiving data In the case where the device operates in a single bidirectional I O mode this pin does not output data and is set to a high impedance state Rev 0 Page 17 of 56 SERIAL PORT OPTIONS The serial port can support both MSB first and LSB first data formats This functionality is contro
15. Mode 4 through Mode 7 modulate the input signal by fno When HB2 operates in Mode 0 and Mode 4 the I and Q paths operate independently and no mixing of the data between channels occurs When HB2 operates in the other six modes mixing of the data between the I and Q paths occurs therefore the data input to the filter is assumed complex Rev 0 Page 33 of 56 Table 18 summarizes the HB2 and HB3 modes Half Band Filter 3 HB3 Table 18 HB2 and HB3 Filter Mode Summary HB3 has eight modes of operation that function the same as HB2 The primary difference between HB2 and HB3 is the filter Mode fcenter fmon Input Data 0 DC None Real or complex baridwidtlis 1 fin 4 None Complex Figure 56 shows the pass band filter response for HB3 In most 2 fin 2 None Complex applications the usable bandwidth of the filter is limited by the 3 3fin 4 None Complex image suppression provided by the stop band rejection not by 4 fin fin Real or complex the pass band flatness Table 20 shows the pass band flatness 5 Sfin 4 fin Complex and stop band rejection that the HB3 filter supports at different 6 6fin 4 fin Complex bandwidths 7 7fin 4 fin Complex 0 02 Figure 55 shows the pass band filter response for HB2 In most applications the usable bandwidth of the filter is limited by the image suppression provided by the stop band rejection not by the pass band flatness Table 19 shows the pass band flatness and stop band rejection that t
16. PLL Clock Multiplication Circuit Rev 0 Page 40 of 56 PLL Settings There are three settings for the PLL circuitry that should be programmed to their nominal values Table 24 lists the recommended PLL settings for these parameters Table 24 PLL Settings Address Optimal PLL SPI Control Register Bits Setting PLL Loop Bandwidth 2 0 OxOC 75 110 PLL Charge Pump Current 4 0 0 0 4 0 10001 PLL Cross Control Enable OxOD 4 1 Configuring the VCO Tuning Band The PLL VCO has a valid operating range from approximately 1 0 GHz to 2 1 GHz covered in 63 overlapping frequency bands For any desired VCO output frequency there may be several valid PLL band select values The frequency bands of a typical device are shown in Figure 65 Device to device variations and operating temperature affect the actual band frequency range Therefore it is required that the optimal PLL band select value be determined for each individual device Automatic VCO Band Select The device has an automatic VCO band select feature on chip Using the automatic VCO band select feature is a simple and reliable method of configuring the VCO frequency band This feature is enabled by writing 0x80 to Register 0x0A When this value is written the device executes an automated routine that determines the optimal VCO band setting for the device The setting selected by the device ensures that the PLL remains locked over the full 40 C t
17. point impedance of the DAC outputs is equal to 2 x Ro Figure 69 illustrates the output voltage waveforms IOUT1P Vip 09016 038 IOUT2N Figure 68 Basic Transmit DAC Output Circuit 09016 039 VpEAK Figure 69 Voltage Output Waveforms The common mode signal voltage Vcw is calculated as I Vom Ro The peak output voltage V zax is calculated as Irs X Ro With this circuit configuration the single ended peak voltage is the same as the peak differential output voltage Transmit DAC Linear Output Signal Swing To achieve optimum performance the DAC outputs have a linear output compliance voltage range that must be adhered to The linear output signal swing is dependent on the full scale output current Iourrs and the common mode level of the output Figure 70 and Figure 71 show the IMD performance vs the common mode output voltage at various full scale currents and output frequencies 10mA 20mA 65 30mA 70 o m 5 75 a 80 85 90 0 0 2 0 4 0 6 0 8 1 0 1 2 14 2 V 8 Figure 70 IMD vs Common Mode Output Voltage four 61 MHz Riosp 50 differential Irs 10 mA 20 mA and 30 mA IMD dBc 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 Vemo V Figure 71 IMD vs Common Mode Output Voltage four 161 MHz Rioap 50 differential Irs 10 mA 20 m
18. x Roll Off The sinc filter is enabled by default It can be bypassed by setting the bypass sinc bit Register 0x1B Bit 6 Rev 0 Page 39 of 56 DAC INPUT CLOCK CONFIGURATIONS DAC INPUT CLOCK CONFIGURATIONS The AD9125 DAC sample clock DACCLK can be sourced directly or by clock multiplying Clock multiplying employs the on chip phased locked loop PLL that accepts a reference clock operating at a submultiple of the desired DACCLK rate most commonly the data input frequency The PLL then multiplies the reference clock up to the desired DACCLK frequency which can be used to generate all the internal clocks required by the DAC The clock multiplier provides a high quality clock that meets the performance requirements of most applications Using the on chip clock multiplier removes the burden of generating and distributing the high speed DACCLK The second mode bypasses the clock multiplier circuitry and allows DACCLK to be sourced directly to the DAC core This mode enables the user to source a very high quality clock directly to the DAC core Sourcing the DACCLK directly through the REFCLKP REFCLKN DACCLKP and DACCLKN pins may be necessary in demanding applications that require the lowest possible DAC output noise particularly when directly synthesizing signals above 150 MHz Driving the DACCLK and REFCLK Inputs The REFCLK and DACCLK differential inputs share similar clock receiver input circuitry Figure 63 shows a sim
19. 0 Page 9 of 56 TYPICAL PERFORMANCE CHARACTERISTICS fpata 125MSPS SECOND HARMONIC 0dBFS 10 fpata 125MSPS THIRD HARMONIC 3 6dBFS fpata 250MSPS SECOND HARMONIC 12dBFS 20 fparA 250MSPS THIRD HARMONIC 71 18dBFS 30 o o m 40 5 8 8 z 50 2 60 ES i 70 80 90 100 0 300 5 8 four MHz 8 four MHz 8 Figure 4 Harmonics vs four over foarta 2 Interpolation Figure 7 Second Harmonic vs four over Digital Scale 2x Interpolation Digital Scale 0 dBFS fsc 20 mA foara 250 MSPS fsc 20 mA 0 50 fpata 125MSPS SECOND HARMONIC 0dBFS 10 125MSPS THIRD HARMONIC 3 55 6dBFS fpata 250MSPS SECOND HARMONIC 12dBFS 20 1 250MSPS THIRD HARMONIC 71 60 18dBFS L 30 65 o o m 40 70 8 8 50 z 75 o z 60 80 i 70 85 80 90 90 95 100 100 0 100 200 300 400 500 600 8 0 50 100 150 200 250 300 8 four MHz 8 four MHz 8 Figure 5 Harmonics vs four over fara 4 Interpolation Figure 8 Third Harmonic vs four over Digital Scale 2x Interpolation Digital Scale 0 dBFS fsc 20 mA foara 250 MSPS fsc 20 mA fpata 125MSPS SECOND HARMONIC HARMONI
20. 0 and is held there until the bit is written low Power Control 0x01 7 Power down DAC I 1 2 powers down DAC I 0 6 Power down DAC Q 1 2 powers down DAC Q 0 Power down data 1 2 powers down the input data receiver 0 receiver 4 Power down auxiliary 1 2 powers down the auxiliary ADC for temperature 0 ADC sensor 0 PLL lock status 1 is locked 0 Data Format 0x03 7 Binary data format 0 input data is twos complement format 0 1 input data is in binary format 6 data first Indicates 1 data pairing on data input 0 0 I data sent to data receiver first 1 data sent to data receiver first 5 MSB swap Swaps the bit order of the data input port 0 0 order of the data bits corresponds to the pin descriptions 1 bit designations are swapped most significant bits become the least significant bits 1 0 Data bus width Data receiver interface mode 0 00 2 dual word mode 32 bit interface bus width 01 2 word mode 16 bit interleaved interface bus width 10 byte mode 8 bit interleaved interface bus width 11 invalid See the CMOS Input Data Ports section for details on the operation of the different interface modes Interrupt Enable 1 0x04 7 Enable PLL lock lost 1 enables interrupt for PLL lock lost 0 6 Enable PLL lock 1 enables interrupt for PLL lock 0 5 Enable syncsignallost 1 enables interrupt for sync signal lock lost 0 4 Enable sync signal lock 1 enables interrupt for sync signal lock 0 3 Enable sync p
21. 0 register or the values in Register 0x70 through Register 0x73 are significant if the SED is not enabled 5 Sample error detected 1 indicates an error is detected The bit remains set 0 until cleared Any write to this register clears this bit to O 3 Autoclear enable 1 enables autoclear mode This activates Bit 1 and Bit 0 of this register and causes Register 0x70 through Register 0x73 to be autocleared whenever eight consecutive error free sample data sets are received 1 Compare fail 1 indicates an error has been detected This bit 0 remains high until it is autocleared by the reception of eight consecutive error free comparisons or until it is cleared by writing to this register 0 Compare pass 1 indicates that the last sample comparison was error free 0 Compare 10 LSBs 0x68 7 0 Compare Value 10 7 0 Compare Value 10 15 0 is the word that is compared B6 with the IO input sample captured at the input interface Compare 10 MSBs 0x69 7 0 Compare Value 10 15 8 See Register 0x68 7A Compare QO LSBs Ox6A 7 0 Compare Value Q0 7 0 Compare Value Q0 15 0 is the word that is compared 45 with the QO input sample captured at the input interface Compare Q0 MSBs Ox6B 7 0 Compare Value See Register 0x6A EA 00115 8 Compare 11 LSBs 0 6 7 0 Compare Value 11 7 0 Compare Value 11 15 0 is the word that is compared 16 with the 11 input sample captured at the input interface Compare 11 MSBs Ox6D 7 0 Compare Value 11 15 8 S
22. 1 Q I Q Q z 0 1 Q I 3 x fs 4 1 1 0 21 0 1 0 1 6 8 1 1 1 0 r I 1 1 Q Q r E 0 1 4I r Q I r Q D r Q I Note that r m As shown in Table 22 the mixing functions of most of the modes result in cross coupling samples between the I and Q channels The I and channels only operate independently in fs 2 mode This means that real modulation using both the I and DAC outputs can only be done in fs 2 mode All other modulation modes require complex input data and produce complex output signals Table 23 Summary of Data Rates and Bandwidths vs Interpolation Modes Filter Modes Bus Width HB3 HB2 HB1 fsus Mbps foata Mbps Real Signal Bandwidth MHz foac MHz Byte Mode 0 0 0 250 62 5 31 25 62 5 8 Bits 0 0 1 250 62 5 25 125 0 1 0 250 62 5 15 625 125 0 1 1 250 62 5 25 250 1 1 0 250 62 5 15 625 250 1 1 1 250 62 5 25 500 Word Mode 0 0 0 250 125 62 5 125 16 Bits 0 0 1 250 125 50 250 0 1 0 250 125 31 25 250 0 1 1 250 125 50 500 1 1 0 250 125 31 25 500 1 1 1 250 125 50 1000 Dual Word Mode 0 0 0 250 250 125 250 32 Bits 0 0 1 250 250 100 500 0 1 0 250 250 62 5 500 0 1 1 250 250 100 1000 1 1 0 250 250 62 5 1000 1 1 1 125 125 50 1000 Rev 0 Page 38 of 56 QUADRATURE PHASE CORRECTION The purpose of the quadrature phase correction block is to enable compensation of
23. 250 300 foarta MHz Figure 78 CVDD18 Power Dissipation vs foara with PLL Disabled 09016 046 Rev 0 Page 45 of 56 300 250 200 150 POWER mW 100 0 200 400 600 800 1000 1200 fpAc MHz 09016 047 Figure 79 DVDD18 Power Dissipation vs Due to Inverse Sinc Filter 300 poate 50 100 150 200 250 300 foata MHz Figure 80 DVDD18 Power Dissipation vs foara Due to Fine NCO e e POWER mW e 09016 048 TEMPERATURE SENSOR The AD9125 has a diode based temperature sensor for measuring the temperature of the die The temperature reading is accessed through Register 0x49 and Register Ox4A The temperature of the die can be calculated by Die Temp 15 0 47 925 88 DIE where is the die temperature in C The temperature accuracy is 5 typical Estimates of the ambient temperature can be made if the power dissipation of the device is known For example if the device power dissipation is 800 mW and the measured die temperature is 50 then the ambient temperature can be calculated as Ta Tp Pp x Tja 50 0 8 x 20 7 33 4 where Ta is the ambient temperature in C Tox is the die temperature in C Pp is the power dissipation is the thermal resistance from junction to ambient of the AD9125 as shown in Table 7 To use the temperature sensor it must be enabled by set
24. 5 Bypass NCO 1 bypasses NCO 1 3 NCO gain 0 default No gain scaling is applied to the NCO input 0 to the internal digital modulator 1 gain scaling of 0 5 is applied to the NCO input to the internal digital modulator This can eliminate saturation of the modulator output for some combinations of data inputs and NCO signals 2 Bypass phase compen 1 bypasses phase compensation and dc offset 1 sation and dc offset Rev 0 Page 24 of 56 Register Name Address Hex Bits Name Description Default Select sideband 0 the modulator outputs high side image 1 the modulator outputs low side image The image is spectrally inverted compared with the input data 0 Send data to Q data 1 ignores Q data from the interface and disables the clocks to the Q datapath Sends data to both the and Q DACs HB1 Control Ox1C 2 1 HB1 1 0 00 input signal is not modulated filter pass band is from 0 4 to 0 4 of fini 01 input signal is not modulated filter pass band is from 0 1 to 0 9 of fin 10 input signal is modulated by f n filter pass band is from 0 6 to 1 4 of fii 11 input signal is modulated by fin filter pass band is from 1 1 to 1 9 of fii Bypass HB1 1 bypasses first stage interpolation filter HB2 Control Ox1D 6 1 HB2 5 0 Modulation mode for Side Half Band Filter 2 000000 input signal is not modulated fil
25. FIFO To maintain synchronization the skew between the REFCLK signals of the devices must be less than tsxew There are also setup and hold times to be observed among the DCI the data of each device and the REFCLK signal When resetting the FIFO the FRAME signal must be held high for the time interval required to write two complete input data words A timing diagram of the input signals is shown in Figure 82 This example shows a REFCLK frequency equal to the data rate Although this is the most common situation it is not strictly required for proper synchronization Any REFCLK frequency that satisfies the following equation is acceptable 1 2 and fsywc 1 lt foara where N 0 1 2 or 3 As an example a configuration with 4x interpolation and clock frequencies of fvco 1600 MHz fpaccix 800 MHz fpara 200 MHz and fsync_1 100 MHz is a viable solution Rev 0 Page 47 of 56 tskew REFCLKP 1 REFCLKN 1 REFCLKP 2 REFCLKN 2 tsu_pci tH pci DCI 2 FRAMEQ N Figure 82 Timing Diagram Required for Synchronizing Devices DACCLKP DACCLKN REFCLKP REFCLKN FRAME IOUT1P IOUT1N SAMPLE RATE CLOCK LOW SKEW CLOCK DRIVER MATCHED LENGTH TRACES DCI DACCLKP DACCLKN REFCLKP REFCLKN FRAME IOUT2P IOUT2N LOW SKEW CLOCK DRIVER DCI Figure 83 Typical Circuit Diagram for Synchronizing Devices to a System Clock Re
26. Supply Supplies clock receivers clock distribution and PLL circuitry 2 DACCLKP DAC Clock Input Positive 3 DACCLKN DAC Clock Input Negative 4 CVSS Clock Supply Common 5 FRAME Frame Input 6 NC No Connect 7 TRQ INT Interrupt Request Open Drain Active Low Output Connect external pull up to IOVDD 8 D31 Data Bit 31 9 D30 Data Bit 30 10 NC No Connect 11 IOVDD Supply for Serial Port Pin RESET Pin and IRQ Pin 1 8 V to 3 3 V can be applied to this pin 12 DVDD18 1 8V Digital Supply Supplies power to digital core and digital data ports 13 D29 Data Bit 29 14 D28 Data Bit 28 15 D27 Data Bit 27 16 D26 Data Bit 26 17 D25 Data Bit 25 18 D24 Data Bit 24 19 D23 Data Bit 23 20 D22 Data Bit 22 21 D21 Data Bit 21 22 D20 Data Bit 20 23 D19 Data Bit 19 24 D18 Data Bit 18 25 D17 Data Bit 17 26 D16 Data Bit 16 27 DCI Data Clock Input Rev 0 Page 8 of 56 Mnemonic Description 28 NC No Connect 29 DVDD18 1 8 V Digital Supply 30 DVSS Digital Common 31 D15 Data Bit 15 32 D14 Data Bit 14 33 D13 Data Bit 13 34 D12 Data Bit 12 35 D11 Data Bit 11 36 D10 Data Bit 10 37 D9 Data Bit 9 38 D8 Data Bit 8 39 D7 Data Bit 7 40 D6 Data Bit 6 41 D5 Data Bit 5 42 D4 Data Bit 4 43 DVDD18 1 8 V Digital Supply 44 DVSS Digital Supply Common 45 D3 Data Bit 3 46 D2 Data Bit 2 47 D1 Data Bit 1 48 DO Data Bit 0 49 DVDD18 1 8 V Digital Supply
27. control voltage Register OxOE Bits 3 0 value Table 25 VCO Control Voltage Range Indications VCO Control Voltage Indication 1111 Move to a higher VCO band 1110 1101 VCO is operating in the higher end of 1100 the frequency band 1011 1010 1001 VCO is operating within an optimal 1000 region of the frequency band 0111 0110 0101 VCO is operating in the lower end of 0100 the frequency band 0011 0010 0001 Move to a lower VCO band 0000 Rev 0 Page 41 of 56 ANALOG OUTPUTS TRANSMIT DAC OPERATION Figure 66 shows a simplified block diagram of the transmit path DACs The DAC core consists of a current source array a switch core a digital control logic and a full scale output current control The DAC full scale output current Iourrs is nominally 20 mA The output currents from the IOUTIP IOUT2P and IOUTIN IOUT2N pins are complementary meaning that the sum of the two currents always equals the full scale current of the DAC The digital input code to the DAC determines the effective differential current delivered to the load DAC FS ADJUST REGISTER 0x40 CURRENT SCALING mu 1 IOUT2N IOUT2P Q DAC FS ADJUST REGISTER 0x44 IOUT1P IOUT1N 09016 037 Figure 66 Simplified Block Diagram of DAC Core The DAC has a 1 2 V band gap reference with an output impedance of 5 The reference output voltage appears on the REFIO pin When using the internal referen
28. frercux 4 e N2 fvcolfoaccix 4 The following NCO settings can be derived from the device configuration e fuco 2 X foara e four 140 122 88 17 12 MHz e FTW 17 12 2 x 122 88 x 2 0x11D55555 Start Up Sequence The following procedure sets the power clock and register write sequencing for reliable device start up 1 Power up the device no specific power supply sequence is required 2 Apply stable REFCLK input signal 3 Apply stable DCI input signal 4 Issue a hardware reset optional As a result the device configuration register write sequence is 0x00 gt 0x20 Issue software reset 0x00 0x00 0x0C gt OxD1 Start PLL OxOD OxD9 0x0A gt 0xC0 0x0A gt 0x80 Verify PLL is locked Read OxOE expect Bit 7 1 Bit 6 0 Read 0x06 expect 0x5C 0x10 gt 0x48 Choose data rate mode 0x17 gt 0x04 Issue software FIFO reset 0x18 gt 0x02 0x18 gt 0x00 Verify FIFO reset Read 0x18 expect 0x05 Read 0x19 expect 0x07 Ox1B gt 0x84 Configure interpolation filters Ox1C gt 0x04 0 1 gt 0x24 0 1 gt 0x01 Configure NCO 0x30 gt 0x55 0x31 gt 0x55 0x32 gt 0xD5 0x33 gt 0 11 0x36 gt 0x01 Update frequency tuning word 0x36 gt 0x00 Rev 0 Page 54 of 56 OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW EXPOSED PAD BOTTOM VIEW 12
29. is enabled Register 0x70 through Register 0x73 accumulate errors as previously described but reset to all Os after eight consecutive error free sample comparisons are made The sample error compare pass and compare fail flags can be configured to trigger an IRQ when active if desired This is done by enabling the appropriate bits in the Event Flag 2 register Register 0x07 Table 28 shows a progression of the input sample comparison results and the corresponding states of the error flags SED EXAMPLE Normal Operation The following example illustrates the SED configuration for continuously monitoring the input data and assertion of an IRQ when a single error is detected 1 Write to the following registers to enable the SED and load the comparison values Register 0x67 0x80 Register 0x68 I0 7 0 Register 0x69 I0 15 8 Register 0x6A QO 7 0 Register Ox6B Q0 15 8 Register 0x6C I1 7 0 Register 0x6D I1 15 8 Register Ox6E Q1 7 0 Register Ox6F Q1 15 8 Comparison values can be chosen arbitrarily however choosing values that require frequent bit toggling provides the most robust test 2 Enable the SED error detect flag to assert the IRQ pin by writing 0x04 to Register 0x05 3 Begin transmitting the input data pattern If IRQ is asserted read Register 0x67 and Register 0x70 through Register 0x73 to verify that a SED error was detected and to deter mine which input bits were in error The bits in Register 0x70 through
30. resynchronizes when a phase change between the REFCLK signal and the state of the clock generation state machine exceeds a threshold To mitigate the effects of jitter and prevent erroneous resynchronizations the relative phase can be averaged The amount of averaging is set by the sync averaging bits Register 0x10 Bits 2 0 and can be set from 1 to 128 The higher the number of averages the more slowly the device recognizes and resynchronizes to a legitimate phase correction Generally the averaging should be made as large as possible while still meeting the allotted resynchronization time interval The value of the sync phase request bits Register Ox11 Bits 5 0 is the state to which the clock generation state machine resets upon initialization By varying this value the timing of the internal clocks with respect to the REFCLK signal can be adjusted Every increment in the value of the sync phase request bits Register Ox11 Bits 5 0 advances the internal clocks by one DACCLK period This offset can be used for two purposes to skew the outputs of two synchronized DAC outputs in increments of the DACCLK period and to change the relative timing between the DCI input and REFCLK This may allow for more optimal placement of the DCI sampling point in data rate synchronization mode Table 27 Synchronization Setup and Hold Times Parameter Min Max Unit tskew tpacc k 2 2 tsv_sync 100 ps Tu 330 ps
31. section for more details PREMODULATION The half band interpolation filters have selectable pass bands that allow the center frequencies to be moved in increments of of their input data rate The premodulation block provides a digital upconversion of the incoming waveform by of the incoming data rate fpara This can be used to frequency shift baseband input data to the center of the interpolation filters pass band INTERPOLATION FILTERS The transmit path contains three interpolation filters Each of the three interpolation filters provides a 2x increase in output data rate The half band HB filters can be individually bypassed or cascaded to provide 1x 2x 4x or 8x interpolation ratios Each of the half band filter stages offers a different combination of bandwidths and operating modes The bandwidth of the three half band filters with respect to the data rate at the filter input is as follows e Bandwidth of HB1 0 8 x fm e Bandwidth of HB2 0 5 x fno e Bandwidth of HB3 0 4 x fins The usable bandwidth is defined as the frequency over which the filters have a pass band ripple of less than 0 001 dB and an image rejection of greater than 85 dB As is discussed in the Half Band Filter 1 HB1 section the image rejection usually sets the usable bandwidth of the filter not the pass band flatness The half band filters operate in several modes providing programmable pass band center frequencies as well as signal mo
32. sss 50 Additional Synchronization Features sss 51 Interrupt Request Operation sss 52 Interrupt Service Routine sss 52 Interface Timing Validation sees 53 SED Operation cae e tate 53 SED Example ita rea E EAS 53 Example Start Up Routine eerte 54 Outlin Dimensions tees 55 Ordering Gilde nti ebd etii tene ebrei etait 55 Rev 0 Page 2 of 56 FUNCTIONAL BLOCK DIAGRAM DATA RECEIVER 1 OFFSET Q OFFSET HB1 CLK HB2 CLK HB3 CLK PHASE CORRECTION INVSINC CLK INTERNAL CLOCK TIMING AND CONTROL LOGIC PROGRAMMING REGISTERS SERIAL INPUT OUTPUT PORT POWER ON RESET MULTICHIP 1 PLL CONTROL SYNCHRONIZATION E ol PLL LOCK Figure 2 AD9125 Functional Block Diagram Rev 0 Page 3 of 56 DACCLK 1 2G DAC 1 16 BIT 1 2G DAC 1 16 BIT 7 DAC CLK SEL MULTIPLIER 2x TO 16x IOUT1P a gt IOUT1N DACCLKP DACCLKN REFCLKP REFCLKN 09016 002 SPECIFICATIONS DC SPECIFICATIONS Tw to Tmax AVDD33 3 3 V DVDD18 1 8 V CVDD18 1 8 V Iourrs 20 mA maximum sample rate unless otherwise noted Table 1 Parameter Min Typ Max Unit RESOLUTION 16 Bits ACCURACY Differential Nonlinearity DNL 21 LSB Integral Nonlineari
33. supply is a function of which digital blocks are enabled and the frequency at which the device is operating The CVDD18 supply powers the clock receiver and clock distribution circuitry The power consumption from this supply varies directly with the operating frequency of the device CVDD18 also powers the PLL The power dissipation of the PLL is typically 80 mA when enabled Figure 76 through Figure 80 detail the power dissipation of the AD9125 under a variety of operating conditions of the graphs are taken with data being supplied to both the I and Q channels The power consumption of the device does not vary significantly with changes in the coarse modulation mode selected or analog output frequency Graphs of the total power dissipation are shown along with the power dissipation of the DVDD18 and CVDD18 supplies Maximum power dissipation can be estimated to be 2096 higher than the typical power dissipation POWER mW o 8 e e 400 a 100 150 200 250 300 foarta MHz Figure 76 Total Power Dissipation vs foara Without PLL Fine NCO and Inverse Sinc 09016 044 1400 1200 1000 POWER mW 0 50 100 150 200 250 300 foarta MHz Figure 77 DVDD18 Power Dissipation vs foara Without Fine NCO and Inverse Sinc 09016 045 250 200 a POWER mW a 100 150 200
34. synchronized DACs 000000 0 DACCLK cycles 000001 1 DACCLK cycle 111111 263 DACCLK cycles Sync Status 1 0x12 7 Sync lost 1 indicates that synchronization had been attained R but was subsequently lost 6 Sync locked 1 indicates that synchronization has been attained R Sync Status 2 0x13 7 0 Sync phase readback 7 0 Indicates the averaged sync phase offset 6 2 format If R the value differs from the requested sync phase value this indicates sync timing errors 00000000 0 0 00000001 0 25 11111110 63 50 11111111 63 75 FIFO Control 0x17 2 0 FIFO phase offset 2 0 FIFO write pointer phase offset following FIFO reset 4 This is the difference between the read pointer and the write pointer values upon FIFO reset The optimal value is nominally 4 000 0 001 1 11127 FIFO Status 1 0x18 7 FIFO Warning 1 FIFO read and write pointers within 1 0 6 FIFO Warning 2 FIFO read and write pointers within 2 0 2 FIFO soft align FIFO read and write pointers are aligned after a serial acknowledge port initiated FIFO reset 1 FIFO soft align request Request FIFO read and write pointers alignment via the 0 serial port 0 FIFO reset aligned FIFO read and write pointers aligned after a hardware 0 reset FIFO Status 2 0x19 7 0 FIFO level 7 0 Thermometer encoded measure of the FIFO level 0 Datapath Control Ox1B 7 Bypass premod 1 bypasses fs 2 premodulator 1 6 Bypass sinc 1 bypasses inverse sinc filter 1
35. 00 20 14 mA Ox3FF 31 66 mA I DAC Control 0x41 7 DAC sleep 1 puts the I channel DAC into sleep mode fast wake 0 up mode 1 0 I DAC FS adjust 9 8 See Register 0x40 1 Aux DAC I Data 0x42 7 0 I aux DAC 7 0 aux DAC 9 0 sets the magnitude of the auxiliary DAC 0 current The range is 0 mA to 2 mA and the step size is 2 0x000 0 000 mA 0x001 0 002 mA Ox3FF 2 046 mA Rev 0 Page 26 of 56 Register Address Name Hex Bits Name Description Default Aux DAC Control 0x43 7 aux DAC sign 0 the auxiliary DAC sign is positive and the currentis 0 directed to the IOUT1P pin Pin 67 1 the auxiliary DAC I sign is negative and the current is directed to the IOUT1N pin Pin 66 6 aux DAC current 0 the auxiliary DAC sources current 0 direction 1 the auxiliary DAC sinks current 5 aux DAC sleep channel auxiliary DAC sleep 0 1 0 Aux DAC 9 8 See Register 0x42 0 Q DAC FS Adjust 0x44 7 0 Q DAC FS adjust 7 0 Q DAC FS adjust 9 0 sets the full scale current of the F9 DAC The full scale current can be adjusted from 8 64 mA to 31 6 mA in step sizes of approximately 22 5 pA 0x000 8 64 mA 0x200 20 14 mA Ox3FF 31 66 mA Q DAC Control 0x45 7 Q DAC sleep 1 2 puts the Q channel DAC into sleep mode fast wake 0 up mode 1 0 Q DAC FS adjust 9 8 See Register 0x44 1 Aux DAC Q Data 0x46 7 0 Q aux
36. 1 8x fparA 125MSPS 162 163 164 165 0 50 100 150 200 250 300 350 400 450 500 four MHz Figure 25 Eight Tone NSD vs four over Interpolation Rate and foarta Digital Scale 0 dBFS fsc 20 mA PLL Off 161 5 0dBFS 1625 18dBFS 163 0 163 5 164 0 164 5 165 0 165 5 166 0 166 5 0 50 100 150 200 250 four MHz 09016 122 09016 123 Figure 26 Eight Tone NSD vs four over Digital Scale foara 200 MSPS 09016 121 Rev 0 Page 13 of 56 NSD dBm Hz 4x Interpolation fsc 20 mA PLL Off 8x fparA 125MSPS 0 100 200 300 400 500 600 four MHz Figure 27 Eight Tone NSD vs four over Interpolation Rate and foarta Digital Scale 0 dBFS fsc 20 mA PLL On 09016 124 ACLR dBc 0 50 100 150 200 250 four MHz 09016 125 Figure 28 One Carrier W CDMA ACLR vs four over Digital Cutback ACLR dBc ACLR dBc Adjacent Channel PLL Off 0 50 100 150 200 250 four MHz Figure 29 One Carrier W CDMA ACLR vs four over foac Alternate Channel PLL Off four MHz Figure 30 One Carrier W CDMA ACLR vs four over foac Second Alternate Channel PLL Off ACLR dBc 2x PLL OFF 4x PLL OFF 2x PLL ON 4x PLL O
37. 1 0 PLL loop divider These bits determine the ratio of the 01 DACCLK to the REFCLK frequencies 00 foaccuk frercik 2 01 foaccuk frercik 4 10 foaccuk frercik 8 11 foaccuk frercik 16 PLL Status 1 OxOE 7 PLL lock The PLL generated clock is tracking the REFCLK input R signal 3 0 VCO control VCO control voltage readback see Table 25 R voltage 3 0 PLL Status 2 OxOF 5 0 VCO band Indicates the VCO band currently selected R readback 5 0 Sync Control 1 0x10 7 Sync enable 1 enables the synchronization logic 0 6 Data FIFO rate toggle 0 operates the synchronization at the FIFO reset rate 1 1 operates the synchronization at the data rate 3 Rising edge sync 0 initiated on the falling edge of the sync input 1 1 sync is initiated on the rising edge of the sync input 2 0 Sync averaging 2 0 Sets the number of input samples that are averaged for 0 determining the sync phase 000 1 001 2 010 4 011 8 100 16 101 32 Rev 0 23 of 56 Register Address Name Hex Bits Name Description Default 1102 64 1112 128 Sync Control 2 0x11 5 0 Sync phase request 5 0 This sets the requested clock phase offset after sync 0 The offset unit is in DACCLK cycles This enables repositioning of the DAC output with respect to the sync input The offset can also be used to skew the DAC outputs between the
38. 100 150 200 250 300 four MHz Figure 19 IMD vs four over Digital Scale 2x Interpolation foata 250 MSPS fsc 20 MA 0 50 100 150 200 250 300 four MHz Figure 20 IMD vs four over fsa 2x Interpolation foarta 250 MSPS Digital Scale 0 dBFS 40 45 0 50 100 150 200 250 300 four MHz Figure 21 IMD vs four PLL On vs PLL Off 09016 116 09016 117 09016 118 154 156 158 160 162 NSD dBm Hz 164 166 168 2x fparA 250MSPS 45 fparA 125MSPS 8x fparA 125MSPS 0 100 200 300 400 500 600 four MHz NSD dBm Hz 09016 119 Figure 22 One Tone NSD vs four over Interpolation Rate and foara Digital 154 156 158 160 162 NSD dBm Hz 164 166 168 Figure 23 One Tone NSD vs four over Digital Scale foara 200 MSPS NSD dBm Hz Scale 0 dBFS fsc 20 mA PLL Off 0dBFS 6dBFS 12dBFS 18dBFS 0 50 100 150 200 250 four MHz 4x Interpolation fsc 20 mA PLL Off 8x fpata 125MSPS four MHz Figure 24 One Tone NSD vs four over Interpolation Rate and fpara Digital Scale 0 dBFS fsc 20 mA PLL On NSD dBm Hz 09016 120 160 2x foata 250MSPS 4x 125MSPS 16
39. 25 1000 Dual Word Mode 1x 250 250 250 2x HB1 250 250 500 2x HB2 250 250 500 4x 250 250 1000 8x 125 125 1000 Rev 0 Page 6 of 56 ABSOLUTE MAXIMUM RATINGS Table 6 With Parameter RespectTo Rating AVDD33 AVSS EPAD 0 3 V to 3 6 V CVSS DVSS IOVDD AVSS EPAD 0 3 V to 3 6 V CVSS DVSS DVDD18 CVDD18 AVSS EPAD 0 3 V to 2 1 V CVSS DVSS AVSS EPAD CVSS 0 3 V to 0 3 V DVSS EPAD AVSS CVSS 0 3 V to 0 3 V DVSS CVSS AVSS EPAD 0 3 V to 0 3 V DVSS DVSS AVSS EPAD 0 3 V to 0 3 V CVSS FSADJ REFIO AVSS 0 3 V to AVDD33 0 3 V IOUT1P IOUT1N IOUT2P IOUT2N D 31 0 FRAME DCI EPAD DVSS 0 3V to DVDD18 0 3 V DACCLKP DACCLKN DVSS 0 3V to CVDD18 0 3 V REFCLKP REFCLKN RESET IRQ CS SCLK EPAD DVSS 0 3 V to IOVDD 0 3 V SDIO SDO Junction Temperature 125 C Storage Temperature 65 C to 150 C Range THERMAL RESISTANCE The exposed paddle EPAD must be soldered to the ground plane for the 72 lead LFCSP The EPAD performs as an electrical and thermal connection to the board Typical and values are specified for a 4 layer board in still air Airflow increases heat dissipation effectively reducing Oya and Table 7 Thermal Resistance Package Unit Conditions 72 Lead LFCSP 20 7 10 9 1 1 C W EPAD soldered ESD CAUTION ESD electrostatic dis
40. A and 30 mA AUXILIARY DAC OPERATION The AD9125 has two auxiliary DACs one is associated with the I path and the other is associated with the Q path These auxiliary DACs can be used to compensate for dc offsets in the transmitted signal Each auxiliary DAC has a single ended current that can sink or source current into either the P or N output of the associated transmit DAC The auxiliary DAC structure is shown in Figure 72 09016 169 AVDD3 AUX DAC AUX DAC CURRENT DIRECTION AUX DAC SIGN O IOUTP 09016 040 O IOUTN Figure 72 Auxiliary DAC Structure The control registers for controlling the I and auxiliary DACs are in Register 0x42 Register 0x43 Register 0x46 and Register 0x47 Rev 0 Page 43 of 56 Interfacing to Modulators The AD9125 interfaces to the ADL537x family of modulators with a minimal number of components An example of the recommended interface circuitry is shown in Figure 73 The baseband inputs of the ADL537x family require a dc bias of 500 mV The nominal midscale output current on each output of the DAC is 10 mA the full scale current Therefore a single 50 resistor to ground from each DAC output results in the desired 500 mV dc common mode bias for the inputs to the ADL537x The signal level can be reduced through the addition of the load resistor in parallel with the modulator inputs The peak to peak voltage swing of the transmitted signal is b xR xR
41. ANALOG DEVICES Dual 16 Bit 1000 MSPS TxDAC Digital to Analog Converter FEATURES Flexible CMOS interface allows dual word word or byte load Single carrier W CDMA ACLR 80 dBc at 122 88 MHz IF Analog output adjustable 8 7 mA to 31 7 250 to 50 Q Novel 2x 4x 8x interpolator complex modulator allows carrier placement anywhere in the DAC bandwidth Gain and phase adjustment for sideband suppression Multichip synchronization interface High performance low noise PLL clock multiplier Digital inverse sinc filter Low power 900 mW at 500 MSPS full operating conditions 72 lead exposed paddle LFCSP APPLICATIONS Wireless infrastructure W CDMA CDMA2000 TD SCDMA WiMAX GSM LTE Digital high or low IF synthesis Transmit diversity Wideband communications LMDS MMDS point to point Cable modem termination systems GENERAL DESCRIPTION The AD9125 is a dual 16 bit high dynamic range TxDAC digital to analog converter DAC that provides a sample rate of 1000 MSPS permitting a multicarrier generation up to the Nyquist frequency It includes features optimized for direct conversion transmit applications including complex digital modulation and gain and offset compensation The DAC outputs are optimized to interface seamlessly with analog quadrature modulators such as the ADL537x F MOD series from Analog Devices Inc A 4 wire serial port interface allows programming readback of many inter nal parameters Fu
42. CS dBc HARMONICS dBc 10mA SECOND HARMONIC 20mA SECOND HARMONIC 30mA SECOND HARMONIC 10mA THIRD HARMONIC 20mA THIRD HARMONIC 30mA THIRD HARMONIC 0 50 100 150 200 250 300 four MHz 09016 103 09016 106 four MHz Figure 6 Harmonics vs four over foara 8x Interpolation Figure 9 Harmonics vs four over fsc 2x Interpolation Digital Scale 0 dBFS fsc 20 mA foata 250 MSPS Digital Scale 0 dBFS Rev 0 Page 10 of 56 HIGHEST DIGITAL SPUR dBc HIGHEST DIGITAL SPUR dBc HIGHEST DIGITAL SPUR dBc fparA 125MSPS fparA 250MSPS 0 50 100 150 200 250 300 Figure 10 Highest Digital Spur vs four over foata 2x Interpolation Digital Scale 0 dBFS fsc 20 mA fpata 125MSPS fparA 250MSPS 0 100 200 300 400 500 600 four MHz Figure 11 Highest Digital Spur vs four over foarta 4x Interpolation Digital Scale 0 dBFS fsc 20 mA Va zr 0 50 100 150 200 250 300 350 400 four MHz Figure 12 Highest Digital Spur vs four over foata 8x Interpolation Digital Scale 0 dBFS fsc 20 mA 09016 107 09016 108 09016 109 Rev 0 Page 11 of 56 2x INTERPOLATION SINGLE TONE SPECTRUM fparA 250MSPS four 101MHz START 1 0MHz VBW 10kHz RES BW 10kHz STOP 500 0MHz SW
43. DAC 7 0 Q aux DAC 9 0 sets the magnitude of the aux DAC current O The range is 0 mA to 2 mA and the step size is 2 uA 0x000 0 000 mA 0x001 0 002 mA Ox3FF 2 046 mA Q Aux DAC Control 0x47 7 Q aux DAC sign 0 the auxiliary DAC Q sign is positive and the current 0 is directed to the IOUT2P pin Pin 58 1 the auxiliary DAC Q sign is negative and the current is directed to the IOUT2N pin Pin 59 6 Q aux DAC current 0 the auxiliary DAC sources current 0 direction 1 the auxiliary DAC sinks current 5 Q aux DAC sleep Q channel auxiliary DAC sleep 1 0 Q aux DAC 9 8 See Register 0x46 0 Die Temp Range 0x48 6 4 FS current 2 0 Auxiliary ADC full scale current 0 Control 000 lowest current 111 highest current 3 1 Reference current 2 0 Auxiliary ADC reference current 1 000 lowest current 111 highest current 0 Capacitor value Auxiliary ADC internal capacitor value 0 0 5 pF 1 10 pF Die Temp LSB 0x49 7 0 Die temp 7 0 Die Temp 15 0 indicates the approximate die R temperature OxADCC 39 9 C 0xC422 25 1 C OxD8A8 84 8 C see the Temperature Sensor section for details Die Temp MSB Ox4A 7 0 Die temp 15 8 See Register 0x49 R Rev 0 Page 27 of 56 Register Address Name Hex Bits Name Description Default SED Control 0x67 7 SED compare enable 1 enables the SED circuitry None of the flags in this
44. E and DCI signals along with the data can be created in the FPGA A circuit diagram of a typical configuration is shown in Figure 81 MATCHED LENGTH TRACES REFCLKP REFCLKN IOUT1P IOUT1N SYSTEM CLOCK LOW SKEW CLOCK DRIVER REFCLKP REFCLKN IOUT2P IOUT2N 09016 049 Figure 81 Typical Circuit Diagram for Synchronizing Devices The Procedure for Synchronization when Using the PLL section outlines the steps required to synchronize multiple devices The procedure assumes that the REFCLK signal is applied to all devices and that the PLL of each device is phase locked to this signal This procedure must be carried out on each individual device Procedure for Synchronization when Using the PLL To synchronize all devices 1 Configure the device for data rate mode and periodic synchronization by writing 0xCO to the Sync Control 1 register Register 0x10 Additional synchronization options are available 2 Read the Sync Status 1 register Register 0x12 and verify that the sync locked bit Bit 6 is set high indicating that the device achieved back end synchronization and that the sync lost bit Bit 7 is low These levels indicate that the clocks are running with a constant known phase relative to the sync signal 3 Reset the FIFO by strobing the FRAME signal high for the time required to write two complete input data words Resetting the FIFO ensures that the correct data is being read from the
45. EEP 6 017s 601 PTS Figure 13 2x Interpolation Single Tone Spectrum 4x INTERPOLATION SINGLE TONE SPECTRUM fparA 125MSPS four 101MHz START 1 0MHz VBW 10kHz RES BW 10kHz STOP 500 0MHz SWEEP 6 017s 601 PTS Figure 14 4x Interpolation Single Tone Spectrum 8x INTERPOLATION fparA 125MSPS four 131MHz SINGLE TONE SPECTRUM START 1 0MHz VBW 10kHz RES BW 10kHz STOP 1 0GHz SWEEP 12 05s 601 PTS Figure 15 8x Interpolation Single Tone Spectrum 09016 110 09016 111 09016 112 IMD dBc IMD dBc IMD dBc fpata 125MSPS fpata 250MSPS 50 100 150 200 250 four MHz Figure 16 IMD vs four over foara 2x Interpolation Digital Scale 0 dBFS fsc 20 mA fpata 125MSPS fpata 250MSPS 300 four MHz Figure 17 IMD vs four over foara 4x Interpolation Digital Scale 0 dBFS fsc 20 mA fpata 125MSPS 0 100 200 300 400 500 four MHz Figure 18 IMD vs four over foara 8x Interpolation Digital Scale 0 dBFS fsc 20 mA 600 IMD dBc 09016 113 IMD dBc 09016 114 IMD dBc 09016 115 Rev 0 Page 12 of 56 0dBFS 6dBFS 12dBFS 18dBFS 60 65 70 75 80 85 90 0 50
46. I DAC offset 15 0 and DAC offset 15 0 values in Register 0x3C through Register 0x3F These values are added directly to the datapath values Care should be taken not to overrange the transmitted values Figure 61 shows how the DAC offset current varies as a function of theI DAC offset 15 0 and Q DAC offset 15 0 values With the digital inputs fixed at midscale 0x0000 twos complement data format Figure 61 shows the nominal and Iovr currents as the DAC offset value is swept from 0 to 65 535 Because Iours and are complementary current outputs the sum of and Tours is always 20 mA 20 0 15 5 x 10 10 5 2 5 15 0 20 0 0000 0 4000 0 8000 0xC000 OxFFFF 3 DAC OFFSET VALUE 8 Figure 61 DAC Output Currents vs DAC Offset Value INVERSE SINC FILTER The inverse sinc sinc filter is a nine tap FIR filter The composite response of the sinc and the sin x x response of the DAC is shown in Figure 62 The composite response has less than 0 05 dB pass band ripple up to a frequency of 0 4 x fpacc x To provide the necessary peaking at the upper end of the pass band the inverse sinc filters have an intrinsic insertion loss of about 3 2 dB Figure 62 shows the composite frequency response 3 0 MAGNITUDE dB b 0 0 1 0 2 0 3 0 4 0 5 four fpac 9016 032 Figure 62 Sample Composite Responses of the Sinc Filter with Sin x
47. ION INTERPOLATION Figure 57 Digital Quadrature Modulator Block Diagram Q DATA 09016 027 The quadrature modulator is used to mix the carrier signal generated by the NCO with the I and Q signal The NCO produces a quadrature carrier signal to translate the input signal to a new center frequency A complex carrier signal is a pair of sinusoidal waveforms of the same frequency offset 90 from each other The frequency of the complex carrier signal is set via FTW 31 0 in Register 0x30 through Register 0x33 The NCO operating frequency fuco is at either HB1 bypassed or twice fpara HB1 enabled The frequency of the complex carrier signal can be set from dc up to fuco The frequency tuning word FTW is calculated as FTW fcarr x2 NCO The generated quadrature carrier signal is mixed with the I and Q data The quadrature products are then summed into the I and Q datapaths as shown in Figure 57 Updating the Frequency Tuning Word The frequency tuning word registers do not update immediately upon writing as other configuration registers After loading the FTW registers with the desired values Bit 0 of Register 0x36 must transition from 0 to 1 for the new FTW to take effect DATAPATH CONFIGURATION Configuring the AD9125 datapath starts with the application requirements of the input data rate the interpolation ratio the output signal bandwidth and the output signal center frequency Given these four para
48. MAX 0 80 MAX as alr 0 65 TYP t 0 05 MAX FOR PROPER CONNECTION OF Y 0 02 NOM THE EXPOSED PAD REFER TO 0 85 T 0 80 HHHHHHHI THE PIN CONFIGURATION AND SEATING J 0 30 0 20 cee ue FUNCTION DESCRIPTIONS PLANE SECTION OF THIS DATA SHEET BR 052809 A COMPLIANT TO STANDARDS MO 220 VNND 4 Figure 89 72 Lead Lead Frame Chip Scale Package LFCSP VO 10mm x 10 mm Body Very Thin Quad CP 72 7 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9125BCPZ 40 to 85 C 72 lead LFCSP_VQ CP 72 7 AD9125BCPZRL 40 C to 85 C 72 lead LFCSP_VQ CP 72 7 AD9125 M5372 EBZ Evaluation Board Connected to ADL5372 Modulator AD9125 M5375 EBZ Evaluation Board Connected to ADL5375 Modulator 17 RoHS Compliant Part Rev 0 Page 55 of 56 NOTES 2010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D09016 0 6 10 0 DEVICES www analo g com Rev 0 Page 56 of 56
49. N four MHz 09016 128 Figure 31 One Carrier W CDMA ACLR vs four over Interpolation Rate Adjacent Channel PLL On vs PLL Off ACLR dBc 09016 126 2x PLL OFF 4x PLL OFF 2x PLL ON 4x PLL ON 200 300 400 500 four MHz 09016 129 Figure 32 One Carrier W CDMA ACLR vs four over Interpolation Rate Alternate Channel PLL On vs PLL Off ACLR dBc 09016 127 75 80 85 2x PLL OFF 4x PLL OFF 2x PLL ON 4x PLL ON 0 100 200 300 400 500 four MHz 09016 130 Figure 33 One Carrier W CDMA ACLR vs four over Interpolation Rate Second Alternate Channel PLL On vs PLL Off Rev 0 Page 14 of 56 START 133 06MHz VBW 30kHz STOP 166 94MHz RES BW 30kHz SWEEP 143 6ms 601 PTS RMS RESULTS FREQ LOWER UPPER OFFSET REFBW dBc dBm dBc dBm CARRIER POWER 5 00MHz 3 840MHz 75 96 85 96 77 13 87 13 10 00dBm 10 00MHz 3 840MHz 85 33 95 33 85 24 95 25 3 840MHz 15 00MHz 2 888MHz 95 81 95 81 85 43 95 43 09016 131 Figure 34 Four Carrier W CDMA ACLR Performance IF 150 MHz Rev 0 Page 15 of 56 TOTAL CARRIER POWER 11 19dBm 15 3600MHz START 125 88MHz RES BW 30kHz VBW 30kHz RRC FILTER OFF FILTER ALPHA 0 22 REF CARRIER PO
50. Register 0x73 are latched therefore the bits indicate any errors that occurred on those bits throughout the test not just the errors that caused the error detected flag to be set Table 28 Progression of Comparison Outcomes and the Resulting SED Register Values Compare Results Pass Fail Register 0x67 Bit 5 Sample Error Detected 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Register 0x67 Bit 1 Compare Fail 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 Register 0x67 Bit 0 Compare Pass 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 Register 0x70 to Register 0x73 Errors Detected x BITS 15 0 Z N2 N2 N2 N N N2 N N Z N2 N N 1Z all Os 2N nonzero Rev 0 Page 53 of 56 EXAMPLE START UP ROUTINE There are certain sequences that should be followed to ensure reliable startup of the AD9125 The example start up routine assumes the following device configuration e fparA 122 88 MSPS e Interpolation 4x using HB1 10 and HB2 010010 e Input data baseband data e four 140 MHz frercix 122 88 MHz e PLL enabled e Fine NCO enabled e Inverse SINC filter enabled e Synchronization enabled The following PLL settings can be derived from the device configuration foara X Interpolation 491 52 MHz e fvco 4 X foaccix 1966 08 MHz 1 GHz lt fico lt 2 1 GHz NI foacctx
51. SOURCE FLAG signal In many cases no specific actions are required 4 Read the event flag to verify that the EVENT FLAG _ SOURCE signal has been cleared 5 Clear the interrupt by writing 1 to the event flag bit 6 Setthe interrupt enable bits of the events to be monitored Note that some of EVENT FLAG SOURCE signals are latched signals These are cleared by writing to the corresponding event flag bit Details of each of the event flags can be found in Table 11 EVENT FLAG 09016 054 Figure 86 Simplified Schematic of IRQ Circuitry Rev 0 Page 52 of 56 INTERFACE TIMING VALIDATION The AD9125 provides on chip sample error detection SED circuitry that simplifies verification of the input data interface The SED compares the input data samples captured at the digital input pins with a set of comparison values which are loaded into registers through the SPI port Differences between these values are detected and stored Options are available for customizing SED test sequencing and error handling SED OPERATION The SED circuitry operates on a data set made up of four 16 bit input words denoted as 10 QO I1 and Q1 To properly align the input samples the first I and data words that is I0 and QO are indicated by asserting the FRAME signal for a minimum of two complete input samples Figure 87 shows the input timing of the interface in dual word mode The FRAME signal can be issued once at the start of the
52. WER 16 89dBm 3 84000MHz BONA 16 92dBm 16 89dBm 17 43dBm 17 64dBm OFFSET FREQ 5 000MHz 10 00MHz 15 00MHz INTEG BW 3 840MHz 3 840MHz 3 840MHz STOP 174 42MHz SWEEP 206 9ms 601 PTS LOWER dBc dBm 65 88 82 76 68 17 85 05 70 42 87 31 UPPER dBc dBm 67 52 84 40 69 91 86 79 71 40 88 28 09016 132 Figure 35 One Carrier W CDMA ACLR Performance IF 150 MHz TERMINOLOGY Integral Nonlinearity INL INL is defined as the maximum deviation of the actual analog output from the ideal output determined by a straight line drawn from zero scale to full scale Differential Nonlinearity DNL DNL is the measure of the variation in analog value normalized to full scale associated with a 1 LSB change in digital input code Offset Error The deviation of the output current from the ideal of zero is called offset error For IOUT1P 0 mA output is expected when the inputs are all 0s For IOUTIN 0 mA output is expected when all inputs are set to 1 Gain Error The difference between the actual and ideal output span The actual span is determined by the difference between the outputs when all inputs are set to 1 vs when all inputs are set to 0 Output Compliance Range The range of allowable voltage at the output of a current output DAC Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown resulting in nonlinear performance
53. able 12 Data Bit Pin Assignments for Data Input Modes Mode Data Bus Pin Assignments Dual Word data D 31 16 data D 15 0 Word and Q data D 29 28 D 25 24 D 21 20 D 17 16 D 15 14 D 11 10 D 7 6 D 3 2 Byte and data D 21 20 D 17 16 D 15 14 D 11 10 In byte and word modes a FRAME signal is required for controlling which DAC receives the data In dual word mode the FRAME signal is not required because each DAC has a dedicated bus DUAL WORD MODE In dual word mode the DCI signal is supplied as a qualifying clock that is time aligned with the input data The rising edge of the DCI signal should be aligned with the changing data of each of the I and input data streams Figure 42 Timing Diagram for Dual Word Mode 09016 142 WORD MODE In word mode the DCI signal is supplied as a qualifying clock that is time aligned with the input data The rising edge of the DCI signal should be aligned with the changing data of the interleaved I and Q input data stream The FRAME signal indicates to which DAC the data is sent When FRAME is high data is sent to the I DAC When FRAME is low data is sent to the Q DAC For 14 and 12 bit resolution devices the two and four LSBs are not significant respectively The complete timing diagram is shown in Figure 43 DCI FRAME Figure 43 Timing Diagram for Word Mode BYTE MODE In byte mode the DCI signal is supplied as a qua
54. alid data is transmitted through the FIFO as long as the FIFO does not overflow or become empty Note that an over flow or empty condition of the FIFO is the same as the write pointer and read pointer being equal When both pointers are equal an attempt is made to read and write a single FIFO register simultaneously This simultaneous register access leads to unreliable data transfer through the FIFO and must be avoided Nominally data is written to the FIFO at the same rate that data is read from the FIFO which keeps the data level in the FIFO constant If data is written to the FIFO faster than data is read the data level in the FIFO increases If data is written to the device slower than data is read the data level in the FIFO decreases For an optimum timing margin the FIFO level should be maintained near half full which is the same as maintaining a difference of four between the write pointer and read pointer values READ POINTER DACCLK 09016 018 Figure 47 Block Diagram of Datapath Through FIFO Rev 0 Page 30 of 56 Initializing the FIFO Data Level To avoid a concurrent read and write to the same FIFO address and to ensure a fixed pipeline delay it is important to initialize the FIFO pointers to known states The FIFO pointers can be initialized in two ways via a write sequence to the serial port or by strobing the FRAME input There are two types of FIFO pointer resets a relative reset and an absolute reset A r
55. are compare pass fail fail Clock Receiver 0x08 DACCLK REFCLK DACCLK REFCLK 1 1 1 1 Ox3F Control duty duty cross cross correction correction correction correction PLL Control 1 0 PLL PLL Manual VCO 5 0 0x40 enable manual enable PLL Control 2 0x0C PLL loop bandwidth 2 0 PLL charge pump current 4 0 OxD1 PLL Control 3 0x0D N2 1 0 PLL cross NO 1 0 N1 1 0 OxD9 control enable PLL Status 1 OxOE PLL lock VCO control voltage 3 0 0x00 PLL Status 2 OxOF VCO band readback 5 0 0x00 Sync Control 1 0x10 Sync Data FIFO Rising Sync Averaging 2 0 0x48 enable rate toggle edge sync Sync Control 2 0x11 Sync phase request 5 0 0x00 Sync Status 1 0x12 Sync lost Sync N A locked Sync Status 2 0x13 Sync phase readback 7 0 6 2 format N A FIFO Control 0x17 FIFO phase offset 2 0 0x04 FIFO Status 1 0x18 FIFO FIFO FIFO soft FIFO soft FIFO reset N A Warning 1 Warning 2 align ack align aligned request FIFO Status 2 0x19 FIFO level 7 0 N A Datapath Control 1 Bypass Bypass Bypass NCO gain Bypass Select Send data OxE4 premod sinc NCO phase sideband to Qdata compen sation and dc offset HB1 Control Ox1C HB1 1 0 Bypass HB1 0x00 HB2 Control 0x1D HB2 5 0 Bypass HB2 0x00 HB3 Control Ox1E HB3 5 0 Bypass HB3 0x00 Chip ID Ox1F Chip ID 7 0 0x08 Rev 0 Page 19 of 56 Addr
56. ase detector or the FIFO WARNING 1 signal from the FIFO controller When an interrupt enable bit is set high the corresponding event flag bit reflects a positively tripped signal that is latched on the rising edge ofthe EVENT FLAG SOURCE signal This signal INTERRUPT ENABLE EVENT FLAG SOURCE WRITE 1 TO EVENT FLAG DEVICE RESET INTERRUPT SOURCE OTHER INTERRUPT SOURCES also asserts the external IRQ When an interrupt enable bit is set low the event flag bit reflects the current status ofthe EVENT FLAG SOURCE signal but the event flag has no effect on the external IRQ The latched version of an event flag the INTERRUPT_SOURCE signal can be cleared in two ways The recommended way is by writing 1 to the corresponding event flag bit however a hardware or software reset can also clear the INTERRUPT_SOURCE INTERRUPT SERVICE ROUTINE The interrupt request management starts by selecting the set of event flags that require host intervention or monitoring Those events that require host action should be enabled so that the host is notified when they occur For events requiring host intervention upon IRQ activation run the following routine to clear an interrupt request 1 Read the status of the event flag bits that are being monitored 2 Set the interrupt enable bit low so that the unlatched EVENT_ FLAG_SOURCE signal can be monitored directly 3 Perform any actions that are required to clear the EVENT_
57. c REFCLKP 2 REFCLKN 2 To ensure that each DAC is updated with the correct data on the same CLK edge two timing relationships must be met on each DAC DCI and D 31 0 must meet the setup and hold times with respect to the rising edge of DACCLK and REFCLK must meet the setup and hold times with respect to the rising edge of DACCLK When resetting the FIFO the FRAME signal must be held high for at least three data periods that is 1 5 cycles of DCI When these conditions are met the outputs of the DACs are updated within tsxew tourpty of each other A timing diagram that illustrates the timing requirements of the input signals is shown in Figure 85 Figure 85 shows the synchronization signal timing with 2x interpolation therefore x fax The REFCLK input is shown to be equal to the FIFO rate More generally the maximum frequency at which the device can be resynchronized in FIFO rate mode can be expressed as fsynca foaral 8 x 2 where N is any nonnegative integer FRAME2 09016 053 Figure 85 FIFO Rate Synchronization Signal Timing Requirements 2x Interpolation Rev 0 Page 50 of 56 ADDITIONAL SYNCHRONIZATION FEATURES The synchronization logic incorporates additional features that provide means for querying the status of the synchronization improving the robustness of the synchronization and enabling a one shot synchronization mode These features are detailed in the Sync Status Bits and Timing Opt
58. ce the REFIO pin should be decoupled to AVSS with a 0 1 capacitor Only use the internal reference for external circuits that draw dc currents of 2 uA or less For dynamic loads or static loads greater than 2 uA buf fer the REFIO pin If desired an external reference between 1 10 V and 1 30 V can be applied to the REFIO pin The internal reference can either be overdriven or powered down by setting Register 0x43 Bit 5 10 external resistor Rser must be connected from the FSADJ pin to AVSS This resistor along with the reference control amplifier sets up the correct internal bias currents for the DAC Because the full scale current is inversely proportional to this resistor the tolerance of Rser is reflected in the full scale output amplitude The full scale current equation where the DAC gain is set indi vidually for the I and Q DACs in Register 0x40 and Register 0x44 respectively follows V 3 I 724 DAC ain 16 8 For nominal values 1 2 V Rser 10 DAC gain 512 the full scale current of the DAC is typically 20 16 mA The DAC full scale current can be adjusted from 8 66 mA to 31 66 mA by setting the DAC gain code as shown in Figure 67 35 30 e 25 20 Ifs mA 15 10 0 200 400 600 800 1000 DAC GAIN CODE Figure 67 DAC Full Scale Current vs DAC Gain Code 09016 036 Transmit DAC Transfer Function The
59. charge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Rev 0 Page 7 of 56 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS co aa gt gt RK CVDDi8 1 DACCLKP 2 DACCLKN 3 CVSS 4 FRAME 5 NC 6 RQ 7 D31 8 D30 9 NC 10 IOVDD 11 PIN 1 INDICATOR AD9125 TOP VIEW Not to Scale D23 19 D22 20 NOTES 1 NC NO CONNECT v7 N t 10 XO CO v C t 10 CN CN CN amp 4R22rE 209v9 02z22 2 a dnannan07a592a58282082880880 aao gt a 2 EXPOSED PAD MUST BE CONNECTED TO AVSS Table 8 Pin Function Descriptions Figure 3 Pin Configuration 09016 003 Pin No Mnemonic Description 1 CVDD18 1 8 V Clock
60. curve in Figure 58 shows that the supported bandwidth in this mode varies from 30 to 50 of fpara The available signal bandwidth for 8x interpolation vs output frequency varies between 50 and 80 of the input data rate as shown in Figure 59 Note that in 8x interpolation mode foac 8 therefore the data shown in Figure 59 repeats eight times from dc to fpac Rev 0 Page 35 of 56 HB1 HB2 AND HB3 BANDWIDTH fpATA 0 4 1 0 50 as 0 75 four fpoata 09016 029 Figure 59 Signal Bandwidth vs Center Frequency of the Output Signal 8x Interpolation DETERMINING INTERPOLATION FILTER MODES Table 21 shows the recommended interpolation filter settings for a variety of filter interpolation factors filter center frequencies and signal modulation The interpolation modes were chosen based on the final center frequency of the signal and by determining the frequency shift of the signal required When these are known and put in terms of the input data rate fora the filter configuration that comes closest to matching should be chosen from Table 21 Table 21 Recommended Interpolation Filter Modes Register Ox1C through Register Ox1E Filter Modes Interpolation Factor HB1 1 0 HB2 5 0 HB3 5 0 Modulation fcenter Shift 8 00 0 000000 000000 DC 0 8 01 1 001001 000000 foata 2 8 10 2 010010 001001 foata foata 8 11 3 011011 001001 foara 3 x foata 2 8 00 0 100100 010010 2 X fa
61. d 1 indicates that the internal digital clock generation logic 0 is ready This occurs when internal clocks are present and stable 2 Soft FIFO sync 1 indicates that a FIFO reset originating from a serial 0 port based request has successfully completed This is a latched signal 1 FIFO Warning 1 1 indicates that the difference between the FIFO read 0 and write pointers is 1 0 FIFO Warning 2 1 indicates that the difference between the FIFO read 0 and write pointers is 2 Event Flag 2 0x07 4 AED comparison pass 1 indicates that the SED logic detected a valid input 0 data pattern compared with the preprogrammed expected values This is a latched signal 3 AED comparison fail 1 indicates that the SED logic detected an invalid 0 input data pattern compared with the preprogrammed expected values This is a latched signal that auto matically clears when eight valid I Q data pairs are received 2 SED comparison fail 1 indicates that the SED logic detected an invalid input data pattern compared with the preprogrammed expected values This is a latched signal Clock Receiver 0x08 7 DACCLK duty correction 1 enables duty cycle correction on the DACCLK input 0 Control 6 REFCLK duty correction 1 enables duty cycle correction on the REFCLK input 0 DACCLK cross correction 1 enables differential crossing correction on the DACCLK input 4 REFCLK cross correction 1 enables differential crossing correction on the 1
62. d by the stop band rejection not by the pass band flatness Table 17 shows the pass band flatness and stop band rejection that the HB1 filter supports at different bandwidths 0 02 0 02 GAIN dB b e A 0 06 0 0 04 0 08 0 12 0 16 0 20 0 24 0 28 0 32 0 36 0 40 NORMALIZED FREQUENCY fj 09016 022 Figure 52 Pass Band Detail of HB1 Table 17 HB1 Pass Band Flatness and Stop Band Rejection Pass Band Stop Band Bandwidth 96 of fin1 Flatness dB Rejection dB 80 0 001 85 80 4 0 0012 80 812 0 0033 70 82 0 0 0076 60 83 6 0 0271 50 85 6 0 1096 40 Half Band Filter 2 HB2 HB2 has eight modes of operation as shown in Figure 53 and Figure 54 The shape of the filter response is identical in each of the eight modes The eight modes are distinguished by two factors the filter center frequency and whether the input signal is modulated by the filter y MODE 2 T 5 2 z 0 02 04 06 08 10 12 14 16 18 20 8 NORMALIZED FREQUENCY 5 Figure 53 HB2 Even Filter Modes T 5 2 4 0 02 04 06 08 10 12 14 16 18 20 NORMALIZED FREQUENCY x fino Figure 54 HB2 Odd Filter Modes 09016 024 As shown in Figure 53 and Figure 54 the center frequency in each mode is offset by of the input data rate fno of the filter Mode 0 through Mode 3 do not modulate the input signal
63. d or write and the starting register address for the first byte of the data transfer The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the device A logic high on the CS pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle From this state the next eight rising SCLK edges represent the instruction bits of the current I O operation The remaining SCLK edges are for Phase 2 of the communication cycle Phase 2 is the actual data transfer between the device and the system controller Phase 2 of the communication cycle is a transfer of one or more data bytes Registers change immediately upon writing to the last bit of each transfer byte except for the frequency tuning word and NCO phase offsets which only change when the frequency update bit Register 0x36 Bit 0 is set DATA FORMAT The instruction byte contains the information shown in Table 9 Table 9 Serial Port Instruction Byte I7 MSB l6 15 14 13 12 n IO LSB R W 5 A4 A3 A2 A1 R W Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write Logic 1 indicates a read operation and Logic 0 indicates a write operation to AO Bit 6 to Bit 0 of the instruction byte determine the register that is accessed during the data transfer portion of the communication cycle
64. data transmission or it can be asserted repeatedly at intervals coinciding with the I0 and Q0 data words FRAME Figure 87 Timing Diagram for Dual Word Mode SED Operation 055 09016 In word mode the FRAME signal required to align the data samples needs to be extended The FRAME signal can be issued once at the start of the data transmission or it can be asserted repeatedly at intervals coinciding with the 10 and Q0 data words FRAME Figure 88 Timing Diagram for Two Port Mode SED Operation 09016 056 The SED has three flag bits Register 0x67 Bit 0 Bit 1 and Bit 5 that indicate the results of the input sample comparisons The sample error detected bit Register 0x67 Bit 5 is set when an error is detected and remains set until the bit is cleared The SED also provides registers that indicate which input data bits experienced errors Register 0x70 through Register 0x73 These bits are latched and indicate the accumulated errors detected until cleared The autoclear mode has two effects it activates the compare fail bit and the compare pass bit Register 0x67 Bit 1 and Bit 0 and changes the behavior of Register 0x70 through Register 0x73 The compare pass bit is set if the last comparison indicated that the sample was error free The compare fail bit is set if an error is detected The compare fail bit is automatically cleared by the reception of eight consecutive error free comparisons When autoclear mode
65. dulation The HB1 filter has four modes of operation and the HB2 and HB3 filters each have eight modes of operation Half Band Filter 1 HB1 1 has four modes of operation as shown in Figure 51 The shape of the filter response is identical in each ofthe four modes The four modes are distinguished by two factors the filter center frequency and whether the input signal is modulated by the filter GAIN dB 0 02 04 06 08 10 12 14 16 18 20 NORMALIZED FREQUENCY fj Figure 51 HB1 Filter Modes 09016 021 As shown in Figure 51 the center frequency in each mode is offset by the input data rate fini of the filter Mode 0 and Mode 1 do not modulate the input signal Mode 2 and Mode 3 modulate the input signal by fn When HB1 operates in Mode 0 and Mode 2 the I and Q paths operate independently and no mixing of the data between channels occurs When HB1 operates in Mode 1 and Mode 3 mixing of the data between the I and paths occurs therefore the data input into the filter is assumed complex Table 16 summarizes the HB1 modes Table 16 HB1 Filter Mode Summary Mode fcenter Input Data 0 DC None Real or complex 1 fin 2 None Complex 2 fin fin Real or complex 3 3fin 2 fin Complex Rev 0 Page 32 of 56 Figure 52 shows the pass band filter response for HB1 In most applications the usable bandwidth of the filter is limited by the image suppression provide
66. ee Register Ox6C 1A Compare Q1 LSBs Ox6E 7 0 Compare Value 1 7 0 Compare Value Q1 15 0 is the word that is compared C6 with the O1 input sample captured at the input interface Compare Q1 MSBs Ox6F 7 0 Compare Value See Register Ox6E AA Q1 15 8 SED I LSBs 0x70 7 0 Errors Detected Errors detected BITS 15 0 indicates which bits were 0 BITS 7 0 received in error SED MSBs 0x71 7 0 Errors detected See Register 0x70 0 BITS 15 8 SED QLSBs 0x72 7 0 Errors detected Errors detected Q_BITS 15 0 indicates which bits were 0 Q BITS 7 0 received in error SED Q MSBs 0x73 7 0 Errors detected See Register 0x72 0 Q BITS 15 8 Die Revision Ox7F 5 2 Revision 3 0 Corresponds to device die revision 3 1 All bit event flags are cleared by writing the respective bit high Rev 0 Page 28 of 56 CMOS INPUT DATA PORTS The AD9125 input data port consists of a data clock data bus and FRAME signal The data port can be configured to operate in three modes dual word mode word mode and byte mode In dual word mode I and Q data is received simultaneously on two 16 pin buses One bus receives I datapath input words and the other bus receives Q datapath input words In word mode one 16 pin bus is used to receive interleaved I and Q input words In byte mode an 8 pin bus is used to receive interleaved I and Q input bytes The pin assignments of the bus in each mode is described in Table 12 T
67. elative reset enforces a defined FIFO depth An absolute reset enforces a particular write pointer value when the reset is initiated A serial port initiated FIFO reset is always a relative reset A FRAME strobe initiated reset can be either a relative or an absolute reset The operation of the FRAME initiated FIFO reset depends on the synchronization mode chosen When synchronization is disabled or when the device is configured for data rate mode synchronization the FRAME strobe initiates a relative FIFO reset When FIFO mode synchronization is chosen the FRAME strobe initiates an absolute FIFO reset More details on the synchronization function can be found in the Multichip Synchronization section A summary of the synchronization modes and the type of FIFO reset employed is listed in Table 15 Table 15 Summary of FIFO Resets FIFO Synchronization Mode ResetSignal Disabled Data Rate FIFO Rate Serial Port Relative reset Relativereset Relative reset FRAME Relative reset Relative reset Absolute reset FIFO Level Initialization via Serial Port A serial port initiated FIFO reset can be issued in any mode and always results in a relative FIFO reset To initialize the FIFO data level through the serial port Bit 1 of Register 0x18 should be toggled from 0 to 1 and then back to 0 When the write to the register is complete the FIFO data level is initialized When the initialization is triggered the next time t
68. ge 36 of 56 DATAPATH CONFIGURATION EXAMPLE 8x Interpolation Without NCO Given the following conditions the desired 75 MHz of bandwidth is 7596 of e par 100 MSPS e 8xinterpolation f 75 MHz e fcenrer 100 MHz In this case the ratio of four foara 100 100 1 0 From Figure 59 the bandwidth supported at fpara is 0 8 which verifies that the AD9125 supports the bandwidth required in this configuration The signal center frequency is fpara and assuming the input signal is at baseband the frequency shift required is also fpara Using the settings detailed in the third row of the IF column from Table 21 these settings use the configuration in the 8x interpolation without NCO example selects filter modes that result in a center frequency of and a frequency translation of The selected modes for the three half band filters HB1 Mode 2 HB2 Mode 2 and HB3 Mode 1 Figure 60 shows how the signal propagates through the interpolation filters Because 2 x fmi fno and 2 x fno fins the signal appears frequency scaled by into each consecutive stage The output signal band spans 0 15 to 0 35 of fms 400 MHz Therefore the output frequency supported is 60 MHz to 140 MHz which covers the 75 MHz bandwidth centered at 100 MHz as desired HB1 HB2 B tita lt 0 15 0 35 4x Interpolation with NCO Given the following conditions the desired 140 MHz of bandwidth is 56 of
69. hase 1 enables interrupt for clock generation ready 0 locked 2 Enable soft FIFO sync 1 enables interrupt for soft FIFO reset 0 Rev 0 Page 21 of 56 Register Address Name Hex Bits Name Description Default 1 Enable FIFO Warning 1 1 enables interrupt for FIFO Warning 1 0 0 Enable FIFO Warning 2 1 enables interrupt for FIFO Warning 2 0 Interrupt Enable 2 0x05 7 Setto 0 Set this bit to 0 0 6 Setto 0 Set this bit to 0 0 5 Setto 0 Set this bit to 0 0 4 Enable AED comparison 1 enables interrupt for AED comparison pass 0 pass 3 Enable AED comparison 1 enables interrupt for AED comparison fail 0 fail 2 Enable SED comparison 1 enables interrupt for SED comparison fail 0 fail 1 Setto 0 Set this bit to 0 0 0 Setto 0 Set this bit to 0 0 Event Flag 1 0x06 7 PLL lock lost 1 indicates that the PLL which had been previously 0 locked has unlocked from the reference signal This is a latched signal 6 PLL locked 1 indicates that the PLL has locked to the reference 0 clock input 5 Sync signal lost 1 indicates that the sync logic which had been 0 previously locked has lost alignment This is a latched signal 4 Sync signal locked 1 indicates that the sync logic did achieve sync 0 alignment This is indicated when no phase changes were requested for at least a few full averaging cycles 3 Sync phase locke
70. he HB2 filter supports at different bandwidths GAIN dB b 0 10 0 0 00 008 012 016 020 0 24 028 NORMALIZED FREQUENCY 1 E gt Figure 56 Pass Band Detail of HB3 4 Table 20 HB3 Pass Band Flatness and Stop Band Rejection Complex Bandwidth Pass Band Stop Band of fins Flatness dB Rejection dB 40 0 001 85 40 8 0 0014 80 0 04 0 08 0 12 0 16 020 0 24 0 28 032 8 42 4 0 002 70 NORMALIZED FREQUENCY x 8 45 6 0 0093 60 Figure 55 Pass Band Detail of HB2 49 8 0 03 50 cau 55 6 0 1 40 Table 19 HB2 Pass Band Flatness and Stop Band Rejection Complex Bandwidth Pass Band Stop Band 96 of finz Flatness dB Rejection dB 50 0 001 85 50 8 0 0012 80 52 8 0 0028 70 56 0 0 0089 60 60 0 0287 50 64 8 0 1877 40 Rev 0 Page 34 of 56 NCO MODULATION The digital quadrature modulator makes use of a numerically controlled oscillator a phase shifter and a complex modulator to provide a means for modulating the signal by a programmable carrier signal A block diagram of the digital modulator is shown in Figure 57 The fine modulation provided by the digital modulator in conjunction with the coarse modulation of the interpolation filters and premodulation block allows the signal to be placed anywhere in the output spectrum with very fine frequency resolution INTERPOLATION FTW 31 0 NCO PHASE OFFSET 15 0 I DATA SPECTRAL INVERS
71. he read pointer becomes 0 the write pointer is set to the value of the FIFO phase offset level Register 0x17 Bits 2 0 variable upon initialization By default this is 4 but it can be programmed to a value between 0 and 7 The recommended procedure for a serial port FIFO data level initialization is as follows 1 Request FIFO level reset by setting Register 0x18 Bit 1 to 1 2 Verify that the part acknowledges the request by ensuring that Register 0x18 Bit 2 is 1 3 Remove the request by setting Register 0x18 Bit 1 to 0 Verify that the part drops the acknowledge signal by ensuring that Register 0x18 Bit 2 is 0 FIFO Level Initialization via FRAME Signal The primary function of the FRAME input is indicating to which DAC the input data is written Another function of the FRAME input is initializing the FIFO data level value This is done by asserting the FRAME signal high for at least the time interval needed to load complete data to the I and DACs This corresponds to one DCI period in dual word mode two DCI periods in word mode and four DCI periods in byte mode To initiate a relative FIFO reset with the FRAME signal the device must be configured in data rate mode Register 0x10 Bit 6 When FRAME is asserted in data rate mode the write pointer is set to 4 by default or to the FIFO start level the next time the read pointer becomes 0 see Figure 48 READ 1 7 POINTER E EAE FIFO WRITE RESETS FRAME
72. imization sections Sync Status Bits When the sync locked bit Register 0x12 Bit 6 is set it indicates that the synchronization logic has reached alignment This alignment is determined when the clock generation state machine phase is constant It takes between 11 averaging x 64 and 11 averaging x 128 DACCLK cycles This bit can optionally trigger an IRQ as described in the Interrupt Request Operation section When the sync lost bit Register 0x12 Bit 7 is set it indicates a previously synchronized device has lost alignment This bit is latched and remains set until cleared by overwriting the register This bit can optionally trigger an IRQ as described in the Interrupt Request Operation section The sync phase readback bits Register 0x13 Bits 7 0 report the current clock phase in a 6 2 format Bits 7 2 report which of the 64 states 0 to 63 the clock is currently in When averaging is enabled Bits 1 0 provide state accuracy for 0 34 The lower two bits give an indication of the timing margin issues that may exist If the sync sampling is error free the fractional clock state should be 00 Timing Optimization The REFCLK signal is sampled by a version of the DACCLK If sampling errors are being detected the opposite sampling edge can be selected to improve the sampling point The sampling edge can be selected by setting Register 0x10 Bit 3 1 rising and 0 falling The synchronization logic
73. ion requires both gain and phase matching of the I and Q signals The I phase adjust Register 0x38 and Register 0x39 Q phase adjust Register 0x3A and Register 0x3B I DAC FS adjust Register 0x40 and Register 0x41 and Q DAC FS adjust Register 0x44 and Register 0x45 registers can be used to calibrate I and Q transmit paths to optimize the sideband suppression 22pF 09016 042 Figure 75 DAC Modulator Interface with Fifth Order Low Pass Filter Rev 0 Page 44 of 56 DEVICE POWER DISSIPATION The AD9125 has four supply rails AVDD33 IOVDD DVDD18 and CVDD18 The AVDD33 supply powers the DAC core circuitry The power dissipation of the AVDD33 supply rail is independent of the digital operating mode and sample rate The current drawn from the AVDD33 supply rail is typically 57 mA 188 mW when the full scale current of the I and Q DACs is set to the nominal value of 20 mA Changing the full scale current directly impacts the supply current drawn from the AVDD33 rail For example if the full scale current of the I DAC and the Q DAC is changed to 10 mA the AVDD33 supply current drops by 20 mA to 37 mA The IOVDD voltage supplies the serial port I O pins the RESET pin and the IRQ pin The voltage applied to the IOVDD pin can range from 1 8 V to 3 3 V The current drawn by the IOVDD supply pin is typically 3 mA The DVDD18 supply powers all of the digital signal processing blocks of the device The power consumption from this
74. lifying clock that is time aligned with the input data The rising edge of the DCI signal should be aligned with the changing data of the interleaved I and Q input data stream The FRAME signal indicates to which DAC the data is sent When FRAME is high data is sent to the I DAC When FRAME is low data is sent to the Q DAC Both bytes must be written to each datapath for proper operation For 14 and 12 bit resolution devices the LSBs in the second byte are not significant The complete timing diagram is shown in Figure 44 o tan en ae nns oan mo ana FRAME Figure 44 Timing Diagram for Byte Mode 09016 143 09016 144 Rev 0 Page 29 of 56 INTERFACE TIMING The timing diagram for the digital interface port is shown in Figure 45 The sampling point of the data bus occurs on the falling edge of the DCI signal and has an uncertainty of 2 1 ns as illustrated by the sampling interval shown in Figure 45 The D 31 0 and FRAME signals must be valid throughout this sampling interval The setup ts and hold tu times with respect to the edges are shown in Figure 45 The minimum setup and hold times are shown in Table 13 m z gt 09016 146 Figure 45 Timing Diagram for Input Data Ports Table 13 Data Port Setup and Hold Times Minimum Setup Time ts ns Minimum Hold Time ns 0 86 1 24 lt gt ls FRAME 1 1 1 est 1 1 1 1 1 1 1 b td
75. ll scale output current can be programmed over a range of 8 7 mA to 31 7 mA The AD9125 comes in a 72 lead LFCSP PRODUCT HIGHLIGHTS 1 Ultralow noise and intermodulation distortion IMD enable high quality synthesis of wideband signals from baseband to high intermediate frequencies 2 proprietary DAC output switching technique enhances dynamic performance 3 The current outputs are easily configured for various single ended or differential circuit topologies 4 The flexible CMOS digital interface allows the standard 32 wire bus to be reduced to a 16 wire bus TYPICAL SIGNAL CHAIN DIGITAL BASEBAND PROCESSOR NOTES 1 AGM ANALOG QUADRATURE MODULATOR Rev 0 Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result fromits use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners COMPLEX IF d 09016 001 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2010 Analog Devices Inc All rights reserved TABLE OF CONTENTS Features
76. lled by the LSB FIRST bit Register 0x00 Bit 6 The default is MSB first LSB FIRST 0 When LSB FIRST 0 MSB first the instruction and data bit must be written from MSB to LSB Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte Subsequent data bytes should follow from the high address to the low address In MSB first mode the serial port internal byte address generator decrements for each data byte of the multibyte communi cation cycle When LSB FIRST 1 LSB first the instruction and data bit must be written from LSB to MSB Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes The serial port internal byte address generator increments for each byte of the multibyte communication cycle The serial port controller data address decrements from the data address written toward 0x00 for multibyte I O operations if the MSB first mode is active The serial port controller address increments from the data address written toward 0x7F for multibyte I O operations if the LSB first mode is active cs SCLK INSTRUCTION CYCLE DATA TRANSFER CYCLE L innnnnnnrnnnnnnnr smio fef ao fas aafaa so M irb Figure 38 Serial Register Interface Timing MSB First DATA TRANSFER CYCLE so lebe
77. meters the first step in configuring the datapath is to verify that the device supports the bandwidth requirements The modes of the interpolation filters are then chosen Finally any additional frequency offset requirements are determined and applied with premodulation and NCO modulation Determining Datapath Signal Bandwidth The available signal bandwidth of the datapath is dependent on the center frequency of the output signal in relation to the center frequency of the interpolation filters used Signal center frequencies that are offset from the center frequencies of the half band filters lower the available signal bandwidth When correctly configured the available complex signal band width for 2x interpolation is always 8096 of the input data rate The available signal bandwidth for 4x interpolation vs output frequency varies between 5096 and 8096 of the input data rate as shown in Figure 58 Note that in 4x interpolation mode foac 4 X therefore the data shown in Figure 58 repeats four times from dc to fpac HB1 AND HB2 0 8 4 rp e a 1 0 2 AND HB3 0 2 0 4 0 6 0 8 1 0 four fpata 0901 6 028 Figure 58 Signal Bandwidth vs Center Frequency of the Output Signal 4x Interpolation Configuring 4x interpolation using the HB2 and HB3 filters can lower the power consumption of the device at the expense of reduced bandwidth The lower
78. nd selects the input from the DACCLKP and DACCLKN pins as the source for the internal DAC sample clock The device also has duty cycle correction circuitry and differential input level correction circuitry Enabling these circuits can provide improved performance in some cases The control bits for these functions can be found in Register 0x08 see Table 11 Clock Multiplication The on chip PLL clock multiplier circuit can be used to generate the DAC sample rate clock from a lower frequency reference clock When the PLL enable bit Register 0x0A Bit 7 is set to 1 the clock multiplication circuit generates the DAC sample clock from the lower rate REFCLK input The functional diagram of the clock multiplier is shown in Figure 64 The clock multiplication circuit operates such that the VCO outputs a frequency fvco equal to the REFCLK input signal frequency multiplied by N1 x NO fvco frercix NI x NO The DAC sample clock frequency fpacc x is equal to foaccix freecix NI The output frequency of the VCO must be chosen to keep fvco in the optimal operating range of 1 0 GHz to 2 1 GHz The frequency of the reference clock and the values of N1 and NO must be chosen so that the desired DACCLK frequency can be synthesized and the VCO output frequency is in the correct range REGISTER 0x0E BITS 3 0 O VCO CONTROL VOLTAGE REGISTER 0x0D BITS 3 2 DACCLK REGISTER 0x0D BITS 7 6 N2 09016 034 Figure 64
79. o 85 C operating temperature range of the device without further adjustment The PLL remains locked over the full temperature range even if the temperature during initialization is at one of the temperature extremes PLL BAND e 1000 1200 1400 1600 1800 2000 2200 VCO FREQUENCY MHz 09016 035 Figure 65 PLL Lock Range over Temperature for a Typical Device Manual VCO Band Select The device also has a manual band select mode PLL manual enable Register 0x0A Bit 6 1 that allows the user to select the VCO tuning band When in manual mode the VCO band is set directly with the value written to the manual VCO band Register Ox0A Bits 5 0 To properly select the VCO band follow these steps 1 Put the device in manual band select mode 2 Sweep the VCO band over a range of bands that result in the PLL being locked 3 For each band verify that the PLL is locked and read the PLL using the VCO control voltage Register OxOE Bits 3 0 4 Select the band that results in the control voltage being closest to the center of the range that is 0000 or 1000 see Table 25 for more details The resulting VCO band should be the optimal setting for the device Write this band to the manual VCO band Register 0x0A Bits 5 0 value 5 If desired an indication of where the VCO is within the operating frequency band can be determined by querying the VCO control voltage Table 25 shows how to interpret the PLL VCO
80. o 1 1 Update FTW 1 indicates that the FTW has been updated 0 acknowledge 0 Update FTW request 0 1 the FTW is updated on 0 to 1 transition of this bit 0 Phase Adj LSB 0x38 7 0 phase adjust 7 0 phase adjust 9 0 is used to insert a phase offset 0 between the and datapaths This can be used to correct for phase imbalance in a quadrature modulator See the Quadrature Phase Correction section for details Phase Adj MSB 0x39 1 0 I phase adjust 9 8 Register 0x38 0 Q Phase Adj LSB Ox3A 7 0 Q phase adjust 7 0 phase adjust 9 0 is used to insert a phase offset 0 between the and datapaths This can be used to correct for phase imbalance in a quadrature modulator See the Quadrature Phase Correction section for details Q Phase Adj MSB Ox3B 1 0 Q phase adjust 9 8 See Register 0 DAC Offset LSB 0x3C 70 I DAC offset 7 0 I DAC offset 15 0 is a value added directly to the 0 samples written to the DAC I DAC Offset MSB 0x3D 70 I DAC offset 15 8 See Register Ox3C 0 Q DAC Offset LSB Ox3E 70 Q DAC offset 7 0 Q DAC offset 15 0 is a value added directly to the 0 samples written to the Q DAC Q DAC Offset MSB Ox3F 7 0 Q DAC offset 15 8 See Register 0x3E 0 I DAC FS Adjust 0x40 7 0 IDACFS adjust 7 0 DAC FS adjust 9 0 sets the full scale current of the F9 DAC The full scale current can be adjusted from 8 64 mA to 31 6 mA in step sizes of approximately 22 5 pA 0x000 8 64 mA 0x2
81. on rate a digital filter can be constructed that has a sharp transition band near fpar4 2 Images that typically appear around fpac output data rate can be greatly suppressed Adjacent Channel Leakage Ratio ACLR The ratio in decibels relative to the carrier dBc between the measured power within a channel and that of its adjacent channel Complex Image Rejection In a traditional two part upconversion two images are created around the second IF frequency These images have the effect of wasting transmitter power and system bandwidth By placing the real part of a second complex modulator in series with the first complex modulator either the upper or lower frequency image near the second IF can be rejected CLOCK GENERATOR AND DISTRIBUTOR 1 2 1 foac 09016 136 Figure 36 Defining Data Rates Rev 0 Page 16 of 56 THEORY OF OPERATION The AD9125 combines many features that make it a very attractive DAC for wired and wireless communications systems The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband transmitters The speed and performance of the AD9125 allows wider bandwidths and more carriers to be synthesized than in previously available DACs In addition these devices include an innovative low power 32 bit complex NCO that greatly increases the ease of frequency placement The AD9125 offers features that allow sim
82. onized clock In FIFO rate mode the FIFO rate which is the data rate divided by the FIFO depth of 8 represents the lowest rate clock The advantage of FIFO rate synchronization is increased time between keep out windows for DCI changes relative to the DACCLK or REFCLK input When in data rate mode the elasticity of the FIFO is not used to absorb timing variations between the data source and the DAC resulting in keep out widows repeating at the input data rate The method chosen for providing the DAC sampling clock directly impacts the synchronization methods available When the device clock multiplier is used only data rate mode is available When the DAC sampling clock is sourced directly both data rate mode and FIFO rate mode synchronization are available This section details the synchronization methods for enabling both clocking modes and for querying the status of the synchronization logic SYNCHRONIZATION WITH CLOCK MULTIPLICATION When using the clock multiplier to generate the DAC sample rate clock the REFCLK input signal acts both as the reference dock for the PLL based clock multiplier and as the synchronization signal To synchronize devices distribute the REFCLK signal with low skew to all of the devices that need to be synchronized Skew between the REFCLK signals of the devices shows up directly as a timing mismatch at the DAC outputs The frequency of the REFCLK signal is typically equal to the input data rate The FRAM
83. output currents from the IOUT1P IOUT2P and IOUTIN IOUT2N pins are complementary meaning that the sum of the two currents always equals the full scale current of the DAC The digital input code to the DAC determines the effective differential current delivered to the load IOUT1P IOUT2P provide maximum output current when all bits are high The output currents vs DACCODE for the DAC outputs are expressed as DACCODE Iourp 2N 1 Ioury Dovrzs 7 Toure 2 where DACCODE 0 to 2 1 Transmit DAC Output Configurations The optimum noise and distortion performance of the AD9125 is realized when it is configured for differential operation The common mode error sources of the DAC outputs are significantly reduced by the common mode rejection of a transformer or differential amplifier These common mode error sources include even order distortion products and noise The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and or its amplitude increases This is due to the first order cancellation of various dynamic common mode distortion mechanisms digital feedthrough and noise Rev 0 Page 42 of 56 Figure 68 shows the most basic DAC output circuitry A pair of resistors Ro is used to convert each of the complementary output currents to a differential voltage output Vour Because the current outputs of the DAC are high impedance the differential driving
84. plified circuit diagram of the input The on chip clock receiver has a differential input impedance of about 10 It is self biased to a common mode voltage of about 1 25 V The inputs can be driven by directly coupling differential PECL or LVDS drivers The inputs can also be ac coupled if the driving source cannot meet the input compliance voltage of the receiver DACCLKP REFCLKP DACCLKN REFCLKN 09016 033 Figure 63 Clock Receiver Input Equivalent Circuit REGISTER 0x06 BITS 7 6 PLL LOCK LOST PLL LOCKED PHASE DETECTION REGISTER 0x0D BITS 1 0 Ni REFCLKP REFCLKN PIN 69 AND PIN 70 O DACCLKP DACCLKN PIN 2 AND PIN 3 REGISTER 0x0A BIT 7 PLL ENABLE PLL LOGIC CONTROL CLOCK The minimum input drive level to either clock input is 200 mV p p differential The optimal performance is achieved when the clock input signal is between 800 mV p p differential and 1 6 V p p differential Whether using the on chip clock multiplier or sourcing the DACCLK directly it is necessary that the input clock signal to the device has low jitter and fast edge rates to optimize the DAC noise performance Direct Clocking Direct clocking with a low noise clock produces the lowest noise spectral density at the DAC outputs To select the differential clock inputs as the source for the DAC sampling clock set the PLL enable bit Register 0x0A Bit 7 to 0 This powers down the internal PLL clock multiplier a
85. plified synchronization with incoming data and between multiple devices Auxiliary DACs are also provided on chip for output dc offset compensation for local oscillator LO compensation in single sideband SSB transmitters and for gain matching for image rejection optimization in SSB transmitters SERIAL PORT OPERATION The serial port is a flexible synchronous serial communication port allowing easy interface to many industry standard micro controllers and microprocessors The serial I O is compatible with most synchronous transfer formats including both the Motorola SPI and Intel SSR protocols The interface allows read write access to all registers that configure the AD9125 Single or multiple byte transfers are supported as well as MSB first or LSB first transfer formats The serial interface ports can be configured as a single pin I O SDIO or two unidirectional pins for input output SDIO SDO SDO 60 5010 6 spi PORT os i Figure 37 Serial Port Interface Pins There are two phases of a communication cycle with the AD9125 Phase 1 is the instruction cycle the writing of an instruction byte into the device which is coincident with the first eight SCLK rising edges The instruction byte provides the serial port controller with information regarding the data transfer cycle which is Phase 2 of the communication cycle The Phase 1 instruction byte defines whether the upcoming data transfer is a rea
86. r Up Time 260 ms Rev 0 Page 5 of 56 ACSPECIFICATIONS Tmn to Tmax AVDD33 3 3 V DVDD18 1 8 V CVDDIS 1 8 V Iourrs 20 mA maximum sample rate unless otherwise noted Table 4 Parameter Min Typ Max Unit SPURIOUS FREE DYNAMIC RANGE SFDR foac 100 MSPS four 20 MHz 78 dBc foac 200 MSPS four 50 MHz 80 dBc foac 400 MSPS four 70 MHz 69 dBc foac 800 MSPS four 70 MHz 72 dBc TWO TONE INTERMODULATION DISTORTION IMD foac 200 MSPS four 50 MHz 84 dBc foac 400 MSPS four 60 MHz 86 dBc foac 400 MSPS four 80 MHz 84 dBc foac 800 MSPS four 100 MHz 81 dBc NOISE SPECTRAL DENSITY NSD EIGHT TONE 500 kHz TONE SPACING foac 200 MSPS four 80 MHz 162 dBm Hz foac 400 MSPS four 80 MHz 163 dBm Hz foac 800 MSPS four 80 MHz 164 dBm Hz W CDMA ADJACENT CHANNEL LEAKAGE RATIO ACLR SINGLE CARRIER foac 491 52 MSPS four 10 MHz 82 dBc foac 491 52 MSPS four 122 88 MHz 80 dBc foac 983 04 MSPS four 122 88 MHz 81 dBc W CDMA SECOND ACLR SINGLE CARRIER foac 491 52 MSPS four 10 MHz 88 dBc foac 491 52 MSPS four 122 88 MHz 86 dBc foac 983 04 MSPS four 122 88 MHz 88 dBc Table 5 Interface Speeds Mode Interpolation feus foata foac Byte Mode 1x 250 62 5 62 5 2x HB1 250 62 5 125 2x HB2 250 62 5 125 4x 250 62 5 250 8x 250 62 5 500 Word Mode 1x 250 125 125 2x HB1 250 125 250 2x HB2 250 125 250 4x 250 125 500 8x 250 1
87. ra 2 X foata 8 01 1 101101 010010 2 X fora 5 X fps 2 8 10 2 110110 011011 3 3 X foata 8 11 3 111111 011011 fpa 7 X foata 2 8 00 0 000000 100100 4 X foata 4 X foata 8 01 1 001001 100100 4 X fpara 9 x foata 2 8 10 2 010010 101101 5 X foata 5 X foara 8 11 3 011011 101101 5 X fpara 11 x foata 2 8 00 0 100100 110110 6 X foata 6 X foata 8 01 1 101101 110110 6 foara 13 x foata 2 8 10 2 110110 111111 7 7 X foata 8 11 3 111111 111111 7 X foara 15 x fpa 2 4 00 0 000000 Bypass DC 0 43 01 1 001001 Bypass foata 2 4 10 2 010010 Bypass foata foata 4 11 3 011011 Bypass foara 3 x foata 2 4 00 0 100100 Bypass 2 X foata 2 X foata 4 01 1 101101 Bypass 2 X fona 5 X foata 2 4 10 2 110110 Bypass 3 X foata 3 X foata 4 11 3 111111 Bypass 3 X foara 7 X foata 2 2 00 0 Bypass Bypass DC 0 2 01 1 Bypass Bypass Dc foata 2 2 10 2 Bypass Bypass foata foata 2 11 3 Bypass Bypass 3 foata 2 When HB1 Mode 1 or Mode 3 is used enabling premodulation provides an addition frequency translation of the input signal by foata 2 which centers a baseband input signal in the filter pass band This configuration was used in the 8x interpolation without NCO example In addition see the 8x Interpolation Without NCO section 3 This configuration was used in the 4x interpolation with NCO example In addition see the 4x Interpolation with NCO section Rev 0 Pa
88. rature 4 Die temperature 15 8 N A MSB SED Control 0x67 SED Sample Auto Compare Compare 0x00 compare error Clear fail pass enable detected enable Compare 10 LSBs 0x68 Compare Value 10 7 0 OxB6 Compare 0x69 Compare Value 10 1 5 8 Ox7A 10 MSBs Compare Ox6A Compare Value QO 7 0 0x45 QO LSBs Compare Ox6B Compare Value Q0 15 8 OxEA MSBs Compare 11 LSBs 0x6C Compare Value 11 7 0 0x16 Compare 1 MSBs Ox6D Compare Value 11 15 8 Ox6E Compare Value Q1 7 0 0xC6 Q1 LSBs Rev 0 Page 20 of 56 Addr Register Name Hex Bit7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Default Compare Ox6F Compare Value Q1 15 8 OxAA Q1 MSBs SED LSBs 0x70 Errors detected _BITS 7 0 0x00 SED MSBs 0x71 Errors detected BITS 15 8 0x00 SED QLSBs 0x72 Errors detected BITS 7 0 0x00 SED MSBs 0x73 Errors detected Q BITS 15 8 0x00 Die Revsion Ox7F Revision 3 0 Ox0C DEVICE CONFIGURATION REGISTER DESCRIPTIONS Table 11 Device Configuration Register Descriptions Register Address Name Hex Bits Name Description Default Comm 0x00 7 SDIO SDIO operation 0 0 SDIO operates as an input only 1 SDIO operates as a bidirectional input output 6 LSB_FIRST Serial port communication LSB or MSB first 0 0 MSB first 1 LSB first 5 Reset 1 device is held in reset when this bit is written high
89. strobing the FRAME signal high for the time required to write two complete input data words Resetting the FIFO ensures that the correct data is being read from the FIFO of each of the devices simultaneously tskew DACCLKP 1 DACCLKN 1 DACCLKP 2 DACCLKN 2 REFCLKP 2 REFCLKN 2 1 _ tH pci DCI2 2 FRAME 2 To ensure that each DAC is updated with the correct data on the same CLK edge two timing relationships must be met on each DAC DCI and D 31 0 must meet the setup and hold times with respect to the rising edge of DACCLK and REFCLK must meet the setup and hold times with respect to the rising edge of DACCLK When resetting the FIFO the FRAME signal must be held high for the time required to input two complete input data words When these conditions are met the outputs of the DACs are updated within tskew tourmiy of each other timing diagram that illustrates the timing requirements of the input signals is shown in Figure 84 Figure 84 shows the synchronization signal timing with 2x interpolation therefore x fax The REFCLK input is shown to be equal to the data rate The maximum frequency at which the device can be resynchronized in data rate mode can be expressed as fsynca foaral 27 where N is any nonnegative integer Generally for values of N equal to or greater than 3 select the FIFO rate synchronization mode Table 26 DCI DAC Setup and Hold Times Minimum Setup Time
90. t signal is modulated by fins filter pass band is from 1 55 to 1 95 of fins Bypass HB3 1 bypasses third stage interpolation filter Chip ID Ox1F 7 0 Chip ID 7 0 This register identifies the device as an AD9125 Rev 0 Page 25 of 56 Register Address Name Hex Bits Name Description Default FTW 1 LSB 0x30 7 0 FTW 7 0 FTW 31 0 is the 32 bit frequency tuning word that 0 determines the frequency of the complex carrier generated by the on chip NCO The frequency is not updated when the FTW registers are written The values are only updated when Bit 0 of Register 0x36 transitions from 0 to 1 FIW2 0x31 7 0 FTW 15 8 See Register 0x30 0 FTW 3 0x32 7 0 FTW 23 16 See Register 0x30 0 FTW 4 MSB 0x33 7 0 FTW 31 24 See Register 0x30 0 NCO Phase Offset 0x34 7 0 NCO phase offset 7 0 NCO phase offset 15 0 sets the phase of the complex 0 LSB carrier signal when the NCO is reset The phase offset spans between 0 and 360 Each bit represents an offset of 0 0055 The value is in twos complement format NCO Phase Offset 0x35 7 0 NCO phase offset 15 8 See Register 0x34 0 MSB NCO FTW Update 0x36 5 FRAME FTW 1 indicates that the NCO has been reset due to an 0 acknowledge extended FRAME pulse signal 4 FRAME FTW request 0 1 the NCO is reset on the first extended FRAME 0 pulse after this bit transitions from O t
91. ta level can be read from Register 0x19 at any time The FIFO data level reported by the serial port is denoted as a 7 bit thermometer code of the write counter state relative to the absolute read counter being at 0 The optimum FIFO data level of 4 is therefore reported as a value of 00001111 in the status register It should be noted that depending on the timing relationship between DCI and the main DACCLK the FIFO level value can be off by 1 count Therefore it is important to keep the difference between the read and write pointers to at least 2 Rev 0 Page 31 of 56 DIGITAL DATAPATH The block diagram in Figure 50 shows the functionality of the digital datapath The digital processing includes a premodulation block three half band interpolation filters a quadrature modulator with a fine resolution NCO a phase and offset adjustment block and an inverse sinc filter PHASE AND PREMOD OFFSET SINC 1 Figure 50 Block Diagram of Digital Datapath 09016 020 The digital datapath accepts I and Q data streams and processes them as a quadrature data stream The signal processing blocks can be used when the input data stream is represented as complex data The datapath can be used to process an input data stream representing two independent real data streams as well but the functionality is somewhat restricted The premodulation block can be used as well as any of the nonshifted interpolation filter modes see the Premodulation
92. ter pass band is from 0 25 to 0 25 of fio 001001 input signal is not modulated filter pass band is from 0 0 to 0 5 of fi 010010 input signal is not modulated filter pass band is from 0 25 to 0 75 of finz 011011 input signal is not modulated filter pass band is from 0 5 to 1 0 of finz 100100 input signal is modulated by filter pass band is from 0 75 to 1 25 of fi 101101 input signal is modulated by filter pass band is from 1 0 to 1 5 of fi 110110 input signal is modulated by filter pass band is from 1 25 to 1 75 of fi 111111 input signal is modulated by filter pass band is from 1 5 to 2 0 of Bypass HB2 1 bypasses second stage interpolation filter HB3 Control Ox1E 6 1 HB3 5 0 Modulation mode for Side Half Band Filter 3 000000 input signal is not modulated filter pass band is from 0 2 to 0 2 of fins 001001 input signal is not modulated filter pass band is from 0 05 to 0 45 of fins 010010 input signal is not modulated filter pass band is from 0 3 to 0 7 of fins 011011 input signal is not modulated filter pass band is from 0 55 to 0 95 of fins 100100 input signal is modulated by fins filter pass band is from 0 8 to 1 2 of fins 101101 input signal is modulated by fins filter pass band is from 1 05 to 1 45 of fins 110110 input signal is modulated by fins filter pass band is from 1 3 to 1 7 of fins 111111 inpu
93. the phase imbalance of the analog quadrature modulator following the DAC If the quadrature modulator has a phase imbalance the unwanted sideband appears with significant energy Tuning the quadrature phase adjust value can optimize image rejection in single sideband radios Ordinarily the I and Q channels have an angle of precisely 90 between them The quadrature phase adjustment is used to change the angle between the I and Q channels When the I phase adjust 9 0 is set to 1000000000 the I DAC output moves approximately 1 75 away from the Q DAC output creating an angle of 91 75 between the channels When the I phase adjust 9 0 is set to 0111111111 the I DAC output moves approximately 1 75 toward the Q DAC output creating an angle of 88 25 between the channels The Q phase adjust bits Bits 9 0 work in a similar fashion When the Q phase adjust 9 0 is set to 1000000000 the Q DAC output moves approximately 1 75 away from the I DAC output creating an angle of 91 75 between the channels When the phase adjust 9 0 is set to 0111111111 the Q DAC output moves approximately 1 75 toward the I DAC output creating an angle of 88 25 between the channels Based on these two endpoints the combined resolution of the phase compensation register is approximately 3 5 1024 or 0 00342 per code DC OFFSET CORRECTION The dc value of the I datapath and the Q datapath can be inde pendently controlled by adjusting the
94. ting Register 0x01 Bit 4 to 0 In addition to obtain accurate readings the range control register Register 0x48 should be set to 0x02 Rev 0 Page 46 of 56 MULTICHIP SYNCHRONIZATION System demands may require that the outputs of multiple DACs be synchronized with each other or with a system clock Systems that support transmit diversity or beam forming where multiple antennas are used to transmit a correlated signal require multiple DAC outputs to be phase aligned with each other Systems with a time division multiplexing transmit chain may require one or more DACs to be synchronized with a system level reference clock Multiple devices are considered synchronized to each other when the state of the clock generation state machine is identical for all parts and when time aligned data is being read from the FIFOs of all parts simultaneously Devices are considered synchronized to a system clock when there is a constant known relationship among the clock generation state machine the data being read from the FIFO and a particular clock edge of the system clock The AD9125 has provisions for enabling multiple devices to be synchronized to each other or to a system clock The AD9125 supports synchronization in two modes data rate mode and FIFO rate mode Each of these modes has a different lowest rate clock that the synchronization logic attempts to syn chronize to In data rate mode the input data rate represents the lowest synchr
95. tsu Minimum Hold Time tu pci ns ns 0 16 0 59 09016 052 Figure 84 Data Rate Synchronization Signal Timing Requirements 2x Interpolation Rev 0 Page 49 of 56 FIFO RATE MODE SYNCHRONIZATION The Procedure for FIFO Rate Synchronization when Directly Sourcing the DAC Sampling Clock section outlines the steps required to synchronize multiple devices in FIFO rate mode The procedure assumes that the REFCLK and DACCLK signals are applied to all of the devices The procedure must be carried out on each individual device Procedure for FIFO Rate Synchronization When Directly Sourcing the DAC Sampling Clock To synchronize all devices 1 Configure the device for FIFO rate mode and periodic synchronization by writing 0x80 to the Sync Control 1 register Register 0x10 Additional synchronization options are available and are described in the Additional Synchronization Features section 2 Poll the sync locked bit Register 0x12 Bit 6 to verify that the device is back end synchronized A high level on this bit indicates that the clocks are running with a constant and known phase relative to the sync signal 3 Resetthe FIFO by strobing the FRAME signal high for the time required to write two complete input data words Resetting the FIFO ensures that the correct data is being read from the FIFO of each of the devices simultaneously tskew DACCLKP 1 DACCLKN 1 DACCLKP 2 DACCLKN 2 tsu_sync tH syn
96. ty INL 3 7 LSB MAIN DAC OUTPUTS Offset Error 0 001 0 30 001 96 FSR Gain Error with Internal Reference 3 6 2 3 6 5 Full Scale Output Current 8 66 19 6 31 66 mA Output Compliance Range 1 0 11 0 V Output Resistance 10 MO Gain DAC Monotonicity Guaranteed Settling Time to Within 0 5 LSB 20 ns MAIN DAC TEMPERATURE DRIFT Offset 0 04 100 Reference Voltage 30 REFERENCE Internal Reference Voltage 12 V Output Resistance 5 kQ ANALOG SUPPLY VOLTAGES AVDD33 3 13 3 3 3 47 V CVDD18 1 71 1 8 1 89 V DIGITAL SUPPLY VOLTAGES DVDD18 1 71 1 8 1 89 V IOVDD 1 71 1 8 3 3 3 47 V POWER CONSUMPTION 2x Mode foac 491 52 MSPS IF 10 MHz PLL Off 834 mW 2x Mode foac 491 52 MSPS IF 10 MHz PLL On 913 mW 8x Mode foac 800 MSPS IF 10 MHz PLL Off 1114 1227 mW AVDD33 55 58 mA CVDD18 78 85 mA DVDD18 440 490 mA Power Down Mode 1 5 2 7 mW Power Supply Rejection Ratio AVDD33 0 3 0 3 96 FSR V OPERATING RANGE 40 25 85 C 1 Based on a 10 external resistor Rev 0 Page 4 of 56 DIGITAL SPECIFICATIONS Tmn to Tmax AVDD33 3 3 V IOVDD 3 3 V DVDD18 1 8 V CVDD18 1 8 V Iourrs 20 mA maximum sample rate unless otherwise noted Table 2 Parameter Conditions Min Typ Unit CMOS DATA INPUTS Input Vin Logic High 1 2 V Input Vin Logic Low 0 6 V Maximum Bus Speed 250 MHz SERIAL PORT OUTPUT LOGIC LEVELS Output Vo
97. ulators The DAC output must be level shifted from a 500 mV dc bias to the 1500 mV dc bias Level shifting can be achieved with a purely passive network as shown in Figure 74 In this network the dc bias of the DAC remains at 500 mV while the input to the ADL5375 15 is 1500 mV This passive level shifting network introduces approximately 2 dB of loss in the ac signal AD9125 ADL5375 15 IOUT1P IBBP o R IRO 34800 IOUTIN C IBBN 9 IOUT2N C QBBN TK 34800 IOUT2P 09016 043 Figure 74 Passive Level Shifting Network for Biasing ADL5375 15 REDUCING LO LEAKAGE AND UNWANTED SIDEBANDS Analog quadrature modulators can introduce unwanted signals at the LO frequency due to dc offset voltages in the I and Q baseband inputs as well as feedthrough paths from the LO input to the output The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output This can be done using the auxiliary DACs Register 0x42 Register 0x43 Register 0x46 and Register 0x47 or by using the digital dc offset adjustments Register 0x3C through Register Ox3F The advantage of using the auxiliary DACs is that none of the main DAC dynamic range is used to perform the dc offset adjustment However the disadvantage is that the common mode level of the output signal changes as a function of the auxiliary DAC current The opposite is true when the digital offset adjustment is used Good sideband suppress
98. ur Logic High IOVDD 1 8V 1 4 V IOVDD 2 5 V 1 8 V IOVDD 3 3V 2 0 V Output Vour Logic Low IOVDD 1 8V 0 4 IOVDD 2 5 V 0 4 V IOVDD 3 3 V 0 4 V SERIAL PORT INPUT LOGIC LEVELS Input Vin Logic High IOVDD 1 8V 1 2 V IOVDD 2 5 V 1 6 V IOVDD 3 3V 2 4 V Input Vin Logic Low IOVDD 1 8V 0 6 V IOVDD 2 5 V 0 8 V IOVDD 3 3V 0 8 V DACCLK INPUT DACCLKP DACCLKN Differential Peak to Peak Voltage 100 500 2000 mV Common Mode Voltage Self biased input ac couple 1 25 V Maximum Clock Rate 1000 MHz REFCLK INPUT REFCLKP REFCLKN Differential Peak to Peak Voltage 100 500 2000 mV Common Mode Voltage 1 25 V REFCLKx Frequency PLL Mode 1 GHz lt fvco lt 2 1 GHz 15 625 600 MHz REFCLKx Frequency SYNC Mode See the Multichip Synchronization section for conditions 0 600 MHz SERIAL PERIPHERAL INTERFACE Maximum Clock Rate SCLK 40 MHz Minimum Pulse Width High tewx 12 5 ns Minimum Pulse Width Low tewoi 12 5 ns Setup Time SDI to SCLK tps 1 9 ns Hold Time SDI to SCLK 0 2 ns Data Valid SDO to SCLK tov 2 3 ns Setup Time CS to SCLK 14 ns LATENCY AND POWER UP TIMING SPECIFICATIONS Table 3 Parameter Min Typ Max Unit LATENCY DACCLK Cycles 1x Interpolation with or Without Modulation 64 Cycles 2x Interpolation with or Without Modulation 135 Cycles 4x Interpolation with or Without Modulation 292 Cycles 8x Interpolation with or Without Modulation 608 Cycles Inverse Sinc 20 Cycles Fine Modulation 8 Cycles Powe
99. v 0 Page 48 of 56 09016 050 09016 051 SYNCHRONIZATION WITH DIRECT CLOCKING When directly sourcing the DAC sample rate clock a separate REFCLK input signal is required for synchronization To synchronize devices the DACCLK signal and the REFCLK signal must be distributed with low skew to all of the devices being synchronized If the devices need to be synchronized to a master clock then use the master clock directly for generating the REFCLK input see Figure 83 DATA RATE MODE SYNCHRONIZATION The Procedure for Data Rate Synchronization when Directly Sourcing the DAC Sampling Clock section outlines the steps required to synchronize multiple devices in data rate mode The procedure assumes that the DACCLK and REFCLK signals are applied to all of the devices The procedure must be carried out on each individual device Procedure for Data Rate Synchronization When Directly Sourcing the DAC Sampling Clock To synchronize all devices 1 Configure the device for data rate mode and periodic synchronization by writing 0xCO to the Sync Control 1 register Register 0x10 Additional synchronization options are available and are described in the Additional Synchronization Features section 2 Poll the sync locked bit Register 0x12 Bit 6 to verify that the device is back end synchronized A high level on this bit indicates that the clocks are running with a constant known phase relative to the sync signal 3 Reset the FIFO by

ANALOG DEVICES AD9125 handbook

Contents

Download Pdf Manuals

Related Search

Related Contents