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ANALOG DEVICES ADuC842/ADuC843 user guide

1. Instruction Set Data Transfer Operations Ji move from code memory move to from data memory 2 o Boolean Variable Manipulation s on E clear bit to zero CLR bit SETB C SETB bil set bit to one complement bit ANL C bit AND bit with C ANL C bit AND NOTbit with C ORL C bit OR bit with C ORL C bit OR NOTbit with C MOV C bit ses MOV bitC move bit to bit ACALL addr11 LCALL addr16 call subroutine LIMP adarte Simp re UMP INZ rel ljiumpifAnoto Ads o CINE Rn data rel UTP if not equal Instructions That Affect Flags ADD A x C carry out of bit 7 AC carry out of bit 3 OV carry out of bit 6 but not 7 ADDC A x C carry out of bit 7 AC carry out of bit 3 OV carry out of bit 6 but not 7 SUBB A x C borrow into bit 7 AC borrow into bit 3 OV borrow into bit 6 but not 7 MUL AB C 0 OV result gt 255 C 0 OV divide by zero DIV AB O amp y E p Arithmetic Operations SS PL add source to A ADDC Airea 009 Win cary 77 g y subtract from A with borrow NC direct increment NC DPTR DEC A DEC Rn gt decrement 2 i 2 2 MUL_AB______ multiplyAbyB 1 9 DV_AB_____ divideAbyB_ 1 9 INC DPTR increments the 24bit value DPP DPH DPL AAA clcElc w ol 5 wo wo wo P gt gt 2 z o lu gt 21 N g SUBB A data 2 2 Z A Rn NC Ri Z Z Z O m O e a a m O e g a
2. DPCON Data Pointer Control register general purpose flag 1 A F1 mnemonic SPR1 SPRO SPICON mnemonic DPCON 6 data pointer auto toggle enable O disable P parity of ACC DPCON 5 hadow dat int de control bit aqdaress F9h 0 F8h 0 reset value DPCON 4 Pi b0s2 2 post inc 3 post dec 4 LSBtgl DPP Pen Palmer Page a F8h 04h DPCON 3 main data pointer mode control bits lower RAM SFR details t dd DPCON 2 1 8052 2 post inc 3 post dec 4 LSBtgl DPH DPL DPTR Data Pointer details reset value adaress DPCON 1 not implemented to allow INC DPCON toggling DPCON O data pointer select O main 1 shadow ACC Accumulator calibration coefficients are preconfigured at power up to factory calibrated values T3CON Timer 3 Control register B auxiliary math register T3CON 7 Timer 3 baud rate enable O disable T3CON 2 binary divide factor DIV T3CON 1 DIV log Fcore 16 baudrate log2 T3CON O rounded down
3. Logical Operations ANL A Rn ANL A Ri ANL A direct f ANL A data logical AND ANL direct A ANL direct data ORL A Rn ORL A Ri ORL A direct ORL A data logical oR ORL direct A ORL direct data XRL A Rn XRL A R i XRL A direct logical XOR XRL direct A DA A C C or x gt 100 RRC A C ACC 7 RLC A C ACC 0 SETB C C 1 CLR C C 0 ANL C bit C C and bit ANL C bit C C and NOTbit ORL C bit C C orbit ORL C bit C CorNOTbit MOV C bit C bit CJNE x y rel C x lt y Pin Functions L g YV F e lazajacno TT ow t a o CIS sfx COC 21 23 21 DGND NTODODROWTONT Oo DOLINA ASIS VQ0OFANT ODOR DIJON DOLINA AA O lt pin 1 identifier O lt pin 1 identifier ADuC842 52pin MQFP i bD ADuC842 q 56pin CSP 4 bD O i TOP VIEW not to scale TOP VIEW not to scale RON2O000JXDNIAUN NWWWWWKWWWHWWLhARL OSOSBNWATANBDOOSND SCOONOUORWN dadas ON DONVDROT NNA YN ONO were NANNANANNANN TNORAODMDOrAMTNO Tee TT TH NNNANNANNAN K Q Code Memory Space Options NOP instructions internal code space 62K bytes Flash EE FFFFh NOP instructions 8000h 7FFFh NOP instructions internal code space 32K bytes Flash EE internal code space 8K bytes Flash EE Interrupt Vector Addresses WDS WatchDog Timer Interrupt 5Bh 2 External Interrupt 1 MEET 6 Timer1 Overflow Interrupt ISPI 12C1
4. IZCADD3 TI transmit interrupt flag R6 direct or IC secondary slave Address registers RI receive interrupt flag rs o indirect 1 JOu 2 lt 2 a N Had o 2 lu 2 z I2CDAT FC Data register SBUF Serial port Buffer register rs g os o e WO 118 lle Ia AA a i fad gt PCON Power Control register ressin R4 o 00h add ess 9 S i E Q ip 5 Q ip lt 5 x lt iu e a ig 5 lt i ka p lt E eo E PWMCON PWM Control register PCON 7 double baud rate control TE a w O a O O m ca LW x lt WwW o Lo S PWMCON 7 disable P2 6 P3 4 PWM output O enable PCON 4 ALE disable O normal 1 forces ALE high 5 A E a a PEON general purpose fag se a DVI It Ctwin It Aqua 5 gt PCON 2 general purpose flag A _ aa Sl o E i E e949 gt gt a 2 PWMCON 4 5 dual 8bit 6 dual 1 6bitRZ 7 reserved PCON 1 power down control bit recoverable with hard reset oO UN A O gt N W a x S iL at loreto N 11 4 16 64 PCON O_ idle mode control recoverable with enabled interrupt x n FS C Q cO c E e E e Z W cilo IE ES PWMCON 1 PWM clock source bits O FxTAL 15 1 FxTAL PSW Program Status Word e e TT Y at 5 5 5 T 5 be E 5 5 PWMCON O 2 TO ext int rate 3 Fvco 16 777MHz2 CY carry flag i AC auxiliary carry flag Ro PWMOH PWMOL PvWMO data registers Ed erat edo ee A RS1 i bank l bi these bits are contained in this byte PWM1H PWM1L PwM1 data registers RSO a9 Sotva register bank 01 2 3 E A OV overflow flag
5. data stop external interrupt 1 R4 a FFh D E E CFG842 0 1 CFG842 0 0 LL Ll Ww Ww Q Q Lu O O a faa x x D o 00 12CM master mode select bit O slave mode external interrupt O I2CRS serial port reset serial port transmit data line g 128 bytes SFRs o olle e o gt o o X o 5 o o o e A N ee Ear del Statis O RX 1 TX serial port receive data line serial interface interru 2 Upper RAM intemal extemal Oa Z T 3 wi Nm o 17 zZ 2 e SCON Serial communications Control register z i indirect direct data data a O O YN D Y A E uj Ww 104 12CCON PC Control register in master mode EN A 12 addressing os Ella s JOosgl s ESolla 5 g 5 MF 5 E MDO master mode SDATA output bit SM1 00 8bit shift register Fcore 12 addressing only memory memory ra e o la a a a lt 1 gt 3 3 MDE master mode O abl O7disabie 01 8bit UART variable master mode output bi 10 9bit UART Fcore 64 x2 l o olle o o gt o gt My e o o o o o ria mana ma E EE a 11 9bit UART variable O ar master mode select Di slave mode in modes 2 amp 3 enables multiprocessor communication Ro 2K bytes 16M bytes Ly As o l Lu N N g gt I2CADD PC slave Address register receive enable control bit 128 bytes addressable a c O 9 O IIZ E elle i 2 A E in modes 2 amp 3 9th bit transmitted lt lt x x po lt x iS lt lt in modes 2 amp 3 9th bit received lower RAM Q mE IN a 13 O A ray x a A 3 Q A Q 2 Q B Q 2 I2CADD1 I2CADD2
6. e 8 le HTHSEG TIC Elapsed 126th Second Reistoy a Gusher casa verer 18 e a o N Q SEC TIC El ds ds Regist IEO ternal INTO fl uto cleared tor to ISR 12 a c clnc x A lt E H lt lt lt lt lt lt i0 c c ma c c apse econds Register externa ag au o cleared on vector to ITO IEO t O 1 trig 1 ed t Y TA ay i T lt A A 3 3 a a 2 2 L S o Z MIN TIC Elapsed Minutes Register THO TLO ero aa io 18h Ro HOUR TIC Elapsed Hours Register 8 ECON Data Flash EE comand register SOTA TimerT registers 4K bytes 01h READ page 82h PROGRAM byte T2CON Timer2 Control register 1 K pages 02h PROGRAM page OFh EXIT ULOAD mode TF2 overflow flag 04h VERIFY page FOh ENTER ULOAD mode 22 16n Re data gt gt gt o N g o j a e o z E g aa ERASE dd all others reserved COR ol enable O Timer1 used for RxD clk N 14 a N TCLK transmit clock enable 0 Timer1 used for TxD clk x ey a pa ES i a lt lO x c a x lt 2 z Z E EADRH EADRL Data Flash EE address registers EXEN2 external Eat O ignore Naas 1 cap rid on T2EX lt lt lt E lt TR2 run control O stop 1 run o accessible 00 o foe o Q O o Q Q o o 00 o o Cc y fare Ww a a NT2 timer counter select O timer 1 counter a through bs 2 E a 2 2 2 EDATA1 EDATA2 EDATA3 EDATA4 CAP2 capture reload select O reload 1 capture Data Flash EE data registers SFRs Rese e x lt 2 2 gt 2 A A 2 2 e gt a TH2 TL2 Timer2 regist
7. lt lt lt c PLLCON 1 Foore 16 777 216Hz 2 SIDEl s A 5l a S S o lZo ol lt o 5 al PLLCON O TMOD Timer Mode register a o Ta gt 3 io oj 3 3 D Z la lqt oO clue ejaes jas TIMECON Time Interval Counter Control Registe TMOD 3 7 gate control bit O ignore INTx O O E Z lt E 2 O o O gt a O ou TIMECON 6 24 hour mode select 0 0 255hour 1 0 23hour TMOD 2 6 counter timer select bit O timer 30 1Eh oO oO a Oo o O LU A a TMOD 1 5 timer mode selecton bits s lt x O 17 7 O a o o rf Ww S m O N TIMEGON ADEN Ed ais Saent di penis TMOD 0 4 13bitT 16bitT C SbitT Creload 2x8bitT 29 1Dh R5 x 11 a 5 a 2 2 Q 5 e 2 2 5 ou 5 5 N 5 S TIMECON 3 single time interval control bit O reload restart upper nibble Timer lower nibble Timer0 c Flash EE XRAM ri E qa a a lt H lt o o 00 00 TIMECON 2 time interval interrupt bit TI TCON Timer Control register d t t d d RAM TIMECON 1_ time interval enable bit O0 disable amp clear o E ata space extende spare zl slo s slusl sl_sl_sl sl sl sl l sl TIMECON O tine cock enable bit Onsieable w o Seeman venta Y o O o o o o o o LL LL o LL LL PM o CA A zZ o o Z o o Z o olzoa Z o LL o LL o LL o LL INTVAL TIC Interval Register TFO TimerO overflow flag auto cleared on vector to ISR 27 D O O O O Z Z TRO TimerO run control O off 1 run 0 O i 1Ah aFEn page 1023 FFFFFFh S je 8 3 8 8 9 S fe Je lu Ja 8
8. DCCONS 3 this bit must contain zero z gt z lt m lt c ic x x c ADCCON3 1 cal type select O offset 1 gain PSMCON 6 PSM status bit 1 normal O fault Tt o gt o E o gt o e o gt ADCCONS O start calibration bit cleared by hardware PSMCON 5 PSM interrupt bit O O g S g N g D g 5 a i g ADCDATAH ADC Data registers PSMCON 3 reserved 3 08V 2 93V reserved sS aa E E aa E Ea NIE T ea fa D D xl o lt 2 F lt c 2 c lt E PSM d trol 1 0n O off soles E E EE 2 lus EL F 8 ale DMAP DMAH DMAL DMA address poner ES i power conte eon o O 00 ADCGAINH ADC Gain 5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h 58h clZec c c c c c c c A e Le SPH Stack Pointer High byte z So 2Sl o ol S rSels o o o ADCGAINL calibration coefficients o o O O O o o O o o O o O O o o smn on esn san son san sth son 28 3 3 3 49 4 9 38389 8 q 3 lele En eter 57h O S S z z i z E gt z Z e 2 e ADCOFSH ae Offset f enable interrupts O all interrupts disabled i calibration coefficients enable ADCI ADC interrupt Bit Addressable ARAE S GEEA 2 8 3 Pel coran cracls AOS cra Shertow iterup i E ble RI TI ial rt int t east eal 5 Eligis sE El gg horcom orcos sl el DACCON 7 ModeSelect 0 12bit 1 8bit enable IE1 external interrupt 1 DACCON 6 DAC1 RangeSelect 0 VreF 1 VDD enable TFO TimerO overflow interrupt 5 Z 5 5 I 5 JJ 5 a is 5 5 DACCON 5 DACO RangeS
9. SPI I C Interrupt 3Bh 8 RI TI UART Interrupt 23h 9 TF2 EXF2 Timer2 Interrupt TIMECON 2 Time Interval Counter Interrupt O 2003 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective companies Purchase of licensed C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips IC Patent Rights to use these components in an I C system provided that the system conforms to the IC Standard Specification as defined by Philips Printed in the U S A G03602 4 12 03 0 ANALOG DEVICES Vw analog com microconverter FUNCTIONAL BLOCK DIAGRAM hardware REV 0 ADuC842 843 MicroConverter Quick Reference Guide PWM1 T1 CONVST 3 4 5 ADuC842 ADuC843 DACs on ADuC842 only ADC control DAC amp control calibration 4K x 8 data Flash EE 62K x 8 program counter Flash EE timers baudrate timer downloader debugger asynchronous serial port UART bandgap reference power supply monitor MEA counter synchronous serial interfaces SPI amp 1C single pin emulator N pin numbers refer to MQFP package A Precision Analog Flash MCU The ADuC842 ADuC843 is ADC 12bit 5us 8channel self calibrating 0 5LSB INL amp 70dB SNR DAC AbDuC842 only dual 12bit 15us voltage output lt 1LSB DNL F
10. creas this biemust contain 0 S S aR 0 V Lower RAM G Q O O C QO lt Q 00 O 5 5 lt interrupt flag a this bit must contain 0 Ow YN E gt pal ny wu O DMA DMA mode enable CFG842 2 this bit must contain O EN D o A O 9 cllc 2 lt O c 9 pu A 3 O Ps o CCONV continuous conversion enable bit CFG842 1 select SPI pins O default 1 P3 3 P3 4 P3 5 oD XS NSIC E aula W N W W0nm OQK E SCONV single conversion start bit CFG842 0 internal XRAM select O external XRAM Sa T E u cu a E 2 a 3 CS2 Ju poe ADE WDCON Watchdog Timer control register c c c c c CS1 8 temperature sensor PRE3 watchdog timeout selection bits a S S D J olmo E Z o JJ oO zZ oO CSO 9 DACO A DAC1 B AGND C VREF PRE2 0 7 15 6 31 2 62 5 125 250 500 1000 2000 ms o o o o o PRE1 8 0ms immediate reset General Purpose A B 2 E 0 o g 0 E Y lt p a lt x O A E oO ADCCON3 ADC Control register 3 PREO gt 8 reserved m o o D D 5 z D 5 D Q lt 5 S a O 5 D a ADCCON3 7 busy indicator flag O ADC not active WDIR watchdog interrupt response bit laa ADCCON3 6 this bit must contain zero WDS watchdog status flag 1 indicates watchdog timeout n bit addresses dp ES 8 8 8 o D 2 lt c A lt 2 c Zc Ne c 2 8 ip ADCCON3 5 number of averages selection bits WDE watchdog enable control O disabled i 06 30 E t S Ww H gt a r Q Ww gt E ADCCON3 4 15 1 31 63 WDWR watchdog write enable bit set to enable write O A
11. elect 0 Vrer 1 VDD enable IEO external interrupt 0 5 5 O gej gej TO N o O O o O o nj o o DACCON 4 Clear DAC1 O OV 1 normal operation Int tE ble Priorit ist 2 EEE n E EE EEEF E come erp airy a O 0 o o o s lt x o o o LW lt x lt x mm Qa DACCON 2 SynchronousUpdate 1 asynchronous IEIP2 6 priority of TII interrupt time interval DACCON 1 PowerDown DAC1 O off 1 0n IEIP2 5 priority of PSMI interrupt power supply monitor lt x c D D D Q lt O lt D D lt D Y cx Q lt O F cx a DACCON O PowerDown DACO 0 off 1 0n IEIP2 4 priority of ISPI interrupt serial interface A lt E Qa i N c Ae h mAs oma mM gt N i mi N mM ive DAC1H DACIL DAC1 dat ist IEIP2 3 this bit must contain zero 3 IEIP2 1 enable PSMI power supply monitor interrupt JFE lt 8 8 38 02 Sle g8 8 88 5 8 A iP Interrupt Priority register IS Nan BD O olijolaqec oa O Ts 7 olEs as o o PLLCON PLL Control register Interrupt Priority register o o gt D D ES D o D Lu lt g ath O 18 E E E 2 8 Ed 2 Be E EM E A EA lt x O e e 5 x T e z 2 L O o E a CONE his pas o flag a of lock Priority of RI TI serial port interrupt il C E eee ere eee ee iority of TF1 Timer1 rflow interrupt lt N O lt NIZ lt q O AN IN lt X NaA xt N PLLCON 3 fast interrupt ie priority of IE1 external interrupt 1 pt control bit O normal A E A sa Pom oan een oe oan oan om oon A O a a E Rae AES ac lt lt lt lt
12. er i i 2 o Lge a x 5 O in 2 SPICON SPI Control register RCAP2H RCAP2L Timer2 Reload Capture o OQ VWCOL write collision error flag E x aS Lio iu a a O O O A co 2 x S gt g So SPE SPI enable 0 1 C enable 1 SPI enable PO PortO register also A0 A7 amp DO D7 000h SPIM master mode select O slave a a lt ejje o o o o o o o o o CPOL clock polarity select 0 SCLK idles low P1 Port1 register analog amp digital inputs CPHA clock phase select O leading edge latch timer counter 2 capture reload trigger 16 10h RO p E o EN gt N 2 P 2 U re m SPR1 SPI bitrate select bits i 7 i ba 7FFh a O E c O fe E S g x lt E 5 s E E E SPRO bitrate Fcore 2 4 8 16 slave SPRO SS a e TE 2 A16 A23 15 oFh dEl lssi ellas Pals les Es Mel sesli all ail 8 SPIDAT SPI Data register LL w u W a a oO o sa a lt x lt x o o 0 0 14 OEh M 8 SFRs 12CCON PC Control register in slave mode P3 Ports register e 2 e STING S 2 E ua 2 a j g E o external data memory read strobe qm gt oe o Z o 12CSI slave mode stop interrupt enable bit O disable external data memory write strobe xX O O Ww A E ma E 0 Lu I2CGC slave mode general call status flag timer counter 1 external input c a E c Os Y ie gt lt c ic Ac Z E W lt E ec me 12CID1 slave mode interrupt decode bits timer counter O external input o O ma 5 m 5 m D oO s D m 5 oO 5 a S a S 12CIDO start repeated start
13. lash EEPROM 62K bytes Flash EE program memory 4K bytes Flash EE data memory Microcontroller single cycle 8052 up to 16 8MIPS 32 I O lines programmable PLL clock 131KHz to 16 8MHz from 32KHz crystal Embedded Tools Support on chip download debug amp single pin emulation functions Other on chip features temperature monitor power supply monitor watchdog timer flexible serial interface ports voltage reference time interval counter dual 8 16bit PWM power on reset ANALOG DEVICES ww analog com microconverter ADCCON1 ADC Control register 1 T3FD Timer 3 Fractional Divider register a ADCCON1 7 ADC mode O off 1 on T3FD 2 Fcore baudrate 2 64 ADCCON1 6 t Vref select bit O on chip Vref Data Memory RAM SFRs user Flash EE all read write SFR M A A A a a ap ADCCON1 4 ADCclk 16 777 216Hz 32 4 8 2 p g ADCCON1 3 acquisition time select bits CFG842 CFG843 ADuC84x Confi R ist ADCCON1 2 acq time 1 2 3 4 ADCclk g Register ADCCON1 1 Timer2 convert enable CFG842 7 extended stack pointer enable O disable 5 le 5 Ss s Z ulz gt w Sl lt S lu S 5 Pa pS gt 5 ADCCON1 0__external CONVST enable CFG842 6 PWM pins select 0 P2 6 P2 7 1 P3 4 P3 3 D lt O T D oalo D Cleo o xy ie iS D zo ADCCON2 ADC Control register 2 FEA t ished ste ena Sean re a O fe x E T oo Q o 2 2 O ADCI ADC i fl

ANALOG DEVICES ADuC842/ADuC843 user guide

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