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ANALOG DEVICES AD783 handbook

1. 0 023 0 58 0 014 0 36 gt pe 0 100 2 54 0 070 1 78 BSC 0 030 0 76 8 Pin SOIC R 8 Package 0 198 5 03 F 0 188 4 77 ui 0 158 4 01 0 150 3 81 0 248 6 29 0 224 5 69 le 0 022 0 56 0 050 1 27 Feroa 0 36 0 205 5 21 aa LEN 0 107 2 72 7 ee 0 011 0 275 0 089 2 26 0 015 0 38 0 034 0 86 0 005 0 125 0 007 0 18 0 018 0 46 8 REV A C1733 12 10 92 PRINTED IN U S A
2. 2 REV A AD783 HOLD MODE AC SPECI FICATI ONS Tuin to Tmax With Vec 5 V 5 Ve 5 V 5 C 50 pF unless otherwise noted AD 783 A Parameter Min Typ Max Units TOTAL HARMONIC DISTORTION fiy 100 kHz 85 80 dB fin 500 kHz 72 dB SIGNAL TO NOISE AND DISTORTION fin 100 kHz 77 dB fiy 500 kHz 70 dB INTERMODULATION DISTORTION F1 99 kHz F2 100 kHz Second Order Products 80 dB T hird Order Products 85 dB NOTES fi amplitude 0 dB and fsampLe 300 kH z unless otherwise indicated Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION With Spec Respectto Min Max Units Vcc COM VEE COM Analog Input COM Digital Input M Output Short i Ground Ufc E M akimum Junction NC NO CONNECT T emperature 175 C Storage 65 150 C Lead T emperature 10 sec max 300 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection WARNING Although the AD 783 features proprietary ESD protection circuitry perma
3. 300 OUTPUT NOISE uV rms 3 o 0 1k 10k 100k 1M 10M FREQUENCY Hz Figure 4 RMS Noise vs Input Bandwidth of ADC DRIVING THE ANALOG INPUTS For best performance it is important to drive the AD 783 analog input from a low impedance signal source T his enhances the sampling accuracy by minimizing the analog and digital cross talk Signals which come from higher impedance sources e g over 5 kQ will have a relatively higher level of crosstalk For applications where signals have high source impedance an operational amplifier buffer in front of the AD 783 is required TheAD711 precision BiFET op amp is recommended for these applications HIGH FREQUENCY SAMPLING Aperture jitter and distortion are the primary factors which limit frequency domain performance of a sample and hold amplifier Aperture jitter modulates the phase of the hold command and produces an effective noise on the sampled analog input T he magnitude of the jitter induced noise is directly related to the frequency of the input signal A graph showing the magnitude of the jitter induced error vs frequency of the input signal is given in Figure 5 REV A T he accuracy in sampling high frequency signals is also constrained by the distortion and noise created by the sample and hold T he level of distortion increases with frequency and reduces the effective number of bits of the conversion M
4. C pF unless otherwise noted AD783J A Parameter Min Typ Max Units SAM PLING CHARACTERISTICS Acquisition T ime 5 V Step to 0 0196 250 375 ns 5 V Step to 0 196 200 350 ns Small Signal Bandwidth 15 MHz Full Power Bandwidth 2 MHz HOLD CHARACTERISTICS Effective Aperture D elay 25 C 30 15 30 ns Aperture Jitter 25 C 20 50 ps H old Settling to 1 mV 25 C 150 200 ns Droop Rate 0 02 1 yV us Feedthrough 425 C Vin 2 5 V 500 kH z 80 dB ACCURACY CHARACTERISTICS H old M ode Offset 5 0 5 mv Hold Mode Offset Drift 10 uv C Sample M ode Offset 50 200 mV N onlinearity 10 005 Yo FS Gain Error 0 03 0 1 FS OUTPUT CHARACTERISTICS Output Drive Current 5 5 mA Output Resistance DC 0 3 0 6 Q T otal OutputN oj uV rms Sampled DC uV rms Hold M ode N 5 uV rms Short Circuit Source 20 mA Sink 13 mA INPUT CHARACTERISTICS Input Voltage Range 2 5 12 5 V Bias Current 100 250 nA Input Impedance 10 MQ Input Capacitance 2 pF DIGITAL CHARACTERISTICS Input Voltage L ow 0 8 V Input Voltage High 2 0 V Input Current High Vin 5 V 2 10 pA POWER SUPPLY CHARACTERISTICS Operating Voltage Range 4 75 5 5 25 V Supply Current 9 5 17 mA PSRR 5 V 5 45 65 dB PSRR 5 V 5 45 65 dB Power Consumption 95 175 mW TEMPERATURE RANGE Specified Performance J 0 70 Je A 40 85 C NOTES Specified and tested over an input range of 2 5 V Specifications subject to change without notice
5. easurements of Figures 6 and 7 were made using a 14 bit A D converter with Vin 5 V p p and a sample frequency of 100 kSPS 1 1 2 BIT 8 BS A v2BIT _ 91 10 BIS _ 1 2 BIT 12 BITS 0 01 1 2 BIT 14 BITS Ya ERTURE JITTER TYPICAL 1k 10k 100k 1M FREQUENCY Hz Figure 5 Error Magnitude vs Frequency 100 1k 10k 100k 1M FREQUENCY Hz Figure 6 Total Harmonic Distortion vs Frequency 90 80 S N D dB 30 0 1k 10k 100k 1M FREQUENCY Hz Figure 7 Signal Noise and Distortion vs Frequency AD783 AD783 TO AD6 0 INTERFACE The 15 M Hz small signal bandwidth of the AD 783 makes it a good choice for undersampling applications Figure 8 shows the interface between the AD 783 and the AD 670 ADC where the AD 783 samples the incoming IF signal For this particular application the IF carrier was 10 7 M Hz and the information signal was a 5 kHz FSK modulated tone T he sample and hold signal is applied to the 8 bit AD 670 ADC and then digitally processed for analysis TheCLKIN signal is connected directly to the S H pin of the AD 783 and must comply with the acquisition and settling re quirements of the SHA A delayed version of CLKIN is applied to the R W input of the AD 670 in order to accomm
6. to the nature of the design the SHA output in the sample mode is not intended to provide an accurate representation of the input H owever in hold mode the internal circuitry is reconfigured to produce an accurately held version of the input signal Below is a block diagram of the AD 783 NC NO CONNECT Functional Block Diagram AD783 DYNAMIC PERFORMANCE The AD 783 is compatible with 12 bit A to D converters in terms of both accuracy and speed T he fast acquisition time fast hold settling time and good output drive capability allow the AD 783 to be used with high speed high resolution A to D converters like the AD 671 and AD 7586 T he AD 783 s fast acquisition time provides high throughput rates for multichannel data acquisition systems T ypically the AD 783 can acquire a 5 V step in less than 250 ns Figure 1 shows the settling accuracy as a function of acquisition time 0 08 0 06 0 02 Vour ACQUISITION ACCURACY 96 250 ACQUISITION TIME ns 500 Figure 1 Voy Settling vs Acquisition Time T he hold settling determines the required time after the hold command is given for the output to settle to its final specified accuracy T he typical settling behavior of the AD 783 is 150 ns HOLD MODE OFFSET T he dc accuracy of the AD 783 is determined primarily by the hold mode offset T he hold mode offset refers to the difference between the final held output voltage and the input signal at th
7. ANALOG DEVICES Complete Very High Speed Sample and Hold Amplifier AD783 FEATURES Acquisition Time to 0 01 250 ns Typical Low Power Dissipation 95 mW Low Droop Rate 0 02 V s Fully Specified and Tested Hold Mode Distortion Total Harmonic Distortion 85 dB Aperture J itter 50 ps Maximum Internal Hold Capacitor Self Correcting Architecture 8 Pin Mini Cerdip and SOIC Packages PRODUCT DESCRIPTION The AD 783 is a high speed monolithic sample and hold amplifier SH A T he AD 783 offers a typical acquisition time of 250 ns to 0 01 T he AD 783 is specified and tested for hold mode total harmonic distortion withgi 100 kHz Wh figured and uses a ing hold mode d resfaccure AD 783 is self contained and requires no externa componente or adjustments The AD 783 retains the held value with a droop rate of 0 02 uV us Excellent linearity and hold mode dc and dynamic perfor mance make the AD 783 ideal for high speed 12 and 14 bit analog to digital converters The AD 783 is manufactured on Analog Devices ABCM OS process which merges high performance low noise bipolar circuitry with low power CM OS to provide an accurate high speed low power SHA The grade device is specified for operation from 0 C to 70 C and the A grade from 40 C to 85 C T heJ and A grades are available in 8 pin cerdip and SOIC packages T he military temperature range version is specified for operation from 55 C to 125 C and is ava
8. OUND Figure 3 Basic Grounding and Decoupling Diagram REV A AD783 The AD 783 does not provide separate analog and digital ground leads as is the case with most A to D converters The common pin is the single ground terminal for the device It is the refer ence point for the sampled input voltage and the held output voltage and also the digital ground return path The common pin should be connected to the reference analog ground of the A to D converter with a separate ground lead Since the analog and digital grounds in the AD 783 are connected internally the common pin should also be connected to the digital ground which is usually tied to analog common at the A to D converter Figure 3 illustrates the recommended decoupling and grounding practice NOISE CHARACTERISTICS Designers of data conversion circuits must also consider the effect of noise sources on the accuracy of the data acquisition system A sample and hold amplifier that precedes the A to D converter introduces some noise and represents another source of uncertainty in the conversion process T he noise from the AD 783 is specified as the total output noise which includes both the sampled wideband noise of the SHA in addition to the band limited output noise T he total output noise is the rms sum of the sampled dc uncertainty and the hold mode noise A plot of the total output noise vs the equivalent input bandwidth of the converter being used is given in Figure 4
9. atio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed in decibels Intermodulation Distortion IMD With inputs consisting of sine waves at two frequencies fa and fb any device with nonlinearities will create distortion products of order m n at sum and difference frequency of mfatnfb where m n 0 1 2 3 Intermodulation terms are those for which m or n is not equal to zero For example the second order terms are fa fb and fa fb and the third order terms are 2fa fb 2fa fb fa 2fb and fa 2fb ThelM D products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms T he two signals are of equal amplitude and peak value of their sums is 0 5 dB from full scale The IM D products are normalized to a 0 dB input signal FUNCTIONAL DESCRIPTION T he AD 783 is a complete high speed sample and hold amplifier that provides high speed sampling to 12 bit accuracy ding an on chip onents or adjust ments to perform the sampling fanc Both input and output are treated as a single ended signal referred to common The AD 783 utilizes a proprietary circuit design which includes a self correcting architecture T his sample and hold circuit corrects for internal errors after the hold command has been given by compensating for amplifier gain and offset errors and charge injection errors D ue
10. e T he length of time that the SHA must remain in the sample mode in order to acquire a full scale input step to a given level of accuracy Small Signal Bandwidth T he frequency at which the held output amplitude is 3 dB below the input amplitude under an input condition of a 100 mV p p sine wave Full Power Bandwidth T he frequency at which the held output amplitude is 3 dB below the input amplitude under an input condition of a 5 V p p sine wave Effective Aperture D elay T he difference between the switch delay and the analog delay of the SH A channel A negative number indicates that the analog portion of the overall delay is greater than the switch portion T his effective delay represents the point in time relative to the hold command that the input signal will be sampled Aperture J itter T he variations in aperture delay for successive samples Aperture jitter puts an upper limit on the maximum frequency that can be accurately sampled Hold Settling Time T he time required for the output to settle to within a specified level of accuracy of its final held value after the hold command has been given Droop Rate T he drift in output voltage while in the hold mode Feedthrough T he attenuated version of a changing n signal that appears at the output wh mode Hold voa A and the held output T his offset term applies only in the hold mode and includes the error caused by charge injection and all other i
11. e time the hold command is given T he hold mode offset arises from a voltage error introduced onto the hold capacitor by charge injection of the internal switches T he nominal hold mode offset is specified for a 0 V input condition Over the in put range of 2 5 V to 42 5 V theAD 783 is also characterized for an effective gain error and nonlinearity of the held value as shown in Figure 2 As indicated by the AD 783 specifications the hold mode offset is very stable over temperature Vour HOLD Vin mV 1 Vin VOLTS Figure 2 Hold Mode Offset Gain Error and Nonlinearity For applications where it is important to obtain zero offset the hold mode offset may be nulled externally at the input to the A to D converter Adjustment of the offset may be accom plished through the A to D itself or by an external amplifier with offset nulling capability e g AD 711 T he offset will change less than 0 5 mV over the specified temperature range SUPPLY DECOUPLING AND GROUNDING CONSIDERATIONS ith any high speed h the power i excessive high fr AD transient currents to the device T o achieve the specified accuracy and dynamic performance decoupling capacitors must be placed directly at both the positive and negative supply pins to com mon Ceramic type 0 1 uF capacitors should be connected from Vcc and Veg to common connection DIGITAL P S DIGITAL DATA OUTPUT ANALOG TO DIGITAL CONVERTER SIGNAL GR
12. g clock T he ris ing edge of the sampling clock causes the Q1 output of the flip flop to go low placing the AD 783 into hold mode Simulta neously a low going pulse is generated at the one shot output T he length of this pulse would usually be made long enough to allow the output of the AD 783 to settle hold mode settling time but because of the error correcting ability of the AD 671 the length of this pulse may be reduced to approximately 200 ns T helow going one shot output is connected to the clock input of flip flop2 T he D2 input of flip flop2 is tied high T he rising edge of the low going pulse toggles the 02 output of flip flop2 to a high state T his output which is tied to the EN CODE input of the AD 671 initiates a conversion of the buffered output signal of the AD 783 T he AD 671 issues the signal D AV when the con version is complete T he DAV signal is tied to the asynchronous CLRI and CLR2 inputs of both flip flops When DAV goes low the QI output goes high returning the AD 783 to the sample or acquisition mode T he Q2 output EN CODE returns low until it is again triggered by the rising edge of the one shot output Figure 9 AD783 to AD671 Interface OUTLINE DIMENSIONS Dimensions shown in inches and mm amp Pin Cerdip 0 8 Package LI LI LJ LJ 0 405 10 29 0 320 8 13 Y MAX 0 060 1 52 0 290 7 37 0 200 0 015 0 38 5 08 MAX 4 7 oe 0 015 0 381 G e 0 008 0 204
13. ilable in an 8 pin cerdip package For details refer to the A nalog D evices M ilitary P roducts D atabook or AD 783 883B data sheet Protected by U S Patent Number 4 962 325 REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM NC NO CONNECT PRODUCT HIGHLIGHTS 1 Fast acquisition time 250 ns low aperture jitter 20 ps and fully specified hold mode distortion make the AD 783 an ideal SHA for sampling systems i co droop 0 02 M efr pensated hold Lo small size make the A 783 an ideal choice for a variety of high performance applications 4 The AD 783 requires no external components or adjustments 5 The AD 783 is an excellent choice as a front end SH A for high speed analog to digital converters such as the AD 671 AD 7586 AD674B AD 774B AD 7572 and AD 7672 6 Fully specified and tested hold mode distortion guarantees the performance of the SHA in sampled data systems One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 AD783 SPECIFICATIONS DC SPECIFICATI ONS Tun to Tmax With Vec 5 V 5 Vig 5 V 5
14. nent damage may SRT A occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESDSENSINEDEVICE ORDERING GUIDE Temperature Package Model Range Description Options AD 783JQ 0 C to 70 C 8 Pin Cerdip Q 8 AD 783AQ 40 C to 85 C 8 Pin Cerdip Q 8 AD 783JR 0 C to 70 C 8 Pin SOIC R 8 AD 783AR 40 C to 85 C 8 Pin SOIC R 8 NOTES 1F or details on grade and package offerings screened in accordance with M I L ST D 883 refer to the Analog Devices M ilitary Products D atabook or current AD 783 883B data sheet Q Cerdip R 2 SOIC REV A 3 AD783 Typical Characteristics 10 0 1 0 o E gt ta I R w E 04 E a o tc a 0 01 0 001 1 1 1 1k 10k 100k 1M 0 25 50 75 100 125 150 9 00 9 99 TEMPERATURE C FREQUENCY Hz Power Supply Rejection Ratio vs Frequency Droop Rate vs Temperature Vin O V e e eo 250 BIAS CURRENT nA ACQUISITION TIME ns INPUT STEP V INPUT VOLTAGE V Bias Current vs Input Voltage Acquisition Time to 0 0196 vs Input Step Size 4 REV A AD783 DEFINITIONS OF SPECIFICATIONS Acquisition Tim
15. nternal offsets It is specified for an input of 0 V Sample Mode Offset T he difference between the input and output signals when the SHA is in the sample mode Nonlinearity T he deviation from a straight line on a plot of input vs held output as referenced to a straight line drawn between endpoints over an input range of 2 5 V and 42 5 V Gain Error D eviation from a gain of 1 on the transfer function of input vs held output Power Supply Rejection Ratio A measure of change in the held output voltage for a specified change in the positive or negative supply Sampled DC Uncertainty T he internal rms SHA noise that is sampled onto the hold capacitor Hold Mode Noise T he rms noise at the output of the SHA while in the hold mode specified over a given bandwidth Total Output Noise T he total rms noise that is seen at the output of the SHA while in the hold mode It is the rms summation of the sampled dc uncertainty and the hold mode noise REV A Output Drive Current T he maximum current the SHA can source or sink while maintaining a change in hold mode offset of less than 2 5 mV Signal To Noise and Distortion S N D Ratio S N D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the N yquist frequency including harmonics but excluding dc T he value for S N D is expressed in decibels Total Harmonic Distortion THD THD isthe r
16. odate the hold mode settling requirements of the AD 783 T he 10 us con version speed of the AD 670 combined with the 150 ns hold mode settling time of the AD 783 result in a total system throughput of 10 15 us By keeping the 10 7 M Hz IF input to the AD 783 at alow amplitude 255 mV p p the resultant distortion and jitter induced noise result in approximately 45 dB of dynamic range The AD 670 can be conveniently configured such that its full scale input range is 255 mV in order to retain the full 8 bit dynamic range of the converter T he maximum sample rate of the AD 670 is 10 us therefore to comply with the N yquist criteria the maximum information bandwidth is 50 kHz 10 7MHz 255mV p p Figure 8 AD783 to AD670 Interface AD783to AD 671 12 Bit 500 ns ADC Interface TheAD783 to AD671 interface requires an op amp a dual flip flop and a monostable multivibrator or one shot The op amp amplifies the 2 5 V output of the AD 783 to the full scale input of the AD 671 Appropriate op amps include the AD 841 and AD 845 see the AD 671 data sheet for additional information T he flip flops and one shot are used to generate the AD671 EN CODE pulse and the appropriately timed AD 783 S H pulse A master sampling clock is tied to the clock input of flip flop1 and the input of the one shot T he D1 input of flip flop1 should be tied high and the one shot should be configured to generate a pulse on a rising edge of the samplin

ANALOG DEVICES AD783 handbook

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