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ANALOG DEVICES AD1139 datasheet

1. ANALOG DEVICES High Accuracy 18 Bit Digital to Analog Converter PUIKN FEATURES 18 Bit Resolution Low Nonlinearity Differential 1 2LSB max Integral 1 2LSB max High Stability Differential TC 1ppm C max Integral TC 1 2ppm C max Gain TC with Reference 4ppm C max Fast Settling Full Scale 40ps to 0 00019 LSB Gps to 0 00019 Small Hermetic 32 Lead Triple DIP Package Low Cost APPLICATIONS Automatic Test Equipment Scientific Instrumentation Beam Positioners Digital Audio GENERAL DESCRIPTION The AD1139 is the first DAC ve 18 bit resolution 1 part in 262 144 and true 18 bit accuracy i package Apr accuracy s t or low cost The AD1139 is a complete DAC with precision internal reference latched data inputs and a quality output voltage amplifier The analog output voltage ranges are pin programmable to 5V 10V 5V and x 10V Current output is also provided for use with external amplifiers The internal precision 10V refer ence has a low 3ppm C maximum temperature coefficient and is available for ratiometric applications The AD1139K is a true 18 bit accurate DAC with 1 2LSB maximum differential and integral nonlinearity The differential and integral nonlinearity temperature stability is guaranteed at Ippm C maximum and 1 2ppm C maximum respectively The AD1139 settles to within 1 2LSB at 18 bits 0 00019 in 40ps for a full scale step 10V The glitch energy
2. 1 9 100 Lapis aow 1LSB max 1 2LSB max 0 00038 max 0 00019 max 1LSB max 2LSB max 0 00038 max 0 00019 max 10V 0 1 max 204 V pk pk 10 V pk pk 50u V rms 3ppm C max 400mV 500ns Duration a 0 8V x 3 5V Binary BIN Offset Binary OBN 1mA 0 5mA 5V 10V 5V x 10V 2xFSR 1 x FSR 154V rms 45p V rms 100 amp A x 25mA 30mA Oto 70 C d 40 C to 85 C 450 295 OUTLINE DIMENSIONS Dimensions shown in inches and a SEATING PLANE 0 150 3 81 0 200 5 08 0 015 0 38 0 035 0 89 DOT INDICATES PIN 1 POSITION 0 014 0 36 0 023 0 58 d 1 707 43 41 1 743 144 27 17 0 095 2 41 1 079 27 41 0 105 2 67 i 1 101 27 97 i i 0 192 4 88 0 158 4 01 0 009 0 23 0 012 0 30 0 884 22 45 J 0 916 123 27 WARNING SIGNAL GND BIPOLAR OFFSET DB17 MSB DB16 DB15 NOTES Specifications same as AD 1139 Initial Errors are adjustable to zero via external potentiometers see Figure 1 FSR means Full Scale Range Temperature stability of linearity is guaranteed toa 1 AQL Level I sampling pian per MIL STD 105 See Figure 7 for typical long term linearity stability vs temperature Also sce the BURN IN section on page 6 for caution against preconditioning by the user 5Figure 9 provides ty
3. 329 4700 TWX 710 394 6577 West Coast Atlantic 714 641 9391 215 643 7790 Central 214 231 5094 SPECIFICATIONS pict ic ant rd ie mes ters ctn STS ACCURACY Differential Nonlinearity Integral Nonlinearity Monotonicity 18 Bits Initial Errors Unipolar Gain Error Bipolar Gain Error Offset Error Bipolar Offset Error STABILITY ppm FSR C Differential Nonlinearity Integral Nonlinearity Gain Including Vrer Offset Unipolar Mode Bipolar Mode STABILITY Long Term ppm FSR2 1000 hour Differential Nonlinearity Gain Including VREF Offset Bipolar Offset Reference Output Voltage WARMUP TIME MINIMUM REFERENCE VOLTAGE Vprer Output Voltage 5 mA max Noise BW 0 1 10Hz Noise BW 100kHz Tempco DYNAMIC PERFORMANCE Settling Time to 1 2LSB 18 Bits Voltage Unipolar 10V Step Bipolar 20V Step LSB Step Glitch Energy Major Carry 20MHz Bandwidth 0 to 10V Range DIGITAL INPUTS SV CMOS Compatible Vir Vin Unipolar Code Bipolar Code ANALOG OUTPUT Current Voltage Pin Programmable Noise Includes VREF BW 0 1 10Hz y V pk pk BW 100kHz Unipolar BW 100kHz Bipolar VOLTAGE COMPLIANCE Source Resistance Unipolar Bipolar Source Capacitance POWER SUPPLY REQUIREMENTS 5Vde 5 15V dc 5 POWER SUPPLY REJECTION 15V dc Gain Offset Reference Output 4 5V dc Differential Nonlinearity TEMPERATURE RANGE Operating Rated Performance Storag PRICE
4. be accomplished by two different methods Linearity is first measured at 25 C The DAC is then operated at a fixed elevated temperature for an extended period of time The DAC is then retested at 25 C and the change in linearity error vs time is calculated The ARRHENIUS EQUATION used in reliability calculations can be used to determine what the acceleration factor is from 25 C to the elevated test tem perature Knowing the acceleration factor and the linearity error vs time at the elevated temperature one could calculate the expected long term stability of linearity at nominal temperatures A second test method determines how long it will take for the linearity to shift by a specific error band we chose 2ppm for our example at any specified temperature The first step is to measure the linearity at a moderately elevated temperature e g 85 C and then monitor how long it takes at this temperature to reach the error band limit The second step is to perform the same test at a much higher elevated temperature e g 125 C The two resulting time vs temperature points are then plotted on semilog paper line drawn through the two points allows extrapolation to the length of time expected to reach the error band 2ppm at other temperatures including 25 C 5 Figure 7 shows how long it would take for the AD1139 s linearity to drift 2ppm 1 2LSB at any operating temperature The uppermost plot shows stabilit
5. decodes the address bus and enables each latch including the AD1139 s internal DAC latch to see the appropriate digital word The HCT688 chip and the HCT138 decoder define the I O address space where the four latches will reside In the Figure 6 example they reside in the address space as shown in Table III Data Bits Low Byte DB0 DB7 381H Mid Byte DB8 DB15 High Byte DB16 DB17 AD1139Latch DBO DBI7 Table lil IBM interface Address Locations IBM is a trademark of International Business Machines Corp COMPUTER INTERFACE n ae I CONNECT TO THE PC S 5V SUPPLY BUS PIN D7 A2 D6 A3 D5 A4 D4 A5 D3 A6 D2 A7 Di AS Do A9 AEN A11 NOTE CONNECT TO THE AD1139 S 5V SUPPLY 45V 15V 15V 5V AD1139 THE PC S 4 5V dc LOGIC SUPPLIES SHOULD BE KEPT SEPARATE FROM THE AD1139 5V dc SUPPLY TO KEEP LOGIC INDUCED NOISE TO A MINIMUM Figure 6 AD1139 to IBM PC Compatible Interface LONG TERM STABILITY VS TEMPERATURE Adjusting the linearity of any DAC after it is installed in the application is often difficult or impossible It is preferable to maintain some specified accuracy over the useful working life of the product commonly 5 to 10 years Stable linearity performance over time can therefore be a very important parameter for the DAC Accelerated testing to determine the expected linearity stability over time can
6. a biolar output of 0 5mA Output voltage ranges 5V 10V 5V and 10V are available at 4 Adjust the gain potentiometer until plus full scale output is Pin 7 by connecting the current output Pin 3 to the amplifier obtained see Table I for exact value input Pin 4 and the appropriate internal feedback resistors to the amplifier output Pin 7 as shown in Figure 1 3 Apply a digital input of all 1s 2 reser cam TRIM T Tablel Full Scale and Offset Calibration Voltages JU en9 four REF OUT nr GROUNO 4 1 ame m 5 20V SPAN VOLTAGE Bo iirin 45V D 5v OUTPUT Bo som our POWER d Teri Data Setup Time 1 SIGNAL GNO 7 POWER tpH Data Hold Time 120ns min EV EIS RAN Write Pulse Width 26 CMOS jun O apis 1 oon Table Il Timing Requirements 0812 13 14 oen 10V OPERATION ML RESISTORS ARE METAL PLM RIES OR EQUIVALENT TIMING DIAGRAM amp LATCH CONTROL Timing requirements for the AD1139 are shown in Table II The timing diagram is shown in Figure 2 The WRite line controls an 18 bit wide data input latch This latch is transparent when the WRite line is LOW allowing all bits to be accessed directly When the WRite line is activated HIGH the data present at the inputs is held in the latch and the appropriate analog voltage is seen at the output E 4 ton bs GROUND 5V OPERATION ALL OTHER PIN CONNECTIONS ARE THE SAME AS SHOWN fa es FOR UNIPOLAR 0 TO 10V OPERATION WR F
7. igure 1 Output Voltage and Trim Configuration Figure 2 AD1139 Timing Diagram GROUNDING amp GUARDING The current from measurement ground Pin 1 is small and independent of the digital input code to the DAC This greatly simplifies making error free analog measurements Connect this high quality ground to the system s or application s high quality ground Connect the DAC s power ground Pin 27 to the system return also connect the system s high quality ground to the system return It is most important that the measurement ground Pin 1 and power ground Pin 27 be connected externally for proper circuit operation The current output pin Ioyr Pin 3 is sensitive to external noise sources such as digital input lines This pin and any components connected to this pin should be surrounded by a grounded guard as shown in Figure 3 YP ni fT v a PIN2 7 PIN3 INTERNAL AMPLIFIER BIPOLAR RANGE EXTERNAL AMPLIFIER UNIPOLAR RANGE Figure 3 Guarding Recommendations REMOTE SEN The AD1139 s loads or long cables wi gal By sensing at the load as described in Figure 4 the load current will pass through the amplifier s output and the power ground but not through the sense lines The potential gain errors that would be induced by this load current are therefore minimized The load should not exceed 10mA or 2 nanofarads to insure proper operation of the AD1139 s internal output amplifier Figure 4 Remote Sens
8. ing RATIOMETRIC DAC TESTING APPLICATION The AD1139 s highly stable reference output can be conveniently used in the testing of other high resolution DACs Figure 5 describes how the REF OUT Pin 31 is used as the external reference input to a device under test The gain of the device under test will now accurately track the AD1139 s gain and eliminate reference contribution to gain error When used as a reference DAC to test the integral and differential linearity of 14 and 16 bit DACs the AD1139 provides a meas urement capability with just 1 16LSB of uncertainty at 14 bits Gain and offset errors of the device under test D U T may be accounted for in software Once zeroed the integral linearity error can be measured as the difference between the reference DAC AD1139 and the D U T as seen at the digital voltmeter The differential linearity error is then determined by incrementing or decrementing the D U T digital input by 1LSB and comparing the new output at the DVM with the previous output The difference between these two measurements should be exactly one ideal LSB The amount of disagreement from one ideal LSB is the differential linearity error Figure 5 Ratiometric DAC Testing IBM PC INTERFACE Figure 6 illustrates a typical IBM personal computer interface which uses three 8 bit external latches and two decoder chips The three HCT374 latches are connected to the data bus DO through D7 The HCT138 decoder chip
9. is a low 400mV x 500ns for a major carry and wideband output noise is only 154 V The AD1139 operates from 15V dc and 5V dc power supplies Digital inputs are 5V CMOS compatible with binary input coding for unipolar output ranges and offset binary coding for bipolar ranges Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implica tion or otherwise under any patent or patent rights of Analog Devices PRODUCT HIGHLIGHTS 1 Eighteen bit resolution with 1 2LSB maximum differential and integral nonlinearity in a hermetic 32 lead triple DIP package 2 EEA DAC with inte able low noise out ence output and ble output voltage 3 Temperature compensated internal precision reference with 0 1 maximum initial accuracy and 3ppm C maximum tempco 4 Four pin programmable output voltage ranges 5V 10V x SV 10V and current output available 1mA t 0 5mA 5 The 18 bit parallel input latch assists in microprocessor interface 6 Accurate measurements of the DAC s output are unusually simple since the AD1139 does not suffer from code dependent ground current errors 7 True analog output remote sense capability One Technology Way P O Box 9106 Norwood MA 02062 9106 Tel 617
10. ll scale step Other amplifiers may be chosen for differing tradeoffs The noise gain seen by the output amplifier depends on the output voltage range selected see Table IV The amplifier selected must be stable at the noise gain corresponding to the output range RROR BAND ERROR VS FINAL VALUE O 15V O Vour D 15V O MEASUREMENT GROUND am Figure 8 External Amplifier for High Speed Output Voltage Range Oto 5V Oto 10V 5V 10V 4 Uu bh TablelV Noise Gain vs Output Voltage Range SETTLING TIME The LSB step and full scale step typical settling times to within 1 2LSB at 18 bits are shown in the Specification Table Figure 9 graphically presents the typical settling times to within LSB at resolutions from 12 to 18bi AN AI NCC 1 LLLI 1 L aise RE DR NUS SERRE RAD RR Pe K FULL SCALE RANGE STEP TWoppe a X1 r 1 cH Beer E iu 1004s 10ps PT SETTLING TIME NOTE LSB SETTLING TIMES SHOWN WILL ONLY BE ACHIEVED WITH CLAMPING DIODES FROM THE DAC S AMP IN PIN 4 TO GROUND PER FIGURE 1 Figure 9 Settling Time vs Resolution
11. pical LSB and full ecale settling time to within l 2LSB at 12 to 18 bit resolutions Current Output Operation is structured for input to the summniag junction of an amplifier Specifications subject to change without notice OFFSET amp GAIN CALIBRATION GAIN TRIM Initial offset and gain errors can be adjusted to zero by poten tiometers as shown in Figure 1 The offset adjust range is plus 0 03 to minus 0 02 of full scale range wiper of potentiometer to REF OUT equals plus 0 0396 The gain adjust range is plus 0 06 to minus 0 08 of full scale range wiper to REF OUT equals plus 0 0696 Measurement instruments used should be capable of resolving lj V at plus full scale for the chosen output range and within lV of zero INVERTER x 1 2 Procedure UNIPOLAR MODE 1 Apply a digital input of all Os 2 Adjust the offset potentiometer until a 0 000000V output is obtained 3 Apply a digital input of all 1s 4 Adjust the gain potentiometer until plus full scale output is AD1139 Functional Block Diagram obtained see Table I for exact value BIPOLAR MODE ANALOG OUTPUT RANGE l Apply a digital input of 100 000 The AD1139 is pin programmable to provide a variety of analog 2 Adjust the offset potentiometer until a 0 000000V output is outputs either current or voltage A unipolar output current of obtained 0 to 1m is available at Pin 3 and can be offset by 0 5mA connect Pin 2 to Pin 3 for
12. y under storage conditions no power and the lower plot shows the AD1139 s operating stability under power The operating vs storage difference is due to the 10 C temperature rise when the AD1139 is powered ONES eS SORCNERHI 8 760 M 1 YEAR x ME SE STORAGE NO POWER APPLIED ii NSE ERES 720 a ee PORES GREN Ga PETI ONA 1 MONTH M n TIME hours mE 10 20 30 40 SO 60 70 80 90 100 110 120 130 TEMPERATURE degrees EXPECTED TIME REQUIRED TO PRODUCE A 2ppm LINEARITY SHIFT VS TEST TEMPERATURE NOTE MAX OPERATING TEMPER BURN IN Alt AD1139s undergo a 168 hour powered burn in 125 C prior to laser trimming This burn in produces the optimum stability for the resistor network and eliminates infancy defects As shown in Figure 7 exposure to elevated temperatures produces an acceleration of the normal aging process Preconditioning burn in employed by the user will lead to premature linearity shifts outside of the initial guaranteed specifications The ADI warranty will not cover DACs that exhibit this type of forced premature specification degradation EXTERNAL AMPLIFIER FOR HIGH SPEED OR HIGH OUTPUT CURRENT The AD1139 s internal output amplifier is optimized for very low noise dc stable applications with moderate settling time Applications requiring higher speed or more output current can use an external amplifier such as shown in Figure 8 The AD711 settles to within 16 bits in only 6ps for a unipolar fu

ANALOG DEVICES AD1139 datasheet

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