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ANALOG DEVICES AD7543 handbook

1. require the addition of only an output operational amplifier and a voltage or current reference The simplified D A circuit is shown in Figure 1 An inverted R 2R ladder structure is used that is the binarily weighted currents are switched between the OUT1 and OUT2 bus lines thus maintaining a constant current in each ladder leg indepen dent of the switch state 2R OUT2 OUT1 RFB l DAC REGISTER B Figure 1 AD7543 Functional Diagram One of the current switches is shown in Figure 2 The input resistance at Vprrp Figure 2 is always equal to RLpR Rupr is the R 2R ladder characteristic resistance and is equal to value R The reference terminal can be driven by a reference voltage or a reference current ac or dc of positive or negative polarity If a current source is used a low temperature coefficient external Rpg is recommended to define scale factor TO LADDER FROM INTERFACE LOGIC OUT2 OUT Figure 2 N Channel Current Steering Switch EQUIV ALENT CIRCUIT ANALYSIS The equivalent circuits for all digital inputs LOW and all digital inputs HIGH are shown in Figures 3 and 4 In Figure 3 with all digital inputs LOW the reference current is switched to OUT2 The current source ILEAKAGE is composed of sur face and junction leakages to the substrate while the 1 4096 current source represents a constant 1 least significant bit cur rent drain through the termination resistor on the R 2R ladder
2. 3 05 05 DATA 8 ee 0 065 1 66 0 02 ve A 2 67 0 008 0 203 0 046 115 0 015 0 38 0 095 2 42 LEAD NO 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42 16 Pin Ceramic DIP D 16 Package FROM SYSTEM RESET 0 3 0 62 Figure 9 AD7543 8085 Interface oa oar LABEL MNEMONIC OPERAND COMMENT ai Goss diuo MVI B 05 Shift Data Up to 0 77 19 56 0 06 0 53 LOOP CALL SHIFT Most Significant DCR B Segment of HL with JNZ LOOP MSB as Carry j MVI B OC 0 012 0 305 LUP I 0 008 0 203 R SI ST 8 a 5 2 CALL SHIFT Get Next Bit into to Carty 1 LEAD NO 1 IDENTIFIED BY DOT OR NOTCH DCR B 2 LEADS WILL BE EITHER GOLD OR TIN PLATED IN ACCORDANCE WITH MIL M 38510 REQUIREMENTS JNZ LUP Go Back if Not Finished STA A000 Load DAC Register of AD7543 E 20A P ackage RET Return to Main Program 20 Pin Leadless Ceramic Chip Carrier ag SHIFT MOV A L Shift H and L Left ome z boig RAL One Place and EE 03805008 0 040 x 45 7 je fay oop SA gt 1 02 x 45 MOV LA Leave Uppermost Bit i REF 3 PLCS MOV A H of H in Carry jt RETRETO RAL TF 0 635 0 075 MOV H A RET Table VI Sample Routine for AD7543 8085 Interface 0 020 x 45 d 0 51 45 BONDING DIAGRAM Be 0an 0 096 2 438 Outes outi Bre 20 Pin Plastic Leaded Chip Carrier P 20A Package AGND 0 173 0 008 4 385 0 185 0 390 0 005 co 9 905 0 125 0 105 0 015 2 665 0 375 0 383 0 003 8 966 0 076 SQ foe M
3. NO CONNECT NC NO CONNECT REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its usex No license is granted by implica tion or otherwise under any patent or patent rights of Analog Devices Oo NC NOCONNECT One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 Twx 710 394 6577 Telex 924491 Cable ANALOG NORWOODMASS AD7543 SPECIFICATIONS Von 5V Veer 10V Vouri Vour2 OV unless otherwise noted Limit At Limit At Limit At Ta 40 C Ta 55 C Parameter Ta 25 C 10 485 C amp 4125 C Units Conditions Comments ACCURACY Resolution 12 12 12 Bits Relative Accuracy J A S Versions ti 41 1 LSB max K B T Versions 21 2 41 2 t1 2 LSB max GK GB GT Versions 41 2 1 2 1 2 LSB max Differential Nonlinearity J A S Versions 2 t2 2 LSB max Monotonic to 11 bits from Tmin to Tmax K B T Versions ti 1 1 LSB max Monotonic to 12 bits from Tmin to Tmax GK GB GT Versions 1 41 LSB max Monotonic to 12 bits from Tmin t0 Tmax Gain Error J K A B S T 412 3 413 5 414 5 LSB max Using internal RFB only gain error can be GK GB GT 1 1 2 LSB max trimmed to zero using circuits of Figures 6 amp 7 Gain Temperature Coeffic
4. 1 GENERAL GROUND MANAGEMENT Voltage differen ces between the AD7543 AGND and DGND cause loss of accuracy dc voltage difference between the grounds intro duces gain error AC or transient voltages between the grounds cause noise injection into the analog output The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7543 In more complex systems where the AGND DGND connection is on the back plane it is recommended that diodes be connected back to back between the AD7543 AGND and DGND pins to prevent possible device damage 2 OUTPUT AMPLIFIER OFFSET CMOS DACs exhibit a code dependent output resistance which in turn causes a code dependent amplifier noise gain The effect is a differ ential nonlinearity term at the amplifier output which de pends on Vos Vos is amplifier input offset voltage This differential nonlinearity term adds to the R 2R differential nonlinearity To maintain monotonic operation it is rec ommended that amplifier Vos be no greater than 10 of the DAC s output resolution over the temperature range of interest output resolution Vggp 2 where n is the number of bits exercised REV B AD7543 3 HIGH FREQUENCY CONSIDERATIONS AD7543 out put capacitance works in conjunction with the amplifier feedback resistance to add a pole to the open loop response This not only reduces closed loop bandwidth but can also cause ringing or oscillat
5. N 16 Digital Input Voltage to DGND 0 3V Voo 0 3V AD7543JP 40 Cto 85 C ILSB 12 3LSB P 20A ve Ten AGND orb insite 0 3V Vopn to a AD7543KP 40 Cto 85 C 1 2LSB 12 3LSB P 20A Vow ia RONDo choc A ct ee ne e2sy AD7543GKP 40 Cto 85 C 1 2LSB 1LSB P 20A ee OR aR ae ee AD7543JR 40 Cto 85 C ILSB 12 3LSB R l6 ower Dissipation Package AD7543KR 40 Cto 85 C 1 2LSB 12 3LSB R 16 pane AD7543GKR 40 Cto 85 C 1 2LSB ILSB R l6 By eee al EE EA 670mW AD7543AQ 40 C to 85 C ILSB 12 3LSB Q 16 Derates above 70 C by 0 8 3mW C AD7543BQ 40 Cto 85 C 1 2LSB 12 3LSB Q l6 Cerdip AD7543GBQ 40 Cto 85 C 1 2LSB ILSB Q 16 LOFI Cs pipe piah Ba gaua SEs 450mW AD7543S5Q 55 Cto 125 C ILSB 12 3LSB Q l6 Deran aboye TITE Beali Ratia ay 8 6mWC AD7543TQ 55 Cto 125 C 1 2LSB 12 3LSB Q 16 Operating Temperature Range AD7543GTQ 55 Cto 125 C 1 2LSB ILSB Q 16 Commercial J K GK Versions 40 C to 85 C AD7543SE 55 Cto 125 C ILSB 12 3LSB E 20A Industrial A B GB Versions 40 C to 85 C AD7543TE 9 55 Cto 125 C 1 2LSB 12 3LSB E 20A Extended S Tp Versions Eii 55 C to 125 C AD 7543GTE 55 Cto 125 C 1 2LSB ILSB E 20A 65 C to 150 C 300 C Storage Temperature Lead Temperature Soldering 10secs E Leadless Ceramic Chip Carrier LCCC N Plastic DIP P Plastic Leaded Stresses above those li
6. Timing Diagram INTERFACE LOGIC INFORMATION Shown in the AD8543 Functional Diagram Register A is a 12 bit shift register Serial data appearing at pin SR1 is clocked into the shift register on the leading rising edge of STB1 STB2 or STB4 or on the leading falling edge of STB3 Table II defines the various logic states required on the Register A control inputs while Figure 5 illustrates the Register A loading sequence Once Register A is full the data is transferred to Register B by bringing LD1 and LD2 momentarily LOW Register B can be asynchronously reset to 0000 0000 0000 by bringing CLR momentarily LOW This allows the DAC output voltage to be set to a known condition thus simplify ing system initialization procedure When operating the AD7543 in the unipolar circuit of Figure 6 a CLEAR causes the DAC output voltage to equal OV When using the bipolar circuit of Figure 7 a CLEAR causes the DAC output to equal VREF REV B APPLYING THE AD7543 UNIPOLAR BINARY OPERATION 2 QUADRANT MULTIPLICATION Figure 6 shows the analog circuit connections required for uni polar binary 2 quadrant multiplication operation The logic inputs are omitted for clarity With a dc reference voltage or current positive or negative polarity applied at pin 15 the circuit is a unipolar D A converter With an ac reference volt age or current again of or polarity the circuit provides 2 quadrant multiplication digitally controlle
7. 60 160 ns min Hold Tii STB3 used as a strobe tpH2 60 120 120 ns min is STB2 used as a strobe tsRI 80 160 160 ns min SRI data pulse width tSTB1 80 160 160 ns min STB1 pulse width tsTB4 100 200 200 ns min STB4 pulse width tstB3 100 200 200 ns min STB3 pulse width IsTB2 80 160 160 ns min STB2 pulse width tELD1 gt LD2 150 300 300 ns min Load pulse width TASB 0 0 0 ns min Min time between strobing LSB into Register A and loading Register B tcCLR 200 400 400 ns min CLR pulse width a aaaea POWER SUPPLY Vpp Supply Voltage 45 5 Ipp Supply Current 2 5 2 5 5 2 5 Digital Inputs Vinu or VINL NOTES Temperature ranges as follows JN KN GKN Version 40 C to 85 C AQ BQ GBQ Versions 40 C to 85 C SQ TQ GTQ Versions 55 C to 125 C See Terminology on following page Guaranteed but not tested Logic inputs are MOS gates Typical input current 25 C is less than InA Sample tested at 25 C to ensure compliance Specifications subject to change without notice REV B AD7543 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Ta 25 C unless otherwise noted Temperature Relative Gain Package VpptoAGND 000 0V 7V Model Range Accuracy Error Option eee oe ee ee Ve gay AD7543JN 40 Cto 85C ILSB 12 3LSB N 16 DGNDtoAGND 00000 0 ve ear AD7543KN 40 Cto 85 C 1 2LSB 12 3LSB N 16 Hite Boos E a Gut gp Aka nat te et ys Ge DD ee AD7543GKN 40 Cto 85 C 1 2LSB 1LSB
8. ANALOG DEVICES CMOS Serial Input 12 Bit DAC AD7543 FEATURES Resolution 12 Bits Nonlinearity 1 2LSB Tmin to Tmax Low Gain T C 2ppm C typ 5ppm C max Serial Load on Positive or Negative Strobe Asynchronous CLEAR Input for Initialization Full 4 Quadrant Multiplication Low Multiplying Feedthrough 1LSB max 10kHz Requires no Schottky Diode Output Protection Low Power Dissipation 40mW max 5V Supply Small Size Package Low Cost 16 Pin DIP or 20 Terminal Surface Mount GENERAL DESCRIPTION The AD7543 is a precision 12 bit monolithic CMOS multi plying DAC designed for serial interface applications The DAC s logic circuitry consists of a 12 bit serial in parallel out shift register Register A and a 12 bit DAC input register Register B Seri ed in Register A strobe inpu to Register FUNCTIONAL BLOCK DIAGRAM RFB OuT1 VREF 12 BIT ar oja convenr CONVERTER DAC B oe ee Initialization is simplified by the use of the CLR input which provides an asynchronous reset of Register B Packaged in 16 pin DIP and 20 pin LCCC and PLCC the 3 PG typ operation PIN CONFIGURATIONS DIP LCCC PLCC Noe roe a er M gt e N S n 33 ag E 28 E oo 2a gt 3 2 1 20 19 2 It 21 Ieo 13 Voo acno 4 vi oD CLR a AD7543 AD7543 STi L5 AD7543 om TOP VIEW TOP VIEW me nc 6 TOP VIEW NC Not to Scale Not to Scale DGND Not to Scale LD1 DGND STB4 nc 8 STB4 3 wo NC
9. IN STB1 t l gt ae R 0 035 0 01 gt 7 0 89 0 25 LDT a 0 045 0 003 1 143 0 076 T 029 0 003 0 737 0 076 0 020 0 017 0 004 0 51 T 10 432 0101 NC i ale k 0 025 T 0 64 MIN RI ip 0 02 AA ESS 1051 MAX 1 27 0 060 pay PADS ARE 0 004 X 0 004 INCHES 0 102 X 0 102mm MIN 183 TO MINIMIZE ESD HAZARD BOND DGND FIRST 8 REV B C572c 5 5 84 PRINTED IN U S A
10. The ON capacitance of the output N channel switch is 260pF as shown on the OUT2 terminal The OFF switch capacitance is 75pF as shown on the OUT1 terminal Analysis of the circuit for all digital inputs HIGH as shown in Figure is Similar to Figure on terminafOU Figure 3 AD7543 DAC Equivalent Circuit All Digital Inputs LOW RFB VREF OUT1 260pF ILEAKAGE BE ILEAKAGE aE Figure 4 AD7543 DAC Equivalent Circuit All Digital Inputs HIGH 75pF REV B AD7543 Logic Inputs Register A Control Inputs AD7543 Operation Notes STB4 STB3 STB2 STB1 0 1 0 A Data Appearing At SRI Strobed Into Register A 0 1 ey 0 Data Appearing At SRI Strobed Into Register A 0 pA 0 0 Data Appearing At SRI Strobed Into Register A ake 1 0 0 x x xX Data Appearing At SRI Strobed Into Register A 1 X X X X 0 X X X x i a No Operation Register A X X X 1 13 eps No Operation Register B 3 NOTES 1 CLR 0 Asynchronously resets Register B to 0000 0000 0000 but has no effect on Register A 2 Serial data is loaded into Register A MSB first on edges shown is positive edge Vis negative edge 3 O Logic LOW 1 Logic HIGH X Don t Care Table Il AD7543 Truth Table SRI i tps1 tDS2 tDS4 STROBE INPUT LD1AND LD2 NOTE STROBE WAVEFORM IS INVERTED IF STB3 IS USED TO STROBE SERIAL DATA BITS INTO REGISTER A BIT 12 LSB ya LOADING REGISTER B WITH CONTENTS OF REGISTER A Figure 5
11. ad 4 Most Significant Bits LOOP ROL A Reposition in the Data DEC B in ACCA BNE LOOP LDA B 04 BSR SHIFT Output Data LDA B 08 LDA A 0001 Load 8 Least Significant Bits BSR SHIFT Output Data STA A 4000 Load DAC Register RTS Return to Main Program SHIFT STA A 2000 Strobe Data ROL A into AD7543 DEC B BNE SHIFT RTS Table V Sample Routine for AD7543 MC6800 Interface AD7543 INTERFACE TO MCS 85 Figure 9 shows the AD7543 interfaced to the 8085 This sys tem makes use of the serial output facility SOD on the 8085 The data is presented serially on the SOD line and strobed into the AD7543 by executing memory write instructions In this example the strobe signal STB2 is supplied by decod ing address 8000 and WR A memory write instruction to a different address A000 loads the DAC Register with Register AD7543 A data Table VI gives a listing of this procedure Note it is OUTLINE DIMENSIONS assumed that the required serial data is already present in Dimensions shown in inches and mm right justified format in Registers H and L when this proce dure is implemented Note that the sample routine of Table VI can be speeded up by replacing the SHIFT routine with a DAD H instruction 16 Pin Plastic DIP N 16 Package 0 26 6 61 0 24 pea a ADRESS BUS ite ADDRESS 16 p mes 0 755 wm 0 306 7 78 0745 18 93 seer y nas E Bank 012 3 08 Ses 08 DECODER max 0 175 cate 48 012
12. coefficient is increased by only 0 25ppm C Where possible R1 should be a select on test fixed resistor since the resulting gain temperature coeffi efficient will be tighter in all cases For further gain T C information refer to application note Gain Error and Gain Temperature Coefficients of CMOS Multiplying DACs Publication Number E630 10 6 81 available from Analog Devices 5 For additional information on multiplying DACS refer to Application Guide to CMOS Multiplying D A Con verters Publication Number G479 15 8 78 available from Analog Devices REV B AD7543 INTERFACE TO MC6800 In this example it is assumed that the 12 bit data is con tained in two memory locations 0000 and 0001 The four most significant bits are assumed to occupy the lower half of memory location 0000 The eight least significant bits occupy memory location 0001 The data is presented bit by bit on the D7 line and strobed into the AD7543 by executing memory write instructions In this case the strobe signal STB1 is sup plied by decoding address 2000 R W and 2 A memory write instruction to a different address 4000 loads the data from Register A to the DAC register Figure 8 shows the interface circuitry and Table V gives a listing of the procedure ADDRESS BUS 16 A0 15 ADDRESS 16 DECODER DATA 8 Figure 8 AD7543 MC6800 Interface LABEL MNEMONIC OPERAND COMMENT LDA B 04 LDA A 0000 Lo
13. d attenuation The input output relationship is shown in Table III R1 provides full scale trim capability i e load the DAC register to 1111 1111 1111 adjust R1 for Vout VREF 4095 4096 Alternatively Full Scale can be adjusted by omitting R1 and R2 and trimming the reference voltage magnitude C1 phase compensation 10pF to 25pF may be required for stability when using high speed amplifiers C1 is used to can cel the pole formed by the DAC internal feedback resistance and output capacitance at OUT1 AD7543 ADS5S44L SEE TEXT OGND AGND NOTES 1 LOGIC INPUTS OMITTED FOR CLARITY 2 SEE APPLICATION HINT NO 4 Figure 6 Unipolar Binary Operation 2 Quadrant Multiplication BINARY NUMBER IN DAC REGISTER MSB LSB ANALOG OUTPUT Vout 1111 1111 1111 Vrer 482 1000 0000 0000 VREF 2048 1 2 VREF 0000 0000 0001 Vrer 3996 0000 0000 0000 ov Table Ill NINN fo Amplifier A1 should be selected or trimmed to provide Vos lt 10 of the voltage resolution at Vout Additionally the amplifier should exhibit a bias current which is low over the temperature range of interest bias current causes output offset at VouT equal to Ip times the DAC feedback resistance nominally 15k The AD544L is a high speed implanted FET input op agp with low factory trimmed Vos BIPOLAR OPERATION 4 QUADRANT MULTIPLICATION Figure 7 and Table IV illustrate the circuitry and code rela tionship for bipola
14. ient AGain ATemperature 5 5 5 ppm C max Typical value is 2ppm C Power Supply Rejection AGain AVpp 0 005 0 01 0 01 per max Vpn 4 75V to 5 25V Output Leakage Current lout Pin 4 1 10 200 nA max DAC Register loaded with all Os IouTz2 Pin 5 1 10 200 nA max DAC Register loaded with all 1s DYNAMIC PERFORMANCE Current Settling Time 2 0 2 0 2 0 us max To 1 2LSB OUT load 10082 DAC output measured from falling edge of LD1 and LD2 see Figure 5 Multiplying Feedthrough Error 25 2 5 2 5 mV p p max Vrer 10V 10kHz sine wave REFERENCE INPUT Input Resistance pin 15 8 15 25 8 15 25 8 15 25 kQ min ty p max Typical temperature coefficient is 300ppm C ANALOG OUTPUTS Output Capacitance f CouT1 T3 75 73 pF max Register B loaded to 0000 0000 0000 Cout 260 260 260 pF max Register B loaded to 1111 1111 1111 Cout2 75 75 75 pF max Register B loaded to 1111 11111111 Cout2 260 260 260 pf max Register B loaded to 0000 0000 0000 LOGIC INPUTS VinH Logic HIGH Voltage 3 0 3 0 3 0 V min Vinu Logic LOW Voltage 0 8 lin A max T Cp Input Capaci F max Input Coding it ary MSB First SWITCHING CHARACTERISTICS tps1 50 100 100 ns min Serial 1 STB1 used as a strobe tps4 0 0 0 ns min a nput STB4 used as a strobe o Strobe a tps3 0 0 0 ns min Setup Time STB3 used as a strobe tps2 20 40 40 ns min STB2 used as a strobe tDH1 30 60 60 ns min Serial Input STB1 used as a strobe tpH4 80 160 160 ns min K Sie be STB4 used as a strobe tpH3 80 1
15. ion if the spurious pole frequency is less than the amplifier s OdB crossover frequency Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor GAIN TEMPERATURE COEFFICIENTS The gain temper ature coefficient of the AD7543 has a maximum value of Sppm C and a typical value of 2ppm C This corresponds to gain shifts of 2 0LSBs and 0 82LSBs respectively over a 100 C temperature range When trim resistors are used to adjust full scale range as shown in Figures 6 and 7 the temperature coefficient of R1 and R2 should be taken into account It may be shown that the additional gain temperature coefficients introduced by R1 and R2 may be approximately expressed as follows Temperature Coefficient Ry contribution due to R1 Rin Y 300 Temperature Coefficient 2 contribution due to R2 R Y2 300 Where y and 72 are the temperature coefficients in ppm C of R1 and R2 respectively and Ryn is the DAC input resist wound resisto of 50ppm tif pared with r iDWtion t ficient will also be small For the standard AD7543 gain error specification of 12 3 LSBs it is recommended that R1 120Q and R2 6022 With y 50 these values result in an overall maximum gain error temperature coefficient of 5 2 06 50 300 8ppm C However if the AD7543GTD is used which has a specified gain error of 1LSB then with R1 1022 and R2 52 the overall maximum gain temperature
16. r operation With a dc reference positive or negative polarity the circuit provides offset binary operation With an ac reference the eleven LSBs provide digitally con trolled attenuation of the ac reference while the MSB pro vides polarity control With the DAC register loaded to 1000 0000 0000 adjust R1 for Vout OV alternatively one can omit R1 and R2 and adjust the ratio of R3 to R4 for Vout OV Full scale trim ming can be accomplished by adjusting the amplitude of VREF or by varying the value of R5 As in unipolar operation A1 must be chosen for low Vos and low Ip R3 R4 and R5 must be selected for matching and tracking Mismatch of 2R3 to R4 causes both offset and Full Scale error Mismatch of R5 to R4 to 2R3 causes Full Scale error C1 phase compensation 10pF to 25pF may be re quired for stability SEE TEXT DGND AGND NOTES 1 LOGIC INPUTS OMITTED FOR CLARITY 2 SEE APPLICATION HINT NO 4 Figure 7 Bipolar Operation 4 Quadrant Multiplication BINARY NUMBER IN DAC REGISTER MSB LSB ANALOG OUTPUT Vout 1111 1111 1111 Vrer 20r 1000 0000 0001 Vrer z047 1000 0000 0000 ov 0111 1111 1111 Vrer 30485 0000 0000 0000 VREF 2048 CO Circuit of APPLICATION HINTS The AD7543 is a precision 12 bit multiplying DAC designed for serial interface To ensure system performance consistent with AD7543 specifications careful attention must be given to the following points
17. sted under Absolute Maximum Ratings may cause Chip Carrier PLEC Q Cerdip R Small Outline IC SOIC permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those above those indicated in the operational pe ation is not implied lute maxi onditions for extended peri ity O ESD electrostatic discharge sensitive device The digital control inputs are diode protect CAUTION ed however permanent damage may occur on unconnected devices subject to high energy electrostatic fields Unused devices must be stored in conductive foam or shunts The protective foam should be discharged to the destination socket before devices are removed WARNING _ ye ESD SENSITIVE DEVICE PIN MNEMONIC FUNCTION DAC current output bus Normally terminated at op amp virtual ground DAC current output bus Normally terminated at AGND Analog Ground Register A Strobe 1 input see Table II DAC Register B Load 1 input When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B No Connection Serial Data Input to Register A Register A Strobe 2 input see Table II DAC Register B Load 2 input When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B Register A Strobe 3 input see Table II Register A Strobe 4 input see Table II Digital Ground Register B CLEAR input active LOW can be used to as
18. ynchronously reset Register B to 0000 0000 0000 5V Supply Input Reference input Can be positive or negative dc voltage or ac signal DAC Feedback Resistor Table I Pin Function Description DIP Configuration REV B AD7543 TERMINOLOGY RELATIVE ACCURACY Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function It is measured after adjusting for ideal zero and full scale and is expressed in or ppm of full scale range or sub multiples of 1LSB DIFFERENTIAL NONLINEARITY Differential nonlinearity is the difference between the mea sured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB max over the operating temperature range ensures monotonicity GAIN ERROR Gain is defined as the ratio of the DAC s Full Scale output to its reference input voltage An ideal AD7543 would exhibit a gain of 4095 4096 Gain error is adjustable using external trims as shown in Figures 6 and 7 OUTPUT LEAKAGE CURRENT Current which appears at OUT1 with Register B loaded to all 0 s or at OUT 2 with Register B loaded to all 1 s MULTIPLYING FEEDTHROUGH ERROR AC error due to capacitive feedthrough from Vypr terminal to OUT1 with DAC register loaded to all 0 s GENERAL CIRCUIT INFORMATION The AD7543 a W2 D a highly stable thin fi and current switches a ol chip Mo

ANALOG DEVICES AD7543 handbook

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