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ANALOG DEVICES AD630 handbook

1. lock in amplifier is basically a synchronous demodulator followed by a low pass filter An important measure of performance in a lock in amplifier is the dynamic range of its demodulator The schematic diagram of a demonstration circuit which exhibits the dynamic range of an AD630 as it migh edi j CLIPPED BAND LIMITED WHITE NOISE OUTPUT MODULATED 400Hz CARRIER REFERENCE Figure 14 Lock In Amplifier 10 MODULATED SIGNAL UNATTENUATED ATTENUATED SIGNAL PLUS NOISE B MEMENCAMEBMBE Figure 15 Lock In Amplifier Waveforms test signal is produced by modulating a 400 Hz carrier with a 0 1 Hz sine wave The signals produced for example by chopped radiation 1 e IR optical detectors may have similar low frequency components sinusoidal modulation is used for clarity of illustration This signal is produced by a circuit similar to Figure 9b and is shown in the upper trace of Figure 15 It is attenuated 100 000 times normalized to the output B of the summing amplifier A noise signal that might represent for example background and detector noise in the chopped radia tion case is added to the modulated signal by the summing amplifier This signal is simply band limited clipped white noise Figure 15 shows the sum of attenuated signal plus noise in the center trace This combined signal is demodulated synchro nously using phase information derived from the modulator and t
2. to 70 Chip AD630SCHIPS 55 C to 125 C Chip CHIP METALLIZATION AND PINOUT PIN CONFIGURATIONS Dimensions shown in inches ands mnillimeters 20 Lead SOI CHIP AVAILABILITY AD630 is available in laser trimmed passivated chip form The figure above shows the AD630 metallization pattern bonding pads and dimensions AD630 chips are available con sult factory for details CAUTION TOP VIEW CM OFF ADJ 6 Not to Scale DIFF OFF ADJ 4 18 CHB CM OFF ADJ 5 17 RB CM OFF ADJ 6 TOP VIEW 16 Ra CHANNEL STATUS B A 7 Not to Scale 15 Vs 8 14 9 10 11 12 13 m ava gt 2 oun O ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD630 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING ESD SENSITIVE DEVICE REV E 3 AD630 Typical Performance Characteristics 15 5 10 lt lt lt E E E al ip 9 9 5 E E a z 5 2 5 2 0 3 100pF 5 5 o o o 0 0 1k 10k 100k 1M 1
3. 10 100 1k 10k 100k 1M 0 5 10 15 FREQUENCY Hz RESISTIVE LOAD 0 SUPPLY VOLTAGE V TPC 1 Output Voltage vs Frequency TPC 2 Output Voltage vs Resistive TPC 3 Output Voltage Swing vs Load Supply Voltage UNCOMPENSATED IN UNCOMPENSATED gt OPEN LOOP GAIN dB OPEN LOOP PHASE C COMMON MODE REJECTION dB o o 4 Common Mode Rejection 5 vs Frequency vs Input Voltage TPC 6 Gain and Phase vs Frequency 4 REV E TT ae z10V20kHz BERE S x io pena iia 20mV DIV Vo 1mV DIV Miama LN NI mmm a MET Lll OTTO TOP TRACE Vo TOP TRACE Vj BOTTOM TRACE Vj MIDDLE TRACE SETTLING ERROR B BOTTOM TRACE Vo 20mV DIV 84 i TPC 7 Channel to Channel Switch Settling Characteristic TPC 9 Large Signal Inverting Step Response C com AL TORR imV DIV A 100mV DIV Vo TOP TRACE Vj MIDDLE TRACE SETTLING ERROR A BOTTOM TRACE Vo TPC 8 Small Signal Noninverting Step Response REV E b AD630 TWO WAYS TO LOOK AT THE AD630 functional block diagram of the AD630 see page 1 shows the pin connections of the internal functions An alterna
4. a waveform of the same frequency is applied to the refer ence input The dc level of the output obtained by low pass filtering will be proportional to the signal amplitude and phase difference between the input signals If the signal amplitude is held constant the output can be used as a direct indication of the phase When these input signals are 90 out of phase they are said to be in quadrature and the AD630 dc output will be zero PRECISION RECTIFIER ABSOLUTE VALUE If the input signal is used as its own reference in the balanced modulator topologies the AD630 will act as a precision recti fier The high frequency performance will be superior to that which can be achieved with diode feedback and op amps There are no diode drops that the op amp must over with the commutating amplifier LVDT SIG R Many transdut e y A linear variable differential transformer LVDT is a transducer of this type The amplitude of the output signal corresponds to core displacement Figure 11 shows an accurate synchronous demodulation system which can be used to produce a dc voltage that corresponds to the LVDT core position The inherent precision and temperature stability of the AD630 reduce demodulator drift to a second order effect E1000 SCHAEVITZ AD544 AD630 FOLLOWER A LVDT ag sko 2DEMODULATOR 2 5kHz 2V p p SINUSOIDAL EXCITATION Figure 11 LVDT Signal Conditioner AC BRIDGE Bridge ci
5. 110 dB 1 2 Closed Loop Gain Error 0 1 0 05 0 1 Closed Loop Gain Match 0 1 0 05 0 1 Closed Loop Gain Drift 2 2 2 ppm C CHANNEL INPUTS Operational Limit Vs 4 V to Vs 1 V Vs 4 V to Vs 1 V Vs 4 V to Vs 1 V V Input Offset Voltage 500 100 500 uV Input Offset Voltage Tmn to Tmax 800 160 1000 uV Input Bias Current 100 300 100 300 100 300 nA Input Offset Current 10 50 10 50 10 50 nA Channel Separation 10 kHz 100 100 100 dB COMPARATOR Operational Limit CVs 3 V to Vs 1 5 V CVs 3 V to Vs 1 5 V Vs 3 V to 1 3 V V Switching Window 15 EIS 15 mV Switching Window Tmn to Tmax t2 0 t2 0 2 5 mV Input Bias Current 100 300 100 300 100 300 nA Response Time 5 mV to 5 mV Step 200 200 200 ns Channel Status Is Vor Vs 0 4 V 1 6 1 6 1 6 mA Pull Up Voltage Vs 33 V 33 V Vs 33 V DYNAMIC PERFORMANCE Unity Gain Bandwidth 2 2 2 MHz Slew Rate 45 45 45 V s Settling Time to 0 1 20 V Step 3 3 3 us OPERATING CHARACTERISTICS Common Mod Rejecti 85 90 110 dB Power Supply R je 90 90 110 dB Supply Voltage ge 5 5 5 V Supply Current 4 5 4 5 5 mA OUTPUT VOLTAGE 2 Tmn to Tmax 10 10 10 V Output Short Circuit Current 25 25 25 mA TEMPERATURE RANGES Rated Performance N Package 0 70 0 70 N A D Package 25 85 25 85 55 125 C NOTES one terminal of each differential channel or comparator input is kept withi
6. 5 0 4193 1 10 10 00 0 3937 2 65 0 1043 0 75 0 0295 2 35 0 0925 825 0 0095 lt 49 0 30 0 0118 7l 0 25 0 0098 0 10 0 0039 1 4 gt je gt a 1 8 gt COPLANARITY onsen 0 51 0 0201 SFATING 0 33 0 0130 0 1 27 0 0500 0 10 Bsc 931 0 0122 0 20 0 0079 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 013AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location 6 04 Data Sheet Changes to on AAS 25 Replaced 2 a col so Changes AC BRIDGE Gre ope AL HECHO E EET be RA Racks 9 Replaced Figure 13 c 10 Changes to LOCK IN AMPLIFIER APPLICATIONS 1 41 10 Updated OUTLINE DIMENSIONS 25555 95 ERROR awe E e abe deep v Sed FPE DRESS 11 6 01 Data Sheet changed from REV C to REV D Changes to SPECIFICATION TABLE 244444 G4 GREEN DRA Oe DOA REA EA E RR NER RR AR XA ER SER 2 Changes to THERMAL CHARACTERISTICS 6 66 3 Changes to ORDERING GUIDE rege e RU pel UR Re Ren Ug ce Hu Ru ea e a OR 3 Changes PIN CONFIGURATIONS seat HE qa e Pes ea b
7. 7 87 0 180 4 57 0 300 7 62 VaL 62 0 150 3 81 pu 0 015 0 38 MIN 0 135 3 43 0 135 3 43 0 120 3 05 0 150 8 8 BAN i 0 130 3 30 elle 0 015 0 38 0 110 2 79 0 022 0 56 n x3 Bao SEATING 0 010 025 0 018 0 46 0 050 1 27 0 008 0 20 0 014 0 36 0 045 1 14 COMPLIANT TO JEDEC STANDARDS MO 095 AE CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 20 Terminal Ceramic Leadless Chip Carrier LCC E 20A Dimensions shown in inches and millimeters 0 100 2 54 0 064 1 63 0 200 5 08 0 075 1 91 0 100 2 54 0 095 2 41 mew ees y 0 0 015 0 38 0 075 1 90 MM AS MI T 0 358 9 09 0 358 9 09 0 011 0 28 0 342 8 69 0 007 018 i sa i BOTTOM VIEW 10050 1 27 oars M i men 45 TYP 0 088 2 24 0 055 1 40 mer 0 054 1 37 0 045 1 14 BSC CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETERS DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV E 11 AD630 AD630 20 Lead Standard Small Outline Package SOIC Wide Body R 20 Dimensions shown in millimeters and inches 13 00 0 5118 12 60 0 4961 20 11 7 60 0 2992 7 40 0 2913 10 6
8. ANALOG DEVICES Balanced Modulator Demodulator AD630 FEATURES Recovers Signal from 100 dB Noise 2 MHz Channel Bandwidth 45 Slew Rate 120 dB Crosstalk 1 kHz Pin Programmable Closed Loop Gains of 1 and 2 0 05 Closed Loop Gain Accuracy and Match 100 uV Channel Offset Voltage AD630BD 350 kHz Full Power Bandwidth Chips Available PRODUCT DESCRIPTION The AD630 is a high precision balanced modulator that combines a flexible commutating architecture with the accuracy and tem perature stability afforded by laser wafer trimmed thin film resistors Its signal processing applications include balanced modulation and demodulation synchronous detection phase detection quadrature detection phase sensitive detection lock in amplification and square wave multiplication A network of on board applications resistors provides precision closed loop gains of 1 and 2 with 0 05 accuracy AD630B These resistors may also be used to accurately configure d The AD630 can be thought of as a precision op amp with two independent differential input stages and a precision comparator that is used to select the active front end The rapid response time of this comparator coupled with the high slew rate and fast settling of the linear amplifiers minimize switching distortion In addition the AD630 has extremely low crosstalk between chan nels of 100 dB 10 kHz The AD630 is used in precision signal processing and instru
9. annel A is selected This output can also be used to supply positive feedback around the comparator This produces hysteresis which serves to increase noise immunity Figure 7 shows an example of how hysteresis may be implemented Note that the feedback signal is applied to the inverting terminal of the comparator to achieve positive feedback This is because the open collector channel status output inverts the output sense of the internal comparator Figure 7 Comparator Hysteresis channel status output may be interfaced with TTL inputs as shown in Figure 8 This circuit provides appropriate level shifting from the open collector AD630 channel status output to TTL inputs TTL INPUT Figure 8 Channel Status TTL Interface APPLICATIONS BALANCED MODULATOR Perhaps the most commonly used configuration of the AD630 is the balanced modulator The application resistors provide precise symmetric gains of 1 and 2 The 1 arrangement is shown in Figure 9a and the 2 arrangement is shown in Figure 9b These cases differ only in the connection of the 10 feedback resistor Pin 14 and the compensation capacitor Pin 12 Note the use of the 2 5 bias current compensation resistors in these examples These resistors perform the identical function in the 1 gain case Figure 10 demonstrates the performance of the AD630 when used to modulate 100 kHz square wave carrier with a 10 sinusoid The result is th
10. cations that require precisely fixed gain switched gain multiplexing integrating switching functions and high speed precision amplification 3 100 dB dynamic range of the AD630 exceeds that of any hybrid or IC balanced modulator demodulator and is compa rable to that of costly signal processing instruments 4 The op amp format of the AD630 ensures easy implementa tion of high gain or complex switched feedback functions application resistors facilitate the implementation of most common applications with no additional parts 5 AD630 can be used as a 2 channel multiplexer with gains of 1 2 3 or 4 The channel separation of 100 dB 10 KHz approaches the limit achievable with an empty IC package 6 The AD630 has pin strappable frequency compensation no external capacitor required for stable operation at unity gain without sacrificing dynamic performance at higher gains 7 Laser trimming of comparator and amplifying channel offsets eliminates the need for external nulling in most cases One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved 0630 5 0 NS 25 C and V 15 V unless otherwise noted AD630J AD630A AD630K AD630B AD630S Model Min Typ Max Min Max Min Typ Max Unit GAIN Open Loop Gain 90 110 100 120 90
11. configuration shown in Figure 4 In this case RA will appear across the op amp input terminals but since the amplifier drives this difference voltage to zero the closed loop gain is unaffected The two closed loop gain magnitudes will be equal when 1 Rg Rg which will result from making R4 equal to RgRp Rg Rg the parallel equivalent resistance of Rp and The 5 kQ and the two 10 kQ resistors on the AD630 chip can be used to make a gain of 2 as shown below By paralleling the 10 resistors to make equal to 5 and omitting the circuit can be programmed for a gain of 1 as shown in Figure 9a These and other configurations using the on chip resistors present the inverting inputs with a 2 5 source imped ance The more complete AD630 diagrams show 2 5 kQ resistors available at the noninverting inputs which can be conveniently used to minimize errors resulting from input bias currents 10kQ Ra Vi 5 F Vo VI 10kO o Ra i ation CIRCUIT DESCRIPTION The simplified schematic of the AD630 is shown in Figure 5 It has been subdivided into three major sections the comparator the two input stages and the output integrator The compara tor consists of a front end made up of Q52 and Q53 a flip flop load formed by Q3 and Q4 and two current steering switching cells Q28 Q29 and Q30 Q31 This structure is designed so that a differential input voltage greater than 1 5 mV in mag
12. e double sideband sup pressed carrier waveform These balanced modulator topologies accept two inputs a signal or modulation input applied to the amplifying channels and a reference or carrier input applied to the comparator MODULATION INPUT Vs MODULATED OUTPUT SIGNAL INPUT Figure 9a AD630 Configured as a Gain of One Balanced Modulator MODULATED OUTPUT SIGNAL INPUT Figure 9b AD630 Configured as a Gain of Two Balanced Modulator MODULATION INPUT CARRIER INPUT 110444141 Ec fla ATER LAT A EEXEE OUTPUT SIGNAL Figure 10 Gain of Two Balanced Modulator Sample Waveforms REV E AD630 BALANCED DEMODULATOR balanced modulator topology described above will also act as a balanced demodulator if a double sideband suppressed carrier waveform is applied to the signal input and the carrier signal is applied to the reference input The output under these circumstances will be the baseband modulation signal Higher order carrier components that can be removed with a low pass filter will also be present Other names for this function are synchro nous demodulation and phase sensitive detection PRECISION PHASE COMPARATOR balanced modulator topologies of Figures 9a and 9b can also be used as precision phase comparators In this case an ac waveform of a particular frequency is applied to the signal input and
13. he result is low pass filtered using a 2 pole simple filter also provides a gain of 109 to t 15 recovered signal is th lof Ri 15 The combined igmal lan ise used for illustration is s signals often requiring a lock in amplifier for detection The precision input performance of the AD630 provides more than 100 dB of signal range and its dynamic response permits it to be used with carrier frequencies more than two orders of magnitude higher than in this example A more sophisticated low pass output filter will aid in rejecting wider bandwidth interference REV E OUTLINE DIMENSIONS 20 Lead Side Brazed Ceramic Dual In Line Package SBDIP D 20 Dimensions shown in inches and millimeters 0 005 0 13 MIN 0 080 2 03 MAX gt je gt 0 300 7 62 0 280 7 11 1 060 28 92 0 060 1 52 990 25 15 Each ed 0 990 25 15 0 015 0 38 0 200 5 08 0 150 0 200 5 08 3 81 0 125 3 18 5i NE MIN lt 0 023 58 0 100 0 070 1 78 0 014 0 36 esc 0 030 0 76 0 320 8 13 0 300 7 62 0 015 0 38 0 008 0 20 CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 20 Lead Plastic Dual In Line Package PDIP N 20 Dimensions shown in inches and millimeters 0 325 9 26 0 985 25 02 0 310
14. mentation applications that require wide dynamic range When used as a synchronous demodulator in a lock in amplifier configuration it can recover a small signal from 100 dB of inter fering noise see Lock In Amplifier Applications section Although optimized for operation up to 1 kHz the circuit is useful at frequencies up to several hundred kilohertz Other features of the AD630 include pin programmable frequency compensation optional input bias current compensation resis tors common mode and differential offset voltage adjustment and a channel status output that indicates which of the two differential inputs is active This device is now available to Standard Military Drawing DESC numbers 5962 8980701RA and 5962 89807012A REV E Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM CMOFF CMOFF DIFFOFF DIFF OFF AD ADJ ADJ ADJ PRODUCT HIGHLIGHTS 1 The configuration of the AD630 makes it ideal for signal 3 2 odulation and detection and The application flexibility of the AD630 makes it the best choice for appli
15. n these limits the other terminal may be taken to the positive supply smk Vor CVs 1 V is typically 4 mA 3Pin 12 Open Slew rate with Pin 12 and Pin 13 shorted is typically 35 V us Specifications subject to change without notice REV E AD630 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Supply Voltage ss sss er RR px He 18 V Internal Power Dissipation 600 mW Output Short Circuit to Ground Indefinite 20 Lead PDIP N 24 C W 61 C W Storage Temperature Ceramic Package 65 C to 150 C 20 Lead Ceramic DIP D 35 C W 1209C W Storage Temperature Plastic Package 559 to 125 C 20 1 Leadless Chip Carrier LCC E 35 C W 120 C W Lead Temperature Range Soldering 10 sec 300 C 20 Lead SOIC R 20 38 C W 75 C W Maximum Junction Temperature 150 C ORDERING GUIDE Model Temperature Ranges Package Description Package Option AD630JN 0 C to 70 C PDIP N 20 AD630KN 0 C to 70 C PDIP N 20 AD630AR 259 to 85 C SOIC R 20 AD630AR REEL 25 C 85 C SOIC 13 Tape and Reel R 20 AD630AD 25 C to 85 C SBDIP D 20 AD630BD 25 C 85 C SBDIP D 20 AD630SD 55 C to 125 C SBDIP D 20 AD630SD 883B 55 C to 125 C SBDIP D 20 5962 8980701RA 55 C to 125 C SBDIP D 20 AD630SE 883B 55 C to 125 C CLCC E 20A 5962 89807012A 55 C to 125 C CLCC E 20A AD630JCHIPS 09
16. nce of the circuit undergoes an abrupt change as the gain is switched under control of the comparator If gain is switched when the input signal is not zero as it is in many practical cases a tran sient will be delivered to the circuitry driving the AD630 In most applications this will require the AD630 circuit to be driven by a low impedance source which remains stiff at high requencies Generally thisgwill 1 buffer amplifier FREQUE TI AY he 630 convenient rnal frequency compensation With l xibility of external compensation by means of an optional self contained compensation capacitor In gain of 2 applications the noise gain that must be addressed for stability purposes is actually 4 In this circumstance the phase margin of the loop will be on the order of 60 without the optional compensation This condition provides the maximum bandwidth and slew rate for closed loop gains of 2 and above When the AD630 is used as a multiplexer or in other configura tions where one or both inputs are connected for unity gain feedback the phase margin will be reduced to less than 20 This may be acceptable in applications where fast slewing is a first priority but the transient response will not be optimum For these applications the self contained compensation capacitor may be added by connecting Pin 12 to Pin 13 This connection reduces the closed loop bandwidth somewhat and improves the phase margin For in
17. nitude applied to the comparator inputs will completely select one of the switching cells The sign of this input voltage determines which of the two switching cells is selected CHA CH A ad CH B Q F 8 fo Wwe bd i DIFF OFF ADJ CM CM OFF ADJ OFF ADJ l prr OFF ADJ Figure 5 AD630 Simplified Schematic REV AD630 collectors of each switching cell connect to an input trans conductance stage The selected cell conveys bias currents 12 and 1 to the input stage it controls causing it to become active deselected cell blocks the bias to its input stage which as a consequence remains off structure of the transconductance stages is such that it presents a high impedance at its input terminals and draws no bias current when deselected deselected input does not interfere with the operation of the selected input ensuring maxi mum channel separation Another feature of the input structure is that it enhances the slew rate of the circuit The current output of the active stage follows a quasi hyperbolic sine relationship to the dif ferential input voltage This means that the greater the input voltage the harder this stage will drive the output integrator and the faster the output signal will move This feature helps ensure rapid symmetric settling when switching between inverting and noninverting closed loop configurations output
18. onal amp feedback circuits Virtually any function that can be realized with simple noninverting L net work feedback can be used with the AD630 A common arrangement is shown in Figure 6 The low frequency gain of this circuit is 10 The response will have a pole 3 dB at a frequency f 1 2 100 and a zero 3 dB from the high frequency asymptote at about 10 times this frequency The 2 resistor in series with each capacitor mitigates the loading effect on circuitry driving this circuit eliminates stability problems and has a minor effect on the pole zero locations As a result of the reactive feedback the high frequency com ponents of the switched input signal will be transmitted at unity gain while the low frequency components will be ampli fied This arrangement is useful in demodulators and lock in amplifiers It increases the circuit dynamic range when the modulation or interference is substantially larger than the desired signal amplitude The output signal will contain the REV E desired signal multiplied by the low frequency gain which may be several hundred for large feedback ratios with the switching signal and interference superimposed at unity gain Figure 6 AD630 with External Feedback SWITCHED INPUT IMPEDANCE The noninverting mode of operation is a high input impedance configuration while the inverting mode is a low input impedance configuration This means that the input impeda
19. ore e ape war eC be x ra eer EP 3 Changesto OUTLINE DIMENSIONS 2 5 2582 0 Rx eR PR OUR RUE Roe d RR RR SU e acus 11 12 REV E 00784 0 6 04
20. rcuits that use dc excitation are often plagued by errors caused by thermocouple effects 1 f noise dc drifts in the electronics and line noise pick up One way to get around these problems is to excite the bridge with an ac waveform amplify the bridge output with an ac amplifier and synchronously demodulate the resulting signal The ac phase and amplitude information from the bridge is recovered as a dc signal at the output of the synchronous demodulator The low frequency system noise dc drifts and demodulator noise all get mixed to the carrier frequency and can be removed by means of a low pass filter Dynamic response of the bridge must be traded off against the amount of attenuation required to adequately suppress these residual carrier components in the selection of the filter igure a used d a sy 5 V4 n c lator and Trace C is the filtered dc system output SEL B 4 99kO 4 99 0 14 99 Figure 12 AC Bridge System REV E AD630 C 200mV DIV Figure 13 AC Bridge Waveforms 1 V Excitation LOCK IN AMPLIFIER APPLICATIONS Lock in amplification is a technique used to separate a small narrow band signal from interfering noise The lock in amplifier acts as a detector and narrow band filter combined Very small signals can be detected in the presence of large amounts of uncorrelated noise when the frequency and phase of the desired signal are known
21. section of the AD630 includes a current mirror load Q24 and Q25 an integrator voltage gain stage Q32 and a complementary output buffer 044 and 074 outputs of both transconductance stages are connected in parallel to the current mirror Since the deselected input stage produces no output current and presents a high impedance at its out puts there is no conflict The current mirror translates the differential output current from the active input transconductance amplifier into single ended form for the output integrator The complementary output driver then b outp to produc output OTHER G IO Many applications require switched gains other than the 1 and 2 which the self contained applications resistors provide The AD630 can be readily programmed with three external resistors over a wide range of positive and negative gain by selecting and Rg and Rz to give the noninverting gain 1 and subsequent Ra to give the desired inverting gain Note that when the inverting magnitude equals the noninverting magnitude the value of is found to be RgRgE Rg Rp That is RA should equal the parallel combination of Rg and to match positive and negative gain The feedback synthesis of the AD630 may also include reactive impedance The gain magnitudes will match at all frequencies if the A impedance is made to equal the parallel combination of the B and F impedances The same considerations apply to the AD630 as to conventi
22. termediate conditions such as gain of 1 where loop attenuation is 2 use of the compensation should be determined by whether bandwidth or settling response must be optimized The optional compensation should also be used when the AD630 is driving capacitive loads or whenever conservative frequency compensation is desired OFFSET VOLTAGE NULLING The offset voltages of both input stages and the comparator have been pretrimmed so that external trimming will only be required in the most demanding applications The offset adjust ment of the two input channels is accomplished by means of a differential and common mode scheme This facilitates fine adjustment of system errors in switched gain applications With 7 AD630 the system input tied to 0 V and a switching or carrier wave form applied to the comparator a low level square wave will appear at the output The differential offset adjustment potenti ometers can be used to null the amplitude of this square wave Pins 3 and 4 The common mode offset adjustment can be used to zero the residual dc output voltage Pins 5 and 6 These functions should be implemented using 10k trim poten tiometers with wipers connected directly to Pin 8 as shown in Figures 9a and 9b CHANNEL STATUS OUTPUT channel status output Pin 7 is an open collector output referenced to Vs that can be used to indicate which of the two input channels is active The output will be active pulled low when Ch
23. tive archi tectural diagram is shown in Figure 1 In this diagram the individual A and B channel preamps the switch and the inte grator output amplifier are combined in a single op amp This amplifier has two differential input channels only one of which 15 active at a time Vs Figure 1 Architectural Block Diagram HOW THE AD630 WORKS The basic mode of operation of the AD630 may be easier to recog nize as two fixed gain stages which can be inserted into the signal path under the control of a sensitive voltage comparator When the circuit is switched between inverting at provides the bas 1 15 unique in that back resistors on Figure 2 yields a gain of 2 and can be easily changed shifting Rg from its ground connection to the output to 1 by The comparator selects one of the two input stages to complete an operational feedback connection around the AD630 The deselected input is off and has a negligible effect on the operation Figure 2 AD630 Symmetric Gain 2 When Channel B is selected the resistors Ra and Rr are connected for inverting feedback as shown in the inverting gain configuration diagram in Figure 3 The amplifier has suffi cient loop gain to minimize the loading effect of Rg at the virtual ground produced by the feedback connection When the sign of the comparator input is reversed Input B will be dese lected and A will be selected The new equivalent circuit will be the noninverting gain

ANALOG DEVICES AD630 handbook

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