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ANALOG DEVICES AD7541A datasheet

1. 20 Terminal Ceramic Leadless Chip Carrier 20 Lead Plastic Leadless Chip Carrier E 20A P 20A 0 180 4 57 0 200 5 08 0 048 1 21 0 165 4 19 0 100 2 54 181 BSC 0 042 1 07 0 056 1 42 0 025 0 63 0 064 1 63 REF 0 100 2 54 BSC I 0 042 1 07 r 0 015 0 38 je lt Xy 0 015 0 38 0 048 az H m i 7 0 095 2 41 F 4 HT K MIN 0 042 Cor rer s 0 021 0 53 f 0 358 9 09 0 358 en 5 18 3 Y 0 028 0 71 IDENTIFIER 0 013 0 33 0 330 8 38 aa 9 09 0 011 0 28 0 022 0 56 TOP VIEW 0 032 0 81 0 290 7 37 0342 868 pe 5 007 0 18 gt BOTTOM Q4 PINS DOWN 0 026 0 66 sa RTYP m ped 1 27 0 075 1 91 Ay ry 0 020 4 ac rs 0 50 1 0 356 9 04 IL ai keon a e 45 TYP R 380155 50 0 025 0 64 0 088 2 24 0 055 1 40 0 150 3 81 J 0 395 10 02 L 0 110 2 79 0 054 1 37 0 045 1 14 BSC 0 385 9 78 SA 0 085 2 16 18 Lead Plastic DIP 18 Lead Cerdip N 18 Q 18 0 925 23 49 0 005 0 13 MIN 0 098 2 49 MAX B 0 845 21 47 al gt 18 10 m A 0 2 gt en 0 320 8 13 dip M T odse 0290 737 6 33 TOME EE l oh 6 08 0 015 0 38 0 160 4 06 ja AE 1 3 81 0 115 2 93 mia he iet 0 015 0 381 0 200 5 08 LA fin 0 022 0 558 0 100 0 070 1 77 SEATING 0 008 0 204 0 125 3 18 mile gt la a 0 015 0 38 LANE 0 023 0 58 0 100 0 070 1 78 SEATING 45 0 008 0 20 0 014 0 356 254 0 045 1 15 0 023 0 58 0 358
2. GAIN ERROR Gain error is a measure of the output error between an ideal DAC and the actual device output For the AD7541A ideal 4095 maximum output is E Vrer Gain error is adjustable to zero using external trims as shown in Figures 4 5 and 6 OUTPUT LEAKAGE CURRENT Current which appears at OUTI with the DAC loaded to all 0s or at OUT2 with the DAC loaded to all 1s MULTIPLYING FEEDTHROUGH ERROR AC error due to capacitive feedthrough from Vrrr terminal to OUTI with DAC loaded to all 0s DAC to settle to us i e O to full PROPAGATION DELAY This is a measure of the internal delay of the circuit and is mea sured from the time a digital input changes to the point at which the analog output at OUT reaches 90 of its final value DIGITAL TO ANALOG CHARGE INJECTION QDA This is a measure of the amount of charge injected from the digital inputs to the analog outputs when the inputs change state It is usually specified as the area of the glitch in nV secs and is measured with Vper GND and a Model 50K as the output op amp C1 phase compensation 0 pF PIN CONFIGURATIONS DIP SOIC LCCC No or i Er m w OUT e RFEEDBACK 332 S our2 2 Vref IN St ieg y GND 3 16 Vop E PIN 1 GND 4 18 Vpp GND IDENTIFIER Vop BIT 1 MSB A Ap75414 55 BIT 12 LSB BIT 1 MSB 5 AD7541A 17 BIT 12 LSB BIT 1 MSB KO TER A BIT 12 LSB BIT 2 TOP VIEW BIT 11 16 BIT 11 H 14 BIT 2
3. accuracy of the D A con verter Mismatch between R4 and R5 introduces a gain error GROUND FOR VALUES OF R1 AND R2 SEE TABLE 1 BIT 1 BIT 12 Figure 6 12 Bit Plus Sign Magnitude Operation Table IV 12 Bit Plus Sign Magnitude Code Table for Circuit of Figure 6 Sign Binary Number in DAC Bit MSB LSB Analog Output Vour 4095 l 4096 0 0 0 1 0000 0000 0000 0 Volts 4095 1 1114 1111 1111 IN X 2096 Note Sign bit of 0 connects R3 to GND AD7541A APPLICATIONS HINTS Output Offset CMOS D A converters exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the amplifier The maximum am plitude of this offset which adds to the D A converter nonlin earity is 0 67 Vos where Vos is the amplifier input offset voltage To maintain monotonic operation it is recommended that Vos be no greater than 25 x 10 Vper over the tempera ture range of operation Suitable op amps are AD517L and AD544L The AD517L is best suited for fixed reference appli cations with low bandwidth requirements it has extremely low offset 50 UV and in most applications will not require an offset trim The AD544L has a much wider bandwidth and higher slew rate and is recommended for multiplying and other appli cations requiring fast settling An offset trim on the AD544L may be necessary in some circuits Digital Glitches One cause of digital glitches is c
4. current source I gaxagg is composed of surface and junc tion leakages to the substrate while the I 4096 current source represents a constant l bit current drain through the termina tion resistor on the R 2R ladder The ON capacitance of the output N channel switch is 200 pF as shown on the OUT2 terminal The OFF switch capacitance is 70 pF as shown on the OUTI terminal Analysis of the circuit for all digital inputs HIGH as shown in Figure 3 is similar to Figure 2 however the ON switches are now on terminal OUT1 hence the 200 pF at that terminal ILEAKAGE T i 1 4096 t ILEAKAGE I OUT2 200pF Figure 2 DAC Equivalent Circuit All Digital Inputs LOW R 15kQ VREF 200pF ILEAKAGE r 4 ILEAKAGE in Figure 3 DAC Equivalent Circuit All Digital Inputs HIGH OUT2 70pF APPLICATIONS UNIPOLAR BINARY OPERATION 2 QUADRANT MULTIPLICATION Figure 4 shows the analog circuit connections required for uni polar binary 2 quadrant multiplication operation With a dc reference voltage or current positive or negative polarity ap plied at Pin 17 the circuit is a unipolar D A converter With an ac reference voltage or current the circuit provides 2 quadrant multiplication digitally controlled attenuation The input output relationship is shown in Table II RI provides full scale trim capabilitv i e load the DAC register to 1111 1111 1111 adjust RI for Vour Vrer 4095 4096 Alternativelv Full Scal
5. digital inputs 0 V to Vpp or IMPULSE Vpp to 0 V All 1000 nV sec typ Measured using Model 50K as output amplifier MULTIPLYING FEEDTHROUGH ERROR Vper to OUTI All 1 0 mV p p typ Vrer 10 V 10 kHz sine wave OUTPUT CURRENT SETTLING TIME All 0 6 us typ To 0 01 of full scale range OUT 1 Load 100 Q Cexr 13 pF Digital Inputs 0 V to Vpp or Vpp to 0 V OUTPUT CAPACITANCE Cour Pin 1 All 200 200 pF max Digital Inputs Cour Pin 2 All 70 70 pF max Vin Covr Pin 1 All 70 70 pF max Digital Inputs Cour Pin 2 All 200 200 pF max Vir NOTES Temperature range as follows J K versions 0 C to 70 C A B versions 25 C to 85 C S T versions 55 C to 125 C Guaranteed by design but not production tested gt To minimize feedthrough in the ceramic package Suffix D the user must ground the metal lid Specifications subject to change without notice EE REV B AD7541A ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Operating Temperature Range Commercial J K Versions 0 C to 70 C Vip 0 GND riss een 17 V Industrial A B Versions 25 C to 85 C Virto GND ars er aaa 25 V Extended S T Versions 55 C to 125 C VerB O GND sun ee one ae 25 V Storage Temperature 0000000 65 C to 150 C 300 C Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This i
6. 6 TOP VIEW BIT 2 T P VIEW BIT 11 Bir 3 6 BIT 10 BITS Tp Notto Scale jq 16 BiT 10 BIT3 Not to Scale BIT 10 BIT 4 8 14 BIT9 BIT 4 12 Bir 9 BIT4 BIT 9 BIT 5 8 BIT 8 9 10 11 12 13 o Thomi N 0 BIT 6 9 BIT 7 NC NOCONNECT ER SEE wo OF oo mu NC NOCONNECT E E ZE m m m a REV B 3 AD7541A GENERAL CIRCUIT INFORMATION The simplified D A circuit is shown in Figure 1 An inverted R 2R ladder structure is used that is the binarilv weighted currents are switched between the OUT1 and OUT bus lines thus maintaining a constant current in each ladder leg indepen dent of the switch state 10kQ 10kQ 10kQ VREF O O OUT2 O OUT1 n ju L H O RFEEDBACK BIT1 MSB BIT2 BIT3 BIT 12 LSB DIGITAL INPUTS DTL TTL CMOS COMPATIBLE LOGIC A SWITCH IS CLOSED TO Ioyr FOR ITS DIGITAL INPUT IN A HIGH STATE Figure 1 Functional Diagram Inputs HIGH The input resistance at Vper Figure 1 is always equal to Rr pn Ripp is the R 2R ladder characteristic resistance and is equal to value R Since Rin at the Vggg pin is constant the reference terminal can be driven by a reference voltage or a reference current ac or dc of positive or negative polarity If a current source is used a low temperature coefficient external Rpg is recommended to define scale factor EQUIVALEN The equivalent inputs HIGH are shown in Figures 2 and 3 In Figure 2 with all digital inputs LOW the reference current is switched to OUT The
7. ANALOG CMOS DEVICES 12 Bit Monolithic Multiplving DAC AD7541A FEATURES FUNCTIONAL BLOCK DIAGRAM Improved Version of AD7541 Full Four Quadrant Multiplication Vper 10ka ORG bos 12 Bit Linearity Endpoint All Parts Guaranteed Monotonic TTL CMOS Compatible Low Cost Protection Schottky Diodes Not Required Low Logic Input Leakage 20kQ 20kQ 12 OUT2 OUTI E 4 mn 1 RFEEDBACK GENERAL DESCRIPTION BIT1 MSB BIT2 BIT 3 BIT 12 LSB The Analog Devices AD7541A is a low cost high performance m ciis DIGITAL INPUTS DTL TTL CMOS COMPATIBLE 12 bit monolithic multiplying digital to analog converter It is LOGIC A SWITCH IS CLOSED TO Ioyr FOR fabricated using advanced low noise thin film on CMOS ITS DIGITAL INPUT IN A HIGH STATE technology and is available in a standard 18 lead DIP and in 20 terminal surface mount packages PRODUCT HIGHLIGHTS The AD7541A is functionally and pin compatible with the in Compatibility The AD7541A can be used as a direct replace dustry standard AD7541 device and offers improved specifica ment for any AD7541 type device As with the Analog Devices tions and performance The improved design ensures that the AD7541 the digital inputs are TTL CMOS compatible and device is latch up free so no output protection Schottky diodes have been designed to have a 1 WA maximum input current are required requirement so as not to load the driving itry This new devi fi Im
8. Class B process parts add 883B to part number Contact local sales office for military data sheet 3E Leadless Ceramic Chip Carrier N Plastic DIP P Plastic Leaded Chip Carrier Q Cerdip R Small Outline IC REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A which may result from its use No license is granted by implication or Tel 617 329 4700 World Wide Web Site http www analog com otherwise under any patent or patent rights of Analog Devices Fax 617 326 8703 Analog Devices Inc 1997 AD7541 A SPEC Fl CATI 0 NS Voo 15 V Vper 10 V OUT 1 OUT 2 GND 0 V unless otherwise noted Ta Ta Parameter Version 25 C Tmn Tmax Units Test Conditions Comments ACCURACY Resolution All 12 12 Bits Relative Accuracy LAS 1 ti LSB max 1 LSB 0 024 of Full Scale K B T 1 2 1 2 LSB max 1 2 LSB 0 012 of Full Scale Differential Nonlinearity LAS 1 1 LSB max All Grades Guaranteed Monotonic K B T 1 2 1 2 LSB max to 12 Bits Tum to Tmax Gain Error J A S 6 8 LSB max Measured Using Internal Rpp and Includes K B T 3 5 LSB max Effect of Leakage Current and Gain TC Gain Error Can Be Trimmed to Zero Gain Temperature Coefficient AGain ATemper
9. GROUND Vout Vrer D 1 R2 R1 WHERE 0 D 1 i e D IS A FRACTIONAL REPRESENTATION OF THE DIGITAL INPUT Figure 7 Single Supply Operation Using Voltage Switch ing Mode The reference voltage must always be positive If OUTI goes more than 0 3 V less than GND an internal diode will be turned on and a heavy current may flow causing device damage the AD7541A is however protected from the SCR latch up phenomenon prevalent in many CMOS devices Suitable refer nces include the AD580 and The loading on ti gt ere e ime behavior of the reference voltage with changing load conditions To maintain linearity the voltage at OUTI should remain within 2 5 V of GND for a Vpp of 15 V If Vpp is reduced from 15 V or the reference voltage at OUTI increased to more than 2 5 V the differential nonlinearity of the DAC will increase and the linearity of the DAC will be degraded SUPPLEMENTAL APPLICATION MATERIAL For further information on CMOS multiplying D A converters the reader is referred to the following texts CMOS DAC Application Guide Publication Number G872b 8 1 89 available from Analog Devices Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs Application Note Publication Number E630c 5 3 86 available from Analog Devices Analog Digital Conversion Handbook available from Analog Devices REV B AD7541A OUTLINE DIMENSIONS Dimensions shown in inches and mm
10. apacitive coupling from the digital lines to the OUTI and OUT termi nals This should be minimized by screening the analog pins of the AD7541A Pins 1 2 17 18 from the digital pins by a ground track run between Pins 2 and 3 and between Pins 16 and 17 of the AD7541A Note how the analog pins are at one end of the package and separated from the digital pins by Vpp and GND to aid screening at the board level On chip capacitive coupling can also give rise to crosstalk from the digital to analog sections of the AD7541A particularly in circuits with high cur rents and fast rise and fall times Temperature Coefficients The gain tel of the AD7541Ah i cal value of 2 pp i of 2 LSBs and 0 8 LSBS re range When trim resistors RI and R2 are used to adjust full scale range the temperature coefficient of RI and R2 should also be taken into account The reader is referred to Analog Devices Application Note Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs Publication Number E630c 5 3 86 SINGLE SUPPLY OPERATION Figure 7 shows the AD7541A connected in a voltage switching mode OUTI is connected to the reference voltage and OUT2 is connected to GND The D A converter output voltage is available at the Vper pin Pin 17 and has a constant output impedance equal to Rrpr The feedback resistor Rpg is not used in this circuit Vpp 15V VREF 17 O Vout OV TO 10V AD7541A OUT2 G ND SYSTEM
11. ature All 5 5 ppm C max Typical Value Is 2 ppm C Output Leakage Current OUTI Pin 1 LK t5 10 nA max All Digital Inputs 0 V A B 5 10 nA max Scb T5 200 nA max OUT Pin 2 LK t5 10 nA max All Digital Inputs Vpp A B 5 10 nA max ST 5 200 nA max REFERENCE INPUT Input Resistance Pin 17 to GND All 7 18 7 18 kQ min max Typical Input Resistance 11 kQ Typical Input Resistance Temperature Coefficient 300 ppm C DIGITAL INPUTS Vin Input HIGH Voltage All 2 4 2 4 V min Vir Input LOW Voltage All 0 8 0 8 V max Im Input Current All 1 1 HA max Logic Inputs Are MOS Gates Im typ 25 C 1 nA Cm Input Capacitance All 8 8 pF max Vn 0V POWER SUPPLY AGain AVpp 082 T 96 DD POWER SUPPLY Vpp Range All 5 to 16 5 to 16 V min V max Accuracy Is Not Guaranteed Over This Range Ipp All 2 2 mA max All Digital Inputs Vu or V 100 500 HA max All Digital Inputs 0 V or Vpp AC PERFORMANCE CHARACTERISTICS These Characteristics are included for Design Guidance only and are not subject to test Vp 15 V Vy 10 V except where noted 0UTI OUT2 GND 0 V Output Amp is AD544 except where noted Ta Ta Parameter Version 25 C Tmn Tmax Units Test Conditions Comments PROPAGATION DELAY From Digital Input OUT 1 Load 100 Q Cexr 13 pF Change to 90 of Final Analog Output All 100 ns typ Digital Inputs 0 V to Vpp Or Vpp to 0 V DIGITAL TO ANALOG GLITCH Veer 0 V All
12. e can be adjusted by omitting RI and R2 and trimming the reference voltage magnitude C1 phase compensation 10 pF to 25 pF may be required for stability when using high speed amplifiers C1 is used to cancel the pole formed by the DAC internal feedback resistance and output capacitance at OUT Amplifier Al should be selected or trimmed to provide Vos 10 of the voltage resolution at Vour Additionally the ampli fier should exhibit a bias current which is low over the tempera ture range of interest bias current causes output offset at Vour equal to Ip times the DAC feedback resistance nominally 11 kO The AD544L is a high speed implanted FET input op amp with low factory trimmed Vos Vpp SEE TEXT ANALOG V V7 DIGITAL COMMON BIT 1 BIT 12 GROUND REFER TO TABLE 1 Figure 4 Unipolar Binary Operation Table I Recommended Trim Resistor Values vs Grades Trim Resistor JN AQ SD KNIBQITD Rl 100 Q 100 Q R2 470 330 Table II Unipolar Binarv Code Table for Circuit of Figure 4 Binarv Number in DAC MSB LSB Analog Output Vour 4095 1111 1111 1111 Vn 4006 2048 1000 0000 0000 Vn 4096 1 2 Vin a 0000 0000 0001 Vin 4096 0000 0000 0000 0 Volts REV B AD7541A BIPOLAR OPERATION 4 QUADRANT MULTIPLICATION Figure 5 and Table III illustrate the circuitry and code relation ship for bipolar operation With a dc reference positive or nega tive polarity the circ
13. pr 41 lowing improved endpoint li i T specificatio 1 Gain Error for all grades has been reduced with premium ORDERING GUIDE grade versions having a maximum gain error of 3 LSB Relative Gain 2 Gain Error temperature coefficient has been reduced to Temperature Accuracy Error Package 2 ppm C typical and 5 ppm C maximum Model Range Tmn to Tmax TA 25 C Options 3 Digital to analog charge injection energy for this new device AD7541AJN 0 C to 70 C 1 LSB 6 LSB N 18 is typically 20 less than the standard AD7541 part AD7541AKN 0 C to 70 C 1 2 LSB 1 LSB N 18 AD7541AJP 0 C to 70 C 1 LSB 6 P 20A 4 Latch up proof AD7541AKP 0 C to 70 C 1 2 LSB tl P 20A AD7541AKR 0 C to 70 C 1 2 LSB m Eis 5 nn di 7 laser MuR provides ee max AD7541AAQ 25 C to 85 C 1 LSB 6 LSB Q 18 differential nonlinearity for top grade devices over the operat AD7541ABQ 25 C to 85 C 1 2 LSB 1 LSB Q 18 ing temperature range vs 1 LSB on older 7541 types AD7541ASQ 55 C to 125 C 1 LSB 6 LSB Q 18 6 All grades are guaranteed monotonic to 12 bits over the AD7541ATQ 55 C to 125 C 1 2 LSB 1 LSB Q 18 Oneratinstermberan restange AD7541ASE 55 C to 125 C 1 LSB 6LSB E 20A p 8 temp En AD7541ATE 55 C to 125 C 1 2 LSB 1 LSB E 20A NOTES Analog Devices reserves the right to ship either ceramic D 18 or cerdip Q 18 hermetic packages 2To order MIL STD 883
14. s a stress rating only functional operation ofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods mav affect device reliabilitv Digital Input Voltage to GND OUT 1 OUT 2 to GND Power Dissipation Anv Package To 75 C Derates above 75 C 0 3 V Vpp 0 3 V 0 3 V Vpp 0 3 V Lead Temperature Soldering 10 secs CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD7541A features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING SAT 4 ESD SENSITIVE DEVICE wes TERMINOLOGY RELATIVE ACCURACY Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function It is measured after adjusting for zero and full scale and is expressed in of full scale range or sub multiples of 1 LSB DIFFERENT Differential change and a codes A specified differential nonlinearity E 1 LSB max over the operating temperature range insures monotonicity
15. sc 0014 36 259 0 030 0 76 PLANE 18 Lead SOIC R 18 0 4625 11 75 0 4469 11 35 l 18 0 2992 7 60 0 2914 7 40 0 4193 10 65 0 3937 10 00 PIN 1 0 1043 2 65 0 0291 0 74 0 0926 2 35 M 0 0098 0 25 9 a it gt H e 8 0 0500 1 27 0 0118 0 30 0 0500 0 0192 0 49 t oO 0 0157 940 TIT 0 0118 0 30 Ciy 2204 SEATING 0 0125 0 32 0 0040 0 10 Bgc 0 0138 0 35 PLANE 50091 0 23 REV B 7 L6 9 1 48129 V SA NI GILNIHd ww BDI C com AD
16. uit provides offset binary operation With an ac reference the circuit provides full 4 quadrant multiplication With the DAC loaded to 1000 0000 0000 adjust R1 for Vout 0 V alternatively one can omit RI and R2 and adjust the ratio of R3 to R4 for Vour 0 V Full scale trimming can be accomplished by adjusting the amplitude of Vper or by vary ing the value of R5 As in unipolar operation Al must be chosen for low Vos and low Ig R3 R4 and R5 must be selected for matching and track ing Mismatch of 2R3 to R4 causes both offset and full scale error Mismatch of R5 to R4 or 2R3 causes full scale error C1 phase compensation 10 pF to 50 pF may be required for sta bility depending on amplifier used ANALOG COMMON DIGITAL GROUND Table III Bipolar Code Table for Offset Binary Circuit of Figure 5 BIT 1 BIT 12 Binary Number in DAC MSB LSB Analog Output Vour 2047 1111 1111 1111 V 2048 1 1000 0000 0001 Vin 2048 1000 0000 0000 0 Volts 1 piii 1111 1111 Vi 2048 2048 0000 0000 0000 Vm 2048 REV B Figure 6 and Table IV show an alternative method of achieving bipolar output The circuit operates with sign plus magnitude code and has the advantage of giving 12 bit resolution in each quadrant compared with 11 bit resolution per quadrant for the circuit of Figure 5 The AD7592 is a fully protected CMOS changeover switch with data latches R4 and R5 should match each other to 0 01 to maintain the

ANALOG DEVICES AD7541A datasheet

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