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ANALOG DEVICES OP215 handbook(1)

1. 25 C i20 25 C 90 T LII E oo POSITIVE ay Ave 100 gt SUPPLY z NEGATIVE 2 u SUPPLY a 2 80 60 amp a gt a 50 m Ay 10 a 60 E 5 o a 40 2 1 2 tr 2 40 30 9 1 CORNER 20 FREQUENCY amp Ay 1 20 gt 10 0 0 1 0 10 100 1k 10k 100k 1M 10M 4k 10k 100k 1M 10M 1 10 100 1k 10k FREQUENCY Hz FREQUENCY Hz FREQUENCY Hz TPC 10 Power Supply Rejection vs TPC 11 Output Impedance vs TPC 12 Voltage Noise Density vs Frequency Frequency Frequency BASIC CONNECTIONS 20 0 1 15V iv 2N4416 0 15V Vout SUMMING MODE 0 1 _ Figure 3 Slew Rate Test Circuit pm ch AYE Vos CAN BE TRIMMED WITH POTENTIGMETERS RANGING FROM 10 1410 FOR MOST UNITS 5 WILL BE MINIMUM WHEN Vos IS ADJUSTED WITH A 100kO POTENTIOMETER Figure 4 Input Offset Voltage Nulling REV A APPLICATIONS INFORMATION Dynamic Operating Considerations As with most amplifiers care should be taken with lead dress component placement and supply de coupling in order to ensure stability For example resistors from the output to an input should be placed with the body close to the input to minimize pick up and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground A feedback pole is created when the feedback around any amplifier is resistive The parallel resistance and capacitance from the
2. input of the device usually the inverting input to ac ground sets the frequency of the pole In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin However if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the negative input of the op amp The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant 8 Lead CERDIP Z Suffix 0 055 1 4 0 005 0 13 MIN MAX rm 0 310 7 87 0 220 5 59 iu 0 100 2 54 BSC 0 405 10 29 MAX 0 320 8 13 0 290 7 37 0 060 1 52 0 200 5 08 0 015 0 38 MAX gt gt 0 1 0 200 5 08 5 81 0 125 3 18 x MIN 0 015 0 38 SEATING 7 0 015 0 38 0 023 0 58 0 070 1 78 PLANE 15 0 008 0 20 5 0 014 0 36 0 030 0 76 REV A BASIC CONNECTIONS FP OUTLIN DIMENSIONS 5 shown in inches and 100kQ 15V NOTES 1 125 C TO 150 C 2 RESISTORS ARE TYPE RN55D 1 Figure 5 Burn In Circuit 8 Lead Plastic DIP P Suffix 0 430 10 92 0 280 7 11 0 240 6 10 PIN 1 0 325 8 25 0 300 7 62 0 060 1 52 0 210 0 015 0 38 0
3. 5 4 MHz Product Closed Loop Bandwidth CLBW 1 13 12 MHz Setting Time ts To 0 01 2 3 2 4 ps 1 1 1 2 ps 1 0 Input Voltage Range Toas 10 14 8 V 10 2 11 5 10 1 11 5 V Common Mode CMRR Vem IVR 82 100 80 96 dB Rejection Ratio E G Grades Power Supply Rejection PSRR Vs 10V to 16 V 10 51 p V V Ratio 10V to 15 V 16 100 p V V Input Noise Voltage 0n fo 100 Hz 20 20 nV VHz Density fo 1 000 Hz 15 15 nV VHz Input Noise Current I fo 100 Hz 0 01 0 01 pA Hz Density fo 1 000 Hz 0 01 0 01 pA VHz Input Capacitance 3 pF NOTES Input bias current is specified for two different conditions The T 25 C specification is with the junction at ambient temperature the device operating specification is with the device operating in a warmed up condition at 25 C ambient The warmed up bias current value is correlated to the junction temperature value via the curves of Is versus T and Is versus PMI has a bias current compensation circuit that gives improved bias current and bias current over temperature versus standard JFET input op amps I and Ios are measured at Voy 0 Setting time is defined here for a unity gain inverter connection using 2 resistors It is the time required for the error voltage the voltage at the inverting input pin on the amplifier to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter See se
4. PMI has a bias current compensation circuit that gives improved bias current and bias current over temperature versus standard JFET input op amps Is and Ios are measured at Voy 0 Specifications are subject to change without notice REV A 3 215 ABSOLUTE MAXIMUM RATINGS Package Type Oya Orc Unit Supply Voltage OP2ISB DP3ISG 18 8 Hermetic DIP 7 134 12 C W Operating Temperature Range 8 Lead Plastic DIP P 96 37 C W OTIDE si prepa ana EE TOC to FTO G 0j4 is specified for worst case mounting conditions i e 0j is specified for OP215G 40 85 ds in socket for CaeDIP and P DIP packages a Maximum Junction Temperature T 150 C Differential Input Voltage 215 nee ga de 40 V PIN CONFIGURATION 215 eR Rede ada tapes 30 V Input Voltage OP2I5E o cR RE po IRURE aoe 20 V OP QU DG ana rto MRTASE RE OE prd exe t16V Output Short Circuit Duration Indefinite Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 60 sec 300 C Junction Temperature 65 C to 150 NOTES Absolute maximum ratings apply to packaged parts unless otherwise noted Unless otherwise specified the absolute maximum negative input voltage is equal to one volt m
5. 195 4 95 5 33 0 115 2 93 0 130 0 160 4 06 3 30 0 115 2 93 MIN we 0 015 0 381 0 022 0 558 0 070 1 77 SEATING 0 008 0 204 0 014 0 356 0 045 1 15 PLANE 215 Revision History Location Page Data Sheet changed from REV 0 to REV A Edits to GENERAL DESCRIPTION Seb o Us UR Re Re IRURE bie aed RD e cart ee o bec ce ace 1 Edits t ELECTRICAL CHARACTERISTICS secre baeo du v d dnb UR ada daar e RR p ee deas 2 3 Edits to ORDERING INFORMATION idee p rrt dite egeo d bn poet b eA le Aa P Rege 4 Bdits to PIN CONNECTIONS tee rat eec doe a eeepc er eg RR RR RC RABAT RO CR RO ined 4 Edits to ABSOLUTE MAXIMUM RATINGS 640004400440 60046 04 RR dere eee aa ark ace dead 4 Edits to PACKAGE TYPE iis ee deed ethane doe Wak OM ota e hee de bode P eq o A bae 4 Deleted WAFER TEST LIMITS de can ae hada Wain Be e omes ede a Wade dread sad ae cns e Sawa 4 Deleted DICE CHARACTERISTICS ade eked 4 Deleted TYPICAL ELECTRICAL CHARACTERISTICS ccc rmn 4 Edits to BUIRN IN CIRCUIT sin niione naa Rate ering dg d aR dae eae eo EL A 7 ww BDI C conh ALI 8 REV C02683 0 4 02 A PRINTED IN U S A
6. ANALOG DEVICES Dual Precision JFET Input Operational Amplifier FEATURES High Slew Rate 10 V ps Min Fast Settling Time 0 9 us to 0 1 Type Low Input Offset Voltage Drift 10 pV C Max Wide Bandwidth 3 5 MHz Min Temperature Compensated Input Bias Currents Guaranteed Input Bias Current 18 nA Max 125 C Bias Current Specified Warmed Up over Temperature Low Input Noise Current 0 01 pA Hz Type High Common Mode Rejection Ratio 86 dB Min Pin Compatible with Standard Dual Pinouts Models with MIL STD 883 Class B Processing Available GENERAL DESCRIPTION The OP215 offers the proven JFET input performance advantages of high speed and low input bias current with the tracking and convenience advantages of a dual op amp configuration Low input offset voltages low input currents and low drift are featured in these high speed amplifiers On chip zener zap trimming is used to achieve low Vos while a so bias current compensation AN a loj bias d at elevated temperature Thus the OP215 features an input bias current of 1 4 nA at 70 C ambient not junction temperature which greatly extends the application usefulness of this device Applications include high speed amplifiers for current output DACs active filters sample and hold buffers and photocell amplifiers For additional precision JFET op amps see the OP249 and Ape data R7 8 ARE ELECTRONICALLY ADJUSTED ON CHIP FOR
7. MINIMUM OFFSET VOLTAGE Figure 1 Simplified Schematic 1 2 OP215 REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2002 0P215 SPECIFICATIONS ELECTRICAL CHARACTERISTICS at V 15 V T 25 C unless otherwise noted OP215E OP215G Parameter Symbol Conditions Min Type Max Min Type Max Unit Input Offset Voltage Vos Rs 500 0 2 1 0 2 0 4 0 mV G Grade 2 5 6 0 mV Input Offset Current Ios T 25 C 3 50 3 100 pA Device Operating 5 100 5 200 pA Input Bias Current Ig 25 C 15 100 15 300 pA Device Operating 18 300 18 600 pA Input Resistance Rw 101 101 Q Large Signal Voltage Ayo Ry 2 150 500 50 200 V mV Gain Vo 10 V Output Voltage Swing Vo Ry 10 12 13 12 13 V Ry 2 11 12 7 11 V Supply Current Isy 6 0 8 5 7 0 10 0 mA Grade 7 0 12 0 mA Slew Rate SR 1 10 18 5 15 V s Gain Bandwidth GBW 3 5 5 7 3 0
8. Shift vs Frequency PEAK TO PEAK AMPLITUDE V 100K 1M 10M FREQUENCYG Hz TPC 7 Maximum Output Swing vs Frequency REV A TPC 2 Small Signal Transient Response 15V BANDWIDTH VARIATION 5 Vs lt 20V IS lt 5 CLOSED LOOP BANDWIDTH Ay GAIN BANDWIDTH PRODUCT BANDWIDTH MHz 50 25 0 25 50 75 100 125 TEMPERATURE TPC 5 Bandwidth vs Temperature 70 60 SLEW RATE V us 0 50 25 0 25 50 75 100 125 AMBIENT TEMPERATURE C TPC 8 Slew Rate vs Temperature OUTPUT VOLTAGE SWING FROM V 0 0 5 1 0 1 5 2 0 2 5 SETTLING TIME ps TPC 3 Settling Time OPEN LOOP VOLTAGE GAIN dB 1 10 100 41k 10k 100k 1M 10M 100M FREQUENCY Hz TPC 6 Open Loop Frequency Response 100 80 60 40 20 COMMON MODE REJECTION RATIO dB 0 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY Hz TPC 9 Common Mode Rejection Ratio vs Frequency 120 100 140 110 Ta 25 C Vg 15V Vg 15V m 25 25 9 100
9. ore positive than the negative power supply voltage ORDERING INFORMATION Package Temperature T4 25 C Model Type Range Vos Max mV OP215bEZ 8 Lead CerDIP COM 1 0 OP215GP 8 Lead Plastic DIP XIND 6 0 SMD Part Number ADI Equivalent 5962 8853801GA OP215AJMDA 5962 8853801PA OP215AZMDA 5962 8838032A OP215BRCMDA NOTES Burn in is available on commercial and industrial temperature range parts in CerDIP and plastic DIP packages Not for new design obsolete April 2002 CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although WARN N G S the OP215 features proprietary ESD protection circuitry permanent damage may occur on devices Sp 4 subjected to high energy electrostatic discharges Therefore proper ESD precautions are B ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality 4 REV A GAIN dB Aedes ce Typical Performance Characteristics OP215 EE ERES Tom it TPC 1 Large Signal Transient Response 90 100 110 120 130 140 150 160 170 180 190 200 PHASE SHIFT Degrees 1M 10M 100M FREQUENCY Hz TPC 4 Closed Loop Bandwidth and Phase
10. tting time test circuit 5Sample tested Specifications are subject to change without notice REV A 215 SPECIFICATIONS ELECTRICAL CHARACTERISTICS otherwise noten SS OP215E OP215G Parameter Symbol Conditions Min Type Max Min Type Max Unit Input Offset Voltage Vos Rs 50 Q 0 4 1 65 3 5 8 0 mV Average Input Offset Voltage Drift Without External Trim TCVog 3 15 6 With External Trim TCVosn Rp 100 3 4 Input Offset Current Ios T 70 C 0 06 0 45 0 08 0 65 nA 70 C 0 08 0 80 0 10 1 2 nA Device Operating Input Bias Current Is T 70 C 012 0 70 0 14 0 9 nA 70 C 0 16 1 40 0 19 1 8 nA Device Operating Input Voltage Range IVR 10 2 14 7 10 1 14 7 V 10 2 11 4 10 1 11 3 V Common Mode CMRR Vem IVR 80 98 76 94 dB Rejection Ratio Power Supply Rejection PSRR Vs 10Vto l6V 13 100 Ratio Vs 10V to 15 V 20 159 p V V Large Signal 0 180 130 V mV Output Voltage Swing o 10 12 13 12 13 V NOTES Sample tested Input bias current is specified for two different conditions The T 25 C specification is with the junction at ambient temperature the Device Operating specification is with the device operating in a warmed up condition at 25 C ambient The warmed up bias current value is correlated to the junction temperature value via the curves of Is versus T and Is versus T4

ANALOG DEVICES OP215 handbook(1)

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