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ANALOG DEVICES ADF4360-1 handbook

1. 04414 009 E 04414 006 100 1000 10k 100k 1M 10 FREQUENCY OFFSET Hz 1MHz 0 5MHz 2250MHz 0 5MHz 1MHz Figure 6 VCO Phase Noise 1125 MHz Figure 9 Reference Spurs at 2250 MHz Divide by 2 Enabled 200 kHz PFD 10 kHz Loop Bandwidth 1 MHz Channel Spacing 25 kHz Loop Bandwidth Rev B Page 8 of 24 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 10 SW1 and SW2 are normally closed switches SW3 is normally open When power down is initiated SW3 is closed and SW1 and SW2 are opened This ensures that there is no loading of the REFw pin on power down POWER DOWN CONTROL TO R COUNTER z o ro 04414 010 Figure 10 Reference Input Stage PRESCALER P P 1 The dual modulus prescaler P P 1 along with the A and B counters enables the large division ratio N to be realized BP A The dual modulus prescaler operating at CML levels takes the clock from the VCO and divides it down to a manage able frequency for the CMOS A and B counters The prescaler is programmable It can be set in software to 8 9 16 17 or 32 33 and is based on a synchronous 4 5 core Theregis a minimum divide ratio possible for fully AMA output frequencies this minimum is determined by P the preScaler valuesand is given by P P A AND B COUNTERS The A and B CMOS counters combine with the dual mod
2. Wo 3 3 V P 32 gt These characteristics are guaranteed for VCO Core Power 15 mA 6 Jumping from 2 05 GHz to 2 45 GHz PFD frequency 200 kHz loop bandwidth 10 kHz 7 Using 50 resistors to Vvco into a 50 load For tuned loads see the Output Matching section 8 The noise of the VCO is measured in open loop conditions The synthesizer phase noise floor is estimated by measuring the in band phase noise at the output of the VCO and subtracting 20 log N where N is the N divider value 10 The phase noise is measured with the EVAL ADF4360 xEB1 Evaluation Board and the HP8562E Spectrum Analyzer The spectrum analyzer provides the for the synthesizer offset frequency 1 kHz 1 frein 10 MHz fero 200 kHz N 12500 Loop B W 10 kHz 12 10 MHz fero 1 MHz N 2400 Loop B W 25 kHz 13 The spurious signals are measured with the EVAL ADF4360 xEB1 Evaluation Board and the HP8562E Spectrum Analyzer The spectrum analyzer provides the REFin for the synthesizer frerour 10 MHz 0 dBm 1 WA D ALI Rev B Page 4 of 24 ADF 4360 1 TIMING CHARACTERISTICS DVpp 3 3 V 10 DGND 0 V 1 8 V and 3 V logic levels used Ta Tus to Tmax unless otherwise noted Table 2 Parameter Limit at Tmn to Tmax B Version Unit Test Conditions Comments t 20 ns min LE Setup Time t 10 ns min DATA to CLOCK Setup Time ts 10 ns min DATA to CLOCK Hold Time ta 25 n
3. Tmn to Tmax unless otherwise noted Table 1 Parameter BVersion Unit Conditions Comments REFin CHARACTERISTICS REFin Input Frequency 10 250 MHz min max For f lt 10 MHz use a dc coupled CMOS compatible square wave slew rate gt 21 V us REF Input Sensitivity 0 7 p p min max AC coupled AVop V max CMOS compatible REF Input Capacitance 5 0 pF max REFin Input Current 100 max PHASE DETECTOR Phase Detector Frequency 8 MHz max CHARGE PUMP lce Sink Source With 4 7 High Value 2 5 mA typ Low Value 0 312 mA typ Rser Range 2 7 10 kQ lc 3 State Leakage Current 0 2 nA typ Sink and Source Current Matching 2 typ 1 25 V lt lt 2 5 V lce vs Vce 1 5 96typ 1 25 V lt Vo lt 2 5 V Ice vs Temperature 2 96typ 2 0 V LOGIC INPUTS Input High Voltage 1 5 j V min Vint Input Low Voltage i 0 6 V max i Input Current d Input Capacitance 3 0 pF max LOGIC OUTPUTS Output High Voltage DVpp 0 4 Vmin CMOS output chosen lon Output High Current 500 max Output Low Voltage 0 4 V max lo 500 pA POWER SUPPLIES AVop 3 0 3 6 V min V max DVpp AVop Alpp 10 mA typ 2 5 mA typ lvco 24 0 mA typ 15 mA 35 110 typ RF output stage is programmable Low Power Sleep 7 typ RF OUTPUT CHARACTERISTICS VCO Output Frequency 2050 2450 M
4. DB22 DB18 DB17 DB16 DB15 DB14 DB13 DB12 086 085 Uu D DBO P2 P1 CPI5 CPI3 CPI2 PL1 M2 M1 C1 0 N COUNTER LATCH 13 BIT B COUNTER 5 BIT A COUNTER 2 DB11 DB10 DBs DB7 DBO B4 B3 C1 0 R COUNTER LATCH ANTI BACKLASH CONTROL PULSE 14 BIT REFERENCE COUNTER BITS WIDTH LOCK DETECT PRECISION DB23 DB22 DB21 DB16 DB15 DBO RSV RSV 5 2 BSC1 LDP ABP2 C1 1 04414 016 Rev B Page 12 of 24 Table 7 Control Latch PRESCALER VALUE CURRENT SETTING 2 OUTPUT POWER LEVEL MUXOUT CONTROL CURRENT SETTING 1 CP GAIN PHASE DETECTOR POLARITY COUNTER RESET ADF 4360 1 CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB6 DB5 DBO P2 CPI5 CPI M2 M1 CPI2 a PHASE DETECTOR POLARITY NEGATIVE POSITIVE CHARGE PUMP CP OUTPUT 0 NORMAL 1 THREE STATE CPG CP GAIN 0 CURRENT SETTING 1 1 CURRENT SETTING 2 gt MTLD MUTE TILL LOCK DETECT 0 DISABLED 1 ENABLED OUTPUT POWER LEVEL PC1 2 0 C1 0 CORE
5. If vias are used they should be incorporated in the thermal pad at a 1 2 mm pitch grid The via diameter should be between 0 3 mm and 0 33 mm and the via barrel should be plated with 1 ounce of copper to plug the via The user should connect the printed circuit thermal pad to AGND This is internally connected to AGND OUTPUT MATCHING There are a number of ways to match the output of the ADF4360 1 for optimum operation themost basic 1510 use 50 resistor to Vvco A dc bypass NYA Y 00 pF islcon2 nected in series as shown Figure 21 Because the resistor is not frequency dependent this provides a good broadband match The output power in this circuit typically gives 6 dBm output power into a 50 Q load Vvco 510 100pF RFour 500 04414 025 Figure 21 Simple ADF4360 1 Output Stage A better solution is to use a shunt inductor acting as an RF choke to Vvco This gives a better match and hence more output power Additionally a series inductor is added after the dc bypass capacitor to provide a resonant LC circuit This tunes the oscillator output and provides approximately 10 dB addi tional rejection of the second harmonic The shunt inductor needs to be a relatively high value 240 nH Experiments have shown that Figure 22 provides an excellent match to 50 Q over the operating range of the ADF4360 1 This gives approximately 4 dBm output power across the frequency range of the ADF4360 1 Both single ended arc
6. The low pass filter was designed using ADIsimPLL for a channel spacing of 8 MHz and an open loop bandwidth of 40 kHz The maximum PFD frequency of the ADF4360 1 is 8 MHz Because using a larger PFD frequency allows users to use a smaller N the in band phase noise is reduced to as low as possible 99 dBc Hz The 40 kHz bandwidth is chosen to be just greater than the point at which the open loop phase noise of the VCO is 99 dBc Hz thus giving the best possible inte grated noise The typical rms phase noise 100 Hz to 100 kHz of the LO in this configuration is 0 3 The reference frequency is from a 16 MHz TCXO from Fox thus an R value of 2 is pro grammed Taking into account the high PFD frequency and its effect on the band select logic the band select clock divider is enabled In this case a value of 8 is chosen A very simple pull up resistor and dc blocking capacitor complete the RF output stage LOCK Vypp DETECT O RFoy7B 5 0 990999 69 SPI COMPATIBLE SERIAL BUS 04414 022 Figure 18 Fixed Frequency LO INTERFACING The ADF4360 family has a simple SPI compatible serial inter face for writing to the device CLK DATA and LE control the data transfer When LE goes high the 24 bits that are clocked into the appropriate register on each rising edge of CLK get transferred to the appropriate latch See Figure 2 for the timing diagram and Table 5 for the latch truth table
7. lock time depends on the value of capacitance on the Cx pin which is 5 ms for 10 uF capacitance The smaller capacitance of 440 nF on this pin enables lock times of 600 us The N counter value cannot be changed while the part is in power down because it may not lock to the correct frequency on power up If it is updated the correct programming se quence for the part after power up is to the R counter latch followed by the control latch and finally the N counter latch with the required interval between the control latch and N counter latch as described in the Initial Power Up section Rev B Page 17 of 24 ADF 4360 1 CONTROL LATCH With C2 C1 0 0 the control latch is programmed Table 7 shows the input data format for programming the control latch Prescaler Value In the ADF4360 family P2 and P1 in the control latch set the prescaler values Power Down DB21 PD2 and DB20 PD1 provide programmable power down modes In the programmed asynchronous power down the device powers down immediately after latching a 1 into Bit PD1 with the condition that PD2 has been loaded with a 0 In the pro grammed synchronous power down the device power down is gated by the charge pump to prevent unwanted frequency jumps Once the power down is enabled by writing a 1 into Bit PD1 on the condition that a 1 has also been loaded to PD2 the device will go into power down on the second rising edge of the R counter output
8. INDICATOR 0 80 MAX 100 12 0 65 0 85 0 05 MAX 0 08 SEATING 29 PLANE 0 0 20 REF ADF 4360 1 0 60 MAX 2 50 REF COMPLIANT TO STANDARDS MO 220 VGGD 2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 24 24 Lead Lead Frame Chip Scale Package VO LFCSP 4mm x 4 Body Very Thin Quad CP 24 2 Dimensions shown in millimeters ORDERING GUIDE Model Temperature lt Frequency Range Package Option ADF4360 1BCP Hodos d y 2050 MHz 19 2450 MHz i CP 24 2 ADF4360 1BCPRL 40 C to 85 C 0s0 MHI to 3450 MHZ CP 24 2 ADF4360 1BCPRL7 40 to 85 C 2050 MHz to 2450 MHz CP 24 2 ADF4360 1BCPZ A40 C to 85 C 2050 MHz to 2450 MHz CP 24 2 ADF4360 1BCPZRL 40 to 85 C 2050 MHz to 2450 MHz CP 24 2 ADF4360 1BCPZRL7 40 to 85 C 2050 MHz to 2450 MHz CP 24 2 EVAL ADF4360 1EB1 Evaluation Board 17 Pb free part Rev B Page 23 of 24 ADF 4360 1 NOTES i AL Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips PC Patent Rights to use these components in an system provided that the system conforms to the Standard Specification as defined by Philips 2004 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their
9. POWER LEVEL 5mA 10mA 15mA 20mA COUNTER OPERATION NORMAL R A B COUNTERS HELD IN RESET OUTPUT CE PIN PD2 CURRENT POWER INTO 500 USING 500 TO Vyco 3 5mA 13dBm 5 0mA 10 5dBm 7 5mA 8dBm 11 0mA 6dBm MODE 0 1 1 1 PRESCALER VALUE 8 9 16 17 32 33 32 33 04414 017 ASYNCHRONOUS POWER DOWN NORMAL OPERATION ASYNCHRONOUS POWER DOWN SYNCHRONOUS POWER DOWN Rev B Page 13 of 24 THREE STATE OUTPUT DIGITAL LOCK DETECT ACTIVE HIGH N DIVIDER OUTPUT DVpp R DIVIDER OUTPUT N CHANNEL OPEN DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND ADF 4360 1 Table 8 N Counter Latch CT 13 BIT B COUNTER 5 BIT A COUNTER ES X 2 gt 0 an DB8 DB7 DB6 DB5 DBO m o C1 0 THIS BIT IS NOT USED BY THE DEVICE AND IS ADON T CARE BIT A COUNTER DIVIDE RATIO 0 1 2 3 B COUNTER DIVIDE RATIO NOT ALEOWED a NOT ALLOWED NOT ALLOWED F4 FUNCTION LATCH FASTLOCK ENABLE CP GAIN OPERATION 0 0 CHARGE PUMP CURRENT SETTING 1 IS PERMANENTLY USED 0 1 CHARGE PUMP CURRENT SETTING 2 IS PERMANENTLY USED N BP A PIS PRESCALER VALUE SET IN THE CONTROL LATCH B MUST BE GREATER THAN OR EQUAL TO A FOR CONTINUOUSLY ADJACENT VALUES OF x AT THE OUTPUT IS 2 04414 018 DIV2 DIVIDE BY 2 0 FUNDAMENT
10. POWER UP PEE DATA R COUNTER CONTROL LATCH DATA LATCH DATA 1 N COUNTER LATCH DATA REQUIRED INTERVAL CONTROL LATCH WRITE TO N COUNTER LATCH WRITE 04414 020 Figure 16 ADF4360 1 Power Up Timing Rev B Page 16 of 24 Hardware Power Up Power Down If the ADF4360 1 is powered down via the hardware using the CE pin and powered up again without any change to the N counter register during power down it locks at the correct fre quency because the part is already in the correct frequency band The lock time depends on the value of capacitance on the Cy pin which is lt 5 ms for 10 capacitance The smaller ca pacitance of 440 nF on this pin enables lock times of lt 600 us The N counter value cannot be changed while the part is in power down because it may not lock to the correct frequency on power up If it is updated the correct programming se quence for the part after power up is to the R counter latch followed by the control latch and finally the N counter latch with the required interval between the control latch and N counter latch as described in the Initial Power Up section ADF4360 1 Software Power Up Power Down If the ADF4360 1 is powered down via the software using the control latch and powered up again without any change to the N counter latch during power down it locks at the correct fre quency because it is already in the correct frequency band The
11. Vpp lop 2 5mA PFD FREQUENCY 200kHz LOOP BANDWIDTH 10kHz RES BANDWIDTH 10Hz VIDEO BANDWIDTH 10Hz SWEEP 1 9 SECONDS AVERAGES 10 OUTPUT POWER dB OUTPUT POWER dB 04414 004 04414 007 1k 10k 100k 1M 10 FREQUENCY OFFSET Hz 2kHz 1kHz 2250MHz 1kHz 2kHz Figure 4 Open Loop VCO Phase Noise Figure 7 Close In Phase Noise at 2250 MHz 200 kHz Channel Spacing Vpp Vyco 3V 2 5mA PFD FREQUENCY 200kHz LOOP BANDWIDTH 10kHz RES BANDWIDTH 1kHz VIDEO BANDWIDTH 1kHz SWEEP 1 3 SECONDS AVERAGES 1 OUTPUT POWER dB OUTPUT POWER dB 04414 008 04414 005 5 100 1000 10k 100k 1M 10 FREQUENCY OFFSET Hz 200kHz 100kHz 2250MHz 100kHz 200kHz Figure 8 Reference Spurs at 2250 MHz Figure 5 VCO Phase Noise 2250 MHz 200 kHz PFD 10 kHz Loop Bandwidth 200 kHz Channel Spacing 10 kHz Loop Bandwidth Vpp Vyco Icp 2 5mA PFD FREQUENCY 1MHz LOOP BANDWIDTH 25kHz RES BANDWIDTH 10kHz VIDEO BANDWIDTH 10kHz SWEEP 1 9 SECONDS AVERAGES 10 OUTPUT POWER dB OUTPUT POWER dB
12. after LE goes high When the CE pin is low the device is immediately disabled regardless of the state of PD1 or PD2 When a power down is activated either in synchronous or asynchronous mode the following events occur All active dc current paths are rentoved e The R N and timeout counters are forced to their load state conditions The charge pump is forced into three state mode The digital lock detect circuitry is reset The RF outputs are debiased to a high impedance state The reference input buffer circuitry is disabled The input register remains active and capable of loading and latching data Charge Pump Currents CPI3 2 and CPI1 in the ADF4360 family determine Current Setting 1 CPI6 CPI5 and CPI4 determine Current Setting 2 See the truth table in Table 7 Output Power Level Bits PL1 and PL2 set the output power level of the VCO See the truth table in Table 7 Mute Till Lock Detect DB11 of the control latch in the ADF4360 family is mute till lock detect bit This function when enabled ensures that the RF outputs are not switched on until the PLL is locked CP Gain DB10 of the control latch in the ADF4360 family is the charge pump gain bit When it is programmed to a 1 Current Setting 2 is used When it is programmed to a 0 Current Setting 1 is used Charge Pump Three State This bit puts the charge pump into three state mode when programmed to a 1 It should be
13. loop bandwidth of 25 kHz The frequency range of the ADF4360 1 2 05 GHz to 2 45 GHz makes it ideally suited for implementation of a Bluetooth transceiver MODULATED DIGITAL DATA DETECT 0 0 9 20 DVpp AVpp CE MUXOUT Vrune 7 DGND RFoyrB 9 999699 69 ITTI SPI COMPATIBLE SERIAL BUS The LO ports of the AD8349 can be driven differentially from the complementary RFourA and RFourB outputs of the ADF4360 1 This gives a better performance than a single ended LO driver and eliminates the often necessary use of a balun to convert from a single ended LO input to the more desirable differential LO inputs for the AD8349 The typical rms phase noise 100 Hz to 100 kHz of the LO in this configuration is 1 09 The AD8349 accepts LO drive levels from 10 dBm to 0 dBm The optimum LO power can be software programmed on the ADF4360 1 which allows levels from 13 dBm to 6 dBm from each output The RF output is designed to drive a 50 O load but must be ac coupled as shown in Figure 17 If the I and Q inputs are driven in quadrature by 2 V p p signals the resulting output power from the modulator will be approximately 2 dBm 330pF 1 5pF 3 9nH PHASE LOIN SPLITTER AN 1 5pF 3 9nH 04414 021 Figure 17 Direct Conversion Modulator Rev B Page 20 of 24 FIXED FREQUENCY LO Figure 18 shows the ADF4360 1 used as a fixed frequency LO at 2 2 GHz
14. respective owners www ana l 0 g com DEVICES Rev Page 24 of 24
15. the transient behavior of the ADF4360 1 during initial power up to have settled Table 10 Cx Capacitance vs Interval and Phase Noise During initial power up a write to the control latch powers up the part and the bias currents of the VCO begin to settle If these currents have not settled to within 10 of their steady state value and if the N counter latch is then programmed the VCO may not oscillate at the desired frequency which does not allow the band select logic to choose the correct frequency band and the ADF4360 1 may not achieve lock If the recommended interval is inserted and the N counter latch is programmed the band select logic can choose the correct frequency band and the part locks to the correct frequency The duration of this interval is affected by the value of the capacitor on the Cx pin Pin 14 This capacitor is used to reduce the close in noise of the ADF4360 1 VCO The recom mended value of this capacitor is 10 uF Using this value requires an interval of gt 5 ms between the latching in of the control latch bits and latching in of the N counter latch bits If a shorter delay is required this capacitor can be reduced A slight phase noise penalty is incurred by this change which is explained in the Table 10 Cn Value Recommended Interval between Control Latch and N Counter Latch Open Loop Phase Noise 10 kHz Offset 10 uF 25ms 440 nF gt 600 us 85 dBc VV 84 dBC
16. AL OUTPUT 1 DIVIDE BY 2 DIVSEL DIVIDE BY 2 SELECT PRESCALER INPUT 0 FUNDAMENTAL OUTPUT SELECTED 1 DIVIDE BY 2 SELECTED Rev B Page 14 of 24 Table 9 R Counter Latch a a gt gt tc tc o o tc tc ANTI BACKLASH 14 BIT REFERENCE COUNTER ADF4360 1 CONTROL BITS DB23 DB22 DB21 0816 0815 DB11 DB10 THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON T CARE BITS RSV RSV BSC2 TEST MODE BIT SHOULD BE SET TOO FOR NORMAL OPERATION R10 R9 DIVIDE RATIO ANTIBACKLASH PULSE WIDTH LOCK DETECT PRECISION 3 0ns 1 3ns 6 0ns 3 0ns THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN UST OCCUR BEFORE LOCK DETECT IS SET 15ns BAND SELECT CLOCK DIVIDER 1 2 4 8 04414 019 Rev B Page 15 of 24 Not Allowed ADF 4360 1 POWER UP Power Up Sequence The correct programming sequence for the ADF4360 1 after power up is 1 R counter latch 2 Control latch 3 N counter latch Initial Power Up Initial power up refers to programming the part after the application of voltage to the AVpp DVpp and CE pins On initial power up an interval is required between programming the control latch and programming the N counter latch This interval is necessary to allow
17. ANALOG DEVICES Integrated Synthesizer and VCO ADF 4360 1 FEATURES GENERAL DESCRIPTION Output frequency range 2050 MHz to 2450 MHz The ADF4360 1 is a fully integrated integer N synthesizer and Divide by 2 output voltage controlled oscillator VCO The ADF4360 1 is 3 0 V to 3 6 V power supply designed for a center frequency of 2250 MHz In addition there 1 8 V logic compatibility is a divide by 2 option available whereby the user gets an RF Integer N synthesizer output of between 1025 MHz and 1225 MHz Programmable dual modulus prescaler 8 9 16 17 32 33 Programmable output power level Control of all the on chip registers is through a simple 3 wire 3 wire serial interface interface The device operates with a power supply ranging from Analog and digital lock detect 3 0 V to 3 6 V and can be powered down when not in use Hardware and software power down mode APPLICATIONS Wireless handsets DECT GSM PCS DCS WCDMA Test equipment Wireless LANs CATV equipment FUNCTIONAL BLOCK DIAGRAM AVpp DVpp CE Rset Q Q O O ADE4360 i MULTIPLEXER MUXOUT REF COUNTER CLK D LEO PUMP PHASE COMPARATOR VTUNE Cc O Cn INTEGER REGISTER RFourA OUTPUT STAGE 13 BIT B COUNTER Q RFourB PRESCALER LOAD 1 LOAD 4 5 BIT A COUNTER E DIVSEL 1 x ul al a E 5 ja gt DI
18. Hz min max Icore 15 MA VCO Sensitivity 57 MHz V typ Lock Time 400 Us typ To within 10 Hz of final frequency Frequency Pushing Open Loop 6 MHzN typ Frequency Pulling Open Loop 15 kHz typ Into 2 00 VSWR load Harmonic Content Second 20 dBc typ Harmonic Content Third 35 dBc typ Output Power 13 6 dBm typ Programmable in 3 dB steps See Table 7 Output Power Variation 3 dB typ For tuned loads see the Output Matching section VCO Tuning Range 1 25 2 5 V min max Rev B Page 3 of 24 ADF 4360 1 Parameter BVersion Unit Conditions Comments NOISE CHARACTERISTICS gt VCO Phase Noise Performance 110 dBc Hz typ 100 kHz offset from carrier 130 dBc Hz typ 1 MHz offset from carrier 141 dBc Hz typ 9 3 MHz offset from carrier 148 dBc Hz typ 10 MHz offset from carrier Synthesizer Phase Noise Floor 172 dBc Hz typ 25 kHz PFD frequency 163 dBc Hz typ 200 kHz PFD frequency 147 dBc Hz typ 8 MHz PFD frequency In Band Phase Noise 81 dBc Hz typ 1 kHz offset from carrier RMS Integrated Phase Error 0 72 Degrees typ 100 Hz to 100 kHz Spurious Signals due to PFD Frequency 70 dBc typ Level of Unlocked Signal with MTLD Enabled 38 dBm typ 1 Operating temperature range is 40 C to 85 C Guaranteed by design Sample tested to ensure compliance 3 is internally modified to maintain constant loop gain over the frequency range Ta 25 AVpp
19. The maximum allowable serial clock rate is 20 MHz This means the maximum update rate possible is 833 kHz or one update every 1 2 us This is certainly more than adequate for systems that will have typical lock times in hundreds of micro seconds ADF4360 1 ADuC812 Interface Figure 19 shows the interface between the ADF4360 family and the ADuC812 MicroConverter Because the ADuC812 is based on an 8051 core this interface can be used with any 8051 based microcontroller The MicroConverter is set up for SPI master mode with CPHA 0 To initiate the operation the I O port driving LE is brought low Each latch of the ADF4360 family needs a 24 bit word which is accomplished by writing three 8 bit bytes from the MicroConverter to the device When the third byte is written the LE input should be brought high to complete the transfer SCLOCK SCLK MOSI SDATA ADuC812 Ports Lock Detect 04414 023 Figure 19 ADuC8 12 to ADF4360 x Interface T O port lines on the ADuC812 are also used to control power down CE input and detect lock MUXOUT configured as lock detect and polled by the port input When operating in the described mode the maximum SCLOCK rate of the ADuC812 Thiy means that hin rate at which the out p tfr gdency be changed is 166 kHz ADSP 21xx Interface Figure 20 shows the interface between the ADF4360 family and the ADSP 21xx digital signal processor The ADF4360 family needs a 24 bit s
20. VSEL 2 E O AGND DGND CPGND Figure 1 Rev B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A or otherwise under any patent or patent rights of Analog Devices Trademarks and Tel 781 329 4700 www analog com registered trademarks are the property of their respective owners Fax 781 326 8703 2004 Analog Devices Inc All rights reserved ADF 4360 1 TABLE OF CONTENTS Specifications uere t REN N ette ds 3 Timing Characteristics iet teet 5 Absolute Maximum Ratings seen 6 Transistor Co nt iie berti ee 6 ESD Caution iiceeieteneseitenteene teint 6 Pin Configuration and Function 5 7 Typical Performance Characteristics 8 Carcuit IDDeScriptlOn ica iecit tb erbe mers 9 Reference Input Section 9 Prescaler P P 3E ys te 9 A and B Counters tente 9 aeu 9 9 MUXOUT and Lock Detect s ar ar a 10 Input Sh
21. ay ele ment that controls 6f the antibacklash pulse This pulse ensures that there is zone in PFD transfer function and minimizes phase noise and reference spurs Two bits in the R counter latch ABP2 and ABPI control the width of the pulse see Table 9 VP CHARGE PUMP _ocP CPGND R DIVIDER N DIVIDER CP OUTPUT Figure 12 PFD Simplified Schematic and Timing In Lock 04414 012 Rev B Page 9 of 24 ADF 4360 1 MUXOUT AND LOCK DETECT The output multiplexer on the ADF4360 family allows the user to access various internal points on the chip The state of MUXOUT is controlled by M3 M2 and M1 in the function latch The full truth table is shown in Table 7 Figure 13 shows the MUXOUT section in block diagram form Lock Detect MUXOUT can be programmed for two types of lock detect digital and analog Digital lock detect is active high When LDP in the R counter latch is set to 0 digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns With LDP set to 1 five consecutive cycles of less than 15 ns phase error are required to set the lock detect It stays set high until a phase error greater than 25 ns is detected on any subse quent PD cycle The N channel open drain analog lock detect should be oper ated with an external pull up resistor of 10 kO nominal When lock has been detected the output wil
22. erial word for each latch write The easiest way to accomplish this using the ADSP 21xx family is to use the autobuffered transmit mode of operation with alternate fram ing This provides a means for transmitting an entire block of serial data before an interrupt is generated ADSP 21xx yo Porte 04414 024 Figure 20 ADSP 21xx to ADF4360 x Interface Set up the word length for 8 bits and use three memory loca tions for each 24 bit word To program each 24 bit latch store the 8 bit bytes enable the autobuffered mode and write to the transmit register of the DSP This last operation initiates the autobuffer transfer Rev B Page 21 of 24 ADF 4360 1 PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The leads on the chip scale package CP 24 are rectangular The printed circuit board pad for these should be 0 1 mm longer than the package lead length and 0 05 mm wider than the package lead width The lead should be centered on the pad to ensure that the solder joint size is maximized The bottom of the chip scale package has a central thermal pad The thermal pad on the printed circuit board should be at least as large as this exposed pad On the printed circuit board there should be a clearance of at least 0 25 mm between the thermal pad and the inner edges of the pad pattern to ensure that short ing is avoided Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package
23. hitectures can be examined using the EVAL_ADF4360 1EB1 evaluation board Vvco 47nH 1 5pF 3 9nH RFour n 500 Figure 22 Optimum ADF4360 1 Output Stage 044 14 026 If the user does not need the differential outputs available on the ADF4360 1 the user may either terminate the unused out put or combine both outputs using a balun The circuit in Figure 23 shows how best to combine the outputs Vvco 3 6nH RFoyrB 15 04414 027 Figufe 23 Balun f r Combinihig ADF4360 1 RF Outputs The circuit in Figure 23 is a lumped lattice type LC balun It is designed for a center frequency of 2 2 GHz and outputs 1 0 dBm at this frequency The series 1 nH inductor is used to tune out any parasitic capacitance due to the board layout from each input and the remainder of the circuit is used to shift the output of one RF input by 90 and the second by 90 thus combining the two The action of the 3 6 nH inductor and the 1 5 pF capacitor accomplish this The 47 nH is used to provide an RF choke in order to feed the supply voltage and the 10 pF capacitor provides the necessary dc block To ensure good RF performance the circuits in Figure 22 and Figure 23 were im plemented with Coilcraft 0402 0603 inductors and AVX 0402 thin film capacitors Alternatively instead of the LC balun shown in Figure 23 both outputs may be combined using a 180 rat race coupler Rev B Page 22 of 24 OUTLINE DIMENSIONS PIN 1
24. ift MM B me h 10 REVISION HISTORY 12 04 Rev A to Rev B Updated Format sei epe PPI Universal Changes to Specifications 3 Changes to the Timing Characteristics 5 Changes to the Power Up Section sse 16 Added Table 10 16 Added Figure 16 16 Changes to Ordering Guide 2523 Updated Outline Dimensions 23 6 04 Data Sheet Changed from Rev 0 to Rev A Changes to Specifications sse 3 Chianges to Table tentes 12 Chariges to Table 7 entrer ent ener optet reete reed 13 Changes to 15 8 03 Revision 0 Initial Version Meo 10 Output Stage iei eR Ri EEEE 11 Latch Structure 2 ettet toe e ned iaa 12 Powet Up c uiii RES RICE RHET 16 Control Latch c taste ee e eet 18 Ni Counter Latcb eee RE 19 R Counter Latcb one en HIERRO 19 20 Direct Conversion Modulator sss 20 Fixed Frequency LO 21 Interfacing oque E 21 PCB Design Guidelines for Chip Scale Package 22 Output Matching gen tierce pte pene 22 Outline Dimensions 23 t Ordering Guide E Met 23 Rev Page 2 of 24 SPECIFICATIONS Vvco 3 3 V 10 DGND 0 V Ta ADF 4360 1
25. in bit When this is programmed to 1 Current Setting 2 is used When programmed to 0 Current Setting 1 is used This bit can also be programmed through DB10 of the control latch The bit will always reflect the latest value written to it whether this is through the control latch or the N eeunterdatcha Divide by 2 1822 is divide by 2 When set to 1 the output divide by 2 function is chosen When it is set to 0 normal operation occurs Divide by 2 Select DB23 is the divide by 2 select bit When programmed to 1 the divide by 2 output is selected as the prescaler input When set to 0 the fundamental is used as the prescaler input For exam ple using the output divide by 2 feature and a PFD frequency of 200 kHz the user will need a value of N 12 000 to generate 1 2 GHz With the divide by 2 select bit high the user may keep N 6 000 R COUNTER LATCH With C2 C1 0 1 the R counter latch is programmed Table 9 shows the input data format for programming the R counter latch R Counter R1 to R14 set the counter divide ratio The divide range is 1 00 001 to 16383 111 111 Antibacklash Pulse Width DB16 and DB17 set the antibacklash pulse width Lock Detect Precision DB18 is the lock detect precision bit and sets the number of reference cycles with less than 15 ns phase error for entering the locked state With LDP at 1 five cycles are taken and with LDP at 0 three cycles are take
26. l be high with narrow low going pulses DVpp ANALOG LOCK DETECT DIGITAL LOCK DETECT R COUNTER OUTPUT CONTROL MUXOUT N COUNTER OUTPUT SDOUT DGND i Figure 13 MUXOUT Circuit INPUT SHIFT REGISTER The ADF4360 family s digital section includes a 24 bit input shift register a 14 bit R counter and an 18 bit N counter com prising of a 5 bit A counter and a 13 bit B counter Data is clocked into the 24 bit shift register on each rising edge of CLK The data is clocked in MSB first Data is transferred from the shift register to one of four latches on the rising edge of LE The destination latch is determined by the state of the two control bits C2 C1 in the shift register The two LSBs are DB1 and DBO as shown in Figure 2 The truth table for these bits is shown in Table 5 Table 6 shows a summary of how the latches are programmed Note that the test mode latch is used for factory testing and should not be programmed by the user Table 5 C2 and C1 Truth Table Control Bits C2 C1 Data Latch 0 0 Control Latch 0 1 R Counter 1 0 N Counter A and B 1 1 Test Mode Latch VCO The VCO core in the ADF4360 family uses eight overlapping bands as shown in Figure 14 to allow a wide frequency range to be covered without a large VCO sensitivity Kv and resultant poor phase noise and spurious performance The correct band is chosen automatically by the band select logic at power up or whenever the N counter la
27. mbly CSP Thermal Impedance Paddle Soldered 50 C W Paddle Not Soldered 88 C W TRANSISTOR COUNT Lead Temperature Soldering 12543 CMOS and 700 Bipolar Vapor Phase 60 sec 215 C Infrared 15 sec 220 C 1 GND AGND DGND OV a ESD CAUTION NVWV ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features WARNING S proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy elec Ah trostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev B Page 6 of 24 ADF 4360 1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3 TE 55425 BIBIBIBIBIE ua PIN 1 CPGND 1 e IDENTIFIER 18 DATA AVpp 2 EK AGND 5 ADF4360 1 16 REF iy TOP VIEW RFourA 4 Not to Scale 15 BEND RFoyrB 5 14 Cy 6 2 a z 0 e Q z e o o AGND H Q 2 lt 04414 003 gt lt Figure 3 Pin Configuration Table 4 Pin Function Descriptions Pin No Mnemonic Description 1 CPGND Charge Pump Ground This is the ground return path for the charge pump 2 AVop Analog Power Supply This ranges from 3 0 V to 3 6 V Decoupling capacitors
28. n Test Mode Bit DBI9 is the test mode bit TMB and should be set to 0 With TMB 0 the contents of the test mode latch are ignored and normal operation occurs as determined by the contents of the control latch R counter latch and N counter latch Note that test modes are for factory testing only and should not be pro grammed by the user Band Select Clock seta dividerfor pos select logic clock input The Output of the R counter ig by default the value used to clock the band select logic but if this value is too high 21 MHz divider can be switched on to divide the R counter output to a smaller value see Table 9 Reserved Bits DB23 to DB22 are spare bits that are reserved They should be programmed to 0 Rev B Page 19 of 24 ADF 4360 1 APPLICATIONS DIRECT CONVERSION MODULATOR Direct conversion architectures are increasingly being used to implement base station transmitters Figure 17 shows how ADI parts can be used to implement such a system The circuit block diagram shows the AD9761 TxDAC being used with the AD8349 The use of dual integrated DACs such as the AD9761 with its specified 0 02 dB and 0 004 dB gain and offset matching characteristics ensures minimum error contribution over temperature from this portion of the signal chain The local oscillator is implemented using the ADF4360 1 The low pass filter was designed using ADIsimPLL for a channel spacing of 1 MHz and an open
29. old of Voo 2 and a dc equivalent input resistance of 100 See Figure 10 This input can be driven from a TTL or CMOS crystal oscillator or it can be ac coupled 17 CLK Serial Clock Input This serial clock is used to clock in the serial data to the registers The data is latched into the 24 bit shift register on the CLK rising edge This input is a high impedance CMOS input 18 DATA Serial Data Input The serial data is loaded MSB first with the two LSBs being the control bits This input is a high impedance CMOS input 19 LE Load Enable CMOS Input When LE goes high the data stored in the shift registers is loaded into one of the four latches and the relevant latch is selected using the control bits 20 MUXOUT This multiplexer output allows either the lock detect the scaled RF or the scaled reference frequency to be accessed externally 21 DVpp Digital Power Supply This ranges from 3 0 V to 3 6 V Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin DVpp must have the same value as AVpp 23 CE Chip Enable A logic low on this pin powers down the device and puts the charge pump into three state mode Taking the pin high powers up the device depending on the status of the power down bits 24 CP Charge Pump Output When enabled this provides lc to the external loop filter which in turn drives the internal VCO Rev B Page 7 of 24 ADF 4360 1 TYPICAL PERFORMANCE CHARACTERISTICS
30. rential pair driven by buffered outputs of the VCO as shown in Figure 15 To allow the user to optimize the power dissipation versus the output power requirements the tail current of the differential pair is programmable via Bits PL1 and PL2 in the control latch Four current levels may be set 3 5 mA 5 mA 7 5 mA and 11 mA These levels give output power levels of 13 dBm 10 5 dBm 8 dBm and 6 dBm respectively using a 50 Q resistor to and ac coupling into a 50 load Alternatively both outputs can be combined in a 1 1 1 transformer or a 180 microstrip coupler see the Output Matching section ADF4360 1 If the outputs are used individually the optimum output stage consists of a shunt inductor to Vp Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry This is enabled by the mute till lock detect MTLD bit in the control latch RFoutA RFourB 04414 015 Figure 15 Output Stage ADF4360 1 Rev B Page 11 of 24 ADF 4360 1 LATCH STRUCTURE Table 6 shows the three on chip latches for the ADF4360 family The two LSBs determine which latch is programmed Table 6 Latch Structure CONTROL LATCH PRESCALER CURRENT CURRENT OUTPUT VALUE SETTING 2 SETTING 1 POWER LEVEL MUXOUT CONTROL CONTROL BITS MUTE TILL PHASE DETECTOR POLARITY COUNTER RESET DB23
31. s min CLOCK High Duration ts 25 ns min CLOCK Low Duration 6 10 ns min CLOCK to LE Setup Time t7 20 ns min LE Pulse Width See the Power Up section for the recommended power up procedure for this device ty ts 1 1 1 CLOCK 1 1 1 1 1 DB1 DBO LSB DATA ee MSB DB2 CONTROL BIT C2 CONTROL BIT C1 1 1 ie t 1 LE MS _ E LE a 8 x 5 Figure 2 Timing Diagram Rev B Page 5 of 24 ADF 4360 1 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 3 Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device This is a stress rat AVo to GND 03Vto 3 9 V ing only functional operation of the device at these or any to 0 3 V to 40 3 V other conditions above those indicated in the operational sec Wco to GND 0 3 V to 3 9 V tions of this specification is not implied Exposure to absolute Vvco to 0 3 V to 0 3 V maximum rating conditions for extended periods may affect Digital I O Voltage to GND 0 3 V to Vpp 0 3 V device reliability Analog I O Voltage to GND 0 3 V to Vpp 0 3 V REFin to GND 0 3 V to Vop 0 3 V This device is a high performance RF integrated circuit with an Operating Temperature Range ESD rating of 1 kV and it is ESD sensitive Proper precautions Maximum Junction Temperature 150 C should be taken for handling and asse
32. set to 0 for normal operation Phase Detector Polarity The PDP bit in the ADF4360 family sets the phase detector polarity The positive settixig riabled by programming a 1 is used when using the on hip V a passive loop filter or With noninverting filter It can also be set to 0 This is required if an active inverting loop filter is used MUXOUT Control The on chip multiplexer is controlled by M3 M2 and M1 See the truth table in Table 7 Counter Reset DB4 is the counter reset bit for the ADF4360 family When this is 1 the R counter and the A B counters are reset For normal operation this bit should be 0 Core Power Level 1 and PC2 set the power level in the VCO core The recom mended setting is 15 mA See the truth table in Table 7 Rev B Page 18 of 24 ADF 4360 1 N COUNTER LATCH With C2 C1 1 0 the N counter latch is programmed Table 8 shows the input data format for programming the N counter latch A Counter Latch A5 to A1 program the 5 bit A counter The divide range is 0 00000 to 31 11111 Reserved Bits DB7 isa spare bit that is reserved It should be programmed to 0 B Counter Latch B13 to B1 program the B counter The divide range is 3 00 0011 to 8191 11 111 Overall Divide Range The overall divide range is defined by P x B A where P is the prescaler value CP Gain DB21 of the N counter latch in the ADF4360 family is the charge pump ga
33. tch is updated It is important that the correct write sequence be followed at power up This sequence is 1 R counter latch 2 Control latch 3 N counter latch During band select which takes PFD cycles the VCO is disconnected from the output of the loop filter and connected to an internal referente voltage VOLTAGE V 04414 014 Figure 14 Frequency vs Vrune ADF4360 1 The R counter output is used as the clock for the band select logic and should not exceed 1 MHz A programmable divider is provided at the R counter input to allow division by 1 2 4 or 8 and is controlled by Bits BSC1 and BSC2 in the R counter latch Where the required PFD frequency exceeds 1 MHz the divide ratio should be set to allow enough time for correct band selection Rev B Page 10 of 24 After band select normal PLL action resumes The nominal value of Kv is 57 MHZ V or 28 MHZ V if divide by 2 operation has been selected by programming DIV2 DB22 high in the N counter latch The ADF4360 family contains linearization circuitry to minimize any variation of the product of Ice and Kv The operating current in the VCO core is programmable in four steps 5 mA 10 mA 15 mA and 20 mA This is controlled by Bits PC1 and PC2 in the control latch OUTPUT STAGE The RFovrA and RFou7B pins of the ADF4360 family are con nected to the collectors of an NPN diffe
34. to the analog ground plane should be placed as close as possible to this pin AVop must have the same value as DVpp 3 8 to 11 22 AGND Analog Ground This is the ground return path of the prescaler and VCO 4 RFourA VCO Output The output level is programmable from 6 dBm to 13 dBm See the Output Matching section for a description of the various output stages 5 RFourB VCO Complementary Output The output level is programmable from 6 dBm to 13 dBm See the Output Matching section for a description of the various output stages 6 Vvco forthe VCO This ranges from 3 0 V 6 3 6 NDE coupling carpecitors to the analog ground plane 5 placed as possible tothis pin must haye the sameWalue as 7 Control Input to the VCO This voltage determines the output frequency and is derived from filtering the CP output voltage 12 Cc Internal Compensation Node This pin must be decoupled to ground with a 10 nF capacitor 13 Rset Connecting a resistor between this and CPenp sets the maximum charge pump output current for the synthesizer The nominal voltage potential at the Rser pin is 0 6 V The relationship between Ice and Rser is IcPmax Ie Rsgr where 4 7 2 5 14 Internal Compensation Node This pin must be decoupled with a 10 uF capacitor 15 DGND Digital Ground 16 REFin Reference Input This is a CMOS input with a nominal thresh
35. ulus prescaler to allow a wide range division ratio in the PLL feed back counter The counters are specified to work when the prescaler output is 300 MHz or less Thus with a VCO frequency of 2 5 GHz a prescaler value of 16 17 is valid but a value of 8 9 is not valid Pulse Swallow Function The A and B counters in conjunction with the dual modulus prescaler make it possible to generate output frequencies that are spaced only by the reference frequency divided by R The VCO frequency equation is VP x B A x fagg where fvcois the output frequency of the VCO is the preset modulus of the dual modulus prescaler 8 9 16 17 and so on B is the preset divide ratio of the binary 13 bit counter 3 to 8191 A is the preset divide ratio of the binary 5 bit swallow counter 0 to 31 frern is the external reference frequency oscillator ADF 4360 1 13 BIT B COUNTER TO PFD FROM VCO MODULUS CONTROL 04414 011 Figure 11 A and B Counters RCOUNTER The 14 bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector PFD Division ratios from 1 to 16 383 are allowed PFD AND CHARGE PUMP The PFD takes inputs from the R counter and N counter N BP A and produces an output proportional to the phase and frequency difference between them Figure 12 is a simpli fied schematic The PFD includes a programmable del

ANALOG DEVICES ADF4360-1 handbook

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