Home

ANALOG DEVICES ADF4360-9 handbook

1. 2 60 40 80 F 0 80 100 ul ul 0 Q 110 2 2 7100 120 7 7 120 a 190 140 x 140 5 150 E 160 160 5 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY Hz FREQUENCY Hz Figure 4 Open Loop VCO Phase Noise at 218 MHz L1 L2 2 56nH Figure 7 DIVOUT Phase Noise 95 MHz VCO 380 MHz PFD Frequency 1 MHz Loop Bandwidth 40 kHz Jitter 1 3 ps Divide by A 2 Selected A 2 60 60 70 70 80 80 90 90 o o 100 100 110 1 2 410 o o 2 2 120 120 4 2 130 130 140 140 150 8 150 8 160 5 160 5 100 1k 10k 100k 1k 10M 100 1k 10k 100k 1M 10M FREQUENCY OFFSET Hz FREQUENCY OFFSET Hz Figure 5 VCO Phase Noise 360 MHz 1 MHz PFD 40 kHz Loop Bandwidth Figure 8 DIVOUT Phase Noise 80 MHz VCO 320 MHz RMS Jitter 1 4 ps PFD Frequency 1 MHz Loop Bandwidth 40 kHz Jitter 1 3 ps Divide by A 2 Selected A 2 o o m m B W ul o o o o o o I I 100 1k 10k 100k 1M 10M FREQUENCY OFFSET Hz FREQUENCY OFFSET Hz Figure 6 DIVOUT Phase No
2. 0 0 the control latch is programmed Figure 23 shows the input data format for programming the control latch Power Down DB21 PD2 and DB20 PD1 provide programmable power down modes In the programmed asynchronous power down the device powers down immediately after latching a 1 into Bit PD1 with the condition that PD2 is loaded AY programmed synchronous power down the device power down is gated by the charge pump to prevent unwanted frequency jumps Once the power down is enabled by writing a 1 into Bit PD1 on the condition that a 1 is also loaded in PD2 the device goes into power down on the second rising edge of the R counter output after LE goes high When a power down is activated either synchronous or asynchronous mode the following events occur e active dc current paths are removed e TheR N and timeout counters are forced to their load state conditions The charge pump is forced into three state mode e digital lock detect circuitry is reset e RF outputs are debiased to a high impedance state The reference input buffer circuitry is disabled The input register remains active and capable of loading and latching data Charge Pump Currents CPI3 2 and in the ADF4360 family determine Current Setting 1 CPI6 CPI5 and CPI4 determine Current Setting 2 see the truth table in Figure 23 Output Power Level Bit PL1 and Bit PL2 set the output power l
3. ADF4360 9 CONTROL BITS DB23 DB22 DB17 DB16 DB15 DB14 DB13 DB12 CPI N COUNTER LATCH 13 BIT B COUNTER RESERVED RESERVED CP GAIN 5 BIT DIVOUT RESERVED C2 0 C1 0 CONTROL BITS DB23 DB22 DB21 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 RSV RSV CPG R COUNTER LATCH ANTI BACKLASH ULSE WIDTH LOCK DETECT PRECISION P DB13 0812 DB11 14 BIT REFERENCE COUNTER DB10 DB9 C2 1 C1 0 CONTROL BITS DB1 DBO HH RESERVED DB23 DB22 DB21 DB20 DB19 E 4 710816 DB15 DB14 RSV RSV BSC2 BSC1 4 ABP2 ABP1 614 R18 R9 Figure 22 Latch Structure Rev A Page 13 of 24 C2 0 C1 1 07139 034 ADF4360 9 ESERVED ESERVED POWER DOWN 2 CURRENT SETTING 2 4 ourPUT CURRENT E SETTING 1 POWER 19 Level 5 GAIN 4 Woe aba lt 94 RESET COUNTER CONTROL BITS DB3 DB2 DB1 DB0 POWER DOWN 1 c x DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 RSV RSV PD2 PD1 CPI6 CPI5 CPI4 2 MTLD MUTE TIL LOCK DETECT DB13 DB12 11 DB10 089 DB8 DB7 086 085 PL2 PL1 MTLD CPG CP PDP 03 D2 D1 PHASE DETECTOR POLARITY NEGATIVE POSI
4. The digital section of the ADF4360 family includes a 24 bit input shift register a 14 bit R counter and an 18 bit N counter comprising a 5 bit A counter and a 13 bit B counter Data is clocked into the 24 bit shift register on each rising edge of CLK The data is clocked in MSB first Data is transferred from the shift register to one of four latches on the rising edge of LE The destination latch is determined by the state of the two control bits C2 C1 in the shift register The two LSBs DB1 and DBO are shown in Figure 2 Rev A Page 10 of 24 The truth table for these bits is shown in Table 5 Figure 22 shows a summary of how the latches are programmed Note that the test modes latch is used for factory testing and should not be programmed by the user Table 5 C2 and C1 Truth Table Control Bits C2 C1 Data Latch 0 0 Control 0 1 R Counter 1 0 N Counter B 1 1 Test Modes VCO The VCO core in the ADF4360 family uses eight overlapping bands as shown in Figure 18 to allow a wide frequency range to be covered without a large VCO sensitivity Kv and resultant poor phase noise and spurious performance The correct band is chosen automatically by the band select logic at power up or whenever the N counter latch is updated It is important that the correct write sequence be followed at power up The correct write sequence is as follows 1 R Counter Latch 2 Control Latch 3 N Counter Latch During b
5. 2 and 2 are selected respectively for each of the output frequencies previously mentioned The low pass filter was designed using ADIsimPLL for a channel spacing of 1 MHz and an open loop bandwidth of 40 kHz Larger PFD frequencies can be used to reduce in band noise and therefore rms jitter However for the purposes of this example 1 MHz is used The measured rms jitter from this circuit at each frequency is less than 1 5 ps 801BE 160 SPI COMPATIBLE SERIAL BUSg 8 ADF4360 9 Two 21 nH inductors are required for the specified frequency range The reference frequency is from a 20 MHz TCXO from Fox therefore an R value of 20 is programmed Taking into account the high PFD frequency and its effect on the band select logic the band select clock divider is enabled In this case a value of 8 is chosen A very simple shunt resistor and dc blocking capacitor complete the RF output stage Because these outputs are not used they are terminated in 50 Q resistors This is recommended for circuit stability Leaving the RF outputs open is not recommended The CMOS level output frequency is available at DIVOUT If the frequency has to drive a low impedance load a buffer is recommended 07139 027 Figure 30 GSM Test Clock Rev A Page 21 of 24 ADF4360 9 INTERFACING The ADF4360 family has a simple SPI compatible serial interface for writing to the device CLK DATA and LE control the data transfer When LE goes high
6. THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON T CARE BITS 07139 023 Figure 24 N Counter Latch Rev A Page 15 of 24 ADF4360 9 ANTI BACKLASH PULSE 14 BIT REFERENCE COUNTER WIDTH BAND SELECT CLOCK CONTROL BITS x5 2 RESERVED RESERVED PRECISION DB23 DB22 DB21 DB20 DB19 18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB4 DB3 082 sv rev scs an tor ars a me mw ro m m me e e 0 e DIVIDE RATIO 1 TEST MODE BIT SHOULD BE SET TO 0 THESE BITS ARE FOR NORMAL NOT USED BY OPERATION THE DEVICE AND ARE DON T CARE BITS 2 3 4 16380 16381 16382 16383 ANTIBACKLASH PULSE WIDTH 3 0ns 1 3ns 6 0ns 3 0ns LOCK DETECT PRECISION THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET BAND SELECT CLOCK DIVIDER 1 07139 024 Figure 25 R Counter Latch Rev A Page 16 of 24 POWER UP Power Up Sequence The correct programming sequence for the ADF4360 9 after power up is as follows 1 R Counter Latch 2 Control Latch 3 N Counter Latch Initial Power Up Initial power up refers to programming the part after the application of voltage to the DVpp and Vvco pins On initial power up an interval is requ
7. 50 REF 0 05 1 00 12 MAX 0 65 0 60 COMPLIANT STANDARDS MO 220 VGGD 2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 36 24 Lead Lead Frame Chip Scale Package VO 4mm x 4 Body Very Thin Quad CP 24 2 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Frequency Range Package Option ADF4360 9BCPZ 40 C to 85 C 24 Lead LFCSP_VQ 65 MHz to 400 MHz CP 24 2 ADF4360 9BCPZRL 3400 G tou85 C 24 Lead LECSP VO 65 MfIz 107400 24 2 ADF4360 9BCPZRL7 24 Lead LFCSP4VO 65 to 400 24 2 EVAL ADF4360 9EBZ1 Evaluation Board 17 RoHS Compliant Part 2008 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D07139 0 3 08 A ANALOG DEVICES Rev A Page 24 of 24 www analog com
8. 8191 frern is the external reference frequency oscillator R COUNTER The 14 bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector PFD Division ratios from 1 to 16 383 are allowed PFD AND CHARGE PUMP The takes inputs from counter and N counter B and produces an output proportional to the phase and frequency difference between them Figure 17 is a simplified schematic The PFD includes a programmable delay element that controls the width of the antibacklash pulse This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs Two bits in the R counter latch ABP2 and ABPI control the width of the pulse see Figure 25 ABP1 ABP2 N DIVIDER R DIVIDER DIVIDER CP OUTPUT Figure 17 PFD Simplified Schematic and Timing In Lock a LOCK DETECT i The LD pin outputs a lock detect signal Digital lock detect is active high When lock detect precision LDP in the R counter latch is set to 0 digital lock detect is set high when the phase error on three consecutive phase detector cycles is lt 15 ns 07139 017 When LDP is set to 1 five consecutive cycles of lt 15 ns phase error are required to set the lock detect It stays set high until a phase error of gt 25 ns is detected on any subsequent PD cycle INPUT SHIFT REGISTER
9. one another The lowest center frequency of oscillation possible is approximately 65 MHz which is achieved using 560 nH inductors This relationship can be expressed by 1 fo 2n 9 3 pF 0 9 nH Lj where Jois the center frequency Lexr is the external inductance 450 400 350 300 250 i 200 FREQUENCY MHz 07139 025 0 100 200 300 400 500 600 INDUCTANCE Figure 27 Output Center Frequency vs External Inductor Value The approximate value of capacitance at the midpoint of the center band of the VCO is 9 3 and the approximate value of internal inductance due to the bond wires is 0 9 nH The VCO sensitivity is a measure of the frequency change vs the tuning voltage It is a very important parameter for the low pass filter Figure 28 shows a graph of the tuning sensitivity in MHz V vs the inductance nH It can be seen that as the inductance increases the sensitivity decreases This relationship can be derived from the previous equation that is because the inductance increased the change in capacitance from the varactor has less of an effect on the frequency 12 10 SENSITIVITY MHz V o 07139 026 0 100 200 300 400 500 600 INDUCTANCE nH Figure 28 Tuning Sensitivity vs Inductance ENCODE CLOCK FOR ADC Analog to digital converters ADCs require a sampling clock for their operation Generally this is
10. provided by TCXO or VCXOs which can be large and expensive The frequency range is usually quite limited An alternative solution is the ADF4360 9 which can be used to generate a CMOS clock signal suitable for use in all but the most demanding converter applications Figure 29 shows an ADF4360 9 with a VCO frequency of 320 MHz and agDIVOUUfredifency of 80 MHz Because a 50 duty cycle is preferred by most samplingiclock circuitry the A 2 mode is selected Therefore A is programmed to 2 giving an overall divide value of 4 The AD9215 80 is a 10 bit 80 MSPS ADC that requires an encode clock jitter of 6 ps or less The ADF4360 9 takes a 10 MHz TCXO frequency and divides this to 1 MHz therefore 10 is programmed and 320 is programmed to achieve a VCO frequency of 320 MHz The resultant 80 MHz CMOS signal has a jitter of 1 5 ps which is more than adequate for the application SPI TCXO ADF4360 9 SIGNAL GENERATOR ENCODE HC ADC OAN CLOCK EVALA SC AD9215 80 07139 036 Figure 29 The ADF4360 9 Used as an Encode Clock for an ADC Rev A Page 20 of 24 GSM TEST CLOCK Figure 30 shows the ADF4360 9 used to generate three different frequencies at DIVOUT The frequencies required are 45 MHz 80 MHz and 95 MHz This is achieved by generating 360 MHz 320 MHz and 380 MHz and programming the correct A divider ratio Because a 5096 duty cycle is required the A 2 DIVOUT mode is selected This means that A values of 4
11. the 24 bits that are clocked into the appropriate register on each rising edge of CLK are transferred to the appropriate latch See Figure 2 for the timing diagram and Table 5 for the latch truth table The maximum allowable serial clock rate is 20 MHz This means that the maximum update rate possible is 833 kHz or one update every 1 2 us This is more than adequate for systems that have typical lock times in hundreds of microseconds ADuC812 Interface Figure 31 shows the interface between the ADF4360 family and the ADuC812 MicroConverter Because the ADuC812 is based on an 8051 core this interface can be used with any 8051 based microcontrollers The MicroConverter is set up for SPI master mode with CPHA 0 To initiate the operation the I O port driving LE is brought low Each latch of the ADF4360 family needs a 24 bit word which is accomplished by writing three 8 bit bytes from the MicroConverter to the device After the third byte is written the LE input should be brought high to complete the transfer SCLOCK MOSI ADuC812 PORTS MUXOUT LOCK DETECT 07139 028 Figure 31 ADuC812 to ADF4360 x Interface I O port lines on the ADuC812 are used to detect lock MUXOUT configured as lock detect and polled by the port input When operating in the described mode the maximum SCLOCK rate of the ADuC812 is 4 MHz This means that the maximum rate at which the output frequency can be changed is 166 kHz ADSP 21x
12. 0 3V to 3 9V to DVpp 0 3 V to 40 3 V Vvco to GND 0 3V to 43 9 V to AVop 0 3V to 0 3 V Digital Input Output Voltage to GND Analog Input Output Voltage to GND REFin to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature LFCSP Oja Thermal Impedance Paddle Soldered Paddle Not Soldered Lead Temperature Soldering Vapor Phase 60 sec Infrared 15 sec 0 3 V to Voo 0 3 V 0 3 V to Voo 0 3 V 0 3 V to Voo 0 3 V 40 C to 85 65 C to 150 C 150 C 50 C W 88 C W 215 C 220 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability This device is a high performance RF integrated circuit with an ESD rating of lt 1 kV and it is ESD sensitive Proper precautions should be taken for handling and assembly TRANSISTOR COUNT The transistor count is 12 543 CMOS and 700 bipolar 1 GND CPGND DGND OV I I ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or
13. 1 6 MHz DIVOUT 45 MHz 14 ps rms 4 A 2 output selected DIVOUT 10 MHz 1 6 ps rms A 18 A 2 output selected VCO 360 MHz PFD 1 6 MHz DIVOUT Duty Cycle A Output 1 Ax100 typ Divide by A selected A 2 Output 50 96 typ Divide by A 2 selected 1 Operating temperature range is 40 C to 85 C Guaranteed by design Sample tested to ensure compliance is internally modified to maintain constant loop gain over the frequency range Ta 25 Woo 3 3 5 Unless otherwise stated these characteristics are guaranteed for VCO core power 5 L1 L2 270 nH 470 resistors to GND in parallel with L1 L2 Jumping from 90 MHz to 108 MHz PFD frequency 200 kHz loop bandwidth 10 kHz 7 For more detail on using tuned loads see the Output Matching section 8 Using 50 resistors to into a 50 load The noise of the VCO is measured in open loop conditions L1 L2 56 nH 10 The phase noise is measured with the EVAL ADF4360 9EBZ1 evaluation board and the Agilent E5052A signal source analyzer 11 fren 10 MHz fero 1 MHz 360 loop B W 40 kHz The normalized phase noise floor is estimated by measuring the in band phase noise at the output of the VCO and subtracting 20logN where is the divider value and 10logfero 10logfero 20logN 12 The jitter is measured with the EVAL ADF4360 9EBZ1 evaluation board and the Agilent E505
14. 2A signal source analyzer A low noise TCXO provides the REF for the synthesizer and the jitter is measured over the instrument s jitter measurement bandwidth frerin 10 MHz fero 1 MHz 360 loop BW 40 kHz unless otherwise noted The spurious signals are measured with the EVAL ADF4360 9EBZ1 evaluation board and the Agilent 5052 signal source analyzer The spectrum analyzer provides the REFi for the synthesizer frerin 10 MHz 2 0 dBm frerin 10 MHz fero 1 MHz 360 loop BW 40 kHz Rev A Page 4 of 24 TIMING 5 AVpp 3 3 V 10 DGND 0 V 1 8 and 3 V logic levels used Tum to Tmax unless otherwise noted ADF4360 9 Table 2 Parameter Limit at to Tmax B Version Unit Test Conditions Comments t 20 ns min LE setup time t 10 ns min DATA to CLK setup time ts 10 ns min DATA to CLK hold time ta 25 ns min CLK high duration ts 25 ns min CLK low duration 10 5 CLK to LE setup time t 20 ns min LE pulse width 1 Refer to the Power Up section for the recommended power up procedure for this device t t CLK DATA DB23 MSB DB1 DBO LSB CONTROL BIT C2 CONTROL BIT C1 Figure 2 Timing Diagram Rev A Page 5 of 24 a 8 8 E 5 ADF4360 9 ABSOLUTE MAXIMUM RATINGS 25 unless otherwise noted Table 3 Parameter Rating AVpp to GND
15. 9 The recommended value of this inductor changes with the VCO center frequency Figure 35 shows a graph of the optimum inductor value vs center frequency 300 250 200 150 INDUCTANCE nH 100 50 C 07139 032 0 100 200 300 400 CENTER FREQUENCY MHz Figure 35 Optimum Shunt Inductor vs Center Frequency Both complementary architectures can be examined using the EVAL ADF4360 9EBZ1 evaluation board If the user does not need the differential outputs available on the ADF4360 9 the user should either terminate the unused output with the same circuitry as much as possible or combine both outputs using a balun Alternatively instead of the LC balun both outputs can be combined using a 180 rat race coupler If thefuser is only using DIVOUT and does not use the RF is still tO terminate both RF output pins with a shunt inductor resistor to Vvco and also a dc bypass capacitor and a 50 load The circuit in Figure 33 is probably the simplest and most cost effective solution It is important that the load on each pin be balanced because an unbalanced load is likely to cause stability problems Terminations should be identical as much as possible Rev A Page 23 of 24 ADF4360 9 OUTLINE DIMENSIONS PIN 1 4 INDICATOR 0 80 SEATING 0 30 COPLANARITY 023 0 20 REF 0 08 PLANE 0 18 EXPOSED PAD BOTTOMVIEW I T 2
16. ANALOG DEVICES Clock Generator PLL with Integrated VCO ADF 4360 9 FEATURES GENERAL DESCRIPTION Primary output frequency range 65 MHz to 400 MHz The ADF4360 9 is an integrated integer N synthesizer and Auxiliary divider from 2 to 31 output from 1 1 MHz to 200 MHz voltage controlled oscillator VCO External inductors set the 3 0 V to 3 6 V power supply ADF4360 9 center frequency This allows a VCO frequency 1 8 V logic compatibility range of between 65 MHz and 400 MHz Integer N synthesizer Programmable output power level 3 wire serial interface An additional divider stage allows division of the VCO signal The CMOS level output is equivalent to the VCO signal divided by the integer value between 2 and 31 This divided signal can Digitallock detect be further divided by 2 if desired Software power down mode Control of all the on chip registers is through a simple 3 wire APPLICATIONS interface The device operates with a power supply ranging System clock generation from 3 0 V to 3 6 V and can be powered down when not in use Test equipment Wireless LANs CATV equipment FUNCTIONAL BLOCK DIAGRAM AVpp DVpp Rset ADF4360 9 14 COUNTER gt 24 DATA 24 BIT FUNCTION LATCH DETECT PUT RFourA 13 BIT B OUT COUNTER KE STAGE RFourB N B DIVIDE BY A 2 TO 31 07139 001 AGND DGND CPGND Figure 1 Rev Information fumished by Analog Devices is believed to be accur
17. ATCH Figure 24 shows the input data format for programming the N counter latch 5 Bit Divider A5 to Al program the output divider The divide range is 2 00010 to 31 11111 If unused this divider should be set to 0 The output or the output divided by 2 is available at the DIVOUT pin Reserved Bits DB23 DB22 and DB7 are spare bits and are designated as reserved They should be programmed to 0 B Counter Latch B13 to B1 program the B counter The divide range is 3 00 0011 to 8191 11 111 Overall Divide Range The overall VCO feedback divide range is defined by B CP Gain DB21 of the N counter latch in the ADF4360 family is the charge pump gain bit When it is programmed to 1 Current Setting 2 is used When programmed to 0 Current Setting 1 is used This bit can also be programmed through DB10 of the control latch The bit always reflects the latest value written to it whether this is through the control latch or the counter latch R COUNTER LATCH With C2 C1 0 1 the R counter latch is programmed Figure 25 shows the input data format for programming the R counter latch R Counter to R14 set the counter divide ratio The divide range is 1 00 001 to 16 383 111 111 Antibacklash Pulse Width DB16 and DB17 set the antibacklash pulse width Lock Detect Precision DB18 is the lock detect precision bit This bit sets the number of reference cycles with 15 ns phase error fo
18. Cn Value Control Latch and N Counter Latch L1 and L2 18 0 nH L1 and 12 110 0 nH L1 and L2 560 0 nH 10 uF 215 ms 440 nF gt 600 us 4 z100 dBc Hz 99 dBc Hz 97 dBc Hz 99 dBc Hz gt 96 uBt Hz 98 dBc Hz POWER UP d DATA R COUNTER CONTROL LATCH DATA LATCH DATA N COUNTER LATCH DATA 1 REQUIRED INTERVAL CONTROL LATCH WRITE TO N COUNTER LATCH WRITE 07139 033 Figure 26 Power Up Timing Rev A Page 17 of 24 ADF4360 9 Software Power Up Power Down If the part is powered down via the software using the control latch and powered up again without any change to the N counter latch during power down the part locks at the correct frequency because the part is already in the correct frequency band The lock time depends on the value of capacitance on the Cx pin which is 15 ms for 10 capacitance The smaller capacitance of 440 nF on this pin enables lock times of 600 The N counter value cannot be changed while the part is in power down because the part may not lock to the correct frequency on power up If it is updated the correct program ming sequence for the part after power up is to the R counter latch followed by the control latch and finally the N counter latch with the required interval between the control latch and N counter latch as described in the Initial Power Up section CONTROL LATCH With C2 C1
19. Hz 10 Duty Cycle 1096 Divide by A 2 Selected A 1 C1 FREQUENCY 180MHz C1 DUTY 45 32 HHVAHI C1 FREQUENCY 36MHz C1 DUTY 49 4176 07139 012 07139 015 500mV M 2 00ns CH1 S 20mv 500mV M 12 5ns A CH1 920mV Figure 12 DIVOUT 180 MHz Waveform VCO 360 MHz Figure 15 DIVOUT 36 MHz Waveform VCO 360 MHz Divide by A Selected A 2 Duty Cycle 5096 Divide by A 2 Selected A 5 Duty Cycle 25096 Rev A Page 9 of 24 ADF4360 9 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 16 SW1 and SW2 are normally closed switches and SW3 is normally open When power down is initiated SW3 is closed and SW1 and SW2 are opened This ensures that there is no loading of the REF pin at power down POWER DOWN CONTROL TO R COUNTER z 07139 016 Figure 16 Reference Input Stage N COUNTER The CMOS N counter allows a wide division ratio in the PLL feedback counter The counters are specified to work when the VCO output is 400 MHz or less To avoid confusion this is referred to as the B counter It makes it possible to generate output frequencies that are spaced only by the reference frequency divided by R The VCO frequency equation is B x frerw R where fvco is the output frequency of the VCO B is preset divide ratio ofthe binary 13 bit counter 3 to
20. Hz max CHARGE PUMP Sink Source With Rset 4 7 High Value 2 5 mA typ Low Value 0 312 mA typ Rser Range 2 7 10 max Three State Leakage Current 0 2 nA typ Sink and Source Current Matching 2 96 typ 1 25 lt lt 2 5 V vs 1 5 typ 1 25 lt lt 2 5 V Ice vs Temperature 2 96typ 2 0V LOGIC INPUTS Input High Voltage 15 Input Low Voltage Viu i 0 6 V Input Current F1 max i Input Capacitance Cin 3 0 pF max LOGIC OUTPUTS Output High Voltage Vou DVpp 0 4 Vmin CMOS output chosen Output High Current lou 500 max Output Low Voltage Vo 0 4 V max lo 500 pA POWER SUPPLIES AVpp 3 0 3 6 V min V max DVpp AVop Vvco AVop Alpo 5 mA typ 2 5 mA typ lvco 5 12 0 mA typ 5 mA Inrour 35to11 0 mA typ RF output stage is programmable Low Power Sleep 7 typ RF OUTPUT CHARACTERISTICS Maximum VCO Output Frequency 400 MHz 5 mA depending on L1 and L2 see the Choosing the Correct Inductance Value section Minimum VCO Output Frequency 65 MHz VCO Output Frequency 90 108 MHz min MHz max L1 L2 270 nH see the Choosing the Correct Inductance Value section for other frequency values VCO Frequency Range 12 Ratio fivax fium VCO Sensitivity 2 MHz V typ 11 12 270 nH see the Choosing the Correct Inductance Value section for other sensitivity values Lock Time 400 Us t
21. TIVE CHARGE PUMP OUTPUT H NORMAL THREE STATE CPG CP GAIN a PC2 PC1 2 0 C1 0 C2 PC1 CORE POWER LEVEL 0 CURRENT SETTING 1 1 CURRENT SETTING 2 0 1 OUTPUT POWER LEVEL DISABLED ENABLED MODE CURRENT USING TUNED LOAD USING 500 TO 3 5mA 5 0mA 6dBm I 7 5 3dBm 11 0mA THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON T CARE BITS ASYNCHRONOUS POWER DOWN NORMAL OPERATION ASYNCHRONOUS POWER DOWN SYNCHRONOUS POWER DOWN 19dBm 15dBm 12dBm Figure 23 Control Latch Rev A Page 14 of 24 2 5mA 5mA RECOMMENDED 7 5 10mA COUNTER OPERATION NORMAL R A B COUNTERS HELD IN RESET DVpp DIGITAL LOCK DETECT ACTIVE HIGH N DIVIDER OUTPUT DVpp R DIVIDER OUTPUT A CNTR 2 OUT A CNTR OUT DGND 07139 022 ADF4360 9 CONTROL 13 BIT B COUNTER 5 BIT DIVOUT BITS RESERVED 0823 DB22 DB21 DB20 DB19 DB18 DB17 DB16 10815 DB14 DB13 DB12 DB11 DB10 089 RESERVED 087 086 DB5 DB4 DB3 RSV RSV CPG B13 RSV A5 A4 C2 1 C1 0 THIS BIT IS NOT USED BY THE DEVICE AND IS A DON T CARE BIT OUTPUT DIVIDE RATIO NOT ALLOWED NOT ALLOWED 2 0 0 NOT ALLOWED 0 1 NOT ALLOWED 1 0 NOT ALLOWED 1 1 CP GAIN OPERATION CHARGE PUMP CURRENT SETTING 1 IS PERMANENTLY USED CHARGE PUMP CURRENT SETTING 2 IS PERMANENTLY USED
22. and selection which takes five PED cycles the VCO is disconnected from the output of the loop filter and connected to an internal reference voltage 1 ADF4360 9 V 07139 019 0 80 85 90 95 100 105 110 115 FREQUENCY MHz Figure 18 Vrune ADF4360 9 L1 and L2 270 nH vs Frequency The R counter output is used as the clock for the band select logic and should not exceed 1 MHz A programmable divider is provided at the R counter input to allow division by 1 2 4 or 8 and is controlled by the BSC1 bit and the BSC2 bit in the R counter latch Where the required PFD frequency exceeds 1 MHz the divide ratio should be set to allow enough time for correct band selection For many applications it is usually best to set this to 8 After band selection normal PLL action resumes The value of Kv is determined by the value of the inductors used see the Choosing the Correct Inductance Value section The ADF4360 familyContainsTinearization Gircuitry to minimize any variation ofthe product of The operating current in VCO core is programmable in four steps 2 5 mA 5 mA 7 5 mA and 10 mA This is controlled by the PCI bit and the PC2 bit in the control latch It is strongly recommended that only the 5 mA setting be used However in applications requiring a low VCO frequency the high temperature coefficient of some inductors may lead to the VCO tuning
23. ate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2008 Analog Devices Inc All rights reserved ADF4360 9 TABLE CONTENTS Features Lu Le a OE RSC 1 Applications utere ette ua una IS EUER SIE 1 General Description eerte tette 1 Functional Block Diagram seen 1 REVISION HIStory d ens 2 Sp cifications 3 Timing Characteristics 5 Absolute Maximum 6 Transistor Count e erect ene tenete ette 6 ESD Caution iioc ey E ene 6 Pin Configuration and Function 5 7 Typical Performance Characteristics sse 8 Circuit Description uet titer tiet tette teni 10 Reference Input Section 10 IN Counter ici ne EAM 10 REG OUI dem 10 PED arid Charge 10 Lock Detection ede etel a ubere s d0 INN D REVISION HISTORY 3 08 Rev 0 to Rev A Changes to Table T itecto S
24. ed into the 24 bit shift register on the CLK rising edge This input is a high impedance CMOS input 18 DATA Serial Data Input The serial data is loaded MSB first with the two LSBs being the control bits This input is a high impedance CMOS input 19 LE Load Enable CMOS Input When LE goes high the data stored in the shift registers is loaded into one of the four latches and the relevant latch is selected using the control bits 20 DIVOUT This output allows the user to select VCO frequency divided by A or VCO frequency divided by 2A Alternatively the scaled RF or the scaled reference frequency can be accessed externally through this output 21 DVpp Digital Power Supply This ranges from 3 0 V to 3 6 V Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin must have the same value as AVpp 23 LD Lock Detect The output on this pin is logic high to indicate that the part is in lock Logic low indicates loss of lock 24 CP Charge Pump Output When enabled this provides lce to the external loop filter which in turn drives the internal VCO Rev A Page 7 of 24 ADF4360 9 TYPICAL PERFORMANCE CHARACTERISTICS
25. ee EYES 3 Changes t Figure 23s ea nte b ies 14 Changes to Output Matching Section sss 23 1 08 Revision 0 Initial Version Input Shift Register xo e ERE 10 oor 11 iiir c M 12 DIVOUT ice ege 12 u ero EE 13 Powerz Up huu ees e Dat 17 Control Latches tines ikenien ieies iasi 18 N Go nt r Latch o sassa epe e ES 19 R Counter Latch srs 19 Applications aa N N ROREM TET 20 Choosing the Correct Inductance Value 20 Encode Clock for ADQ 20 GSM Test Clock b reb eee 21 Interfacing iere 2 22 PCB Design Guidelines for Chip Scale Package 22 Output Matching ete e RR a 23 Outline Dimensions tieni 24 Ordering Guides iue needed endete 24 Rev A Page 2 of 24 SPECIFICATIONS ADF4360 9 AV pp DVpp 3 3 V 10 AGND DGND 0 V Ta Tum to Tmax unless otherwise noted Table 1 Parameter BVersion Unit Conditions Comments REFin CHARACTERISTICS Input Frequency 10 250 MHz min MHz max For f 10 MHz use a dc coupled CMOS compatible square wave slew rate 21 V us REFin Input Sensitivity 0 7 AVop V min V AC coupled 0 to AVpp V CMOS compatible REFin Input Capacitance 5 0 pF max REFin Input Current 60 max PHASE DETECTOR Phase Detector Frequency 8 M
26. evel of the VCO see the truth table in Figure 23 Mute Till Lock Detect DB11 ofthe control latch in the ADF4360 family is mute till lock detect bit This function when enabled ensures that the RF outputs are not switched on until the PLL is locked CP Gain DB10 of the control latch in the ADF4360 family is the charge pump gain bit When it is programmed to 1 Current Setting 2 is used When programmed to 0 Current Setting 1 is used Charge Pump Three State This bit DB9 puts the charge pump into three state mode when programmed to a 1 For normal operation it should be set to 0 Phase Detector Polarity The PDP bit in the ADF4360 family sets the phase detector polarity The positive setting enabled by programming a 1 is used whengusing theton chip a passive loop filter or with an active noninverting filterdt can also be set to 0 which is required if an active inverting loop filter is used DIVOUT Control The on chip multiplexer is controlled by D3 D2 and D1 see the truth table in Figure 23 Counter Reset DB4 is the counter reset bit for the ADF4360 family When this is 1 the R counter and the A B counters are reset For normal operation this bit should be 0 Core Power Level and PC2 set the power level in the VCO core The recommended setting is 5 mA The 7 5 mA setting is permissible in some applications see the truth table in Figure 23 Rev A Page 18 of 24 ADF4360 9 N COUNTER L
27. h pulse width equal to the inverse of the VCO frequency Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry This is enabled by the mute till lock detect MTLD bit in the That is control latch Pulse Width seconds 1 fvco Frequency Hz RFourA RFourB See Figure 21 for a graphical description By selecting the divide by 2 function this divided down frequency can in turn be divided by 2 again This provides a 5096 duty cycle in contrast to the A counter output which may be more suitable for some applications see Figure 21 fvco Figure 19 RF Output Stage fvco A A 4 DIVOUT STAGE The output multiplexer on the ADF4360 family allows the user to access various internal points on the chip The state of DIVOUT fuco 2A A 4 is controlled by D3 D2 and D1 in the control latch The full truth table is shown in Figure 23 Figure 20 shows the DIVOUT section in block diagram form 07139020 07139 021 Figure 21 DIVOUT Waveforms Rev A Page 12 of 24 LATCH STRUCTURE Figure 22 shows the three on chip latches for the ADF4360 9 The two LSBs decide which latch is programmed CONTROL LATCH OUTPUT POWER LEVEL CURRENT SETTING 2 CURRENT SETTING 1 RESERVED RESERVED MUTE TILL DIVOUT CONTROL CP GAIN DETECTOR POLARITY
28. ired between programming the control latch and programming the N counter latch This interval is necessary to allow the transient behavior of the ADF4360 9 during initial power up to settle Table 6 Cx Capacitance vs Interval and Phase Noise ADF4360 9 During initial power up a write to the control latch powers up the part and the bias currents of the VCO begin to settle If these currents have not settled to within 10 of their steady state value and if the N counter latch is then programmed the VCO may not oscillate at the desired frequency which does not allow the band select logic to choose the correct frequency band and the ADF4360 9 may not achieve lock If the recommended interval is inserted and the N counter latch is programmed the band select logic can choose the correct frequency band and the part locks to the correct frequency The duration of this interval is affected by the value of the capacitor on the Cx pin Pin 14 This capacitor is used to reduce the close in noise of the ADF4360 9 VCO The recommended value of this capacitor is 10 uF Using this value requires an interval of 215 ms between the latching in of the control latch bits and latching in of the N counter latch bits If a shorter delay is required the capacitor can be reduced A slight phase noise penalty is incurred by this change which is further explained in Table 6 Recommended Interval Between Open Loop Phase Noise 2 10 kHz Offset
29. ise 180 MHz VCO 360 MHz Figure 9 DIVOUT Phase Noise 52 MHz VCO 312 MHz PFD Frequency 1 MHz Loop Bandwidth 40 kHz Jitter 1 3 ps PFD Frequency 1 6 MHz Loop Bandwidth 40 kHz Jitter 1 4 ps Divide by A Selected 2 Divide by A 2 Selected A 3 Rev A Page 8 of 24 ADF4360 9 60 80 SEN ORBI ARS N 90 2 100 110 120 7 130 C1 FREQUENCY 90MHz a C1 DUTY 28 98 140 C1 PEAK TO 1 55 150 160 5 5 100 1 10 100 1 10 500mV M 2 00ns A CH1 20mV FREQUENCY OFFSET Hz Figure 10 DIVOUT Phase Noise 45 MHz VCO 360 MHz Figure 13 DIVOUT 90 MHz Waveform VCO 360 MHz Divide by A Selected PFD Frequency 1 6 MHz Loop Bandwidth 60 kHz Jitter 1 4 ps A 4 Duty Cycle 2596 Divide by A 2 Selected A 2 100 PHASE NOISE dBc Hz IN o C1 FREQUENCY 36 01MHz 4 n C1 DUTY 13 13 C1 PEAK TO 1 28V 07139 011 07139 014 160 1k 10k 100k 1M 10M 500mV M 5 00ns A CH1 7 920mV FREQUENCY OFFSET Hz Figure 11 DIVOUT Phase Noise over Temperature 52 MHz VCO 312 MHz Figure 14 DIVOUT 36 MHz Waveform VCO 360 MHz Divide by A Selected PFD Frequency 1 MHz Loop Bandwidth 60 k
30. proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev Page 6 of 24 ADF4360 9 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 20 DIVOUT Qa Za gt 2 o2 aaza2 TONTK OD ANNAN CPGND 18 DATA 7 CLK AGND ADF4360 9 6 REFiy RFoutB VIEW to Scale 07139 003 Figure 3 Pin Configuration Table 4 Pin Function Descriptions Pin No Mnemonic Description 1 CPGND Charge Pump Ground This is the ground return path for the charge pump 2 AVop Analog Power Supply This ranges from 3 0 V to 3 6 V Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin AVop must have the same value as DVpp 3 8 11 22 AGND Analog Ground This is the ground return path of the prescaler and VCO 4 RFoutA VCO Output The output level is programmable from 0 dBm to 9 dBm See the Output Matching section for a description of the various output stages 5 RFourB VCO Complementary Output The output level is programmable from 0 dBm to 9 dBm See the Output Matching section for a description of the various output stages 6 Vvco Power Supply the VCO This ranges from 3 0 V to 2 6 capaditors to the analog ground plane shduld be dlose a
31. r entering the locked state With LDP at 1 five cycles are taken with LDP at 0 three cycles are taken Test Mode Bit DBI9 is the test mode bit TMB and should be set to 0 With TMB 0 the contents of the test mode latch are ignored and normal operation occurs as determined by the contents of the control latch R counter latch and N counter latch Note that test modes are for factory testing only and should not be programmed by the user Band Select Clock DB20 and B21 Set a divider for the band select logic clock input The output of the R counter is by default the value used to clock the band select logic if this value is too high gt 1 MHz a divider can be switched on to divide R counter output to a smaller value see Figure 25 A value of 8 is recommended Reserved Bits DB23 to DB22 are spare bits that are designated as reserved They should be programmed to 0 Rev A Page 19 of 24 ADF4360 9 APPLICATIONS CHOOSING THE CORRECT INDUCTANCE VALUE The ADF4360 9 can be used at many different frequencies simply by choosing the external inductors to give the correct output frequency Figure 27 shows a graph of both minimum and maximum frequency vs the external inductor value The correct inductor should cover the maximum and minimum frequencies desired The inductors used are 0603 CS or 0805 CS type from Coilcraft To reduce mutual coupling the inductors should be placed at right angles to
32. rmal pad to improve thermal performance of the package If vias are used they should be incorporated into the thermal pad at 1 2 mm pitch grid The via diameter should be between 0 3 mm and 0 33 mm and the via barrel should be plated with 1 ounce of copper to plug the via The user should connect the printed circuit thermal pad to AGND This is internally connected to AGND Rev A Page 22 of 24 OUTPUT MATCHING There are a number of ways to match the VCO output of the ADF4360 9 for optimum operation the most basic is to use a 51 resistor to Vvco A dc bypass capacitor of 100 pF is connected in series as shown in Figure 33 Because the resistor is not frequency dependent this provides a good broadband match The output power in the circuit in Figure 33 typically gives 9 dBm output power into a 50 load Vvco 510 100pF RFour F 500 Figure 33 Simple Output Stage 07139 030 better solution is to use a shunt inductor acting as an RF choke to Vvco This gives a better match and therefore more output power Experiments have shown that the circuit shown in Figure 34 provides an excellent match to 50 over the operating range of the ADF4360 9 This gives approximately 0 dBm output power across the specific frequency range of the ADF4360 9 using the recommended shunt inductor followed by a 100 pF dc blocking capacitor 1 s y RFour NF 500 Figure 34 Optimum Output Stage 07139 031 ADF4360
33. s possible to this pin must have the same 1 as 7 Control Input to the VCO This voltage determines the output frequency and is derived from filtering the CP output voltage 9 L1 An external inductor to AGND should be connected to this pin to set the ADF4360 9 output frequency L1 and L2 need to be the same value 470 resistor should be added in parallel to AGND 10 L2 An external inductor to AGND should be connected to this pin to set the ADF4360 9 output frequency L1 and L2 need to be the same value A 470 O resistor should be added in parallel to AGND 12 Cc Internal Compensation Node This pin must be decoupled to ground with a 10 nF capacitor 13 Rser Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the synthesizer The nominal voltage potential at the pin is 0 6 V The relationship between Ice and Rser is 11 7 5 Rser For example 4 7 and lcemax 2 5 mA 14 Cn Internal Compensation Node This pin must be decoupled with 10 uF capacitor 15 DGND Digital Ground 16 REFin Reference Input This is a CMOS input with a nominal threshold of Vop 2 and dc equivalent input resistance of 100 see Figure 16 This input can be driven from a TTL or CMOS crystal oscillator it can be ac coupled 17 CLK Serial Clock Input This serial clock is used to clock in the serial data to the registers The data is latch
34. voltage varying as temperature changes The 7 5 mA VCO core power setting shows less tuning voltage variation over temperature in these applications and can be used provided that 240 resistors are used in parallel with Pin 9 and Pin 10 instead of the default 470 Rev A Page 11 of 24 ADF4360 9 OUTPUT STAGE PVop The RFovrA and RFourB pins of ADF4360 family are connected to the collectors of an NPN differential pair driven A GOUNTER 2 OUTPUT by buffered outputs of the VCO as shown in Figure 19 To COUNTER OUTPUT ie CONTROL DIVOUT allow the user to optimize the power dissipation vs the output R COUNTER OUTPUT power requirements the tail current of the differential pair is N COUNTER OUTPUT programmable via Bit PL1 and Bit PL2 in the control latch Four current levels can be set 3 5 mA 5 mA 7 5 mA and 11 mA These levels give output power levels of 9 dBm 6 dBm 07139 018 DGND 3 dBm and 0 dBm respectively using the correct shunt inductor s 5 Figure 20 DIVOUT Circuit to Vp and ac coupling into a 50 load Alternatively both outputs can be combined in 1 1 1 transformer or 180 The primary use of this pin is to derive the lower frequencies microstrip coupler see the Output Matching section from the VCO by programming various divider values to the auxiliary A divider Values ranging from 2 to 31 are possible The duty cycle of this output is 1 A times 10096 with the logic hig
35. x Interface Figure 32 shows the interface between the ADF4360 family and the ADSP 21xx digital signal processor The ADF4360 family needs a 24 bit serial word for each latch write The easiest way to accomplish this using the ADSP 21xx family is to use the autobuffered transmit mode of operation with alternate framing This provides a means for transmitting an entire block of serial data before an interrupt is generated ADSP 21xx 1 0 ports LOCK DETECT 07139 029 Figure 32 ADSP 21xx to ADF4360 x Interface Set up the word length for 8 bits and use three memory locations for each 24 bit word To program each 24 bit latch store the 8 bit bytes enable the autobuffered mode and write to the transmit register of the DSP This last operation initiates the autobuffer transfer PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The leads the chip scale bilo CP 24 2 are rectangular The pad for these mm longer than the package lead length and 0 05 mm wider than the package lead width The lead should be centered on the pad to ensure that the solder joint size is maximized The bottom of the chip scale package has a central thermal pad The thermal pad on the PCB should be at least as large as this exposed pad On the PCB there should be a clearance of at least 0 25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided Thermal vias can be used on the PCB the
36. yp To within 10 Hz of final frequency Rev A Page 3 of 24 ADF4360 9 Parameter BVersion Unit Conditions Comments Frequency Pushing Open Loop 0 24 MHz V typ Frequency Pulling Open Loop 10 Hztyp Into 2 00 VSWR load Harmonic Content Second 16 dBctyp Harmonic Content Third 21 dBc typ Output Power 7 9 0 dBm typ Using tuned load programmable in 3 dB steps see Figure 35 Output Power 8 14 9 dBm typ Using 50 resistors to Vvco programmable in 3 dB steps see Figure 33 Output Power Variation t3 dB typ VCO Tuning Range 1 25 2 5 V min V max VCO NOISE CHARACTERISTICS VCO Phase Noise Performance 91 dBc Hz typ 10 kHz offset from carrier 117 dBc Hz typ 100 kHz offset from carrier 139 dBc Hz typ 1 MHz offset from carrier 140 dBc Hz typ 3 MHz offset from carrier 147 dBc Hz typ 10 MHz offset from carrier Normalized In Band Phase Noise 19 1 218 dBc Hz typ In Band Phase Noise 110 dBc Hz typ 1 kHz offset from carrier RMS Integrated Jitter 1 4 ps typ Measured at RFourA Spurious Signals Due to PFD Frequency 75 dBc typ DIVOUT CHARACTERISTICS Integrated Jitter Performance VCO frequency 320 MHz to 380 MHz Integrated from 100 Hz to 1 GHz DIVOUT 180 MHz 14 2 output selecte DIVOUT 95 MHz 1 4 ps rms A 32 A Z outputselected DIVOUT 80 MHz b14 ps rms t A 5 NP output sef amp tted 52 MHz 14 ps rms A 3 A 2 output selected VCO 312 MHz PFD

ANALOG DEVICES ADF4360-9 handbook

Contents

Download Pdf Manuals

Related Search

Related Contents