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ANALOG DEVICES ADF4113HV handbook

1. OV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability This device is a high performance RF integrated circuit with an ESD rating of lt 1 kV and it is ESD sensitive Proper precautions should be taken for handling and assembly Rev A Page 5 of 20 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 5 Pin Function Descriptions TOP VIEW 15 MUXOUT Not to Scale 14 LE ADF4113HV 13 DATA TOP VIEW 12 CLK Not to Scale 11 3 aozaa E s lt 8 Figure 3 TSSOP Pin Configuration Figure 4 LFCSP Pin Configuration TSSOP LFCSP Pin No Pin No Mnemonic Description 1 19 Rset Connecting a resistor between this pin and CPGND sets the maximum charge pump output current The nominal voltage potential at the Rser pin is 0 56 V for the ADF4113HV The relationship between Ice and Rser is lcemax 3 Rser Therefore with Rser 4 7 Icpmax 640 pA 2 20 CP Charge Pump Output When enabled this pin provides lcp to the external loop filter in turn this drives the external VCO 3 1 CPGND Charge Pump Ground CPGND is the ground return path for the char
2. seen 4 Input Shift Register seen 10 Absolute Maximum Ratings esee 5 FurictiomLEatchi sooo ad 13 Transistor enero itenenee tenenti istis 5 Applications eene tte et ee ribi vetta 15 Thermal Resistancesn eintritt 5 Using a Digitial to Analog Converter to Drive the Rser Pinas dieser erret 15 ESD Caution 5 Wetten ARR m 15 Pin Configurations and Function Descriptions 6 PCB Design Guidelines for Chip Scale Package 16 Typical Performance Characteristics sse 7 Outline Dimensions sees 17 Circuit Description 9 Ordering Guide oe rote RT REIR 17 Reference Input Section eerte 9 RE Input eee thin eh en eie ie 9 REVISION HISTORY 9 08 Rev 0 to Rev A Changes to Figure 22 entere tenen tertiae 13 1 07 Revision 0 Initial Version Rev A Page 2 of 20 SPECIFICATIONS DVpp 3 V 1096 5 V 10 13 5 V lt 16 5 AGND DGND CPGND 0 V 4 7 dBm referred to 50 Ta Tmn to Tmax unless otherwise noted Operating temperature range for B version 40 to 85 C Table 1 Parameter B Version B Chips Unit Test Conditions Comments RF CHARACTERISTICS 3 V RF Input Sensitivity 15 0 15 0 dBm min max RF Input Frequency 0 2 3 7 0 2 3 7 GHz min max For lower frequ
3. DATA 1 T Figure 2 Timing Diagram Rev A Page 4 of 20 Ds DB1 DBO LSB CONTROL BIT C2 CONTROL BIT C1 06223 002 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted TRANSISTOR COUNT Table 3 The transistor count is 12 150 CMOS and 348 bipolar Parameter Rating THERMAL RESISTANCE AVpp to GND 0 3Vto 7 V Table 4 Thermal Resistance AVopp to DVpp 0 3V to 40 3 V Package Type On Unit Ve to GND 0 3V to 18 V TSSOP 1504 C W Digital I O Voltage to GND 0 3 V to Voo 0 3 V LFCSP Paddle Soldered 122 C W Analog Voltage to GND 0 3V to Ve 0 3 V LFCSP Paddle Not Soldered 216 C W REFin RFinA RFinB to GND 0 3 V to Voo 0 3 V RFinA to RFinB 320 mV Operating Temperature Range Industrial B Version Storage Temperature Range Maximum Junction Temperature Lead Temperature Soldering Vapor Phase 60 sec Infrared 15 sec 40 to 85 C 65 to 150 C 150 C 215 C 220 C ESD CAUTION without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge 1GND AGND
4. 89207 0 9512 0 8886 0 93458 0 89022 i 0 94782 0 96323 0 96875 0 90566 0 92216 0 90307 3 0 93755 a 0 89318 3 0 96178 0 89806 4 0 94354 0 89565 4 0 95189 ul 0 88538 5 0 97647 0 89699 5 0 98619 9 0 89927 6 0 95459 0 87797 E 0 97945 0 90765 7 0 98864 0 88526 T 0 97399 0 81267 8 0 97216 0 90357 0 92954 0 92087 3 0 93788 8 2 2 2 O S gt gt wo e e e 1 1 1 1 1 FREQUENCY Hz Figure 5 S Parameter Data for the ADF4113HV RF Input Up to 1 8 GHz Figure 8 Reference Spurs RF 1000 MHz PFD 1 MHz 70 Y LU 9o HH 1kHz 5 100 86 33dBc Hz x 2 440 1 120 CARRIER POWER 0 88dBm a o 5 130 m 140 150 8 160 170 0 1k 2k 3k 4k 5k 6k 100 1k 10k 100k 1M RF INPUT FREQUENCY MHz FREQUENCY OFFSET Hz Figure 6 Input Sensitivity Figure 9 Integrated Phase Noise RF 1800 MHz PFD 1 MHz 13 1 V RMS Noise 1 16 70 0 80 10 Al T 90 Bb T IN 20 100 Ir 1kHz T 30 8 91 08dBc Hz m 5 110 40 hn u RA W 429 CARRIER POWER 5 09dBm 5 o 130 Q 60 a E 2 140 70 150 80 160 3 90 170 8 100 100 1k 10k 100k 1M 2 gt gt 2 gt a 6 d 8 A R A FREQUENCY OFFSET T e g qu x So FREQUENCY Hz Figure 7 Integrated Phase Noise Figure 10 Referenc
5. AVop Vp 13 5 16 5 13 5 16 5 V min V max Ipp Aloo 05 16 11 mA max 11 mA typical lp 0 25 0 25 mA max 25 Low Power Sleep Mode 1 1 typ NOISE CHARACTERISTICS Normalized Phase Noise Floor 212 212 dBc Hz typ The B chip specifications are given as typical values This is the maximum operating frequency of the CMOS counters The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value 3 AC coupling ensures AVpp 2 bias Guaranteed by characterization TA 25 C AVpp DVpp 5 5 V P 16 RF 900 MHz 6 The synthesizer phase noise floor is estimated by measuring the in band phase noise at the output of the VCO PNror and subtracting 20logN where is the divider value and 10logfero PNsyn 10logfrro 20logN Rev Page 3 of 20 TIMING CHARACTERISTICS Guaranteed by design but not production tested DVpp 3 V 10 5 V 10 13 5 V lt Ve 16 5 V AGND CPGND 0 V 4 7 Ta Tmn to Tmax unless otherwise noted Table 2 Parameter Limit at Tmn to Tmax B Version Unit Test Conditions Comments t 20 ns min LE setup time t 10 ns min DATA to CLK setup time ts 10 ns min DATA to CLK hold time ta 25 ns min CLK high duration ts 25 ns min CLK low duration te 10 ns min CLK to LE setup time t7 20 ns min LE pulse width Timing Diagram t4 ts CLK
6. The destination latch is determined by the state of the two control bits C2 C1 in the shift register These are the two LSBs DB1 and DBO as shown in Figure 2 The truth table for these bits is shown in Table 6 Figure 19 shows a summary of how the latches are programmed Table 6 C2 C1 Truth Table Control Bits C2 C1 Data Latch 0 0 R counter 0 1 N counter A and B 1 0 Function latch including prescaler Rev A Page 10 of 20 Latch Summary REFERENCE COUNTER LATCH ANTI BACKLASH RESERVED PULSE 14 BIT REFERENCE COUNTER WIDTH CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB1 ZHNEHERENENENLLZLZLZLJEGLOLOEGEGEJEJICIENXCQEJES N COUNTER LATCH 13 BIT B COUNTER 6 BIT A COUNTER DB7 DB6 DB5 DB4 DB3 CONTROL BITS FUNCTION LATCH PRE SCALER CURRENT VALUE RESERVED SETTING RESERVED MUXOUT CONTROL CP THREE STATE POLARITY PD DB23 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 C2 0 C1 1 P2 Figure 19 Latch Summary Tables Reference Counter Latch Map ANTI BACKLASH RESERVED rr 14 BIT REFERENCE COUNTER 06223 019 C2 1 C1 0 CONTROL BITS fama ee tee ee ee THESE BITS MUST SET AS INDICATED FOR NORMAL OPERATION ANTI BACKLASH DIVIDE RATIO ABP2 1 1 0 PULSE WID
7. in Figure 22 Prescaler Value P2 and P1 in the function latch set the prescaler values The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 200 MHz Thus with an RF frequency of 2 GHz a prescaler value of 16 17 is valid but a value of 8 9 is not PD Polarity This bit sets the phase detector polarity bit See Figure 22 CP Three State This bit controls the CP output pin With the bit set high the CP output is put into three state With the bit set low the CP output is enabled Rev A Page 13 of 20 DEVICE PROGRAMMING AFTER INITIAL POWER UP After initial power up of the device there are two ways to program the device CE Pin Method 1 Apply Vr 2 Bring CE low to put the device into power down This is an asynchronous power down in that it happens immediately 3 Program the function latch 10 Program the R counter latch 00 Program the AB counter latch 01 4 Bring CE high to take the device out of power down The R and AB counters resume counting in close alignment After CE goes high a duration of 1 us is sometimes required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state CE can be used to power the device up and down to check for channel activity The input register does not need to be repro grammed each time the device is disabled and enabled as long as it has been programmed at least once after Vpp
8. is 4 MHz This means that the maximum rate at which the output frequency can be changed is 166 kHz SCLOCK CLK MOSI DATA ADuC812 ADF4113HV LE PORTS CE MUXOUT LOCK DETECT 06223 024 Figure 24 ADuC812 to ADF4113HV Interface Rev A Page 15 of 20 ADSP 21xx Interface Figure 25 shows the interface between the ADF4113HV and the ADSP 21xx digital signal processor The ADF4113HV needs a 24 bit serial word for each latch write The easiest way to accomplish this using the ADSP 21xx family is to use the auto buffered transmit mode of operation with alternate framing This provides a means for transmitting an entire block of serial data before an interrupt is generated ADSP 21xx ADF4113HV TFS 1 0 zl Figure 25 ADSP 21xx to ADF4113HV Interface MUXOUT LOCK DETECT 06223 025 Set up the word length for eight bits and use three memory locations for each 24 bit word To program each 24 bit latch store the three 8 bit bytes enable the auto buffered mode and then write to the transmit register of the DSP This last opera tion initiates the autobuffer transfer PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package CP 20 1 are rectangular The printed circuit board pad for these should be 0 1 mm longer than the package land length and 0 05 mm wider than the package land width The land should be centered on the pad to ensure that the solder joint size is maximized T
9. to 1 0 respectively Figure 22 shows the input data format for programming the function latch Counter Reset DB2 F1 is the counter reset bit When DB2 is 1 the counter and the AB counters are reset For normal operation this bit should be 0 Upon powering up the F1 bit must be disabled and the N counter resumes counting in close alignment with the R counter The maximum error is one prescaler cycle Power Down DB3 F2 in the function latch provides a software power down for the ADF4113HV The device powers down immediately after latching a 1 into Bit F2 When the CE pin is low the device immediately powers down regardless of the state of the power down bit F2 When a power down is activated either through software or a CE pin activated power down the following events occur e Allactive dc current paths are removed e TheR and timeout counters are forced to their load state conditions e The charge pump is forced into three state mode e digital clock detect circuitry is reset e The RFwA and inputs are debiased e The reference input buffer circuitry is disabled e The input register remains active and capable of loading and latching data MUXOUT Control The on chip multiplexer is controlled by M3 M2 and M1 on the ADF4113HV Figure 22 shows the truth table Charge Pump Currents CPI3 12 and CPI1 program the current setting for the charge pump The truth table is given
10. with a power supply ranging from 2 7 V to 5 5 V and can be powered down when not in use FUNCTIONAL BLOCK DIAGRAM AVpp DVpp Vp CPGND Rset REFERENCE PHASE FREQUENCY Ec DETECTOR R COUNTER LATCH 24 BIT INPUT REGISTER SDour FROM FUNCTION LATCH MUXOUT IT 13 COUNTER Q M3 M2 M1 6 BIT A COUNTER ADF4113HV 06223 001 Figure 1 Rev Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2007 2008 Analog Devices Inc All rights reserved TABLE OF CONTENTS Features ERR D aoa 1 Prescaler P Pie 9 Applications oe n ORDRE UR Etre 1 Aand B Counters iicet ee HESS 9 Functional Block Diagram seen 1 R Counter 9 Revision History 2 Phase Frequency Detector PFD and Charge Pump 10 Specifications 3 Muxout and Lock Detect sssssseeeeeeen 10 Timing Characteristics
11. ANALOG High Voltage DEVICES Charge Pump PLL Synthesizer ADF4113HV FEATURES GENERAL DESCRIPTION High voltage charge pump 15 V The ADF4113HV is an integer N frequency synthesizer with a 2 7 V to 5 5 V power supply high voltage charge pump 15 V The synthesizer is designed 200 MHz to 4 0 GHz frequency range for use with voltage controlled oscillators VCOs that have Pin compatible with ADF4110 ADF4111 ADF4112 ADF4113 high tuning voltages up to 15 V Active loop filters are often ADF4106 and ADF4002 synthesizers used to achieve high tuning voltages but the ADF4113HV Two selectable charge pump currents charge pump can drive a high voltage VCO directly with a Digital lock detect passive loop filter The ADF4113HV can be used to implement Power down mode local oscillators in the upconversion and downconversion Loop filter design possible with ADIsimPLL sections of wireless receivers and transmitters It consists of a low noise digital phase frequency detector PFD a precision APPLICATIONS high voltage charge pump a programmable reference divider Applications using high voltage VCOs programmable A and B counters and a dual modulus prescaler IF RF local oscillator LO generation in base stations P P 1 Point to point radio LO generation Clock for analog to digital and digital to analog converters Wireless LANs PMR Communications test equipment A simple 3 wire interface controls all of the on chip registers The devices operate
12. DF4113HV has a simple SPI compatible serial interface for writing to the device CLK DATA and LE control the data transfer When latch enable LE goes high the 24 bits that have been clocked into the input register on each rising edge of CLK are transferred to the appropriate latch See Figure 2 for the timing diagram and Table 6 for the latch truth table The maximum allowable serial clock rate is 20 MHz This means that the maximum update rate possible for the device is 833 kHz or one update every 1 2 us This rate is more than adequate for systems that have typical lock times in the hundreds of microseconds ADuC812 Interface Figure 24 shows the interface between the ADF4113HV and the ADuC812 MicroConverter Because the ADuC812 is based on an 8051 core this interface can be used with any 8051 based microcontroller The MicroConverter is set up for SPI master mode with CPHA 0 To initiate the operation the I O port driving LE is brought low Each latch of the ADF4113HV needs a 24 bit word This is accomplished by writing three 8 bit bytes from the MicroConverter to the device When the third byte has been written the LE input should be brought high to complete the transfer I O port lines on the ADuC812 are also used to control power down CE input and to detect lock MUXOUT configured as lock detect and polled by the port input When the ADuC812 is operating in the SPI master mode the maximum SCLOCK rate of the ADuC812
13. P 1 Together with the A and B counters the dual modulus prescaler P P 1 enables the large division ratio N to be realized by N BP A The dual modulus prescaler operating at CML levels takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and CMOS B counters The pre scaler is programmable it can be set in software to 8 9 16 17 32 33 or 64 65 It is based on a synchronous 4 5 core A AND B COUNTERS The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter The counters are specified to work when the prescaler output is 200 MHz or less for AVpp 5 V Thus with an RF input frequency of 2 5 GHz a prescaler value of 16 17 is valid but a value of 8 9 is not Pulse Swallow Function The A and B counters in conjunction with the dual modulus prescaler make it possible to generate output frequencies that are spaced only by the reference frequency divided by R The equation for the VCO frequency is fvco P x B A frerw R where fvco output frequency of external voltage controlled oscillator VCO P preset modulus of dual modulus prescaler B preset divide ratio of binary 13 bit counter 3 to 8191 A preset divide ratio of binary 6 bit swallow counter 0 to 63 frer output frequency of the external reference frequency oscillator preset divide ratio of binary 14 bit
14. TH 1 7 2ns ONLY ALLOWED SETTING Figure 20 Reference Counter Latch Bit Map Rev A Page 11 of 20 06223 020 AB Counter Latch Map CONTROL 13 BIT B COUNTER 6 BIT A COUNTER BITS 0816 DB15 DB14 DB13 DB12 DB6 DB5 DB4 DB1 DBO B9 B7 B6 B5 5 4 C2 0 C1 1 A COUNTER DIVIDE RATIO 0 1 2 3 LOCK DETECT PRECISION 10ns 3ns B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED NOT ALLOWED 06223 021 Figure 21 B Counter Latch Map Rev A Page 12 of 20 Function Latch Map CURRENT SETTING RESERVED MUXOUT CONTROL CONTROL BITS CP THREE STATE COUNTER RESET DB6 DB5 DB4 o w N DB1 DBO CPI2 1 0 0 1 1 PRESCALER VALUE 8 9 16 17 32 33 64 65 CHARGE PUMP TPUT NORMAL THREE STATE M3 M2 M1 EN C2 1 C1 0 F1 COUNTER OPERATION 0 NORMAL 1 R A B COUNTERS HELD IN RESET PHASE DETECTOR POLARITY OPERATION POSITIVE NORMAL NEGATIVE POWER DOWN OUTPUT THREE STATE OUTPUT DIGITAL LOCK DETECT ACTIVE HIGH N DIVIDER OUTPUT DVpp R DIVIDER OUTPUT ANALOG LOCK DETECT SERIAL DATA OUTPUT DGND 06223 022 Figure 22 Function Latch Map FUNCTION LATCH The on chip function latch is programmed with C2 and C1 set
15. e Spurs RF 1800 MHz PFD 1 MHz RF 1000 MHz PFD 1 MHz 1 8 V RMS Noise 0 93 Rev A Page 7 of 20 06223 043 06223 040 06223 041 FIRST REFERENCE SPUR LEVEL dBc PHASE NOISE dBc Hz 20 40 60 80 100 0 2 4 6 8 10 12 14 16 TUNING VOLTAGE V Figure 11 PFD Spurs 1 MHZ vs Vrune 40 20 0 20 40 60 80 100 TEMPERATURE C Figure 12 Phase Noise vs Temperature RF 1500 MHz PFD 1 MHZ 06223 044 06223 045 Rev A Page 8 of 20 CHARGE PUMP CURRENT pA 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 Vcp V Figure 13 Charge Pump Output Characteristics 06223 026 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 14 SW1 and SW2 are normally closed switches NC in Figure 14 SW3 is normally open NO in Figure 14 When power down is initiated SW3 is closed and SW1 and SW2 are opened This ensures that there is no loading of the REF pin on power down POWER DOWN CONTROL TO R COUNTER z ES 06223 014 Figure 14 Reference Input Stage RF INPUT STAGE The RF input stage is shown in Figure 15 It is followed by a two stage limiting amplifier to generate the current mode logic CML clock levels needed for the prescaler 06223 015 AGND Figure 15 RF Input Stage PRESCALER P
16. encies ensure SR 130 V us Prescaler Output Frequency 165 165 MHz max RF CHARACTERISTICS 5 V RF Input Sensitivity 10 0 10 0 dBm min max RF Input Frequency 0 2 3 7 0 2 3 7 GHz min max For lower frequencies ensure SR 130 V us 0 2 4 0 0 2 4 0 GHz min max Input level 5 dBm Prescaler Output Frequency 200 200 MHz max REFin CHARACTERISTICS REFin Input Frequency 5 150 5 150 MHz min max For f 5 MHz ensure SR gt 100 V us Reference Input Sensitivity 0 4 AVop 0 4 AVop V p p min max AVpp 3 3 V biased at AVpp 2 1 0 AVpp 1 0 AVop V p p min max For f gt 10 MHz AVpp 5 V biased at AVpp 2 REFin Input Capacitance 10 10 pF max REFw Input Current 100 100 max PHASE DETECTOR FREQUENCY 5 5 MHz max CHARGE PUMP Sink Source Rser 4 7 High Value 640 640 typ Low Value 80 80 typ Absolute Accuracy 2 5 2 5 96 typ Rser Range 3 9 10 3 9 10 kO typ Three State Leakage Current 5 5 nA max Sink and Source Current Matching 3 3 96 typ 1VsVesVe 1V lce vs 1 5 1 5 96typ 1VsVesVe 1V vs Temperature 2 2 typ Vp 2 LOGIC INPUTS Input High Voltage 0 8 x DVpp 0 8 x DVpp V min Input Low Voltage 0 2 x DVpp 0 2 x DVpp V max Input Current 1 1 max Cn Input Capacitance 10 10 pF max LOGIC OUTPUTS Output High Voltage DVoo 0 4 DVop 0 4 V min lon 500 Output Low Voltage 0 4 0 4 V max lo 500 uA POWER SUPPLIES AVop 2 7 5 5 2 7 5 5 V min V max DVop AVpp
17. ge pump 4 2 3 AGND Analog Ground This is the ground return path of the prescaler 5 4 RFinB Complementary Input to the RF Prescaler This point should be decoupled to the ground plane with a small bypass capacitor typically 100 pF 6 5 RFinA Input to the RF Prescaler This small signal input is ac coupled from the VCO 7 6 7 Analog Power Supply The power supply can range from 2 7 V to 5 5 V Decoupling capacitors to the analog ground plane should be placed as close as possible to this AVop must be the same value as DVpp 8 8 REFin Reference Input This pin is a CMOS input with a nominal threshold of Vop 2 and an equivalent input resistance of 100 This input can be driven from a TTL or CMOS crystal oscillator can be ac coupled 9 9 10 DGND Digital Ground 10 11 CE Chip Enable A Logic low on this pin powers down the device and puts the charge pump output into three state mode Taking the pin high powers up the device depending on the status of the Power Down Bit PD1 11 12 CLK Serial Clock Input This serial clock is used to clock in the serial data to the registers The data is latched into the 24 bit shift register on the CLK rising edge This input is a high impedance CMOS input 12 13 DATA Serial Data Input The serial data is loaded MSB first with the two LSBs being the control bits This input is a high impedance CMOS input 13 14 LE Load Enable CMOS Input When LE goes high the data stored in the shift register
18. he bottom of the chip scale package has a central thermal pad The thermal pad on the printed circuit board should be at least as large as this exposed pad On the printed circuit board provide a clearance of at least 0 25 mm between the thermal pad and the inner edges of the pad pattern This ensures that shorting is avoided Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package If vias are used they should be incorporated in the thermal pad at a 1 2 mm pitch grid The via diameter should be between 0 3 mm and 0 33 mm and the via barrel should be plated with 1 oz copper to plug the via The user should connect the printed circuit board thermal pad to AGND Rev A Page 16 of 20 OUTLINE DIMENSIONS 0 60 PIN 1 INDICATOR U 20 4 6 PIN 17 INDICATOR UUU EXPOSED PAD OT TOM VIEW NAN 16 15 11 10 0 80 MAX 12 MAX I 1 00 _ 0 65 TYP oss 1 0 05 MAX 060 0 02 NOM SEATING X Sag 0 20 COPLANARITY PLANE BSC REF 0 08 COMPLIANT TO JEDEC STANDARDS MO 220 VGGD 1 Figure 26 20 Lead Lead Frame Chip Scale Package LFCSP VO 4mm x 4 mm Body Very Thin Quad CP 20 1 Dimensions shown in millimeters TER H yoy 4 0 30 4 8 0 60 4l E SEATING 0 65 BSC PLANE COPLANARITY 0 10 COMPLIANT TO JEDEC STANDARDS MO 153 AB Figure 27 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 Dimensions shown in mill
19. imeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADF4113HVBRUZ 40 to 85 C 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 ADF4113HVBRUZ RL 40 to 85 C 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 ADF4113HVBRUZ RL7 40 C to 85 C 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 ADF4113HVBCPZ 40 to 85 C 20 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 20 1 ADF4113HVBCPZ RL 40 to 85 C 20 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 20 1 ADF4113HVBCPZ RL7 40 to 85 C 20 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 20 1 EVAL ADF41 13HVEB1Z Evaluation Board 17 RoHS Compliant Part Rev A Page 17 of 20 ADF4113HV NOTES Rev A Page 18 of 20 ADF4113HV NOTES Rev A Page 19 of 20 NOTES 2007 2008 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D06223 0 9 08 A DEVICES www analo g com Rev A Page 20 of 20
20. programmable reference counter 1 to 16 383 ee e eet Ng N BP A 13 BIT B COUNTER PRESCALER mE PIP 1 1 1 1 1 1 1 INPUT STAGE 1 1 1 1 1 1 1 6 BITA COUNTER jl Figure 16 A and B Counters 06223 016 R COUNTER The 14 bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase fre quency detector PFD Division ratios from 1 to 16 383 are allowed Rev A Page 9 of 20 PHASE FREQUENCY DETECTOR PFD AND CHARGE PUMP The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them Figure 17 is a simplified schematic The PFD includes a programmable delay element that controls the width of the antibacklash pulse This pulse ensures that there is no dead zone in the PFD transfer function and mini mizes phase noise and reference spurs Two bits in the reference counter latch ABP2 and ABPI control the width of the pulse See Figure 20 The only recommended setting for the antiback lash pulse width is 7 2 ns Vp CHARGE PUMP HIGH O R DIVIDER gt PROGRAMMABLE CP DELAY ABP1 ABP2 HIGH O N DIVIDER R DIVIDER N DIVIDER CP OUTPUT Figure 17 PFD Simplified Schematic and Timing in Lock 06223 017 MUXOUT AND LOCK DETECT The output multiplexer on the ADF4113HV allows the user to access vario
21. s is loaded into one of the four latches the latch is selected using the control bits 14 15 MUXOUT Multiplexer Output This multiplexer output allows either the lock detect the scaled RF or the scaled reference frequency to be externally accessed 15 16 17 DVpp Digital Power Supply This can range from 2 7 V to 5 5 V Decoupling capacitors to the digital ground plane 1pF 1nF should be placed as close as possible to this pin For best performance the 1 uF capacitor should be placed within 2 mm of the pin The placing of the 1nF capacitor is less critical but should still be within 5 mm of the pin DVop must have the same value as AVpp 16 18 Ve Charge Pump Power Supply Ve can range from 13 5 V to 16 5 V and should be decoupled appropriately Rev A Page 6 of 20 TYPICAL PERFORMANCE CHARACTERISTICS Loop bandwidth 25 kHz reference 10 MHz reference from Agilent E4440A PSA VCO Sirenza VCO190 1500T Y evaluation board EVAL ADF4113HVEBZ1 FREQ PARAM KEYWORD IMPEDANCE UNIT TYPE FORMAT 5 FREQ MAGS11 ANGS11 MAGS11 ANGS11 0
22. us internal points on the chip The state of MUXOUT is controlled by M3 M2 and M1 in the function latch Figure 22 shows the full truth table function latch map Figure 18 shows the MUXOUT section in block diagram form DVpp ANALOG LOCK DETECT 3 DIGITAL LOCK DETECT R COUNTER OUTPUT j_ MUX CONTROL MUXOUT N COUNTER OUTPUT SDOUT E DGND 8 Figure 18 MUXOUT Circuit Lock Detect MUXOUT can be programmed for two types of lock detect digital lock detect and analog lock detect Digital lock detect is active high When LDP in the AB counter latch is set to 0 digital lock detect is set high when the phase error on five consecutive phase detector PD cycles is less than 10 ns With LDP set to 1 five consecutive cycles of less than 3 ns are required to set the lock detect It stays high until a phase error greater than 25 ns is detected on any subsequent PD cycle Operate the N channel open drain analog lock detect with a 10 nominal external pull up resistor When lock has been detected this output is high with narrow low going pulses INPUT SHIFT REGISTER The ADF4113HV digital section includes a 24 bit input shift register a 14 bit R counter and a 19 bit N counter comprising a 6 bit A counter and a 13 bit B counter Data is clocked into the 24 bit shift register on each rising edge of CLK MSB first Data is transferred from the shift register to one of three latches on the rising edge of LE
23. was initially applied Counter Reset Method 1 Apply Vp 2 Conduct a function latch load 10 in 2 LSBs As part of this load 1 to the F1 bit This enables the counter reset 3 Conduct an R counter load 00 in 2 LSBs 4 Conduct an AB counter load 01 in 2 LSBs 5 Conduct a function latch load 10 in 2 LSBs As part of this load 0 to the F1 bit This disables the counter reset This sequence provides the same close alignment as the initiali zation method It offers direct control over the internal reset Note that counter reset holds the counters at load point and three states the charge pump but does not trigger synchronous power down Rev A Page 14 of 20 APPLICATIONS FREF AD5320 12 BIT V OUT DAC SPI COMPATIBLE SERIAL BUS NOTES 1 POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS ARE OMITTED FOR CLARITY LOOP FILTER 06223 023 Figure 23 Driving the Rser Pin with a Digital to Analog Converter USING A DIGITIAL TO ANALOG CONVERTER TO DRIVE THE PIN A digital to analog converter DAC can be used to drive the Rser pin of the ADF4113HV thus increasing the level of control over the charge pump current Ice This can be advantageous in wideband applications where the sensitivity of the VCO varies over the tuning range To compensate for this Ic can be varied to maintain good phase margin and ensure loop stability See Figure 23 for this configuration INTERFACING The A

ANALOG DEVICES ADF4113HV handbook

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