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ANALOG DEVICES AD9516-1 handbook

1. 120 110 125 120 130 9 a 435 aso 140 o o 2 2 145 u 140 150 150 155 160 2 160 10 100 1 10k 100 1 10M 100M 10 100 1k 10k 100k 1M 10M 100 FREQUENCY Hz i FREQUENCY Hz u Figure 31 Phase Noise Additive LVPECL 245 76 MHz Divide by 1 Figure 34 Phase Noise Additive LVDS 200 MHz Divide by 1 110 100 120 110 N N o o 130 120 o o z 2 140 130 4 4 150 140 H 160 150 we 10 100 1k 10k 100 1M 10M 100M 2 10 100 1k 10k 100k 1M 10M 100M 2 FREQUENCY Hz 3 FREQUENCY Hz Figure 32 Phase Noise Additive LVPECL 200 MHz Divide by 5 Figure 35 Phase Noise Additive LVDS 800 MHz Divide by 2 100 120 110 130 Mi N N 5 8 120 8 140 ul o o 2 2 130 150 2 140 160 150 E 170 10 100 1k 10k 100 1M 10M 100M 5 10 100 1k 10k 100 1M 10M 100M 2 FREQUENCY Hz 3 FREQUENCY
2. 1600 70 80 1400 90 z N 5 5 100 1200 10 5 120 lt x 1000 130 a 140 800 150 0 1 2 3 10k 100k 1M 10M 100M FREQUENCY GHz FREQUENCY Hz Figure 25 LVPECL Differential Swing vs Frequency Figure 28 Internal VCO Phase Noise Absolute Direct to LVPECL 2650 MHz ENSE 80 gt _ 90 z 100 4 0 110 2 600 5 m 2 120 cT u 130 a 500 z 150 0 100 200 300 400 500 600 700 800 40k ADOK Em pm 100M FREQUENCY MHz FREQUENCY Hz Figure 26 LVDS Differential Swing vs Frequency Figure 29 Internal VCO Phase Noise Absolute Direct to LVPECL 2475 MHz 70 80 _ 90 z a 100 5 ur 110 5 o E z 2 M a 2 120 130 140 0 100 200 300 400 500 8 m 8 OUTPUT FREQUENCY MH 19 M M 100M S MHz FREQUENCY Hz Figure 27 CMOS Output Swing vs Frequency and Capacitive Load Figure 30 Internal VCO Phase Noise Absolute Direct to LVPECL 2300 MHz Rev 0 Page 22 of 84 AD9516 1
3. VCO Dx Output Duty Cycle Divider N M 2 DCCOFF 1 DCCOFF 0 Even 1 divider 50 50 bypassed Odd 3 1 divider 33 3 1 X 3 bypassed Odd 5 1 divider 40 2 X 5 bypassed Even Even N 1 50 N M 2 requires M N Odd N 1 50 N M 2 requiresM N 1 3 Even 1 50 2 requires Odd 3 Odd N 1 4 X96 6N 9 2 requires 1 Odd 5 Even N 1 50 N M 2 requires M N Odd 5 Odd N 1 5N 7 X 10N 15 2 requires M N 1 Table 37 Channel Divider Output Duty Cycle When the Output Duty Cycle Divider N M 2 DCCOFF 1 DCCOFF 0 Even 1 divider 50 50 bypassed Odd 1 divider 33 3 50 bypassed 5 1 divider 40 50 bypassed Even Odd Even N 1 50 requires M N 2 Even Odd N 1 50 requiresM N 1 2 VCO Divider Is Not Used Input Clock Dx Output Duty Cycle Duty Cycle N M 2 DCCOFF 1 DCCOFF 0 Any 1 1 divider Same as input l bypassed duty cycle Any Even N 1 50 requires M N 2 5090 N 1 50 requires 2 M N 1 X Odd N 1 N 1 X99 2 x N 3 2 requires M N 1 The internal VCO has a duty cycle of 50 Therefore when VCO is connected direct to output the duty cycle is 50 If the CLK input is r
4. B 35 Digital Lock Detect DLD 37 Analog Lock Detect Current Source Digital Lock Detect DLD External VCXO VCO Clock Input CLK CLK 37 RE 38 Manual Holdover Mode 38 Automatic Internal Holdover 38 Frequency ENIM dhitors 4 39 VCO Calibration LS mer 40 Glock Distribution ses csc tte tte e eterne 41 Internal VCO or External CLK as Clock Source 41 CLK or VCO Direct to LVPECL Outputs 41 Clock Frequency 42 VCO Dividers u tee b tes 42 Channel Dividers LVPECL 42 Channel Dividers LVDS CMOS 44 Synchronizing the Outputs SYNC Function 47 s 49 LVPECL Outputs OUTO to 49 LVDS CMOS Outputs OUT6 to 50 Reset Modes duet 50 Power On Reset Start Up Conditions When Vs Is Applied as ah EU ERE 50 Asynchronous Reset via the RESET Diu osuere 50 Soft Reset viai0x00 lt 5 gt oc 50 Power Down 50 Chip Power Down via PD 50 PLL 51 Distribution Power Down 51 Rev 0 Page 2 of 84 AD9516 1 Individual Clock Output Power Down 51 Register Map Overview sse 56 Individual Circuit Block Power Do
5. 10 Clock Output Absolute Time Jitter Clock GenerationpUsing External VCXO 5 44 5 10 Clock Output Additive Time Jitter VCO Divider Not Used 11 Clock Output Additive Time Jitter VCO Divider Used 11 Delay Block Additive 12 Serial Control Port e eiecit heec 12 PD SYNC and RESET Pins s 13 LD STATUS REFMON 13 Power 14 Timing Diagrams niece tete nier enger posted ue 15 Absolute Maximum 16 Thermal 16 ESD CaUtlOTi uet ie A 16 Pin Configuration and Function Descriptions 17 Typical Performance Characteristics 19 Terminology zi ete RE 25 Detailed Block Diagram 26 Theory of Operation 27 Operational Configurations sse 27 High Frequency Clock Distribution CLK or External VCO STOO MHZ 27 Clock Distribution or External VCO 1600 MHZ 31 Phase Locked Loop 33 Configuration of the 33 Phase Frequency Detector PFD 33 Charge Pump CP ciet t ERR ERES 34 One Chip ite ERO Em 34 External Loop Filter eerte 34 PLL Reference Inputs eite obuia 34 Reference Switchover 35 Reference Divider 35 VCXO VCO Feedback Divider
6. lt 5 gt lt 4 gt lt 3 gt Number of Capacitors 0 0 4 0 9 O 2 1 0 3 1 1 0 3 1 2 0 2 1 1 A7 2 0 OUT8 Ramp Ramp current for the delay function The combination of the number of capacitors and the ramp Current current sets the delay full scale 2 1 0 Current pA 0 0 200 400 600 800 1000 1200 1400 1 1 1600 0 A8 lt 5 0 gt 0078 Delay Selects the fraction of the full scale delay desired 6 bit binary Fraction 000000 gives zero delay Only delay values up to 47 decimals 101111b Ox2F are supported A9 lt 0 gt OUT9 Delay Bypass or use the delay function Bypass 0 0 use delay function lt 0 gt 1 bypass delay function Rev 0 Page 69 of 84 AD9516 1 Reg Addr Hex Bit s Name Description AA lt 5 3 gt OUT9 Ramp Selects the number of ramp capacitors used by the delay function The combination of the number of Capacitors capacitors and the ramp current sets the delay full scale 5 4 3 Number of Capacitors 0 0 0 4 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 AA 2 0 OUT9 Ramp Ramp current for the delay function The combination of the number of capacitors and the ramp Current current sets the delay full scale 2 1 0 Current Value 0 0 0 200 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400
7. 0 0 Normal operation 0 1 Asynchronous power down 1 0 Normal operation 1 1 Synchronous power down 11 7 0 14 Bit R divider LSBs lower eight bits R Divider Bits lt 7 0 gt LSB 12 lt 5 0 gt 14 R divider MSBs upper six bits R Divider Bits lt 13 8 gt MSB 13 lt 5 0 gt 6 A counter part of divider A Counter 14 7 0 13 Bit B counter part of N divider lower eight bits B Counter Bits 7 0 LSB 15 4 0 13 Bit B counter part of N divider upper five bits B Counter Bits 12 8 MSB 16 7 SetCPPin 5 CP pin to one half of the supply voltage to Vcp 2 7 0 CP normal operation 7 1 CP pin set to 2 16 6 ResetR Reset R counter R divider Counter 6 0 normal 6 1 reset R counter 16 5 Reset A and B Reset A and B counters part of N divider Counters 5 0 normal 5 1 reset A and B counters Rev 0 Page 61 of 84 AD9516 1 Reg Addr Hex 5 Name Description 16 lt 4 gt All Reset A and counters Counters lt 4 gt 0 normal lt 4 gt 1 reset R A and B counters 16 lt 3 gt BCounter B counter bypass This is valid only when operating the prescaler in FD mode Bypass lt 3 gt 0 normal lt 3 gt 1 B counter is set to divide by 1 This allows the prescaler setting to determine the divide for the N divider 16 2 0 Presca
8. 4 1 start high 191 lt 3 0 gt Divider 0 Phase Offset Phase offset Rev 0 Page 74 of 84 AD9516 1 Reg Addr Hex Bit s Name Description 192 lt 1 gt Divider 0 Direct to Output Connect OUTO and 1 to Divider 0 or directly to VCO CLK 1 0 OUTO and OUT1 are connected to Divider 0 lt 1 gt 1 If OX1ET1 1 0 10b the VCO is routed directly to OUTO and OUT1 If OX1ET1 1 0 00b the CLK is routed directly to OUTO and OUT1 If Ox1E1 lt 1 0 gt 01b there is no effect 192 0 Divider 0 DCCOFF Duty cycle correction function 0 0 enable duty cycle correction 0 1 disable duty cycle correction 193 7 4 Divider 1 Low Cycles Number of clock cycles of the divider input during which divider output stays low 193 3 0 Divider 1 High Cycles Number of clock cycles of the divider input during which divider output stays high 194 7 Divider 1 Bypass Bypass and power down the divider route input to divider output 7 0 use divider 7 1 bypass divider 194 6 Divider 1 Nosync Nosync 6 0 obey chip level SYNC signal 6 1 ignore chip level SYNC signal 194 5 Divider 1 Force High Force divider output to high This requires that nosync also be set 5 0 divider output forced to low 5 1 divider output forced to high 194
9. Yes 1 CLK VCO 2to6 1 bypassed No 2 to 6 x 1 CLK VCO 2to6 2 to 32 No 2 to 6 x 2 to 32 CLK Not 1 bypassed No 1 used CLK Not 2 to 32 No 2 to 32 used Low Cycles High Cycles Divider M N Bypass DCCOFF 0 0x190 lt 7 4 gt 0x190 lt 3 0 gt 0x191 lt 7 gt 0x192 lt 0 gt 1 0x193 lt 7 4 gt 0x193 lt 3 0 gt 0x194 lt 7 gt 0 195 lt 0 gt 2 0x196 lt 7 4 gt 0x196 lt 3 0 gt 0x197 lt 7 gt 0x198 lt 0 gt Table 33 Frequency Division for Divider 3 and Divider 4 CLK or Channel Divider Frequency Selected Divider X 1 2 Division CLK VCO 2106 1 1 2 to 6 x bypassed bypassed 1 x 1 CLK VCO 2106 21032 1 2 to 6 x bypassed 2 to 32 x 1 CLK VCO 2to6 2 to 32 2 to 32 2 to 6 x 2 to 32 x 2 to 32 CLK Not 1 1 1 used CLK Not 2 to 32 1 2 to 32 x 1 used CLK Not 2 to 32 2 to 32 2 to 32 x used 2 to 32 Channel Frequency Division 0 1 and 2 For each channel where the channel number is x 0 1 or 2 the frequency division Dx is set by the values of M and N four bits each representing decimal 0 to 15 where Number of Low Cycles M 1 Number of High Cycles N 1 The cycles are cycles of the clock signal currently routed to the input of the channel dividers VCO divider out or CLK When a divider is bypassed Dx 1 Otherwise Dx N 1 M 1 N M 2 This allows each channel
10. At Txa 2 16 Mx2 1 x Tx2 Case 3 When x gt 16 and 2 lt 15 At Ox 16 Mxi 1 x Txi 0x2 x Tx2 Case 4 When Ox gt 16 and gt 16 A bxi 16 1 x Txi 16 1 x Tx2 Fine Delay Adjust Divider 3 and Divider 4 Each AD9516 LVDS CMOS output OUT6 to OUT9 includes an analog delay element that can be programmed to give variable time delays in the clock signal at that output vco CLK DIVIDER FINE DELAY ADJUST VV BYPASS OUTPUT DRIVERS FINE DELAY ADJUST 06420 072 Figure 54 Fine Delay OUT6 to OUT9 The amount of delay applied to the clock signal is determined by programming four registers per output see Table 46 Table 46 Setting Analog Fine Delays OUTPUT Ramp Ramp Delay Delay LVDS CMOS Capacitors Current Fraction Bypass OUT6 OxA1 lt 5 3 gt 0 1 lt 2 0 gt 0 2 lt 5 0 gt OxA0 lt 0 gt OUT7 0 4 lt 5 3 gt 0 4 lt 2 0 gt 0 5 lt 5 0 gt OxA3 lt 0 gt OUT8 0 7 lt 5 3 gt OxA7 lt 2 0 gt 0 8 lt 5 0 gt 0 lt 0 gt OUT9 OxAA lt 5 3 gt OxAA lt 2 0 gt lt 5 0 gt OxA9 0 AD9516 1 Calculating the Fine Delay The following values and equations are used to calculate the delay of the delay block Tramp 200 x Ramp Current 1 Number of Capacitors Number of lt Bits gt 0 in Ramp Capacitors 1 Exampl
11. Calculated from SNR of ADC method Divider 12 Duty Cycle Correction Off CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL and VCO uses rising edge of clock signal CLK 2 4 GHz VCO Div 2 CMOS 100 MHz 350 fsrms Calculated from SNR of ADC method Divider 12 Duty Cycle Correction Off Rev 0 11 of 84 AD9516 1 DELAY BLOCK ADDITIVE TIME JITTER Table 13 Parameter Min Typ Max Unit Test Conditions Comments DELAY BLOCK ADDITIVE TIME JITTER Incremental additive jitter 100 MHz Output Delay 1600 uA 1C Fine Adj 000000 0 54 ps rms Delay 1600 uA 1C Fine Agj 101111 0 60 ps rms Delay 800 uA 1C Fine Adj 000000 0 65 ps rms Delay 800 uA 1C Fine 101111 0 85 ps rms Delay 800 pA 4 Fine Adj 000000 0 79 ps rms Delay 800 uA 4C Fine 101111 1 2 ps rms Delay 400 uA 4 Fine Adj 000000 1 2 ps rms Delay 400 uA AC Fine 101111 2 0 ps rms Delay 200 uA 1C Fine Adj 000000 1 3 ps rms Delay 200 uA 1C Fine 101111 2 5 ps rms Delay 200 uA AC Fine Adj 000000 1 9 ps rms Delay 200 uA 4C Fine 101111 3 8 ps rms 1 This value is incremental That is it is in addition to the jitter of the LVDS or CMOS output without the delay To estimate the total jitter the LVDS or CMOS output jitter should be added to this value using the root sum of squares RSS method SERIAL CONTROL PORT Table
12. 0 1 disable duty cycle correction Table 59 VCO Divider and 1 Reg Addr Hex Bit s Name Description lt 2 0 gt VCO Divider lt 2 gt lt 1 gt lt 0 gt Divide 0 0 0 2 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 Output static 1 1 0 Output static 1 1 1 Output static 1E1 lt 4 gt Clock Input Section Power down the clock input section including CLK buffer VCO divider and CLK tree lt 4 gt 0 normal operation lt 4 gt 1 power down 1E1 lt 3 gt Power Down VCO Clock Interface Power down the interface block between VCO and clock distribution lt 3 gt 0 normal operation lt 3 gt 1 power down 1E1 lt 2 gt Power Down VCO and CLK Power down both VCO and CLK input lt 2 gt 0 normal operation 2 1 power down lt 1 gt Select VCO or CLK Select either the VCO or the CLK as the input to VCO divider 1 0 Select external CLK as input to VCO divider 1 1 Select VCO as input to VCO divider cannot bypass VCO divider when this is selected 1E1 lt 0 gt 5 VCO Divider Bypass or use the VCO divider 0 0 use VCO divider lt 0 gt 1 bypass VCO divider cannot select VCO as input when this is selected Rev 0 77 of 84 AD9516 1 Table 60 System Reg Addr Hex Bit s Description 230 lt 2 gt Power Down Sync Power down the SYNC
13. 1 1 1 1600 AB lt 5 0 gt OUTO9 Delay Selects the fraction of the full scale delay desired 6 bit binary Fraction 000000 gives zero delay 7 D Onlydelay Values up t0 47 decimals 10114 1b 0x2F are supported Table 55 LVPECL Outputs Reg Addr Hex Bit s Name Description FO 4 OUTOInvert Sets the output polarity 4 0 noninverting 4 1 inverting FO 3 2 OUTO LVPECL Sets the LVPECL output differential voltage Differential lt 3 gt 2 Voltage 0 0 400 0 1 600 1 0 780 1 1 960 FO 1 0 OUTO LVPECL power down modes Power Down 1 0 Mode Output 0 0 Normal operation On 0 1 Partial power down reference on use only if there are no external load resistors Off 1 0 Partial power down reference on safe LVPECL power down Off 1 1 Total power down reference off use only if there are no external load resistors Off F1 4 OUT1 Invert Sets the output polarity 4 0 noninverting 4 1 inverting Rev 0 Page 70 of 84 AD9516 1 Reg Addr Hex 5 Description F1 lt 3 2 gt OUT1 LVPECL Sets the LVPECL output differential voltage Differential 3 2 mV Voltage 0 0 400 0 1 600 1 0 780 1 1 960 F1 1 0 OUT1 LVPECL power down modes Power Down 1 0 Mode Output 0 0 Normal operation On 0 1 Partial power down reference o
14. 1 kHz Offset 54 dBc Hz 10 kHz Offset 78 dBc Hz 100 kHz Offset 106 dBc Hz 1 MHz Offset 125 dBc Hz 10 MHz Offset 141 dBc Hz 40 MHz Offset 146 dBc Hz CLOCK OUTPUT ABSOLUTE TIME JITTER CLOCK GENERATION USING INTERNAL VCO Table 8 Parameter Min Typ Unit Test Conditions Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is clean so a wider PLL loop bandwidth is used reference 15 36 MHz R 1 VCO 2 46 GHz LVPECL 491 52 MHz PLL LBW 55 kHz 142 fsrms Integration BW 200 kHz to 10 MHz 370 fsrms Integration BW 12 kHz to 20 MHz VCO 2 46 GHz LVPECL 122 88 MHz PLL LBW 55 kHz 145 fsrms Integration BW 200 kHz to 10 MHz 356 fsrms Integration BW 12 kHz to 20 MHz VCO 2 46 GHz LVPECL 61 44 MHz PLL LBW 55 kHz 195 fsrms Integration BW 200 kHz to 10 MHz 402 fsrms Integration BW 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER CLOCK CLEANUP USING INTERNAL VCO Table 9 I I I Parameter Min Typ Max Unit Test Conditions Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is jittery so a narrower PLL loop bandwidth is used reference 10 0 MHz R 20 VCO 2 49 GHz LVPECL 622 08 MHz PLL LBW 125 Hz 745 fsrms Integration BW 12 kHz to 20 MHz VCO 2 49 GHz LVPECL 155 52 MHz PLL LBW 1
15. 1C lt 0 gt Differential Selects the PLL reference mode differential or single ended Single ended must be selected for the Reference auto switchover REF1 REF2 to work lt 0 gt 0 single ended reference mode 0 1 differential reference mode 1D lt 4 gt PLLStatus Disables the PLL status register readback Register 4 0 PLL status register enable Disable lt 4 gt 1 status register disable Rev 0 Page 66 of 84 AD9516 1 Reg Addr Hex Bit s Name Description 1D 3 Enables the LD pin voltage comparator This is used with the LD pin current source lock detect mode Comparator When the internal automatic holdover mode this enables the use of the voltage on the LD pin to Enable determine if the PLL was previously in a locked state see Figure 51 Otherwise this can be used with the REFMON and STATUS pins to monitor the voltage on this pin 3 0 disable LD pin comparator internal automatic holdover controller treats this pin as true high 3 1 enable LD pin comparator 1D lt 2 gt Holdover Along with 0 enables the holdover function Enable 2 0 holdover disabled 2 1 holdover enabled 1D lt 1 gt External Enables the external hold control through the SYNC pin This disables the internal holdover mode Holdover 1 0 automatic holdover mode holdover controlled by automatic holdover circuit Contro
16. 4 Divider 1 Start High Selects clock output to start high or start low 4 0 start low 194 3 0 Divider 1 Phase Offset lt gt 3 start high 195 lt 1 gt Divider 1 Direct to Output Connect OUT2 and OUT3 to Divider 1 or directly to VCO or CLK lt 1 gt 0 OUT2 and OUT3 are connected to Divider 1 lt 1 gt 1 If0x1E1 lt 1 0 gt 10b the VCO is routed directly to OUT2 and OUT3 If0x1E1 lt 1 0 gt 00b the CLK is routed directly to OUT2 and OUT3 If0x1E1 lt 1 0 gt 01b there is no effect 195 lt 0 gt Divider 1 DCCOFF Duty cycle correction function lt 0 gt 0 enable duty cycle correction lt 0 gt 1 disable duty cycle correction 196 lt 7 4 gt Divider 2 Low Cycles Number of clock cycles of the divider input during which divider output stays low 196 lt 3 0 gt Divider 2 High Cycles Number of clock cycles of the divider input during which divider output stays high 197 lt 7 gt Divider 2 Bypass Bypass and power down the divider route input to divider output lt 7 gt 0 use divider lt 7 gt 1 bypass divider 197 lt 6 gt Divider 2 Nosync Nosync lt 6 gt 0 obey chip level SYNC signal lt 6 gt 1 ignore chip level SYNC signal 197 lt 5 gt Divider 2 Force High Force divider output to high This requires that nosync also be set 5 0 divider ou
17. Selects REF1 low or REF2 high This pin has an internal 30 kO pull down resistor 8 SYNC Manual Synchronizations and Manual Holdover This pin initiates a manual synchronization and is also used for manual holdover Active low This pin has an internal 30 kO pull up resistor 9 LF Loop Filter Input Connects to VCO control voltage node internally 10 BYPASS This pin is for bypassing the LDO to ground with a capacitor 13 CLK Along with CLK this is the differential input for the clock distribution section 14 CLK Along with CLK this is the differential input for the clock distribution section 15 18 19 20 NC No Connection 16 SCLK Serial Control Port Data Clock Signal 17 CS Serial Control Port Chip Select Active Low This pin has an internal 30 kO pull up resistor 21 SDO Serial Control Port Unidirectional Serial Data Out 22 SDIO Serial Control Port Bidirectional Serial Data In Out 23 RESET Chip Reset Active Low This pin has an internal 30 kO pull up resistor 24 PD Chip Power Down Active Low This pin has an internal 30 kO pull up resistor 27 41 54 VS LVPECL Extended Voltage 2 5 V to 3 3 V LVPECL Power Pins 37 44 59 EPAD GND Ground Pins Includes External Paddle EPAD 56 OUTO LVPECL Output One Side of a Differential LVPECL Output Rev 0 Page 17 of 84 AD9516 1 Pin No Mnemonic Description 55 OUTO LVPECL Output One Side of a Differential LVPECL Output 53 OUT1 LVPECL Output One Side of a Differ
18. X96 Even Even 50 Mx Nx2 Mx 50 Odd Even 50 Nx2 Mx X Odd Even 50 Mx 50 Odd Qdd 50 MES N 1 X96 Odd Odd 2Nx1Nx2 Nxi 1 Mx2 Nx2 1 4 2Nx1 3 2Nx2 3 Phase Offset or Coarse Time Delay Divider 3 and Divider 4 Divider 3 and Divider 4 can be set to have a phase offset or delay The phase offset is set by a combination of the bits in the phase offset and start high registers see Table 45 Table 45 Setting Phase Offset and Division for Divider 3 and Divider 4 Start Phase Low High Divider High SH Offset PO CyclesM Cycles N 3 3 1 0 19 lt 0 gt 0 19 lt 3 0 gt 0x199 lt 7 4 gt 0x199 lt 3 0 gt 3 2 0 19 lt 1 gt 0 19 lt 7 4 gt 0x19B lt 7 4 gt 0x19B lt 3 0 gt 4 41 1 1 lt 0 gt 0x19F lt 3 0 gt 0 19 lt 7 4 gt 0x19E lt 3 0 gt 4 2 Ox1A1 lt 1 gt 0 19 lt 7 4 gt 0 1 0 lt 7 4 gt 0x1A0 lt 3 0 gt Let A delay in seconds 16 x SH lt 0 gt 8 x PO lt 3 gt Ax PO lt 2 gt 2x PO lt 1 gt 1 x lt 0 gt Tx period of the clock signal at the input to Dx in seconds Tx period of the clock signal at the input to Dx in seconds Rev 0 Page 46 of 84 Case 1 When lt 15 and lt 15 At Qa x Tx1 Ox2 x Case 2 When lt 15 and gt 16
19. the user must know what bit pattern to write to the reserved registers to preserve proper operation of the part It does not matter what data is written to blank registers Because data is written into a serial control port buffer area not directly into the actual control registers of the AD9516 an additional operation is needed to transfer the serial control port buffer contents to the actual control registers of the AD9516 thereby causing them to become active The update registers operation consists of setting 0x232 lt 0 gt 1b this bit is self clearing Any number of bytes of data can be changed before executing an update registers The update registers simultaneously actuates all register changes that have been written to the buffer since any previous update Rev 0 Page 52 of 84 Read If the instruction word is for a read operation the next N x 8 SCLK cycles clock out the data from the address specified in the instruction word where N is 1 to 3 as determined by W1 W0 If N 4 the read operation is in streaming mode continuing until CS is raised Streaming mode does not skip over reserved or blank registers The readback data is valid on the falling edge of SCLK The default mode of the AD9516 serial control port is the bidirectional mode In bidirectional mode both the sent data and the readback data appear on the SDIO pin It is also possible to set the AD9516 to unidirectional mode SDO enable register 0x00 lt 7 g
20. 000000 gives zero delay Only delay values up to 47 decimals 101111b Ox2F are supported lt 0 gt OUT7 Delay Bypass or use the delay function Bypass 0 0 use delay function lt 0 gt 1 bypass delay function A4 5 3 OUT7 Ramp Selects the number of ramp capacitors used by the delay function The combination of number of the Capacitors capacitors and the ramp current sets the delay full scale 5 4 3 Number of Capacitors 0 0 4 0000 N N Q N WW Rev 0 Page 68 of 84 AD9516 1 Reg Addr Hex Bit s Description A4 2 0 OUT7 Ramp Ramp current for the delay function The combination of the number of capacitors and the ramp Current current sets the delay full scale 2 1 0 Current pA 0 0 200 400 600 800 1000 1200 1400 1 1600 25 o0 500 2 5 lt 5 0 gt 0077 Delay Selects the fraction of the full scale delay desired 6 bit binary Fraction 000000 give zero delay Only delay values up to 47 decimals 101111b 0x2F are supported lt 0 gt OUTS8 Delay Bypass or use the delay function Bypass 0 0 use delay function lt 0 gt 1 bypass delay function A7 lt 5 3 gt OUT8 Ramp Selects the number of ramp capacitors used by the delay function The combination of the number of Capacitors capacitors and the ramp current sets the delay full scale
21. 14 Parameter Min Typ JUnit Test Conditions Comments CS INPUT 30 pull up resistor Input Logic 1 Voltage 2 0 V Input Logic 0 Voltage 0 8 V Input Logic 1 Current 3 Input Logic 0 Current 110 Input Capacitance 2 pF SCLK INPUT SCLK has an internal 30 kO pull down resistor Input Logic 1 Voltage 2 0 V Input Logic 0 Voltage 0 8 V Input Logic 1 Current 110 Input Logic 0 Current 1 Input Capacitance 2 pF SDIO WHEN INPUT Input Logic 1 Voltage 2 0 V Input Logic 0 Voltage 0 8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF SDIO SDO OUTPUTS Output Logic 1 Voltage 2 7 V Output Logic 0 Voltage 0 4 V Rev 0 Page 12 of 84 AD9516 1 Parameter Min Typ Max Unit Test Conditions Comments TIMING Clock Rate SCLK 1 tsc k 25 MHz Pulse Width High tui 16 ns Pulse Width Low tio 16 ns SDIO to SCLK Setup tps 2 ns SCLK to SDIO Hold 1 1 ns SCLK to Valid SDIO and SDO 8 ns CS to SCLK Setup and Hold ts tu 2 ns CS Minimum Pulse Width High 3 ns PD SYNC AND RESET PINS Table 15 Parameter Min Typ Max Unit Test Conditions Comments INPUT CHARACTERISTICS These pins each have a 30 kO internal pull up resistor Logic 1 Voltage 2 0 V Logic 0 Voltage 0 8 V Logic 1 Current 110 Logic 0 Current 1 Capacitance 2 pF RESET TIMING Pulse Width Low 50 ns S
22. 5 V to 3 3 V The WPECT wutput polarity be set as noninverting inverting which allows forth polarity of outputs within an application without requiring a board layout change Each LVPECL output can be powered down or powered up as needed Because of the architecture of the LVPECL output stages there is the possibility of electrical overstress and breakdown under certain power down conditions For this reason the LVPECL outputs have several power down modes This includes a safe power down mode that continues adjustment of the relative to protect the output devices while powered down although it consumes somewhat more power than a total power down If the LVPECL output pins are terminated it is best to select the safe power down mode If the pins are not connected unused it is acceptable to use the total power down mode 3 3V GND Figure 57 LVPECL Output Simplified Equivalent Circuit 06420 033 Rev 0 Page 49 of 84 AD9516 1 LVDS CMOS Outputs OUT6 to OUT9 OUT6 to OUT can be configured as either an LVDS differential output or as a pair of CMOS single ended outputs The LVDS outputs allow for selectable output current from 1 75 mA to 7 mA The LVDS output polarity can be set as noninverting or inverting which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change Each LVDS output can be powered down if not needed to save power 06
23. 7 gt 0 disable VCO frequency monitor Monitor 7 1 enable VCO frequency monitor 1B lt 6 gt REF2 REFIN Enable or disable REF2 frequency monitor Frequency lt 6 gt 0 disable REF2 frequency monitor Monitor 6 1 enable REF2 frequency monitor 1B 5 REF1 REFIN REFIN frequency monitor enable this is for both single ended and REFIN differential inputs Frequency as selected by differential reference mode Monitor 5 0 disable RERI REFIN sfrequency monitor 452A enable REFI REFIN frequency monitor 1B lt 4 0 gt REFMON Pin signal thatis connected to theREFMON pin i Control Level or Dynamic 4 3 2 1 0 Signal Signal at REFMON Pin 0 0 0 0 0 LVL Ground dc 0 0 0 0 1 DYN REF1 clock differential reference when in differential mode 0 0 0 1 0 DYN REF2 clock N A in differential mode 0 0 0 1 1 DYN Selected reference to PLL differential reference when in differential mode 0 0 1 0 0 DYN Unselected reference to PLL not available in differential mode 0 0 1 0 1 LVL Status of selected reference status of differential reference active high 0 0 1 1 0 LVL Status of unselected reference not available in differential mode active high 0 0 1 1 1 LVL Status REF1 frequency active high 0 1 0 0 0 LVL Status REF2 frequency active high 0 1 0 0 1 LVL Status REF1 frequency AND status REF2 frequency 0 1 0 1 0 LVL DLD AND status of
24. Divider 2 Divider 2 Phase Offset 00 Bypass Nosync Force High Start High 198 Blank Reserved Divider 2 Divider 2 00 Direct to DCCOFF Output LVDS CMOS Channel Dividers 199 Divider 3 Low Cycles Divider 3 1 High Cycles Divider 3 1 22 LVDS CMOS 19A foni Offset Divider 3 2 Phase Offset Divid 3 1 00 19B Low Cycles Divider 3 2 High Cycles Divider 3 2 11 19C Reserved Bypass Bypass Divider 3 Divider 3 Start High Start High 00 Divider 3 2 Divider 3 1 Nosync Force High Divider 3 2 Divider 3 1 19D Blank Reserved Divider 3 00 DCCOFF 19E Divider 4 Low Cycles Divider 4 1 High Cycles Divider 4 1 22 LVDS CMOS 19F Phase Offset Divider 4 2 Phase Offset Divider 4 1 00 1A0 Low Cycles Divider 4 2 High Cycles Divider 4 2 11 1A1 Reserved Bypass Bypass Divider 4 Divider 4 Start High Start High 00 Divider 4 2 Divider 4 1 Nosync Force High Divider 4 2 Divider 4 1 1A2 Blank Reserved Divider 4 00 DCCOFF 1A3 Reserved 1A4 Blank to 1DF VCO Divider and CLK Input 1E0 VCO Divider Blank Reserved VCO Divider 02 1E1 Input CLKs Reserved Power Power Down Power Select Bypass 00 Down VCO Clock Down VCO VCOorCLK VCO Clock Interface and CLK Divider Input Section 1E2 Blank to 22A Rev 0 Page 58 of 84 AD9516 1 Default Addr Bit 7 Value Hex Parameter MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB Hex System 230 Power Down Reserved Power Power Soft Sync 00 and Sync Down Sync Down Distribut
25. Figure 71 LVDS Output Termination See the AN 586 application note at www analog com for more information on LVDS Rev 0 Page 79 of 84 AD9516 1 CMOS CLOCK DISTRIBUTION The AD9516 provides four clock outputs OUT6 to OUT9 that are selectable as either CMOS or LVDS level outputs When selected as CMOS each output becomes a pair of CMOS outputs each of which can be individually turned on or off and set as noninverting or inverting These outputs are 3 3 V CMOS compatible Whenever single ended CMOS clocking is used some of the following general guidelines should be used Point to point nets should be designed such that a driver has only one receiver on the net if possible This allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net Series termination at the source is generally required to provide transmission line matching and or to reduce current transients at the driver The value of the resistor is dependent on the board design and timing requirements typically 10 to 100 is used CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive Typically trace lengths less than 3 inches are recommended to preserve signal rise fall times and preserve signal integrity 60 40 400 1 0 INCH MICROSTRIP 06420 076 Figure 72 Series Output Termination at the far end of the PCB tr
26. Hz Figure 33 Phase Noise Additive LVPECL 1600 MHz Divide by 1 Figure 36 Phase Noise Additive CMOS 50 MHz Divide by 20 Rev 0 Page 23 of 84 AD9516 1 PHASE NOISE dBc Hz PHASE NOISE dBc Hz 10 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M 100M FREQUENCY Hz FREQUENCY Hz Figure 37 Phase Noise Additive CMOS 250 MHz Divide by 4 Figure 39 Phase Noise Absolute Clock Cleanup Internal VCO 2 488 GHz PFD 19 44 MHz LBW 12 8 kHz LVPECL Output 155 52 MHz 06420 132 06420 139 120 130 140 PHASE NOISE dBc Hz PHASE NOISE dBc Hz 150 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M FREQUENCY Hz FREQUENCY Hz Figure 38 Phase Noise Absolute Clock Generation Internal VCO Figure 40 Phase Noise Absolute External VCXO Toyocom TCO 21 12 2 4576 GHz PFD 15 36 MHz LBW 55 kHz LVPECL Output 122 88 MHz 245 76 MHz PFD 15 36 MHz LBW 250 Hz LVPECL Output 245 76 MHz 06420 141 06420 140 Rev 0 Page 24 of 84
27. PLL PLL Reference Inputs The AD9516 features a flexible PLL reference input circuit that allows either a fully differential input or two separate single ended inputs The input frequency range for the reference inputs is specified in Table 2 Both the differential and the single ended inputs are self biased allowing for easy ac coupling of input signals The differential input and the single ended inputs share the two pins REFIN REF1 REFIN REF2 The desired reference input type is selected and controlled by 0x1C see Table 51 and Table 53 When the differential reference input is selected the self bias level of the two sides is offset slightly 100 mV see Table 2 to prevent chattering of the input buffer when the reference is slow or missing This increases the voltage swing required of the driver and overcomegthe offset The singl cended inputs can be by either dc coupled CMOS level signal or an ac coupled sinewave or square wave Each single ended input can be independently powered down when not needed to increase isolation and reduce power Either a differential or a single ended reference must be specifically enabled All PLL reference inputs are off by default The differential reference input is powered down whenever the PLL is powered down or when the differential reference input is not selected The single ended buffers power down when the PLL is powered down and when their individual power down regi
28. REF1 frequency active low 1 1 1 0 0 0 LVL Status of REF2 frequency active low 1 1 1 O 0 1 WL Status of REF1 frequency AND Status of REF2 frequency 1 1 1 0 1 DLD AND Status of selected reference AND Status of VCO 1 1 1 0 1 1 LVL Status of VCO Frequency active low 1 1 1 1 0 0 LVL Selected reference Low REF2 High REF1 1 1 1 1 0 1 LVL Digital lock detect DLD active low 1 1 1 1 1 0 LVL Holdover active active low 1 1 1 1 1 1 LVL LD pin comparator output active low 17 1 0 Antibacklash 1 0 Antibacklash Pulse Width ns Pulse Width AW fof 2 9 0 1 0 6 0 1 1 2 9 18 lt 6 5 gt Detect Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates Counter locked condition 6 5 PFDCycles to Determine Lock 0 0 5 0 1 16 1 0 64 1 1 255 18 lt 4 gt DDigital Lock If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time the Detect digital lock detect flag is set The flag remains set until the time difference is greater than the loss of lock threshold Window 4 0 high range 4 1 low range 18 lt 3 gt Disable Digital lock detect operation Digital 3 0 normal lock detect operation Lock Detect 3 1 disable lock detect 18 lt 2 1 gt Cal VCO Calibration Divider Divider used to generate the VCO calibration clock from the PLL
29. TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle Actual signals however display a certain amount of variation from ideal phase progression over time This phenomenon is called phase jitter Although many causes can contribute to phase jitter one major cause is random noise which is characterized statistically as being Gaussian normal in distribution This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain producing a continuous power spectrum This power spectrum is usually reported as a series of values whose units are dBc Hz at a given offset in frequency from the sine wave carrier The value is a ratio expressed in dB of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency For each measurement the offset from the carrier frequency is also given It is meaningful to integrate the total power contained within some interval of offset frequencies for example 10 kHz to 10 MHz This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency intervak Phase noise has a detrimental effect dd the performance of ADCs DACs and RF mixers It lowers the achievable dynamic range of the converters and mixers although
30. allows for the alignment of the edges of two or more outputs or for the spacing of edges according to the coarse phase offset settings for two or more outputs Rev 0 Page 47 of 84 AD9516 1 Synchronization of the outputs is executed in several ways The SYNC pin is forced low and then released manual sync By setting and then resetting any one of the following three bits the soft sync bit 0x230 lt 0 gt the soft reset bit 0x00 lt 5 gt mirrored and the distribution power down bit 0x230 lt 1 gt Synchronization of the outputs can be executed as part of the chip power up sequence The RESET pin is forced low and then released chip reset The PD pin is forced low and then released chip power down Whenever a VCO calibration is completed an internal SYNC signal is automatically asserted at the beginning and released upon the completion of a VCO calibration CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC The most common way to execute the SYNC function is to use the SYNC pin to do a manual synchronization of the outputs This requires a low going signal on the SYNC pin which is held low and then released when synchronization is desired The timing of the SYNC operation is shown in Figure 55 using VCO divider and Figure 56 VCO divider not used There is an uncertainty of up to 1 cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal
31. divider to divide by any integer from 1 to 32 Rev 0 Page 42 of 84 AD9516 1 Duty Cycle and Duty Cycle Correction 0 1 and 2 The duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions e What are the M and N values for the channel Is DCC enabled Is VCO divider used What is the CLK input duty cycle The internal VCO has a 50 duty cycle The DCC function is enabled by default for each channel divider However the DCC function can be disabled individually for each channel divider by setting the DCCOFF bit for that channel Certain M and N values for a channel divider result in a non 50 duty cycle A non 50 duty cycle can also result with an even division if M z N The duty cycle correction function automatically corrects non 50 duty cycles at the channel divider output to 50 duty cycle Duty cycle correction requires the following channel divider conditions An even division must be set as N e An odd division must be setas M N 1 When not bypassed or corrected by the DCC function the duty cycle of each channel divider output is the numerical value of N 1 N M 2 expressed as a 96 The duty cycle at the outputof di MM divider for yarious configurations is shown in Table 35 to Table 37 Table 35 Duty Cycle with VCO Divider Input Duty Cycle Is 50 Table 36 Duty Cycle with VCO Divider Input Duty Cycle Is X
32. e Program the PLL registers to the proper values for the PLL loop For initial setting of registers after a power up or reset initiate VCO calibration by setting 0x18 lt 0 gt 1 Subsequently whenever a calibration is desired set 0x18 lt 0 gt 0b update registers and set 0x18 lt 0 gt 1b update registers A SYNC operation is initiated internally causing the outputs to go to a static state determined by normal SYNC function operation VCO calibrates to desired setting for requested VCO frequency Internally the SYNC signal is released allowing outputs to continue clocking PLL loop is closed PLL locks A SYNC is executed during the VCO calibration therefore the outputs of the AD9516 are held static during the calibration which prevents unwanted frequencies from being produced However at the end of a VCO calibration the outputs may resume clocking before the PLL loop is completely settled The galibuationsclock dividewis set as shown in Table 53 0 18 lt 2 15 The calibration divider divides the PFD frequency reference frequency divided by R down to the calibration clock The calibration occurs at the PFD frequency divided by the calibration divider setting Lower VCO calibration clock frequencies result in longer times for a calibration to be completed The VCO calibration clock frequency is given by fueril R div where is the frequency of the REFIN
33. function 2 0 normal operation of the SYNC function lt 2 gt 1 power down sync circuitry 230 lt 1 gt Power Down Distribution Reference Power down the reference for distribution section lt 1 gt 0 normal operation of the reference for the distribution section lt 1 gt 1 power down the reference for the distribution section 230 lt 0 gt Soft SYNC The soft SYNC bit works the same as the SYNC pin except that the polarity of this bit is reversed That is a high level forces selected channels into a predetermined static state and a 1 to 0 transition triggers a sync 0 0 same as SYNC high 0 1 same as SYNC low Table 61 Update All Registers Reg Addr Bit s Name Description 232 0 Update This bit must be set to 1 to transfer the contents of the buffer registers into the active registers This happens Registers on the next SCLK rising edge This bit is self clearing that is it does not have to be set back to 0 0 1 self clearing update all active registers to the contents of the buffer registers j Rev 0 Page 78 of 84 APPLICATION NOTES USING THE AD9516 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed ADC is extremely sensitive to the quality of its sampling clock An ADC can be thought of as a sampling mixer and any noise distortion or timing jitter on the clock is combined with the desired
34. gt REF1 Readback register indicates if the frequency of the signal at REF2 is greater than the threshold frequency Frequency gt set by Register 0x1A lt 6 gt Threshold lt 1 gt 0 REF1 frequency is less than threshold frequency 1 1 REF1 frequency is greater than threshold frequency 1 lt 0 gt Digital Lock Readback register digital lock detect Detect 0 0 PLL is not locked 0 1 PLL is locked Rev 0 Page 67 of 84 AD9516 1 Table 54 Fine Delay Adjust OUT6 to OUT9 Reg Addr Hex Bit s Description lt 0 gt OUT6 Delay Bypass or use the delay function Bypass 0 0 use delay function lt 0 gt 1 bypass delay function A1 lt 5 3 gt OUT6 Ramp Selects the number of ramp capacitors used by the delay function The combination of number of the Capacitors capacitors and the ramp current sets the delay full scale lt 5 gt lt 4 gt lt 3 gt Number of Capacitors 0 0 0 4 0 0 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 A1 lt 2 0 gt OUT6 Ramp Ramp current for the delay function The combination of the number of capacitors and the ramp current Current sets the delay full scale lt 2 gt lt 1 gt lt 0 gt Current uA 0 0 0 200 0 0 1 400 0 1 0 600 0 1 1 800 1 50 40 1000 T PLENUM 1200 1 1 0 1400 1 1 1 1600 A2 lt 5 0 gt OUT6 Selects the fraction of the full scale delay desired 6 bit binary Delay Fraction
35. it is asked to produce See the VCO Calibration section for additional information h Wi The on chip VCO is powered by an on chip low drop out LDO linear voltage regulator The LDO provides some isolation of the VCO from variations in the power supply voltage level The BYPASS pin should be connected to ground by a 220 nF capacitor to ensure stability This LDO employs the same technology used in anyCAP line of regulators from Analog Devices Inc making it insensitive to the type of capacitor used Driving an external load from the BYPASS pin is not supported PLL External Loop Filter When using the internal VCO the external loop filter should be referenced to the BYPASS pin for optimal noise and spurious performance An example of an external loop filter for the PLL is shown in Figure 46 A loop filter must be calculated for each desired PLL configuration The values of the components depend upon the VCO frequency the Kvco the PFD frequency the CP current the desired loop bandwidth and the desired phase margin The loop filter affects the phase noise the loop settling time and the loop stability A knowledge of PLL theory is necessary for understanding the subject of loop filter design There are tools available such as ADIsimCLK that can help with the calculation of a loop filter according to the application requirements AD9516 1 CHARGE PUMP 06420 065 Figure 46 Example of External Loop Filter for
36. of 84 AD9516 1 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9516 can be configured in several ways These configurations must be setup by loading the control registers see Table 51 and Table 52 through Table 61 Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers High Frequency Clock Distribution CLK or External VCO gt 1600 MHz The AD9516 power up default configuration has the PLL powered off and the routing of the input set so that the CLK CLK input is connected to the distribution section through the VCO divider divide by 2 divide by 3 divide by 4 divide by 5 divide by 6 This is a distribution only mode that allows for an external input up to 2400 MHz see Table 3 The maximum frequency that can be applied to the channel dividers is 1600 MHz therefore higher input frequencies must be divided down before reaching the channel dividers This input routing can also be used for lower input frequencies but the minimum divide is 2 before the channel dividers When the PLL is enabled this routing also allows the use of the PLL with an external VCO or VCXO with a frequency less than 2400 MHz In this configuration the internal VCO is not used and is powered off The externaljVCQ XCXO feeds directly into the prescaler The register settings shown in Table 21 are the default values of these registers at power up or a
37. proper output through the mux on each pin the DLD function is available at the LD STATUS and REFMON pins The digital lock detect circuit indicates a lock when the time difference of the rising edges at the PFD inputs is less than a specified value the lock threshold The loss of a lock is indicated when the time difference exceeds a specified value the unlock threshold Note that the unlock threshold is wider than the lock threshold which allows some phase error in excess of the lock window to occur without chattering on the lock indicator The lock detect window timing depends on three settings the digital lock detect window bit 0x18 lt 4 gt the antibacklash pulse width setting 0x17 lt 1 0 gt see Table 2 and the lock detect counter 0x18 lt 6 5 gt A lock is not indicated until there is a programmable number of consecutive PFD cycles with a time difference less than the lock detect threshold The lock detect circuit continues to indicate a lock until a time difference greater than the unlock threshold occurs on a single subsequent cycle For the lock detect to work properly the period of the PFD frequency must be greater than the unlock threshold The number of consecutive PFD cycles required for lock is programmable 0x18 lt 6 5 gt Analog Lock Detect ALD The AD9516 provides an ALD funetiomthat maybe selected for use at the LD pin There ar amp fwolVersions pf e N channel open drain lock detect This signal
38. requires a pull up resistor to positive supply VS The output is normally high with short low going pulses Lock is indicated by the minimum duty cycle of the low going pulses e P channel open drain lock detect This signal requires a pull down resistor to GND The output is normally low with short high going pulses Lock is indicated by the minimum duty cycle of the high going pulses The analog lock detect function requires a R C filter to provide a logic level indicating lock unlock Vs 3 3V AD9516 1 ALD 4 06420 067 Figure 48 Example of Analog Lock Detect Filter Using N Channel Open Drain Driver Current Source Digital Lock Detect DLD During the PLL locking sequence it is normal for the DLD signal to toggle a number of times before remaining steady when the PLL is completely locked and stable There may be applications where it is desirable to have DLD asserted only after the PLL is solidly locked This is possible by using the current source lock detect function This function is set by selecting it as the output from the LD pin control 0 1 lt 5 0 gt The current source lock detect provides a current of 110 yA when DLD is true and shorts to ground when DLD is false Ifa capacitor is connected to the LD pin it charges at a rate determined by the current source during the DLD true time but is discharged nearly instantly when DLD is false By monitoring the voltage at the LD pin top of the capacitor
39. selected reference AND status of VCO 0 1 0 1 1 LVL Status of VCO frequency active high 0 1 1 0 0 LVL Selected reference Low REF1 High REF2 0 1 1 0 1 LVL Digital lock detect DLD active low 0 1 1 1 0 LVL Holdover active active high 0 1 1 1 1 LVL LD pin comparator output active high 1 0 0 0 VS PLL supply 1 0 0 0 1 DYN REF1 clock differential reference when in differential mode 1 0 0 1 0 DYN REF2 clock not available in differential mode 1 0 0 1 1 DYN Selected reference to PLL differential reference when in differential mode Rev 0 Page 65 of 84 AD9516 1 Reg Addr Hex Bit s Description Level or Dynamic lt 4 gt lt 3 gt lt 2 gt lt 1 gt lt 0 gt Signal Signal at REFMON Pin 1 0 1 0 DYN Unselected reference to PLL not available when in differential mode 1 0 1 0 1 LVL Status of selected reference status of differential reference active low 1 0 1 1 0 LVL Status of unselected reference not available in differential mode active low 1 0 1 1 1 LVL Status of REF1 frequency active low 1 1 0 0 0 LVL Status of REF2 frequency active low 1 1 0 0 1 Status of REF1 frequency AND Status of REF2 frequency 1 1 0 1 1 DLD AND Status of selected reference AND Status of VCO 1 1 0 1 1 LVL Status of VCO frequency active low 1 1 1 0 0 LVL Selected reference Low 2 High 1 1 1 1 0 1 LVL Digit
40. signal R is the value of the R divider cal div is the division set for the VCO calibration divider 0x18 2 1 The VCO calibration takes 4400 calibration clock cycles Therefore the VCO calibration time in PLL reference clock cycles is given by Time to Calibrate VCO 4400 x R x cal_div PLL Reference Clock Cycles Table 29 Example Time to Complete a VCO Calibration with Different frerm Frequencies frerin MHz R Divider PFD Time to Calibrate VCO 100 1 100 MHz 88 us 10 10 1 MHz 8 8 ms 10 100 100 kHz 88 ms Rev 0 Page 40 of 84 AD9516 1 VCO calibration must be manually initiated This allows for flexibility in deciding what order to program registers and when to initiate a calibration instead of having it happen every time certain PLL registers have their values change For example this allows for the VCO frequency to be changed by small amounts without having an automatic calibration occur each time this should be done with caution and only where the user knows the VCO control voltage is not going to exceed the nominal best performance limits for example a few 100 kHz steps are fine a few MHz might not be Additionally as the calibration procedure results in rapid changes in the VCO frequency the distribution section is automatically placed in SYNC until the calibration is finished Therefore this temporary loss of outputs must be expected A VCO calibration should be initiated under
41. the following conditions e After changing any of the PLL R P B and A divider settings or after a change in the PLL reference clock frequency This in effect means any time a PLL register or reference clock is changed such that a different VCO frequency results Whenever system calibration is desired The VCO is designed to operate properly over extremes of temperatures even when first calibrated at the opposite extreme However a VCO calibration can be initiated at any time if desired CLOCK DISTRIBUTION A clock channel consists of pair or double th the case of CMOS of outputs that share a common divider A clock output consists of the drivers that connect to the output pins The clock outputs have either LVPECL or LVDS CMOS signal levels at the pins The AD9516 has five clock channels three channels are LVPECL six outputs two channels are LVDS CMOS up to four LVDS outputs or up to eight CMOS outputs Each channel has its own programmable divider that divides the clock frequency applied to its input The LVPECL channel dividers contain a divider that can divide by any integer from 1 to 32 Each LVDS CMOS channel divider contains two cascaded dividers that can be set to divide by any integer from 1 to 32 The total division of the channel is the product of the divide value of the two cascaded dividers This allows divide values of 1 to 32 x 1 to 32 or up to 1024 notice that this is not all values fro
42. they are affected in somewhat different ways AD9516 1 Time Jitter Phase noise is a frequency domain phenomenon In the time domain the same effect is exhibited as time jitter When observing a sine wave the time of successive zero crossings varies In a square wave the time jitter is a displacement of the edges from their ideal regular times of occurrence In both cases the variations in timing from the ideal are the time jitter Because these variations are random in nature the time jitter is specified in units of seconds root mean square rms or 1 sigma of the Gaussian distribution Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal to noise ratio SNR and dynamic range of the converter A sampling clock with the lowest possible jitter provides the highest performance from a given converter Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured The phase noise of any external oscillators or clock sources are subtracted This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources each of which contribute its own phase noise to the total In many cases the phase noisesof one glement dominates the system phase noise Wich are ultiple contributors to phase noise th total is the squarefoot o
43. z lt 180 a n 2 CHANNEL 2 CMOS 9 2 160 5 L x 5 3 140 120 5 1 CHANNEL 2 CMOS 100 1 CHANNEL 1 CMOS 80 0 50 100 150 200 250 5 0 05 10 15 20 25 30 35 40 45 50 5 FREQUENCY MHz i VOLTAGE ON CP PIN V i Figure 9 Current vs Frequency CMOS Outputs Figure 12 Charge Pump Characteristics Vcp 5 0 V Rev 0 Page 19 of 84 AD9516 1 140 145 150 155 160 RELATIVE POWER dB 165 PFD PHASE NOISE REFERRED PFD INPUT dBc Hz 170 0 1 1 10 100 PFD FREQUENCY MHz Figure 13 PFD Phase Noise Referred to PFD Input vs PFD Frequency Figure 16 PFD CP Spurs 122 88 MHz PFD 15 36 MHz LBW 55 kHz 4 8 mA 2 46 GHz 06420 137 CENTER 122 88MHz 5MHz DIV SPAN 50MHz 06420 013 RELATIVE POWER dB PLL FIGURE OF MERIT dBc Hz 06420 135 0 0 5 1 0 1 5 2 0 2 5 CENTER 122 88MHz 100kHz DIV SPAN 1MHz SLEW RATE V ns Figure 14 PLL Figure of Merit FOM vs Slew Rate at REFIN REFIN Figure 17 Output Spectrum LVPECL 122 88 MHz PFD 15 36 MHz LBW 55 kHz lce 4 8 mA Fvco 2 46 GHz 06420 136 1 9 1 8 RELATIVE POWER dB VCO TUNING VOLTAGE V 06420 134 CENTER 122 88MH
44. 096 measured differentially PROPAGATION DELAY trec CLK TO LVPECL OUTPUT High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 42 Clock Distribution Configuration 773 933 1090 ps See Figure 44 Variation with Temperature 0 8 ps C OUTPUT SKEW LVPECL OUTPUTS LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps LVDS Termination 100 O differential 3 5 mA Output Rise Time ta 170 350 ps 20 to80 pmeasured differentially Output Fall Time tr 3 160 350 ps 20 to 80 differentially PROPAGATION DELAY tios CLKTO LVDS OUTPUT Delay offered outputs OUT6 OUT7 OUT8 OUT9 For All Divide Values 1 4 1 8 2 1 ns Variation with Temperature 1 25 ps C OUTPUT SKEW LVDS OUTPUTS Delay off on all outputs LVDS Outputs That Share the Same Divider 6 62 ps LVDS Outputs on Different Dividers 25 150 ps All LVDS Outputs Across Multiple Parts 430 ps CMOS Termination open Output Rise Time trc 495 1000 ps 20 to 80 Cioap 10 pF Output Fall Time trc 475 985 ps 80 to 20 10 pF PROPAGATION DELAY tcmos CLK TO CMOS OUTPUT Fine delay off For All Divide Values 1 6 2 1 2 6 ns Variation with Temperature 2 6 ps C OUTPUT SKEW CMOS OUTPUTS Fine delay off CMOS Outputs That Share the Same Divider 4 66 ps All CMOS Outputs on Different Dividers 28 180 ps All CMOS Outputs Across Multiple Parts 675 ps DELAY ADJUST
45. 150 dBc Hz gt 10 MHz Offset 155 dBc Hz CLK TO CMOS ADDITIVE PHASE NOISE Distribution section only does not include PLL and VCO CLK 1 GHz OUTPUT 250 MHz Input slew rate 1 V ns Divider 4 10 Hz Offset 110 dBc Hz 100 Hz Offset 120 dBc Hz 1 kHz Offset 127 dBc Hz 10 kHz Offset 136 dBc Hz 100 kHz Offset 144 dBc Hz 1 MHz Offset 147 dBc Hz gt 10 MHz Offset 154 dBc Hz CLK 1 GHz OUTPUT 50 MHz Input slew rate gt 1 V ns Divider 20 10 Hz Offset 124 dBc Hz 100 Hz Offset 134 dBc Hz 1 kHz Offset ST 1 7 dBc Hz 10 kHz Offset UM 151_ 100 kHz Offset 157 dBc Hz Q 1 MHz Offset 160 dBc Hz gt 10 MHz Offset 163 dBc Hz CLOCK OUTPUT ABSOLUTE PHASE NOISE INTERNAL VCO USED Table 7 Parameter Min Typ Max Unit Test Conditions Comments LVPECL ABSOLUTE PHASE NOISE Internal VCO direct to LVPECL output VCO 2 65 GHz OUTPUT 2 65 GHz Q 1 kHz Offset 46 dBc Hz 10 kHz Offset 76 dBc Hz 100 kHz Offset 104 dBc Hz 1 MHz Offset 123 dBc Hz 10 MHz Offset 140 dBc Hz 40 MHz Offset 146 dBc Hz VCO 2 475 GHz OUTPUT 2 475 GHz 1 kHz Offset 47 dBc Hz 10 kHz Offset 77 dBc Hz 100 kHz Offset 105 dBc Hz 1 MHz Offset 124 dBc Hz 10 MHz Offset 141 dBc Hz 40 MHz Offset 146 dBc Hz Rev 0 Page 9 of 84 AD9516 1 Parameter Min Typ Max Unit Test Conditions Comments VCO 2 3 GHz OUTPUT 2 3 GHz
46. 2 65 GHz Optionally an external VCO VCXO of up to 2 4 GHz may be used The AD9516 1 emphasizes low jitter and phase noise to maximize data converter performance and can benefit other applications with demanding phase noise and jitter requirements Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM CP LF STATUS MONITOR x io gt 92 52 OUT4 OUT6 06420 001 The AD 516 1 feat res SF EVPECL outputs in three pairs four LVDS outputs in two pairs and eight CMOS outputs two per LVDS output The LVPECL outputs operate to 1 6 GHz the LVDS outputs operate to 800 MHz and the CMOS outputs operate to 250 MHz Each pair of outputs has dividers that allow both the divide ratio and coarse delay or phase to be set The range of division for the LVPECL outputs is 1 to 32 The LVDS CMOS outputs allow a range of divisions up to a maximum of 1024 The AD9516 1 is available in a 64 lead LFCSP and can be operated from a single 3 3 V supply An external VCO w
47. 25 Hz 712 fsrms Integration BW 12 kHz to 20 MHz VCO 2 46 GHz LVPECL 122 88 MHz PLL LBW 125 Hz 700 fsrms Integration BW 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER CLOCK GENERATION USING EXTERNAL VCXO Table 10 Parameter Min Typ Max Unit Test Conditions Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup using an external 245 76 MHz VCXO Toyocom TCO 2112 reference 15 36 MHz 1 LVPECL 245 76 MHz PLL LBW 125 Hz 54 fsrms Integration BW 200 kHz to 5 MHz 77 fsrms Integration BW 200 kHz to 10 MHz 109 fsrms Integration BW 12 kHz to 20 MHz LVPECL 122 88 MHz PLL LBW 125 Hz 79 fsrms Integration BW 200 kHz to 5 MHz 114 fsrms Integration BW 200 kHz to 10 MHz 163 fsrms Integration BW 12 kHz to 20 MHz LVPECL 61 44 MHz PLL LBW 125 Hz 124 fsrms Integration BW 200 kHz to 5 MHz 176 fsrms Integration BW 200 kHz to 10 MHz 259 fsrms Integration BW 12 kHz to 20 MHz Rev 0 Page 10 of 84 CLOCK OUTPUT ADDITIVE TIME JITTER VCO DIVIDER NOT USED AD9516 1 Table 11 Parameter Min Typ Max Unit Test Conditions Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL and VCO uses rising edge of clock signal CLK 622 08 MHz LVPECL 622 08 MHz Divider 1 40 fsrms BW 12 kHz to 20 MHz CLK 622 08 MHz LVPECL 155 52 MHz Divider 4 80 fsrms
48. 4 OUT4Invert Sets the output polarity 4 0 noninverting 4 1 inverting F4 3 2 OUTA LVPECL Sets the LVPECL output differential voltage Vopn Differential lt 3 gt lt 2 gt Von mV Voltage 0 0 400 0 1 600 1 0 780 1 1 960 Rev 0 Page 71 of 84 AD9516 1 Reg Addr Hex Bit s Description F4 lt 1 0 gt OUT4 LVPECL power down modes Power Down lt 1 gt 0 Mode Output 0 0 Normal operation On 0 1 Partial power down reference on use only if there are no external load resistors Off 1 0 Partial power down reference on safe LVPECL power down Off 1 1 Total power down reference off use only if there are no external load resistors Off F5 4 5 Invert Sets the output polarity lt 4 gt 0 noninverting lt 4 gt 1 inverting F5 3 2 OUT5 LVPECL Sets the LVPECL output differential voltage Differential lt 3 gt lt 2 gt mV Voltage 0 0 400 0 1 600 1 0 780 1 1 960 F5 lt 1 0 gt OUT5 LVPECL power down modes Power Down lt 1 gt lt 0 gt Mode Output 0 0 Normal operation On 0 1 Partial power down reference on use only if there are no external load resistors Off 1 0 Partial power down reference on safe LVPECL power down Off 1 1 Total power down reference off use only if there are no external load resistors Off 1 a Table 56 LVDS CMOS Outputs JL W Y Reg Addr Hex Bit s Name Descri
49. 420 034 Figure 58 LVDS Output Simplified Equivalent Circuit with 3 5 mA Typical Current Source OUT6 to OUT can also be CMOS outputs Each LVDS output can be configured to be two CMOS outputs This provides for up to eight CMOS outputs OUT6A OUT6B OUTZA OUTSB OUT9A and OD I9 PB When an output is configured as CMOS the CMOS O tput A is amp utoratiCally turned on The CMOS Output B can be turned on or off independently The relative polarity of the CMOS outputs can also be selected for any combination of inverting and noninverting See Table 56 0x140 lt 7 5 gt 0x141 lt 7 5 gt 0x142 lt 7 5 gt and 0x143 lt 7 5 gt Each LVDS CMOS output can be powered down as needed to save power The CMOS output power down is controlled by the same bit that controls the LVDS power down for that output This power down control affects both the CMOS A and CMOS B outputs However when the CMOS A output is powered up the CMOS B output can be powered on or off separately Vs 06420 035 Figure 59 CMOS Equivalent Output Circuit RESET MODES The AD9516 has several ways to force the chip into a reset condition that restores all registers to their default values and makes these settings active Power On Reset Start Up Conditions When V Is Applied A power on reset POR is issued when the Vs power supply is turned on This initializes the chip to the power on conditions that are determined by the default register s
50. 8 RSET Resistor Connected Here Sets Internal Bias Currents Nominal value 4 12 kO 62 CPRSET Resistor Connected Here Sets the CP Current Range Nominal value 5 1 kO 63 REFIN REF2 Along with REFIN this is the differential input for the PLL reference Alternatively this pin is a single ended input for REF2 64 REFIN REF 1 Along with ts the differefitial input for the PLL reference this pin is Bingl ended input for T Rev 0 Page 18 of 84 AD9516 1 TYPICAL PERFORMANCE CHARACTERISTICS 65 3 CHANNELS 6 LVPECL 60 55 2 I 2 3 CHANNELS 3 LVPECL 50 8 5 gt x 45 2 CHANNELS 2 LVPECL 40 1 CHANNEL 1 LVPECL Ge 0 500 1000 1500 2000 2500 3000 2 3 2 4 2 5 2 6 2 7 FREQUENCY MHz VCO FREQUENCY GHz Figure 7 Current vs Frequency Direct to Output LVPECL Outputs Figure 10 VCO vs Frequency 180 2 CHANNELS 4 LVDS 160 lt lt UMP DOWN 140 o e 420 o x x 2 100 9 1 CHANNEL 1 LVDS 80 0 200 400 600 800 5 0 0 5 1 0 1 5 2 0 2 5 3 0 FREQUENCY MHz VOLTAGE ON CP PIN V Figure 8 Current vs Frequency LVDS Outputs Figure 11 Charge Pump Characteristics Vcp 3 3 V 240 220 200 t 2 CHANNEL 8 CMOS
51. AL CONTROL PORT The AD9516 serial control port is a flexible synchronous serial communications port that allows an easy interface with many industry standard microcontrollers and microprocessors The AD9516 serial control port is compatible with most synchronous transfer formats including both the Motorola SPI and SSR protocols The serial control port allows read write access to all registers that configure the AD9516 Single or multiple byte transfers are supported as well as MSB first or LSB first transfer formats The AD9516 serial control port can be configured for a single bidirectional I O pin SDIO only or for two unidirectional I O pins SDIO SDO By default the AD9516 is in bidirectional mode long instruction long instruction is only instruction mode supported SERIAL CONTROL PORT PIN DESCRIPTIONS SCLK serial clock is the serial shift clock This pin is an input SCLK is used to synchronize serial control port reads and writes Write data bits are registered on the rising edge of this clock and read data bits are registered on the falling edge This pin is internally pulled down by a 30 resistor to ground SDIO serial data input output is a dual purpose pin and acts as either an input only unidirectional mode or as both an input output bidirectional mode The AD9516 defaults to the bidirectional I O mode 0x00 lt 7 gt 0 SDO serial data out is used onlyin unidifectional I O mode 0x00 l
52. ANALOG DEVICES 14 Output Clock Generator with Integrated 2 5 GHz VCO AD9516 1 FEATURES Low phase noise phase locked loop On chip VCO tunes from 2 30 GHz to 2 65 GHz External VCO VCXO to 2 4 GHz optional One differential or two single ended reference inputs Reference monitoring capability Auto and manual reference switchover holdover modes Autorecover from holdover Accepts references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect selectable 3 pairs of 1 6 GHz LVPECL outputs Each pair shares 1 to 32 dividers with coarse phase delay Additive output jitter 225 fs rms Channel to channel skew paired outputs lt 10 ps 2 pairs of 800 MHz LVDS clock outputs Each pair shares two cascaded 1 to 32 dividers with coarse phase delay Additive output jitter 275 fs rms Fine delay adjust AT on each LVDS output Eight 250 MHz CMOS outputs two per LVDSjoutput Automatic synchronization of all outputs on power up Manual synchronization of outputs as needed Serial control port 64 lead LFCSP APPLICATIONS Low jitter low phase noise clock distribution Clocking high speed ADCs DACs DDSs DDCs DUCs MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure ATE GENERAL DESCRIPTION The AD9516 1 provides multi output clock distribution function with subpicosecond jitter performance along with an on chip PLL and VCO The on chip VCO tunes from 2 30 GHz to
53. BW 12 kHz 20 MHz CLK 1 6 GHz LVPECL 100 MHz Divider 16 215 fsrms Calculated from SNR of ADC method DCC not used for even divides CLK 500 MHz 100 MHz Divider 5 245 fsrms Calculated from SNR of ADC method DCC on LVDS OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL and VCO uses rising edge of clock signal CLK 1 6 GHz LVDS 800 MHz Divider 2 VCO Divider Not Used 85 fsrms BW 12 kHz 20 MHz CLK 1 GHz LVDS 200 MHz Divider 5 113 fsrms BW 12 kHz 20 MHz CLK 1 6 GHz LVDS 100 MHz Divider 16 280 fsrms Calculated from SNR of ADC method DCC not used for even divides CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL and VCO uses rising edge of clock signal CLK 1 6 GHz CMOS 100 MHz Divider 16 365 fsrms Calculated from SNR of ADC method DCC not used for even divides CLOCK OUTPUT ADDITIVE TIME JITTER VGO DIVIDER USED 4 Table 12 I Parameter Min Typ Max Unit Test Conditions Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL and VCO uses rising edge of clock signal CLK 2 4 GHz VCO Div 2 LVPECL 100 MHz 210 fsrms Calculated from SNR of ADC method Divider 12 Duty Cycle Correction Off LVDS OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL and VCO uses rising edge of clock signal CLK 2 4 GHz VCO Div 2 LVDS 100 MHz 285 fsrms
54. DER REGISTER N DATA REGISTER N 1 DATA Figure 62 Serial Control Port Write MSB First 16 Bit Instruction Two Bytes Data cs DON T CARE DON T CARE snio RW wa as az as as aa 2 A0 DONT eo i fi i em e eee on C EZ os ea 28 16 BIT INSTRUCTION HEADER REGISTER N DATA REGISTER N 1 DATA REGISTER N 2 DATA REGISTER N 3 DATA DON T CARE Figure 63 Serial Control Port Read MSB First 16 Bit Instruction Four Bytes Data I the a 1 1 TE DS 1 1 thu i i 1 1 ts 1 I 1 tek e se toy I I I 1 1 11 1 it SCLK DON T CARE DON T CARE SDIO DON T CARE DON T CARE 06420 040 I l DATA DATA BIT N 14 Figure 65 Timing Diagram for Serial Control Port Register Read 06420 041 pov care A2 AS AT ws w po pa ps Ds oJ DONT CARE 16 BIT INSTRUCTION HEADER REGISTER N DATA REGISTER N 1 DATA Figure 66 Serial Control Port Write LSB First 16 Bit Instruction Two Bytes Data Rev 0 Page 54 of 84 06420 038 06420 039 06420 042 SCLK Figure 67 Serial Control Port Timing Write Table 50 Serial Control Port Timing 06420 043 AD9516 1 Parameter Description
55. EF2 1 0 1 1 0 1 LVL Digital lock detect DLD active high 1 0 1 1 1 0 LVL Holdover active active high 1 0 1 1 1 1 LVL N A do not use 1 1 0 0 VS PLL supply 1 1 0 0 0 1 DYN REF1 clock differential reference when in differential mode 1 1 0 0 1 0 DYN REF2 clock not available in differential mode 1 1 0 0 1 1 DYN Selected reference to PLL differential reference when in differential mode 1 1 0 1 0 0 DYN Unselected reference to PLL not available when in differential mode 1 1 0 1 0 1 LVL Status of selected reference status of differential reference active low Rev 0 Page 64 of 84 AD9516 1 Reg Addr Hex Bit s Name Description Level or Dynamic 5 4 3 2 1 0 Signal SignalatLD Pin 1 1 0 1 1 0 LVL Status of unselected reference not available in differential mode active low 1 1 0 1 1 1 LVL Status of REF1 frequency active low 1 1 1 0 0 0 LVL Status of REF2 frequency active low 1 1 14 0 WL Status of REF1 frequency AND Status of REF2 frequency 0 WL DLD AND Status of selected reference AND Status of VCO 1 1 1 0 1 1 LVL Status of VCO frequency active low 1 1 1 1 0 0 LVL Selected reference Low 2 High REF 1 1 1 1 1 0 1 LVL Digital lock detect DLD active low 1 1 1 1 1 0 LVL Holdover active active low 1 1 1 1 1 1 LVL N A do not use 1B lt 7 gt VCO Enable or disable VCO frequency monitor Frequency lt
56. FF 1 Input Clock Dx Dx Output Duty Cycle Nx Mx 2 Nx2 Mx2 2 Duty Cycle 50 1 1 50 X 1 1 X 50 Even Odd 1 Nx 1 2 X Even Odd 1 1 2 50 Even Odd Even Odd Nx2 1 Nx2 2 2 X Even Odd Even Odd Nx2 1 Nx2 2 2 Table 42 Divider 3 Divider 4 Duty Cycle VCO Divider Used Duty Cycle Correction Is On DCCOFF 0 VCO Divider Input Duty Cycle 50 vco Divider Mx 2 Nx2 Mx2 2 Duty Cycle Even 1 1 50 Odd 1 1 50 Even Even Nx Mx 1 50 Odd Even Nx Mx 1 50 Even odM Z Ny i 1 50 Odd Oddi Mxv Nxat 1 1 50 Even Even Nx Mx Even Nx Mx 50 Odd Even Nx Mx Even Mx 50 Even Odd Mx 1 Even Nx Mx 5096 Odd Odd 1 Even Nx Mx 50 Even Odd 1 Odd Mx2 Nx2 1 50 Odd Odd 1 Odd Mx2 Nx2 1 50 vco Dx Divider Nxi Mxi 2 Nx2 Mx2 2 Output Duty Cycle Even 1 1 50 Odd 3 1 1 33 3 Odd 5 1 1 40 Even Even Odd 1 1 2 Odd Even Odd 1 1 2 Even Even Odd Even Odd Nx2 1 Nx2 2 2 Odd Even Odd Even Odd Nx2 1 Mx 2 Rev 0 Page 45 of 84 AD9516 1 Table 43 Divider 3 Divider 4 Duty Cy
57. GND RSET O O REFERENCE SWITCHOVER R DIVIDER REFIN REF1 REFIN REF2 REFMON PROGRAMMABLE N DELAY AD9516 1 CPRSET VCP LOCK DETECT PHASE FREQUENCY DETECTOR PROGRAMMABLE R DELAY 06420 064 Figure 45 PLL Functional Blocks 1 The AD9516 includes an MM with The PLL blocks can be used either with the on chip VCO to create a complete phase locked loop or with an external VCO or VCXO The PLL requires an external loop filter which usually consists of a small number of capacitors and resistors The configuration and components of the loop filter help to establish the loop bandwidth and stability of the operating PLL The AD9516 PLL is useful for generating clock frequencies from a supplied reference frequency This includes conversion of reference frequencies to much higher frequencies for subsequent division and distribution In addition the PLL can be exploited to clean up jitter and phase noise on a noisy reference The exact choices of PLL parameters and loop dynamics is very application specific The flexibility and depth of the AD9516 PLL allows the part to be tailored to function in many different applications and signal environments Configuration of the PLL The AD9516 allows flexible configuration of the PLL accomodating various reference frequencies PFD comparison frequencies VCO frequencies internal or external VCO VCXO and loop dynamics This is accomplished b
58. However when operating the prescaler in FD mode 1 2 or 3 the A counter is not used A 0 and the equation simplifies to fvco frer R x P x B frer x N R Rev 0 Page 35 of 84 AD9516 1 When A 0 the divide is a fixed divide of P 2 4 8 16 or 32 in which case the previous equation also applies By using combinations of DM and FD modes the AD9516 can achieve values of N all the way down to N 1 Table 28 shows how a 10 MHz reference input may be locked to any integer multiple of N Note that the same value of N may be derived in different ways as illustrated by the case of N 12 The user may choose a fixed divide mode P 2 with B 6 or use the dual modulus mode 2 3 with A 0 B 6 or use the dual modulus mode 4 5 with 0 3 A and B Counters The AD9516 B counter can be bypassed B 1 This B counter bypass mode is only valid when using the prescaler in FD mode When A 0 the divide is a fixed divide of P 2 4 8 16 or 32 Unlike the R counter an A 0 is actually a zero The B counter must 23 or bypassed The maximum input frequency to the A B counter is reflected in the maximum prescaler output frequency 300 MHz specified in Table 2 This is the prescaler input frequency VCO or CLK divided by P Although manual reset is not normally required the A B counters have their own reset bit A and B counters can be reset using the shared reset bit of the R A and B counters Th
59. LVDS and CMOS Shortest Delay Range OxA1 4 7 lt 5 0 gt 101111b Zero Scale 50 315 680 ps 2 5 8 lt 5 0 gt 000000b Full Scale 540 880 1180 ps 2 5 8 lt 5 0 gt 101111b Longest Delay Range OxA1 0xA4 0xA7 OxAA lt 5 0 gt 000000b Zero Scale 200 570 950 ps 2 5 8 lt 5 0 gt 000000b Quarter Scale 172 231 2 89 ns 2 5 8 lt 5 0 gt 001100b Full Scale 5 7 8 0 10 1 ns 2 5 8 lt 5 0 gt 101111b Rev 0 Page 7 of 84 AD9516 1 Parameter Min Typ Max Unit Test Conditions Comments Delay Variation with Temperature Short Delay Range Zero Scale 0 23 ps C Full Scale 0 02 ps C Long Delay Range Zero Scale 0 3 ps C Full Scale 0 24 ps C This is the difference between any two similar delay paths while operating at the same voltage and temperature Corresponding CMOS drivers set to A for noninverting and B for inverting 3 The maximum delay that can used is a little less than one half the period of the clock A longer delay disables the output Incremental delay does not include propagation delay 5 All delays between zero scale and full scale can be estimated by linear interpolation CLOCK OUTPUT ADDITIVE PHASE NOISE DISTRIBUTION ONLY VCO DIVIDER NOT USED Table 6 Parameter Min Typ Max Unit
60. MSB 00 16 PLL Control 1 Set CP Pin Reset R Reset Reset All B Counter Prescaler P 06 to 2 Counter B Counters Counters Bypass 17 PLL Control 2 STATUS Pin Control Antibacklash Pulse Width 00 18 PLLControl3 Reserved Lock Detect Counter Digital Lo k Disable Calibration Divider VCO Cal 06 j Detect Digital Lock Now r Window Detect k 19 PLL Control 4 R A B Counters SYNC R Path Delay N Path Delay 00 Pin Reset 1A PLLControl 5 Reserved Reference LD Pin Control 00 Frequency Monitor Threshold 1B PLL Control 6 VCO REF2 REF1 REFIN REFMON Pin Control 00 Frequency REFIN Frequency Monitor Frequency Monitor Monitor 1C PLLControl7 Disable Select Use Automatic Stay on REF2 REF1 Differential 00 Switchover REF2 REF SELPin Reference REF2 Power On Power On Reference Deglitch Switchover 1D PLL Control 8 Reserved PLL Status LD Pin Holdover External Holdover 00 Register Comparator Enable Holdover Enable Disable Enable Control 1E PLL Control 9 00 Reserved 1F PLL Readback Reserved VCO Cal Holdover REF2 VCO REF2 REF1 Digital Finished Active Selected Frequency Frequency Frequency Lock gt Threshold gt Threshold gt Threshold Detect 20 to Blank 4F Rev 0 Page 56 of 84 AD9516 1 Default Addr Bit 7 Value Hex Parameter MSB Bit 6 Bit 5 Bit 4 B
61. R DELAY REFIN REFIN REF2 eid VCO STATUS 4 PHASE LOW DROPOUT ER QUENGY CHARGE BYPASS OH REGULATOR LDO A PROGRAMMABLE CIDR PUMP REFERENCE e DIVIDE BY Q STATUS 3 4 5 OR 6 DIVIDE BY 1TO 32 DIGITAL DIVIDE BY 119 32 LVPECL DIVIDE BY Low i LVPECL DIVIDE BY DIVIDE BY 1 TO 32 1 TO 32 DIVIDE BY DIVIDE BY 1 TO 32 1 TO 32 AD9516 1 Figure 42 High Frequency Clock Distribution or External VCO gt 1600 MHz Rev 0 Page 28 of 84 06420 029 Internal VCO and Clock Distribution AD9516 1 Table 24 Settings When Using Internal VCO Function When using the internal VCO and PLL the VCO divider must Register be employed to ensure the frequency presented to the channel 0 10 lt 1 0 gt 006 dividers does not exceed their specified maximum frequency 0x10 to Ox1E 1600 MHz see Table 3 The internal PLL uses an external loop filter to set the loop bandwidth The external loop filter is also crucial to the loop stability When using the internal VCO it is necessary to calibrate the VCO 0x18 lt 0 gt to ensure optimal performance For internal VCO and clock distribution applications the register settings shown in Table 24 should be used I 0x18 lt 0 gt 0 0 232 lt 0 gt 1 0 18 lt 0 gt 1 0 232 lt 0 gt 1 0 1 0 lt 2 0 gt Ox1E1 0 Ob 0x1E1 lt 1 gt 1b PLL normal operation PLL on PLL settings Select and en
62. SDIO SDO CS GND 0 3 V to Vs 0 3 V OUTO OUTO OUTI GND 0 3 V to Vs 0 3 V OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUTA OUTS OUTS OUT6 OUT6 OUT7 OUT7 OUT8 OUT8 OUT9 OUTS SYNC GND 0 3 V to Vs 0 3 V REFMON STATUS LD GND 0 3 V to Vs 0 3 V Junction Temperature 150 C Storage Temperature 65 C 150 6 1 Range Lead Temperature 10 sec 360 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE Table 19 Package Osa Unit 64 Lead LFCSP 24 C W Thermal impedance measurements were taken on a 4 layer board in still air in accordance with EIA JESD51 7 ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to 1 See Table 19 for without detection Although this product features avoid performance loss of functionality a Rev 0 Page 16 of 84 AD9516 1 PIN CONFIGURA
63. TION AND FUNCTION DESCRIPTIONS NC NO CONNECT INN D a LE 2120 SEE ees 00200 o NNN gt gt gt gt gt gt gt 39558898589 59055 9 Q i o 0 1 10 ID SF LVPECL LVPECL VS 1H O OUT6 OUT6A REFMON 2 INDICATOR OUT6 OUT6B LD 3 OUT7 OUT7A VCP 4 OUT7 OUT7B CP 5 4 44 GND STATUS 6 4 OUT2 REF SEL 7 AD9516 1 5 OUT2 SYNC 8 TOP VIEW z VS_LVPECL LF 9 Not to Scale OUTS BYPASS 10 eg OUT3 vs 11 vs vs 12 CLK 13 gt OUT9 OUT9B CLK 14 95 0079 OUT9A 15 OUT8 OUT8B SCLK 16 OUTS OUT8A LVPECL LVPECL moos CS 17 NC 18 NC 19 NC 20 SDO 21 SDIO 22 RESET 23 PD 24 OUT4 25 OUT5 28 OUT5 29 VS 30 VS 31 Vs 32 OUT4 26 VS_LVPECL 27 06420 003 Figure 6 Pin Configuration 1 Table 20 Pin Function Descriptions Pin No Mnemonic Description 1 11 12 30 31 VS 3 3 V Power Pins 32 38 49 50 51 57 60 61 2 REFMON Reference Monitor Output This pin has multiple selectable outputs see Table 53 0x1B 3 LD Lock Detect Output This pin has multiple selectable outputs see Table 53 Ox1A 4 VCP Power Supply for Charge Pump CP Vs lt lt 5 0 V 5 CP Charge Pump Output Connects to external loop filter 6 STATUS Status Output This pin has multiple selectable outputs see Table 53 0x17 7 REF_SEL Reference Select
64. Test Conditions Comments CLK TO LVPECL ADDITIVE PHASE NOISE Distribution section only does not include PLL and VCO CLK 1 GHz OUTPUT 1 GHz Input slew rate gt 1 V ns Divider 1 10 Hz Offset 109 dBc Hz 100 Hz Offset 118 dBc Hz Q 1 kHz Offset 130 dBc Hz 10 kHz Offset 189 dBc Hz 100 kHz Offset 144 dBc H2 1 MHz Offset MM 146 10 MHz Offset 147 dBc Hz 100 MHz Offset 149 dBc Hz CLK 1 GHz OUTPUT 200 MHz Input slew rate gt 1 V ns Divider 5 10 Hz Offset 120 dBc Hz 100 Hz Offset 126 dBc Hz 1 kHz Offset 139 dBc Hz 10 kHz Offset 150 dBc Hz 100 kHz Offset 155 dBc Hz 1 MHz Offset 157 dBc Hz gt 10 MHz Offset 157 dBc Hz CLK TO LVDS ADDITIVE PHASE NOISE Distribution section only does not include PLL and VCO CLK 1 6 GHz OUTPUT 800 MHz Input slew rate gt 1 V ns Divider 2 10 Hz Offset 103 dBc Hz 100 Hz Offset 110 dBc Hz 1 kHz Offset 120 dBc Hz 10 kHz Offset 127 dBc Hz 100 kHz Offset 133 dBc Hz 1 MHz Offset 138 dBc Hz 10 MHz Offset 147 dBc Hz 100 MHz Offset 149 dBc Hz Rev 0 Page 8 of 84 AD9516 1 Parameter Min Typ Max Unit Test Conditions Comments CLK 1 6 GHz OUTPUT 400 MHz Input slew rate gt 1 V ns Divider 4 10 Hz Offset 114 dBc Hz 100 Hz Offset 122 dBc Hz Q 1 kHz Offset 132 dBc Hz 10 kHz Offset 140 dBc Hz 100 kHz Offset 146 dBc Hz Q 1 MHz Offset
65. YNC TIMING Pulse Width Low 1 5 Highspeed clockecycles High speed clock is kK input signal j LD STATUS REFMON PINS Table 16 Parameter Min Typ Max Unit Test Conditions Comments OUTPUT CHARACTERISTICS When selected as a digital output CMOS there are other modes in which these pins are not CMOS digital outputs see Table 53 0x17 0x1A and 0x1B Output Voltage High Von 2 7 V Output Voltage Low Voi 0 4 V MAXIMUM TOGGLE RATE 100 MHz Applies when mux is set to any divider or counter output or PFD up down pulse also applies in analog lock detect mode usually only debug mode beware that spurs may couple to output when any of these pins are toggling ANALOG LOCK DETECT Capacitance 3 pF On chip capacitance used to calculate RC time constant for analog lock detect readback use a pull up resistor REF1 REF2 AND VCO FREQUENCY STATUS MONITOR Normal Range 1 02 MHz Frequency above which the monitor always indicates the presence of the reference Extended Range REF1 and REF2 Only 8 kHz Frequency above which the monitor always indicates the presence of the reference LD PIN COMPARATOR Trip Point 1 6 V Hysteresis 260 mV Rev 0 Page 13 of 84 AD9516 1 POWER DISSIPATION Table 17 Parameter Min Typ Max Unit Test Conditions Comments POWER DISSIPATION CHIP Power On Default 10 12 WwW No clock no programming default register values does not include power dissipated in external resistors Full Opera
66. YPASS O REGULATOR LDO T I 0 0 vco gt N DIVIDER 1 1 P P 1 AB i PRESCALER 7 COUNTERS 1 1 DIVIDE BY 2 3 4 5 6 CLK O gt DISTRIBUTION REFERENCE REFMON HA PROGRAMMABLE R DELAY CPRSET VCP O O LOCK DETECT PLL REFERENCE PHASE PROGRAMMABLE FREQUENCY one N DELAY DETECTOR 5 5 gt STATUS 06420 070 Figure 52 Reference and VCO Status Monitors VCO Calibration The AD9516 on chip VCO must be calibrated to ensure proper operation over process and temperature The VCO calibration is controlled by a calibration controller running off of a divided REFIN clock The calibration requires that the PLL be set up properly to lock the PLL loop and that the REFIN dlock be present During the first initializafiow ind power upjor a reset of the AD9516 a VCO calibration sequence is initiated by setting 0 18 lt 0 gt 1b This be done as part of the initial setup before executing update registers 0x232 lt 0 gt 1b Subsequent to the initial setup a VCO calibration sequence is initiated by resetting 0 18 lt 0 gt Ob executing an update registers operation setting 0x18 lt 0 gt 1b and executing another update registers operation A readback bit 0x1F lt 6 gt indicates when a VCO calibration is finished by returning a logic true that is 1b The sequence of operations for the VCO calibration is
67. able a reference input set R N P A B PFD polarity and Ice according to the intended loop configuration Reset VCO calibration first time after power up this does not have to be done but must be done subsequently Initiate VCO calibration VCO divider set to divide by 2 divide by 3 divide by 4 divide by 5 and divide by 6 Use the VCO divider as source for distribution section VCO selected as the source Rev 0 Page 29 of 84 AD9516 1 REF_SEL VS GND ET RECON CPRSET VCP DISTRIBUTION Ex REFERENCE LOCK DETECT lt ES PROGRAMMABLE mm R DELAY STATUS REFIN REF1 Q REFIN REF2 5 PHASE BYPASS H LOW DROPOUT P P 1 AIB PROGRAMMABLE FREQUENCY CHARGE REGULATOR LDO PRESCALER COUNTERS N DELAY DETECTOR RUME N DIVIDER LF 2 i MONUI CE vco DIVIDE BY 2 3 4 5 OR 6 CLK O gt CLK gt DIVIDE BY 2 1 TO 32 PD O DIGITAL LOGIC vco STATUS STATUS PLL REFERENCE LVPECL SYNC gt RESET ne DIVIDE BY 11992 LVPECL SDIO O SERIAL DIVIDE BY 1 TO 32 DIVIDE BY DIVIDE BY 1 TO 32 1 TO 32 DIVIDE BY DIVIDE BY 1 TO 32 1 TO 32 AD9516 1 Figure 43 Internal VCO and Clock Distribution Rev 0 Page 30 of 84 F LD STATUS OUT6 OUT6A OUT6 OUT6B 06420 030 Clock Distribution or External VCO lt 1600 MHz When the external clock source to be distribu
68. ace is a second option The CMOS outputs of the AD9516 do not supply enough current to provide a full voltage swing with a low impedance resistive far end termination as shown in Figure 73 The far end termination network should match the PCB trace impedance and provide the desired switching point The reduced signal swing may still meet receiver input requirements in some applications This can be useful when driving long trace lengths on less critical nets 06420 077 Figure 73 CMOS Output with Far End Termination Because of the limitations of single ended CMOS clocking consider using differential outputs when driving high speed signals over long traces The AD9516 offers both LVPECL and LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters NAL Rev 0 Page 80 of 84 OUTLINE DIMENSIONS 0 50 0 40 0 30 8 4 1 00 12 0 80 MAX fa 0 65 TYP 245 0 05 0 02 NOM SEATING 0 50 BSC COMPLIANT JEDEC STANDARDS MO 220 VMMD 4 Figure 74 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 9 x 9 mm Body Very Thin Quad CP 64 4 Dimensions shown in millimeters PIN 1 INDICATOR 6 35 a EXPOSED PAD 6 20 SQ BOTTOM VIEW 6 05 063006 B AD9516 1 ORDERING GUIDE Model TATA Range Pack
69. age Description AD9516 1BCPZ 40 to 85 C 64 Lead Lead Frame Chip Scale Package LFCSP VQ CP 64 4 AD9516 1BCPZ REEL7 40 to 85 C 64 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 64 4 AD9516 1 PCBZ Evaluation Board 1Z RoHS Compliant Part Rev 0 Page 81 of 84 AD9516 1 NOTES ww C conh AD9516 1 NOTES ww C conh AD9516 1 NOTES WV D i 2007 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners DEVICES Rev 0 Page 84 of 84
70. al CLK as Clock Source The clock distribution of the AD9516 has two clock input sources internal VCO or an external clock connected to the CLK CLK pins Either the internal VCO or CLK must be chosen as the source of the clock signal to distribute When the internal VCO is selected as the source the VCO divider must be used When CLK is selected as the source it is not necessary to usethe V GO dividerAtthe Jd frequency is less than the maximum channel divider input frequency 1600 MHz otherwise the VCO divider must be used to reduce the frequency to one acceptable by the channel dividers Table 30 shows how the VCO CLK and VCO divider are selected 0x1E1 lt 1 0 gt selects the channel divider source and determines whether the VCO divider is used It is not possible to select the VCO without using the VCO divider Table 30 Selecting VCO or CLK as Source for Channel Divider and Whether VCO Divider Is Used 0x1E1 lt 1 gt lt 0 gt Channel Divider Source VCO Divider 0 0 CLK Used 0 1 CLK Not used 1 0 VCO Used 1 1 Not allowed Not allowed CLK or VCO Direct to LVPECL Outputs It is possible to connect either the internal VCO or the CLK whichever is selected as the input to the VCO divider directly to the LVPECL outputs OUTO to OUTS This configuration can pass frequencies up to the maximum frequency of the VCO directly to the LVPECL outputs The LVPECL outputs may not be able to provide full voltage swing at t
71. al lock detect DLD active low 1 1 1 1 0 LVL Holdover active active low 1 1 1 1 1 LVL LD pin comparator output active low 1C lt 7 gt Disable or enable the switchover deglitch circuit Switchover lt 7 gt 0 enable switchover deglitch circuit Deglitch 7 1 disable switchover deglitch circuit 1C 6 Select If Register 0x1C lt 5 gt 0 select reference for PLL 6 0 select lt 6 gt 2 14 A ER2 7 1 5 UseREF SEL If Register0x1C lt 4 gt E 0 manual Set methochofRLL reference selection Pin lt 5 gt 0 use Register 0x1C lt 6 gt lt 5 gt 1 use REF_SEL pin 1C lt 4 gt Automatic Automatic or manual reference switchover Single ended reference mode must be selected by Reference Register 0x1C lt 0 gt 0 Switchover lt 4 gt 0 manual reference switchover lt 4 gt 1 automatic reference switchover 1C lt 3 gt Stay on REF2 Stay REF2 after switchover lt 3 gt 0 return to REF1 automatically when REF1 status is good again lt 3 gt 1 stay on REF2 after switchover Do not automatically return to REF1 1C lt 2 gt REF2 When automatic reference switchover is disabled this bit turns the REF2 power on Power On lt 2 gt 0 REF2 power off lt 2 gt 1 REF2 power on 1C lt 1 gt When automatic reference switchover is disabled this bit turns the REF1 power on Power On lt 1 gt 0 REF1 power off lt 1 gt 1 REF1 power on
72. alue divisions from 1 to 1024 are obtainable only the values that are the product of the separate divisions of the two dividers x Dx can be realized If only one divider is needed when using Divider 3 and Divider 4 use the first one X 1 and bypass the second one X 2 Do not bypass X 1 and use X 2 Duty Cycle and Duty Cycle Correction Divider 3 and Divider 4 The same duty cycle and DCC considerations apply to Divider 3 and Divider 4 as to Divider 0 Divider 1 and Divider 2 see Duty Cycle and Duty Cycle Correction 0 1 and 2 however with these channel dividers the number of possible configurations is even more complex Duty cycle correction on Divider 3 and Divider 4 requires the following channel divider conditions An even must be set with the Mxy Nxy low cycles high cycles e An odd must be set as Mxy Nxy 1 the number of low cycles must be one greater than the number of high cycles If only one divider is bypassed it must be the second divider X 2 If only one divider has an eyen divide by it must be the second divider X 2 The possibilities for the duty cycle of the output clock from Divider 3 and Divider 4 are shown in Table 40 through Table 44 Table 40 Divider 3 Divider 4 Duty Cycle VCO Divider Used Duty Cycle Correction Off DCCOFF 1 AD9516 1 Table 41 Divider 3 Divider 4 Duty Cycle VCO Divider Not Used Duty Cycle Correction Off DCCO
73. be taken to match CLOCK OUTPUTS Table 4 Parameter Min Typ Max Unit Test Conditions Comments LVPECL CLOCK OUTPUTS Termination 50 Q to Vs 2 V OUTO OUT1 OUT2 OUT3 OUT4 OUT5 Differential OUT OUT Output Frequency Maximum 2950 MHz Using direct to output see Figure 25 Output High Voltage Von Vs 1 12 0 98 Vs 0 84 V Output Low Voltage Voi Vs 2 03 Vs 1 77 Vs 149 V Output Differential Voltage 550 790 980 mV LVDS CLOCK OUTPUTS Differential termination 100 O 3 5 mA OUT6 OUT7 OUT8 OUT9 Differential OUT OUT Output Frequency 800 MHz SeeFigure 26 Differential Output Voltage 247 360 454 mV Delta 25 mV Output Offset Voltage Vos 1 125 1 24 1 375 V Delta Vos 25 mV Short Circuit Current Isa Iss 14 24 mA Output shorted to GND Rev 0 Page 6 of 84 AD9516 1 Parameter Min Typ Max Unit Test Conditions Comments CMOS CLOCK OUTPUTS OUT6A OUT6B OUT7A OUT7B OUT8A Single ended termination 10 pF OUT8B OUT9A OUT9B Output Frequency 250 MHz see Figure 27 Output Voltage High Vs 0 1 V 1 mA load Output Voltage Low Voi 0 1 V 1 mA load TIMING CHARACTERISTICS Table 5 Parameter Min Typ Max Unit Test Conditions Comments LVPECL Termination 50 to Vs 2 V level 810 mV Output Rise Time tre 70 180 ps 2096 to 8096 measured differentially Output Fall Time tr 70 180 ps 8096 to 2
74. ch is connected to the LD pin Control Level or Dynamic 5 4 3 2 1 0 Signal SignalatLD Pin 0 0 0 0 0 0 LVL Digital lock detect high lock low unlock 0 0 0 0 0 DYN P channel open drain lock detect analog lock detect 0 0 0 0 1 0 DYN N channel open drain lock detect analog lock detect 0 0 0 0 1 1 HIZ High Z LD pin 0 0 0 1 0 0 CUR Current source lock detect 110 when DLD is true 0 X X X X X Ground dc for all other cases of OXXXXX not specified above The selections that follow are the same as REFMON 1 0 0 0 0 0 WL Ground dc 1 0 0 0 0 1 DYN REF1 clock differential reference When in differential mode 1 30 O 0 10 DYN REF2 in diffetentiat Mode 1 0 0 0 1 1 DYN Selected reference to PLL differential reference when in differential mode 1 0 0 1 0 0 DYN Unselected reference to PLL not available in differential mode 1 0 0 1 0 1 LVL Status of selected reference status of differential reference active high 1 0 0 1 1 0 LVL Status of unselected reference not available in differential mode active high 1 0 0 1 1 1 LVL Status REF1 frequency active high 1 0 1 0 0 0 LVL Status REF2 frequency active high 1 0 1 0 0 1 LVL Status REF1 frequency AND status REF2 frequency 1 0 1 0 1 0 LVL DLD AND status of selected reference AND status of VCO 1 0 1 0 1 1 LVL Status of VCO frequency active high 1 0 1 1 0 0 LVL Selected reference Low REF1 High R
75. cle VCO Divider Used Duty Cycle Correction On DCCOFF 0 VCO Divider Input Duty Cycle Table 44 Divider 3 Divider 4 Duty Cycle VCO Divider Not Used Duty Cycle Correction On DCCOFF 0 vco Dx Divider Mx 2 Nx2 Mx2 2 Duty Cycle Even 1 1 50 Odd 3 1 1 1 X 3 Odd 5 1 1 2 X 5 Even 1 50 Even Odd Mx i 255 Odd Even 1 1 50 _ Odd 3Nxa 4 X Odd 3 Wa m Na 6 1 9 _ 5 7 Odd 5 Ma Na 1 10 15 Even Even d Even Mx Nx2 Mx 20 Even Even Odd Nx1 Mx Nx2 Mx 20 Odd Even Even 1 Nx2 Mx 20 Odd Even 5 Odd Mxi Nxi 1 Nx22 Mx2 30 Odd Odd Even Mia Nar 1 NEM 4826 6Nx 1Nx2 Odd Odd ONx2 13 X m Mx1 Nxit 1 2 2 1 3 2 3 2Nx2 3 10Nx1Nx24 15Nx Odd 5 Odd Odd 15Nx2 22 X E Nxi 1 Mx2 Nx2 1 52 3 2 Nx2 3 Input Clock Dx Duty Output Cycle 2 Nx2 Mx2 2 Duty Cycle 50 1 1 50 50 Even 1 50 Mx X 1 1 X96 High X96 Even 1 50 Mx 50 Odd 1 50 Mx 1 X Odd 1 1 X Mx 1 2Nx 1 3 Odd 1 1 X Mx 1 2Nx 1 3 50 Even Even 50 Nx Mx Nx2 Mx
76. cted reference status of differential reference active high 1 0 0 1 1 Status of unselected reference not available in differential mode active high 1 0 0 1 1 1 LVL Status REF1 frequency active high 1 0 1 0 0 0 WL Status REF2 frequency active high 1 0 1 0 0 1 LVL Status REF1 frequency AND status REF2 frequency 1 0 1 0 1 0 LVL DLD AND status of selected reference AND status of VCO 1 0 1 0 1 1 LVL Status of VCO frequency active high 1 0 1 1 0 0 LVL Selected reference Low REF1 High REF2 1 0 1 1 0 1 LVL Digital lock detect DLD active high 1 0 1 1 1 0 LVL Holdover active active high 1 0 1 1 1 1 LVL LD pin comparator output active high 1 1 0 O 0 VS PLL supply Rev 0 Page 62 of 84 AD9516 1 Reg Addr Hex Bit s Name Description Level or Dynamic lt 7 gt 6 lt 5 gt 4 3 2 Signal Signal at STATUS Pin 1 1 0 0 0 1 DYN REF1 clock differential reference when in differential mode 1 1 0 0 1 0 DYN REF2 clock not available in differential mode 1 1 0 0 1 1 DYN Selected reference to PLL differential reference when in differential mode 1 1 0 1 0 0 DYN Unselected reference to PLL not available when in differential mode 1 1 0 1 0 1 LVL Status of selected reference status of differential reference active low 1 1 0 1 1 0 LVL Status of unselected reference not available in differential mode active low 1 1 0 1 1 1 LVL Status of
77. data transfer portion of the communications cycle Only Bits lt A9 A0 gt are needed to cover the range of the 0x232 registers used by the AD9516 Bits lt A12 A10 gt must always be 0b For multibyte transfers this address is the starting byte address In MSB first mode subsequent bytes increment the address MSB LSB FIRST TRANSFERS The AD9516 instruction word and byte data can be MSB first or LSB first Any data written to 0x000 must be mirrored the upper four bits lt 7 4 gt with the lower four bits lt 3 0 gt This makes it irrelevant whether LSB first or MSB first is in effect As an example of this mirroring see the default setting for this register 0x18 which mirrors Bit 4 and Bit 3 This sets the long instruction mode default and only mode supported The default for the AD9516 is MSB first When LSB first is set by 0x000 lt 2 gt and 0 000 lt 6 gt it takes effect immediately because it only affects the operation of the serial control port and does not require that an update be executed When MSB first mode is active the instruction and data bytes must be written from MSB to LSB Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte Subsequent data bytes must follow ingorder from the high address to the low address In MSB first mode tlle serial control port internal addressgenerator for each data byte of th
78. de 4 0 turn off the CMOS B output lt 4 gt 1 turn on the CMOS B output 143 lt 3 gt 00 9 Select LVDS CMOS Select LVDS or CMOS logic levels lt 3 gt 0 LVDS lt 3 gt 1 CMOS 143 lt 2 1 gt OUT9 LVDS Output Current Set output current level in LVDS mode This has no effect in CMOS mode 2 1 Current mA Recommended Termination 0 SSE TSSE 1 100 4 33 100 1 7077525 50 1 1 7 50 143 lt 0 gt OUT9 Power Down Power down output LVDS CMOS lt 0 gt 0 power on lt 0 gt 1 power off Table 57 LVPECL Channel Dividers Reg Addr Hex Bit s Name Description 190 lt 7 4 gt Divider 0 Low Cycles Number of clock cycles of the divider input during which divider output stays low 190 lt 3 0 gt Divider 0 High Cycles Number of clock cycles of the divider input during which divider output stays high 191 7 Divider 0 Bypass Bypass and power down the divider route input to divider output 7 0 use divider 7 1 bypass divider 191 lt 6 gt Divider 0 Nosync Nosync 6 0 obey chip level SYNC signal 6 1 ignore chip level SYNC signal 191 lt 5 gt Divider 0 Force High Force divider output to high This requires that nosync also be set 5 0 divider output forced to low 5 1 divider output forced to high 191 4 jDivider 0 Start High Selects clock output to start high or start low 4 0 start low
79. e 101 1 1 2 110 1 1 2 100 2 1 3 001 2 1 3 111 0 1 1 Delay Range ns 200 No of Caps 3 Iramp 1 3286 No of Caps 1 6 RAMP Offset ns 0 34 1600 I pa mp x 10 4 Delay Full Scale ns Delay Range Offset Fine Delay ns Delay Range x Delay Fraction x 1 63 Offset Note that only delay fraction values up to 47 decimal 101111b 0x2F are supported In no case can the fine delay exceed one half of the output clock period If a delay longer than half of the clock period is attempted the output stops clocking The delay function adds some jitter greater than that specified for the nondelayed output This means that the delay function shouldbe used pximarily for digital chips such as ASIC 0 An output with this delay enabled may not be suitable for clocking data converters The jitter is higher for long full scales because the delay block uses a ramp and trip points to create the variable delay A slower ramp time produces more time jitter Synchronizing the Outputs SYNC Function The AD9516 clock outputs can be synchronized to each other Outputs can be individually excluded from synchronization Synchronization consists of setting the nonexcluded outputs to a preset set of static conditions and subsequently releasing these outputs to continue clocking at the same instant with the preset conditions applied This
80. e multibyte transfer cycle When LSB first is active the instruction and data bytes must be written from LSB to MSB Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes The internal byte address generator of the serial control port increments for each byte of the multibyte transfer cycle The AD9516 serial control port register address decrements from the register address just written toward 0x000 for multibyte operations if the MSB first mode is active default If the LSB first mode is active the register address of the serial control port increments from the address just written toward 0x232 for multibyte I O operations Streaming mode always terminates when it hits Address 0x232 Note that unused addresses are not skipped during multibyte I O operations Table 48 Streaming Mode No Addresses Are Skipped Write Mode Address Direction Stop Sequence LSB first Increment 0x230 0x231 0x232 stop MSB first Decrement 0x001 0x000 0x232 stop Rev 0 Page 53 of 84 AD9516 1 Table 49 Serial Control Port 16 Bit Instruction Word MSB First MSB LSB Spio cane RW wifwo mo 4 ar 07 ps ps po pe os pa ez pt po K DONT CARE 16 BIT INSTRUCTION HEA
81. ential LVPECL Output 52 OUTI LVPECL Output One Side of a Differential LVPECL Output 43 OUT2 LVPECL Output One Side of a Differential LVPECL Output 42 OUT2 LVPECL Output One Side of a Differential LVPECL Output 40 OUT3 LVPECL Output One Side of a Differential LVPECL Output 39 OUT3 LVPECL Output One Side of a Differential LVPECL Output 25 OUT4 LVPECL Output One Side of a Differential LVPECL Output 26 OUT4 LVPECL Output One Side of a Differential LVPECL Output 28 OUT5 LVPECL Output One Side of a Differential LVPECL Output 29 OUTS LVPECL Output One Side of a Differential LVPECL Output 48 OUT6 OUT6A LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 47 OUT6 OUT6B LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 46 OUT7 OUT7A LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 45 OUT7 OUT7B LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 33 OUT8 OUT8A LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 34 OUT8 OUT8B LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 35 OUT9 OUT9A LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 36 OUT9 OUT9B LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 5
82. es into account the settings in each ofthe channels start high bit and its phase offset These settings govern both the static state of each output when the SYNC operation is happening and the state and outputs when they begin clodkinty again upon completion of the SYNC operation Between outputs and after synchronization this allows for the setting of phase offsets The AD9516 outputs are in pairs sharing a channel divider per pair two pairs of pairs four outputs in the case of CMOS The synchronization conditions apply to both outputs of a pair Each channel a divider and its outputs can be excluded from any SYNC operation by setting the NOSYNC bit of the channel Channels that are set to ignore SYNC excluded channels do not set their outputs static during a SYNC operation and their outputs are not synchronized with those of the nonexcluded channels Clock Outputs The AD9516 offers three different output level choices LVPECL LVDS and CMOS OUTO to 5 are LVPECL differential outputs and OUT6 to OUTS are LVDS CMOS outputs These outputs can be configured as either LVDS differential or as pairs of single ended CMOS outputs LVPECL Outputs OUTO to OUT5 The LVPECL differential voltage is selectable from 400 mV to 960 mV see 0xF0 0xF5 lt 3 2 gt The LVPECL outputs have dedicated pins for power supply VS_LVPECL allowing for a separate power supply to be used Vs can be from 2
83. escription 19B lt 7 4 gt Low Cycles Divider 3 2 Number of clock cycles of 3 2 divider input during which 3 2 output stays low 19B 3 0 High Cycles Divider 3 2 Number of clock cycles of 3 2 divider input during which 3 2 output stays high 19C lt 5 gt Bypass Divider 3 2 Bypass and power down 2 2 divider logic route clock to 3 2 output 4 i 5 0 40 not bypass 45 19C lt 4 gt Bypass Divider 3 1 Bypass and power down 3 1 divider logic route clock to 3 1 output lt 4 gt 0 do not bypass lt 4 gt 1 bypass 19C lt 3 gt Divider 3 Nosync Nosync lt 3 gt 0 obey chip level SYNC signal lt 3 gt 1 ignore chip level SYNC signal 19C lt 2 gt Divider 3 Force High Force Divider 3 output high Requires that nosync also be set lt 2 gt 0 force low lt 2 gt 1 force high 19C lt 1 gt gt High Divider 3 2 Divider 3 2 start high low lt 1 gt 0 start low lt 1 gt 1 start high 19C lt 0 gt Start High Divider 3 1 Divider 3 1 start high low 0 0 start low 0 1 start high 19D lt 0 gt jDivider 3 DCCOFF Duty cycle correction function 0 0 enable duty cycle correction 0 1 disable duty cycle correction 19E lt 7 4 gt Low Cycles Divider 4 1 Number of clock cycles of divider 4 1 input during which 4 1 output stays low 19E lt 3 0 gt High Cycles Divider 4 1 Number of clock cycles of 4 1 divider input during which 4 1 ou
84. ettings These are indicated in the Default Value column of Table 51 At power on the AD9516 also executes a SYNC operation which brings the outputs into phase alignment according to the default settings Asynchronous Reset via the RESET Pin An asynchronous hard reset is executed by momentarily pulling RESET low A reset restores the chip registers to the default settings Soft Reset via 0x00 lt 5 gt A soft reset is executed by writing 0x00 lt 5 gt and 0x00 lt 2 gt 1b This bit is not self clearing therefore it must be cleared by writing 0x00 lt 5 gt and 0x00 lt 2 gt Ob to reset it and complete the soft reset operation A soft reset restores the default values to the internal registers The soft reset bit does not require an update registers command 0x232 to be issued POWER DOWN MODES Chip Power Down via PD The AD9516 can be put into a power down condition by pulling the PD pin low Powex doywn turns off most of the functi ns inside the The chip remains in this power d wn state until PD is rought back to Logic High When woken up the AD9516 returns to the settings programmed into its registers prior to the power down unless the registers are changed by new programming while the PD pin is held low The PD power down shuts down the currents on the chip except the bias current necessary to maintain the LVPECL outputs in a safe shutdown mode This is needed to protect the LVPECL output circuitr
85. ey may also be reset through a SYNC operation R A and B Counters SYNC Pin Reset The R A and B counters may also be reset simultaneously through the SYNC pin This function is controlled by 0x19 lt 7 6 gt see Table 53 The SYNC pin reset is disabled by default Rand N Divider Delays Both the R and N dividers feature a programmable delay cell These delays may be enabled to allow adjustment of the phase relationship between the PLL reference clock and the VCO or CLK Each delay is controlled by three bits The total delay range is about 1 ns See 0x19 in Table 53 Table 28 How a 10 MHz Reference Input May Be Locked to Any Integer Multiple of N FREF R P A B N FVCO Mode Notes 10 1 1 X 1 1 10 FD P 1 B 1 bypassed 10 1 2 X 1 ND 20 FB 4 J 1 bypassed 10 1 1 X 3 3 30 FD PXLB 3 10 1 1 X 4 4 40 FD P 1 B 4 10 1 1 X 5 5 50 FD P 1 B 5 10 1 2 X 3 6 60 FD P 2 B 3 10 1 2 0 3 6 60 DM PandP 1 2and3 A 0 B 3 10 1 2 1 3 7 70 DM PandP 1 2and3 A 1 B 3 10 1 2 2 3 8 80 DM PandP 1 2and3 A 2 B 3 10 1 2 1 4 9 90 DM PandP 1 2and3 A 1 B 4 10 1 2 X 5 10 100 FD P 2 B 5 10 1 2 0 5 10 100 DM PandP 1 2and3 A 0 B 5 10 1 2 1 5 11 110 DM PandP 1 2and3 A 1 B 5 10 1 2 X 6 12 120 FD P 2 B 6 10 1 2 0 6 12 120 DM PandP 1 2and3 A 0 B 6 10 1 4 0 3 12 120 DM PandP 1 4and5 A 0 B 3 10 1 4 1 3 13 130 DM PandP 1 4and5 A 1 B 3 Rev 0 Page 36 of 84 AD9516 1 DIGITAL LOCK DETECT DLD By selecting the
86. f the sum of squares of the individual contributors Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured The time jitter of any external oscillators or clock sources are subtracted This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources each of which contribute its own time jitter to the total In many cases the time jitter of the external oscillators and clock sources dominates the system time jitter Rev 0 Page 25 of 84 AD9516 1 DETAILED BLOCK DIAGRAM REFIN REF1 REFIN REF2 BYPASS vs RSET CPRSET VCP REFMON PROGRAMMABLE R DELAY REF_SEL LD REFERENCE CHARGE PUMP O LOW DROPOUT 5 REGULATOR LDO A B COUNTERS PHASE FREQUENCY DETECTOR PROGRAMMABLE N DELAY 46 0 vco DIVIDE BY STATUS 2 3 4 5 OR 6 CLK OUTO zug LVPECL DIGITAL ouri LOGIC D OUT1 OUT2 LVPECL SCLK OUT3 SDIO SDO cs O OUT4 DIVIDE BY 1 TO 32 OUT6 OUT6A O OUT6 OUT6B 1 TO 32 1 TO 32 0017 OUT7A OUT7 OUT7B OUTS OUT8A O OUTS OUT8B DIVIDE BY DIVIDE BY 1 TO 32 1 TO 32 OUTS OUT9A O OUTS OUT9B AD9516 1 06420 002 Figure 41 Detailed Block Diagram Rev 0 Page 26
87. frequency divided by P PLL DIVIDER DELAYS Register 0x19 R lt 5 3 gt N lt 2 0 gt see Table 53 000 Off ps 001 330 ps 010 440 ps 011 550 ps 100 660 ps 101 770 ps 110 880 ps 111 990 ps NOISE CHARACTERISTICS In Band Phase Noise of the Charge The PLL in band phase noise floor is estimated Pump Phase Frequency Detector by measuring the in band phase noise at the In Band Means Within the LBW output of the VCO and subtracting 20log N of the PLL where N is the value of the N divider 500 kHz PFD Frequency 165 dBc Hz 1 MHz PFD Frequency 162 dBc Hz 10 MHz PFD Frequency 151 dBc Hz 50 MHz PFD Frequency 143 dBc Hz PLL Figure of Merit FOM 220 dBc Hz Reference slew rate gt 0 25 V ns FOM 10log fero is an approximation of the PFD CP in band phase noise in the flat region inside the PLL loop bandwidth When running closed loop the phase noise as observed at the VCO output is increased by 20log N Rev 0 Page 5 of 84 AD9516 1 Parameter Min Typ Max Unit Test Conditions Comments PLL DIGITAL LOCK DETECT WINDOW Signal available at LD STATUS and REFMON pins when selected by appropriate register settings Required to Lock Coincidence of Edges Selected by 0x17 lt 1 0 gt and 0x18 lt 4 gt Low Range ABP 1 3 ns 2 9 ns 3 5 ns 0x17 lt 1 0 gt 00b 01b 11b 0x18 lt 4 gt 1b High Range ABP 1 3 ns 2 9 ns 75 ns 0x17 lt 1 0 gt 00b 01b 11b 0x18 lt 4 gt Ob High Range ABP 6 ns 3 5
88. fter a reset operation If the contents of the registers are altered by prior programming after power up or reset these registers may also be set intentionally to these values Table 21 Default Settings of Some PLL Registers Register Function 0 10 lt 1 0 gt 01b PLL asynchronous power down PLL off 0x1E0 lt 2 0 gt 010b Set VCO divider 4 0x1E1 lt 0 gt 0b Use the VCO divider 0x1E1 lt 1 gt 0b CLK selected as the source When using the internal PLL with an external VCO the PLL must be turned on Table 22 Settings When Using an External VCO Register Function 0x10 to 0x1E PLL normal operation PLL on 0x1E1 lt 1 gt 0b PLL settings Select and enable a reference input set R N P A B PFD polarity and Ice according to the intended loop configuration An external VCO requires an external loop filter that must be connected between CP and the tuning pin of the VCO This loop filter determines the loop bandwidth and stability of the PLL Make sure to select the proper PFD polarity for the VCO being used Table 23 Setting the PFD Polarity R gister 7 Function Ox 9 lt 0b PRD pOlarity positive higher control voltage produces higher frequency 0 10 lt 7 gt 1b PFD polarity negative higher control voltage produces lower frequency Rev 0 Page 27 of 84 AD9516 1 REF_SEL vs GND RSET REFMON CPRSET VCP O DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER
89. he highest frequencies Rev 0 Page 41 of 84 AD9516 1 To connect the LVPECL outputs directly to the internal VCO or CLK the VCO divider must be selected as the source to the distribution section even if no channel uses it Either the internal VCO or the CLK can be selected as the source for the direct to output routing Table 31 Settings for Routing VCO Divider Input Directly to LVPECL Outputs Register Setting Selection 0x1E1 lt 1 0 gt 006 0x1E1 lt 1 0 gt 10b 0x192 lt 1 gt 1b 0x195 lt 1 gt 1b 0x198 lt 1 gt 1b CLK is the source VCO divider selected VCO is the source VCO divider selected Direct to output OUTO OUT1 Direct to output OUT2 OUT3 Direct to output OUT4 OUT5 Clock Frequency Division The total frequency division is a combination of the VCO divider when used and the channel divider When the VCO divider is used the total division from the VCO or CLK to the output is the product of the VCO divider 2 3 4 5 6 and the division of the channel divider Table 32 and Table 33 indicate how the frequency division for a channel is set For the LVPECL outputs there is only one divider per channel For the LVDS CMOS outputs there are two dividers X 1 X 2 cascaded per channel Table 32 Frequency Division for Divider 0 to Divider 2 The channel dividers feeding the LVPECL output drivers contain one 2 to 32 frequency divider This divider provides for division by 1 to 32 Divis
90. hich requires an extended voltage range can be accommodated by connecting the charge pump supply VCP to 5 5 V separate LVPECL power supply can be from 2 375 V to 3 6 V The AD9516 1 is specified for operation over the industrial range of 40 C to 85 1 AD9516 is used throughout to refer to all the members of the AD9516 family However when AD9516 1 is used it is referring to that specific member of the AD9516 family One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2007 Analog Devices Inc All rights reserved AD9516 1 TABLE OF CONTENTS Features sos aaa uer 1 Applications iiie ten e rie CURIE 1 1 Functional Block 1 REVISION History uy aqa u u 3 4 Power Supply Requirements 4 Characteristics 4 Clock Inputs D E aya 6 Clock Outputs 6 Timing Characteristics ett ten 7 Clock Output Additive Phase Noise Distribution Only VCO Divider Not Used dva adi ies 8 Clock Output Absolute Phase Noise Internal VCO Used 9 Clock Output Absolute Time Jitter Clock Generation Using Internal VCO nee EE 10 Clock Output Absolute Time Jitter Clock Cleanup Using Internal tette toe aie
91. ion Reference 231 Blank Reserved 00 Update All Registers 232 Update All Blank Update All 00 Registers Registers Self Clearing Bit I I Rev 0 Page 59 of 84 AD9516 1 REGISTER MAP DESCRIPTIONS Table 52 through Table 61 are a detailed description of each of the control register functions The registers are listed by hexadecimal address Reference to a specific bit or range of bits within a register is indicated by angle brackets Example lt 3 gt refers to Bit 3 while lt 5 2 gt refers to the range of bits from Bit 5 through Bit 2 Table 52 Serial Port Configuration Reg Addr Hex Bit s Name Description 00 lt 7 gt SDO Active Selects unidirectional or bidirectional data transfer mode lt 7 gt 0 SDIO pin used for write and read SDO set high impedance bidirectional mode lt 7 gt 1 SDO used for read SDIO used for write unidirectional mode 00 lt 6 gt LSB First MSB or LSB data orientation lt 6 gt 0 data oriented MSB first addressing decrements lt 6 gt 1 data oriented LSB first addressing increments 00 lt 5 gt Soft Reset Soft Reset lt 5 gt 1 not self clearing Soft reset restores default values to internal registers Not self clearing Must be cleared to to complete reset operation 00 lt 4 gt Long Instruction Short long instruction mode this part uses long instruction mode only so this bit should always be 1 4 0 8 bit inst
92. ion by 1 is accomplished by bypassing the divider The dividers also provide for a programmable duty cycle with optional duty cycle correction when the divide ratio is odd A phase offset or delay in increments of the input clock cycle is selectable The channel dividers operate with a signal at their inputs up to 1600 MHz The features and settings of the dividers are selected by programming the appropriate setup and control registers see Table 51 through Table 61 VCO Divider The VCO divider provides frequency division between the internal VCO or the external CLK input and the clock distribution channel dividers The VCO divider can be set to divide by 2 3 4 5 or 6 see Table 59 0 1 0 lt 2 0 gt Channel Dividers LVPECL Outputs Each pair of LVPECL outputs is driven by a channel divider There are three channel dividers 0 1 and 2 driving a total of six LVPECL outputs OUTO to OUTS Table 34 gives the register locations used for setting the division and other functions of these dividers The division is set by the values of M N The divider can be bypassed equivalent to divide by 1 divider circuit is powered down by setting the bypass bit The duty cycle correction can be enabled or disabled according to the seffing of HE DOGOEF bits Table 34 Setting Dx for Divider 0 Divider 1 and Divider 2 CLKorVCO VCO Channel Directto Frequency Selected Divider Divider Output Division CLK VCO 2to6 1 bypassed
93. it 3 Bit 2 Bit 1 Bit 0 LSB Hex Fine Delay Adjust OUT6 to OUT9 AO OUT6 Delay Blank OUT6 Delay 01 Bypass Bypass A1 OUT6 Delay Blank OUT6 Ramp Capacitors OUT6 Ramp Current 00 Full Scale A2 OUT6 Delay Blank OUT6 Delay Fraction 00 Fraction A3 OUT7 Delay Blank OUT7 Delay 01 Bypass Bypass 4 OUT7 Delay Blank OUT7 Ramp Capacitors OUT7 Ramp Current 00 Full Scale A5 OUT7 Delay Blank OUT7 Delay Fraction 00 Fraction A6 OUTS Delay Blank OUTS Delay 01 Bypass Bypass A7 OUTS Delay Blank OUT8 Ramp Capacitors OUT8 Ramp Current 00 Full Scale A8 OUTS Delay Blank OUTS Delay Fraction 00 Fraction A9 OUT9 Delay Blank OUT9 Delay 01 Bypass Bypass AA OUT9 Delay Blank OUT9 Ramp Capacitors OUT9 Ramp Current 00 Full Scale AB OUT9 Delay Blank OUT9 Delay Fraction 00 Fraction 1 ACto Blank EF LVPECL Outputs FO OUTO Blank OUTO OUTO LVPECL OUTO Power Down 08 Invert Differential Voltage F1 OUT1 Blank OUT1 OUT1 LVPECL OUT1 Power Down A Invert Differential Voltage F2 OUT2 Blank OUT2 OUT2 LVPECL OUT2 Power Down 08 Invert Differential Voltage F3 OUT3 Blank OUT3 OUT3 LVPECL OUT3 Power Down 0A Invert Differential Voltage FA OUTA Blank OUTA OUTA LVPECL OUT4 Power Down 08 Invert Differential Voltage F5 OUT5 Blank OUT5 5 LVPECL OUT5 Power Down 0A Invert Differential Voltage F6to Blank 13F LVDS CMOS Outputs 140 OUT6 OUT6 CMOS Output OUT6LVDS OUT6 OUT6 Select OUT6 LVDS Output OUT6 42 Polarity CMOS CMOS B LVDS CMOS Current Power Down Output Po
94. it is only possible to get a Logic High level after the DLD has been true for a sufficiently long time Any momentary DLD false resets the charging By selecting a properly sized capacitor it is possible to delay a lock detect indication until the PLL is stably locked and the lock detect does not chatter The voltage on the capacitor can be sensed by an external comparator connected to the LD pin However there is an internal LD pin comparator that can be read at the REFMON pin control 0x1B lt 4 0 gt or the STATUS pin control 0x17 lt 7 2 gt as an active high signal It is also available as an active low signal REFMON 0x1B lt 4 0 gt and STATUS 0x17 7 2 The internal LD pin comparator trip point and hysteresis are given in Table 16 AD9516 1 110pA DLD LD Vour B REFMON OR STATUS 06420 068 Figure 49 Current Source Lock Detect External VCXO VCO Clock Input CLK CLK CLK is a differential input that can be used as an input to drive the AD9516 clock distribution section This input can receive up to 2 4 GHz The pins are internally self biased and the input signal should be ac coupled via capacitors CLOCK INPUT STAGE 06420 032 Figure 50 CLK Equivalent Input Circuit The CLK CLK input can be used either as a distribution only input with the PLL off or as a feedback input for an external VCO VCXO using the internal PLL when the internal VCO is not used The CLK CLK input can be used for frequencies u
95. l lt 1 gt 1 external holdover mode holdover controlled by SYNC pin 1D lt 0 gt Holdover Along with lt 2 gt enables the holdover function Enable lt 0 gt 0 holdover disabled lt 0 gt 1 holdover enabled lt 6 gt VCO Cal Readback register status of the VCO calibration Finished lt 6 gt 0 VCO calibration not finished 6 1 VCO calibration finished 1F 5 Readback register indicates if the part is in the holdover state see Figure 51 This is not the same as holdover Active enabled lt 5 gt 0 not in holdover lt 5 gt 1 holdover state active 1 lt 4 gt 2 Readback register indicates which PLL reference is selected as the input to the PLL Selected lt 4 gt 17 W selected or differential reference differential mode lt 4 gt Z REF2 Selected 1F lt 3 gt Readback register indicates if the VCO frequency is greater than the threshold see Table 16 REF1 REF2 and VCO Frequency gt Frequency Status Monitor Threshold 3 0 VCO frequency is less than the threshold 3 1 VCO frequency is greater than the threshold 1 lt 2 gt 2 Readback register indicates if the frequency of the signal at REF2 is greater than the threshold frequency Frequency gt set by Register 0x1A lt 6 gt Threshold lt 2 gt 0 REF2 frequency is less than threshold frequency lt 2 gt 1 REF2 frequency is greater than threshold frequency 1 lt 1
96. l biasing currents connect to ground CPRSET Pin Resistor 5 1 kQ Sets internal CP current range nominally 4 8 mA CP_Isb 600 pA actual current can be calculated by CP_Isb 3 06 CPRSET connect to ground BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator necessary for LDO stability connect to ground PLL CHARACTERISTICS Table 2 Parameter Min Typ Max Unit Test Conditions Comments VCO ON CHIP Frequency Range 2300 2650 MHz See Figure 15 VCO Gain Kvco 50 MHz V See Figure 10 Tuning Voltage Vr 0 5 0 5 V Vc lt Vs when using internal VCO outside of this range the CP spurs may increase due to CP up dowmqmrismatch Frequency Pushing Open Loop i 1 MHz V Phase Noise 100 kHz Offset 105 dBc Hz 2475 MHz Phase Noise 1 MHz Offset 124 dBc Hz 2475 MHz REFERENCE INPUTS Differential Mode REFIN REFIN Differential mode can accommodate single ended input by ac grounding undriven input Input Frequency 0 250 MHz Frequencies below about 1 MHz should be dc coupled be careful to match Vem self bias voltage Input Sensitivity 250 mV p p PLL figure of merit will increase with increasing slew rate see Figure 14 Self Bias Voltage REFIN 1 35 1 60 1 75 V Self bias voltage of Self Bias Voltage REFIN 1 30 1 50 1 60 V Self bias voltage of REFIN Input Resistance REFIN 4 0 4 8 5 9 Self biased Input Resistance REFIN 44 5 3 6 4 kQ Self biased Dual Single Ended Mode REF1 REF2 Two si
97. l operation 00b it is possible for a low impedance load on that LVPECL output to draw significant current during this power down If the LVPECL power down mode is set to 11b the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions 1 AD9516 1 Individual Clock Output Power Down Any of the clock distribution outputs may be powered down individually by writing to the appropriate registers The register map details the individual power down settings for each output The LVDS CMOS outputs may be powered down regardless of their output load configuration The LVPECL outputs have multiple power down modes see Table 55 which give some flexibility in dealing with the various output termination conditions When the mode is set to 10b the LVPECL output is protected from reverse bias to 2 VBE 1 V If the mode is set to 11b the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions This setting also affects the operation when the distribution block is powered down with 0x230 lt 1 gt 1b see the Distribution Power Down section Individual Circuit Block Power Down Other AD9516 circuit blocks such as CLK REF1 and REF2 can be powered down individually This gives flexibility in configuring the part for power savings whenever certain chip functions are not needed NAL Rev 0 Page 51 of 84 AD9516 1 SERI
98. larity 141 OUT7 OUT7 CMOS Output OUT7 LVDS OUT7 OUT7 Select OUT7 LVDS Output OUT7 43 Polarity CMOS CMOS B LVDS CMOS Current Power Down Output Polarity 142 OUT8 OUT8 CMOS Output OUT8LVDS OUT8 OUTS Select OUT8 LVDS Output OUT8 42 Polarity CMOS CMOS LVDS CMOS Current Power Down Output Polarity 143 OUT9 OUT9 CMOS Output OUT9LVDS OUT9 OUTO Select OUT9 LVDS Output OUT9 43 Polarity CMOS CMOS B LVDS CMOS Current Power Down Output Polarity Rev 0 57 of 84 AD9516 1 Default Addr Bit 7 Value Hex Parameter MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB Hex 144 to Blank 18F LVPECL Channel Dividers 190 Divider 0 Divider 0 Low Cycles Divider 0 High Cycles 00 PECL 191 Divider 0 Divider 0 Divider 0 Divider 0 Divider 0 Phase Offset 80 Bypass Nosync Force High Start High 192 Blank Reserved Divider 0 Divider 0 00 Direct to DCCOFF Output 193 Divider 1 Divider 1 Low Cycles Divider 1 High Cycles BB PECL 194 Divider 1 Divider 1 Divider 1 Divider 1 Divider 1 Phase Offset 00 Bypass Nosync Force High Start High 195 Blank Reserved Divider 1 Divider 1 00 Direct to DCCOFF Output 196 Divider 2 Divider 2 Low Cycles Divider 2 High Cycles 00 PECL 197 Divider 2 Divider 2 Divider 2
99. lerP Prescaler dual modulus and FD fixed divide lt 2 gt 1 0 Mode Prescaler 0 0 0 FD Divide by 1 0 0 1 FD Divide by 2 0 1 0 DM Divide by 2 and divide by 3 when A z 0 divide by 2 when A 0 0 1 1 DM Divide by 4 and divide by 5 when A z 0 divide by 4 when A 0 1 0 0 DM Divide by 8 and divide by 9 when A z 0 divide by 8 when A 0 1 0 1 DM Divide by 16 and divide by 17 when A z 0 divide by 16 when A 0 1 1 0 DM Divide by 32 and divide by 33 when A z 0 divide by 32 when A 0 1 1 1 FD Divide by 3 17 lt 7 2 gt STATUS Select the signal which is connected to the STATUS pin Pin Control Level or Dynamic 7 6 5 4 3 2 Signal Signal at STATUS Pin 0 0 0 0 0 0 LVL Ground DC 0 0 0 0 0 4 DYN N divider output after the delay 0 0 0 0 1 0 DYN R divider output after the 0 e 1 1 DYN Adivider output 0 0 0 1 0 0 DYN Prescaler output 0 0 0 1 0 1 DYN PFD up pulse 0 0 0 1 1 0 DYN PFD down pulse 0 X X X X X Ground dc for all other cases of OXXXXX not specified above The selections below are same as REFMON 1 0 0 0 0 0 LVL Ground dc 1 0 0 0 0 1 DYN REF1 clock differential reference when in differential mode 1 0 0 0 1 0 DYN REF2 clock N A in differential mode 1 0 0 0 1 1 DYN Selected reference to PLL differential reference when in differential mode 1 0 0 1 0 0 DYN Unselected reference to PLL not available in differential mode 1 0 0 1 0 1 LVL Status of sele
100. m 1 to 1024 but only the set of numbers that are the product of the two dividers Because the internal VCO frequency is above the maximum channel divider input frequency 1600 MHz the VCO divider must be used after the on chip VCO The VCO divider can be set to divide by 2 3 4 5 or 6 External clock signals connected to the CLK input also require the VCO divider if the frequency of the signal is greater than 1600 MHz The channel dividers allow for a selection of various duty cycles depending on the currently set division That is for any specific division D the output of the divider can be set to high for N 1 input clock cycles and low for M 1 input clock cycles where D N M 2 For example a divide by 5 can be high for one divider input cycle and low for four cycles or a divide by 5 can be high for three divider input cycles and low for two cycles Other combinations are also possible The channel dividers include a duty cycle correction function that can be disabled In contrast to the selectable duty cycle just described this function can correct a non 50 duty cycle caused by an odd division However this requires that the division be set by M N 1 In addition the channel dividers allow a coarse phase offset or delay to be set Depending on the division selected the output can be delayed by up to 31 input clock cycles The divider outputs can also be set to start high or start low Internal VCO or Extern
101. mented or decremented see the MSB LSB First Transfers section CS must be raised at the end of the last byte to be transferred thereby ending the stream mode Communication Cycle Instruction Plus Data There are two parts to a communication cycle with the AD9516 The first writes a 16 bit instruction word into the AD9516 coincident with the first 16 SCLK rising edges The instruction word provides the AD9516 serial control port with information regarding the data transfer which is the second part of the communication cycle The instruction word defines whether the upcoming data transfer is a read or a write the number of bytes in the data transfer and the starting register address for the first byte of the data transfer Write Hithe instruction word 18 for 4 operation second part is the transfer of data into the serial control port buffer of the AD9516 Data bits are registered on the rising edge of SCLK The length of the transfer 1 2 3 bytes or streaming mode is indicated by two bits W1 W0 in the instruction byte When the transfer is 1 2 or 3 bytes but not streaming CS can be raised after each sequence of eight bits to stall the bus except after the last byte where it ends the cycle When the bus is stalled the serial transfer resumes when CS is lowered Raising CS on a nonbyte boundary resets the serial control port During a write streaming mode does not skip over reserved or blank registers therefore
102. n use only if there are no external load resistors Off 1 0 Partial power down reference on safe LVPECL power down Off 1 1 Total power down reference off use only if there are no external load resistors Off F2 4 OUT2Invert Sets the output polarity 4 0 noninverting 4 1 inverting F2 3 2 OUT2 LVPECL Sets the LVPECL output differential voltage Differential lt 3 gt lt 2 gt mV Voltage 0 0 400 0 1 600 1 0 780 1 1 960 F2 1 0 OUT2 LVPECL Power down modes Power Dowh 215 0 T 4 Output 0 4 0 Normal operation On 0 1 Partial power down reference on use only if there are no external load resistors Off 1 0 Partial power down reference on safe LVPECL power down Off 1 1 Total power down reference off use only if there are no external load resistors Off F3 lt 4 gt OUT3Invert Sets the output polarity 4 0 noninverting lt 4 gt 1 inverting F3 3 2 OUT3 LVPECL Sets the LVPECL output differential voltage Differential lt 3 gt 2 mV Voltage 0 0 400 0 1 600 1 0 780 1 1 960 F3 1 0 OUT3 LVPECL power down modes Power Down 1 0 Mode Output 0 0 Normal operation On 0 1 Partial power down reference on use only if there are no external load resistors Off 1 0 Partial power down reference on safe LVPECL power down Off 1 1 Total power down reference off use only if there are no external load resistors Off F4
103. nds to the state of the currently selected reference 0x1C If the loop loses lock during a reference switchover see the Reference Switchover section holdover is triggered briefly until the next reference clock edge at the PFD The following registers affect the internal automatic holdover function 0x18 lt 6 5 gt lock detect counter This changes how many consecutive PFD cycles with edges inside the lock detect window are required for the DLD indicator to indicate lock This impacts the time required before the LD pinreansbegin to charge as well as the delay ofaholdoyer event until the holdover function ean re engaged 0x18 lt 3 gt disable digital lock detect This bit must be set to a 0 to enable the DLD circuit Internal automatic holdover does not operate correctly without the DLD function enabled 0x1A lt 5 0 gt lock detect pin output select Set this to 000100b to put it in the current source lock detect mode if using the LD pin comparator Load the LD pin with a capacitor of an appropriate value 0x1D lt 3 gt enable LD pin comparator 1 enable 0 disable When disabled the holdover function always senses the LD pin as high e 0x1D lt 1 gt enable external holdover control 0 10 lt 0 gt and Register 0x1D lt 2 gt holdover function enable If holdover is disabled both external and internal automatic holdover are disabled AD9516 1 For example to use automatic h
104. ng Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 142 4 OUT8 CMOS B In CMOS mode turn on off the CMOS B output There is no effect in LVDS mode 4 0 turn off the CMOS B output lt 4 gt 1 turn on the CMOS B output 142 lt 3 gt OUT8 Select LVDS CMOS Select LVDS or CMOS logic levels lt 3 gt 0 LVDS lt 3 gt 1 CMOS 142 lt 2 1 gt OUT8 LVDS Output Current Set output current level in LVDS mode This has no effect in CMOS mode 2 1 Current mA Recommended Termination Q 0 0 1 75 100 0 1 3 5 100 1 0 5 25 50 1 1 7 50 Rev 0 Page 73 of 84 AD9516 1 Reg Addr Hex Bit s Name Description 142 lt 0 gt OUT8 Power Down Power down output LVDS CMOS 0 0 power on 0 1 power off 143 lt 7 5 gt OUT9 Output Polarity In CMOS mode 7 5 select the output polarity of each CMOS output In LVDS mode only 5 determines LVDS polarity 7 6 5 OUT9A CMOS OUT9B CMOS OUT9 LVDS 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 143 4 OUT9 CMOS B In CMOS mode turn on off the CMOS B output There is no effect in LVDS mo
105. ngle ended CMOS compatible inputs Input Frequency AC Coupled 20 250 MHz Slew rate gt 50 V us Input Frequency DC Coupled 0 250 MHz Slew rate gt 50 V us CMOS levels Input Sensitivity AC Coupled 0 8 V p p Should not exceed Vs p p Input Logic High 2 0 V Input Logic Low 0 8 V Input Current 100 100 HA Input Capacitance 2 pF Each pin REFIN REFIN REF1 REF2 Rev 0 Page 4 of 84 AD9516 1 Parameter Min Typ Max Unit Test Conditions Comments PHASE FREQUENCY DETECTOR PFD PFD Input Frequency 100 MHz Antibacklash pulse width 1 3 ns 2 9 ns 45 MHz Antibacklash pulse width 6 0 ns Antibacklash Pulse Width 1 3 ns 0 17 lt 1 0 gt 01b 2 9 ns 0x17 lt 1 0 gt 00b 0x17 lt 1 0 gt 11b 6 0 ns 0x17 lt 1 0 gt 10b CHARGE PUMP CP Sink Source Programmable High Value 48 mA With CPrser 5 1 Low Value 0 60 mA Absolute Accuracy 2 5 CPv 2 CPrset Range 2 7 10 Ice High Impedance Mode Leakage 1 nA Sink and Source Current Matching 2 0 5 lt lt 0 5 V vs CPv 1 5 0 5 lt lt 0 5 V vs Temperature 2 CPv 2 V PRESCALER PART OF N DIVIDER Prescaler Input Frequency P 1FD 300 MHz P 2FD 600 MHz P 3FD 900 MHz P 2 DM 2 3 600 MHz P 4DM 4 5 1000 MHz P 8 DM 8 9 2400 MHz P 16 DM 16 17 3000 MHz P 32 DM 32 33 i 3000 2 Prescaler Output Frequency 300 MHz A B counter input frequency prescaler input
106. ns 0x17 lt 1 0 gt 10b 0x18 lt 4 gt Ob To Unlock After Lock Hysteresis Low Range ABP 1 3 ns 2 9 ns 7 ns 0x17 lt 1 0 gt 00b 01b 11b 0x18 lt 4 gt 1b High Range ABP 1 3 ns 2 9 ns 15 ns 0x17 lt 1 0 gt 00b 01b 11b 0x18 lt 4 gt Ob High Range ABP 6 ns 11 ns 0x17 lt 1 0 gt 10b 0x18 lt 4 gt 0b 1 REFIN and REFIN self bias points are offset slightly to avoid chatter on an open input condition For reliable operation of the digital lock detect the period of the PFD frequency must be greater than the unlock after lock time CLOCK INPUTS Table 3 Parameter Min Typ Max Unit Test Conditions Comments CLOCK INPUTS CLK CLK Differential input Input Frequency 0 2 4 GHz High frequency distribution VCO divider 0 1 6 GHz Distribution only VCO divider bypassed Input Sensitivity Differential 150 mV p p Measured at 2 4 GHz Jitter performance is improved with slew rates gt 1 V ns Input Level Differential 2 Vp p Larger voltage swings may turn on the protection diodes and can degrade jitter performance Input Common Mode Voltage Vem 1 3 TM KS j v Self biased enables ac coupling Input Common Mode Range 18 18 With 200 mv signal D dc coupled Input Sensitivity Single Ended 150 mVp p CLKac coupl d CLK ac bypassed to RF ground Input Resistance 3 9 4 7 5 7 kQ Self biased Input Capacitance 2 pF 1 Below about 1 MHz the input should be dc coupled Care should
107. o the PFD is a function of the antibacklash pulse setting as specified in the Phase Frequency Detector section of Table 2 Rev 0 Page 33 of 84 AD9516 1 Charge Pump CP The charge pump is controlled by the PFD The PFD monitors the phase and frequency relationship between its two inputs and tells the CP to pump up or pump down to charge or discharge the integrating node part of the loop filter The integrated and filtered CP current is transformed into a voltage that drives the tuning node of the internal VCO through the LF pin or the tuning pin of an external VCO to move the VCO frequency up or down The CP can be set 0x10 lt 6 4 gt for high impedance allows holdover operation for normal operation attempts to lock the PLL loop pump up or pump down test modes The CP current is programmable in eight steps from nominally 600 uA to 4 8 mA The exact value of the CP current LSB is set by the RSET resistor which is nominally 5 1 On Chip VCO The AD9516 includes an on chip VCO covering the frequency range shown in Table 2 Achieving low VCO phase noise was a priority in the design of the VCO To tune over the wide range of frequencies covered by this VCO ranges are used This is largely transparent to the user but is the reason that the VCO must be calibrated when the PLL loop is first set up The calibration procedure ensures that the VCO is operating within the correct band range for the frequency that
108. oldover with e Automatic reference switchover prefer REF1 e Digital lock detect five PFD cycles high range window e Automatic holdover using the LD pin comparator The following registers are set in addition to the normal PLL registers 0x18 lt 6 5 gt 00b lock detect counter five cycles 0x18 lt 4 gt 0b lock detect window high range 0 18 lt 3 gt 0b normal operation 0 1 lt 5 0 gt 000100b current source lock detect mode 0 1 lt 4 gt Ib automatic reference switchover enabled 0x1C lt 3 gt 05 prefer REF1 0 1 lt 2 1 gt 11b enable REF1 and REF2 input buffers e 0x1D lt 3 gt 1b enable LD pin comparator 0x1D lt 2 gt 1b enable the holdover function e Ox1D 1 0b use internal automatic holdover mode 0 10 lt 0 gt 1b enable the holdover function Frequency Status Monitors The AD9516 contains three frequency status monitors that are t6 the PLL T or references in the case of staglesended have fallen below a threshold frequency A diagram showing their location in the PLL is shown in Figure 52 The PLL reference monitors have two threshold frequencies normal and extended see Table 16 The reference frequency monitor thresholds are selected in Ox1F Rev 0 Page 39 of 84 AD9516 1 REF_SEL O REFERENCE SWITCHOVER RSET O REFIN REF1 9 REFIN REF2 1 LOW DROPOUT B
109. outed direct to output the duty cycle of the output is the same as the CLK input Rev 0 Page 43 of 84 AD9516 1 Phase Offset or Coarse Time Delay 0 1 and 2 Each channel divider allows for a phase offset or a coarse time delay to be programmed by setting register bits see Table 38 These settings determine the number of cycles successive rising edges of the channel divider input frequency by which to offset or delay the rising edge of the output of the divider This delay is with respect to a nondelayed output that is with a phase offset of zero The amount of the delay is set by 5 bits loaded into the phase offset PO register plus the start high SH bit for each channel divider When the start high bit is set the delay is also affected by the number of low cycles M programmed for the divider It is necessary to use the SYNC function to make phase offsets effective See the Synchronizing the Outputs SYNC Function section Table 38 Setting Phase Offset and Division for Divider 0 Divider 1 and Divider 2 Start Phase Low Cycles High Cycles Divider High SH Offset PO M N 0 0x191 4 0x191 lt 3 0 gt 0x190 lt 7 4 gt 0x190 lt 3 0 gt 1 0x194 lt 4 gt 0x194 lt 3 0 gt 0x193 lt 7 4 gt 0x193 lt 3 0 gt 2 0x197 lt 4 gt 0x197 lt 3 0 gt 0x196 lt 7 4 gt 0x196 lt 3 0 gt Let delay in seconds A delay in cycles of clock signal atinput to Dx Tx pe
110. p to 2 4 GHz Rev 0 Page 37 of 84 AD9516 1 Holdover The AD9516 PLL has a holdover function Holdover is implemented by putting the charge pump into a high impedance state This is useful when the PLL reference clock is lost Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock Without this function the charge pump is placed into a constant pump up or pump down state resulting in a massive VCO frequency shift Because the charge pump is placed in a high impedance state any leakage that occurs at the charge pump output or the VCO tuning node causes a drift of the VCO frequency This can be mitigated by using a loop filter that contains a large capacitive component because this drift is limited by the current leakage induced slew rate of the VCO control voltage Both a manual holdover using the SYNC pin and an automatic holdover mode are provided To use either function the holdover function must be enabled 0x1D lt 0 gt and 0x1D lt 2 gt Note that the VCO cannot be calibrated with the holdover enabled because the holdover resets the N divider during calibration which prevents proper calibration Disable holdover before issuing a VCO calibration Manual Holdover Mode manual holdover mode can be enabled that allows theuserto place the charge pump into high impedance state when the SYNC pin is asserted low This operations sen
111. ption 140 lt 7 5 gt OUT6 Output Polarity In CMOS mode lt 7 5 gt select the output polarity of each CMOS output In LVDS mode only lt 5 gt determines LVDS polarity lt 7 gt 6 lt 5 gt OUT6A CMOS OUT6B CMOS OUT6 LVDS 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting 1 0 Inverting Inverting Noninverting 1 1 Inverting Noninverting Noninverting 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 140 lt 4 gt OUT6 CMOS B In CMOS mode turn on off the CMOS B output There is no effect in LVDS mode 4 0 turn off the CMOS B output lt 4 gt 1 turn on the CMOS B output 140 lt 3 gt 00 6 Select LVDS CMOS Select LVDS or CMOS logic levels lt 3 gt 0 LVDS lt 3 gt 1 CMOS 140 lt 2 1 gt 6 LVDS Output Current Set output current level in LVDS mode This has no effect in CMOS mode 2 1 Current mA Recommended Termination Q 0 0 1 75 100 0 1 3 5 100 1 0 5 25 50 1 1 7 50 Rev 0 Page 72 of 84 AD9516 1 Reg Addr Hex Bit s Name Description 140 lt 0 gt OUT6 Power Down Power down output LVDS CMOS 0 0 power 0 1 power off 141 7 5 2 OUT7 Output Polarity In CMOS mode 7 5 select the output polarity of each CMOS output In LVDS mode only 5 determines LVDS pola
112. re the holdover function puts the charge pump into a high impedance state to maintain the VCO frequency as close as possible to the original frequency before the reference clock disappeared A flow chart of the internal automatic holdover function operation is shown in Figure 51 PLL ENABLED LOOP OUT OF LOCK DIGITAL LOCK DETECT SIGNAL GOES LOW WHEN THE LOOP LEAVES LOCK AS DETERMINED BY THE PHASE DIFFERENCE AT THE INPUT OF THE PFD YES ANALOG LOCK DETECT PIN INDICATES LOCK WAS PREVIOUSLY ACHIEVED 0x1D lt 3 gt 1 USE LD PIN VOLTAGE WITH HOLDOVER 0x1D lt 3 gt 0 IGNORE LD PIN VOLTAGE TREAT LD PIN AS ALWAYS HIGH WAS LD PIN HIGH WHEN DLD WENT Low YES HIGH IMPEDANCE CHARGE PUMP PLL COUNTERS CONTINUE OPERATIN k IORMALLY CHARGE PUMP IS MADE a HIGH IMPEDANCE CHARGE PUMP REMAINS HIGH IMPEDANCE UNTIL THE REFERENCE HAS RETURNED REFERENCE EDGE AT PFD YES YES RELEASE CHARGE PUMP HIGH IMPEDANCE TAKE CHARGE PUMP OUT OF HIGH IMPEDANCE PLL CAN NOW RESETTLE WAIT FOR DLD TO GO HIGH THIS TAKES 5 TO 255 CYCLES PROGRAMMING OF THE DLD DELAY COUNTER WITH THE REFERENCE AND FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT THE PFD THIS ENSURES THAT THE HOLDOVER FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK BEFORE THE HOLDOVER FUNCTION CAN BE RETRIGGERED 06420 069 Figure 51 Flow Chart of Au
113. reference clock Divider 2 1 VCOCalibration Clock Divider 0 0 2 0 1 4 1 0 8 1 1 16 default 18 lt 0 gt VCO Cal Bit used to initiate the VCO calibration This bit must be toggled from 0 to 1 in the active registers The sequence Now to initiate a calibration is program to a 0 followed by an update bit Register 0x232 lt 0 gt then programmed to 1 followed by another update bit Register 0x232 0 This sequence gives complete control over when the VCO calibration occurs relative to the programming of other registers that can impact the calibration Rev 0 Page 63 of 84 AD9516 1 Reg Addr Hex Bit s Name Description 19 lt 7 6 gt R A lt 7 gt lt 6 gt Action Counters 0 0 Do nothing on SYNC default SYNCPin 0 1 Asynchronous reset Reset 1 0 Synchronous reset 1 1 Do nothing on SYNC 19 lt 5 3 gt R Path Delay lt 5 3 gt R Path Delay see Table 2 19 2 0 N Path Delay 2 0 N Path Delay see Table 2 1A 6 Reference Sets the reference REF1 REF2 frequency monitor s detection threshold frequency This does not affect Frequency the VCO frequency monitor s detection threshold see Table 16 REF1 REF2 and VCO Frequency Status Monitor Monitor 6 0 frequency valid if frequency is above the higher frequency threshold Threshold 6 1 frequency valid if frequency is above the lower frequency threshold 5 0 LD Pin Select the signal whi
114. riod of the clock signal mput of the divider Dx in seconds 16 x SH lt 4 gt 8 x PO lt 3 gt 4 x PO lt 2 gt 2 x lt 1 gt 1 x lt 0 gt The channel divide by is set as N high cycles and M low cycles Case 1 For lt 15 At ox Tx Ac Ai Tx Case 2 For gt 16 16 M 1 x Tx Ac By giving each divider a different phase offset output to output delays can be set in increments of the channel divider input clock cycle Figure 53 shows the results of setting such a coarse offset between outputs 123 4 5 6 7 8 9 10 11 12 13 14 15 CHANNEL DIVIDER INPUT gt CHANNEL DIVIDER OUTPUTS DIV 4 DUTY 50 SH 0 DIVIDER 0 PO 0 SH 0 DIVIDER 1 PO 1 DIVIDER 2 gt 1x Tx 2 Tx Figure 53 Effect of Coarse Phase Offset or Delay Channel Dividers LVDS CMOS Outputs Channel Divider 3 and Channel Divider 4 each drive a pair of LVDS outputs giving a total of four LVDS outputs OUT6 to OUT9 Alternatively each of these LVDS differential outputs can be configured individually as a pair A and B of CMOS single ended outputs providing for up to eight CMOS outputs By default the B output of each pair is off but can be turned on as desired 06420 071 Channel Divider 3 and Channel Divider 4 each consist of two cascaded 1 to 32 frequency dividers The channel frequency division is Dx x Dx or up to 1024 Both of
115. rity 7 6 5 OUT7A CMOS OUT7B CMOS OUT7 LVDS 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 141 4 OUT7 CMOS B In CMOS mode turn on off the CMOS B output There is no effect in LVDS mode 4 0 turn off the CMOS output 4 1 turn on the CMOS B output 141 lt 3 gt 7 Select LVDS CMOS Select LVDS or CMOS logic levels lt 3 gt 0 LVDS lt 3 gt 1 CMOS 141 2 1 OUT7 LVDS Output Current Set output current level in LVDS mode This has no effect in CMOS mode 2 1 Current mA Recommended Termination 0 7 1 75 100 4 1 17 7M Ji Es 100 1 0 5 25 50 1 1 7 50 141 lt 0 gt OUT7 Power Down Power down output LVDS CMOS lt 0 gt 0 power on lt 0 gt 1 power off 142 lt 7 5 gt OUT8 Output Polarity In CMOS mode lt 7 5 gt select the output polarity of each CMOS output In LVDS mode only lt 5 gt determines LVDS polarity lt 7 gt lt 6 gt lt 5 gt OUT8A CMOS OUT8B CMOS OUT8 LVDS 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 1 Inverting Noninverting Inverting 0 1 1 Inverti
116. ruction short lt 4 gt 1 16 bit instruction long 00 lt 3 0 gt Mirror lt 7 4 gt Bits lt 3 0 gt should always mirror lt 7 4 gt so that it does not matter whether the part is in MSB or LSB first mode see Register 0x00 lt 6 gt User should set bits as follows lt 0 gt lt 7 gt lt 1 gt lt 6 gt lt 2 gt lt 5 gt 53 5 a 04 0 Read yn pan w Registers_ Select register bank used fora readback L lt 0 gt 0 read back buffer registers lt 0 gt 1 read back active registers Rev 0 Page 60 of 84 Table 53 PLL AD9516 1 Reg Addr Hex Bit s Description 10 lt 7 gt PFD Polarity Sets the PFD polarity Negative polarity is for use if needed with external VCO VCXO only The on chip VCO requires positive polarity lt 7 gt 0 7 0 positive higher control voltage produces higher frequency 7 1 negative higher control voltage produces lower frequency 10 6 4 Current Charge pump current with CPRSET 5 1 6 5 4 Ice mA 0 0 0 0 6 0 0 1 1 2 0 1 0 1 8 0 1 1 24 1 0 0 3 0 1 0 1 3 6 1 1 0 42 1 1 1 4 8 10 3 2 Mode Charge pump operating mode 3 2 Charge Pump Mode 0 0 High impedance state 0 1 Force source current pump up 1 0 Force sink current pump down 1 1 Normal operation 10 1 0 Power operating mode Down lt 1 gt x0 a Mode ST
117. signal at the analog to digital output Clock integrity requirements scale with the analog input frequency and resolution with higher analog input frequency applications at gt 14 bit resolution being the most stringent The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored the available SNR can be expressed approximately by 1 SNR dB 20 oe 5 where fais the highest analog frequency being digitized t is the rms jitter on the sampling clock Figure 68 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits ENOB SNR dB ENOB fa MHz 06420 044 Figure 68 SNR and ENOB vs Analog Input Frequency See the AN 756 application note and the AN 501 application note Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB Distributing a single ended clock on a noisy PCB can result in coupled noise on the sample clock Differential distribution has inherent common mode rejection that can provide superior clock performance in a noisy environment The AD9516 features both LVPECL and LVDS outputs that provide differential clock outputs which enable clock solutions that maximize con
118. sitivertiot level sensitive The charge pump enters a high impedance state immediately To take the charge pump out of a high impedance state take the SYNC pin high The charge pump then leaves high impedance state synchronously with the next PFD rising edge from the reference clock This prevents extraneous charge pump events from occurring during the time between SYNC going high and the next PFD event This also means the charge pump stays in high impedance state as long as there is no reference clock present The B counter in the N divider is reset synchronously with the charge pump leaving high impedance state on the reference path PFD event This helps align the edges out of the R and N dividers for faster settling of the PLL Because the prescaler is not reset this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out When using this mode the channel dividers should be set to ignore the SYNC pin at least after an initial SYNC event If the dividers are not set to ignore the SYNC pin any time SYNC is taken low to put the part into holdover the distribution outputs turn off Automatic Internal Holdover Mode When enabled this function automatically puts the charge pump into a high impedance state when the loop loses lock The assumption is that the only reason the loop loses lock is due to the PLL losing the reference clock therefo
119. sters are set When the differential mode is selected the single ended inputs are powered down In differential mode the reference input pins are internally self biased so that they can be ac coupled via capacitors It is possible to dc couple to these inputs If the differential REFIN is driven by a single ended signal the unused side REFIN should be decoupled via a suitable capacitor to a quiet ground Figure 47 shows the equivalent circuit of REFIN Rev 0 Page 34 of 84 Vs 85 85 06420 066 Figure 47 REFIN Equivalent Circuit Reference Switchover The AD9516 supports dual single ended CMOS inputs as well as a single differential reference input In the duaksingle lt ended reference mode the AD9516 Pur automatieand manual PLL reference clock switching between REF1 om Pin REFIN and REF2 on Pin REFIN This feature supports networking and other applications that require redundant references When using reference switchover the single ended reference inputs should be dc coupled CMOS levels and never allowed to go to high impedance If these inputs are allowed to go high impedance noise may cause the buffer to chatter causing a false detection of the presence of a reference There are several configurable modes of reference switchover The switchover can be performed manually or automatically The manual switchover is done either through a register setting 0x1D or by using the REF SEL pin The automatic
120. switchover occurs when disappears There is also a switchover deglitch feature which ensures that the PLL does not receive rising edges that are far out of alignment with the newly selected reference There are two reference automatic switchover modes 0x1C Prefer Switch from to REF2 when disappears Return from REF2 when returns Stay on REF2 Automatically switch to REF2 if REF1 disappears but do not switch back to REF1 if it reappears The reference can be set back to REF1 manually at an appropriate time AD9516 1 In automatic mode REF1 is monitored by REF2 If REF1 disappears two consecutive falling edges of REF2 without an edge transition on REF1 REFI is considered missing Upon the next subsequent rising edge of REF2 REF2 is used as the reference clock to the PLL If 0x1C lt 3 gt 0b default when returns four rising edges of without two falling edges of REF2 between the REF1 edges the PLL reference switchs back to REF1 If 0x1C lt 3 gt 1b the user has control over when to switch back to REF1 This is done by programming the part to manual reference select mode 0x1C lt 4 gt 0b and by ensuring that the registers and or REF SEL pin are set to select the desired reference Auto mode can be re enabled once is reselected Manual switchover requires the presence of a clock on the reference input that is being switched to or
121. t In unidirectional mode the readback data appears on the SDO pin A readback request reads the data that is in the serial control port buffer area or the data in the active registers see Figure 61 Readback of the buffer or active registers is controlled 0x04 lt 0 gt The AD9516 supports only the long instruction mode therefore 0x00 lt 4 3 gt must be set to 11b this register uses mirrored bits Long instruction mode is the default at power up or reset The AD9516 uses Register Address 0x000 to Register Address 0x232 SCLK SDIO SDO CS UPDATE SERIAL REGISTERS CONTROL PORT BUFFER REGISTERS ACTIVE REGISTERS WRITE REGISTER 0x232 0x01 TO UDATE REGISTERS 06420 037 Figure 61 Relationship Between Serial Control Port Buffer Registers and Active Registers of the AD9516 THE INSTRUCTION WORD 16 BITS The MSB of the instruction word is R W which indicates whether the instruction is a read or a write The next two bits W1 W0 indicate the length of the transfer in bytes The final 13 bits are the address A12 A0 at which to begin the read or write operation For a write the instruction word is followed by the number of bytes of data indicated by Bits W1 WO see Table 47 Table 47 Byte Transfer Count W1 wo Bytes to Transfer O Streaming mode AD9516 1 A12 A0 These 13 bits select the address within the register map that is written to or read from during the
122. t 7 gt as a separate output pin for reading back data CS chip select bar is an active low control that gates the read and write cycles When CS is high SDO and SDIO are in a high impedance state This pin is internally pulled up by a 30 resistor to VS 7 AD9516 1 SERIAL 1 CONTROL PORT 06420 036 Figure 60 Serial Control Port GENERAL OPERATION OF SERIAL CONTROL PORT A write or a read operation to the AD9516 is initiated by pulling CS low CS stall high is supported in modes where three or fewer bytes of data plus instruction data are transferred see Table 47 In these modes CS can temporarily return high on any byte boundary allowing time for the system controller to process the next byte CS can go high on byte boundaries only and can go high during either part instruction or data of the transfer During this period the serial control port state machine enters a wait state until all data is sent If the system controller decides to abort the transfer before all of the data is sent the state machine must be reset by either completing the remaining transfers or by returning the CS low for at least one complete SCLK cycle but less than eight SCLK cycles Raising the CS on a nonbyte boundary terminates the serial transfer and flushes the buffer In the streaming mode see Table 47 any number of data bytes can be transferred in a continuous stream The register address is automatically incre
123. ted or the external VCO VCXO is less than 1600 MHz a configuration that bypasses the VCO divider can be used This only differs from the High Frequency Clock Distribution CLK or External VCO gt 1600 MHz section in that the VCO divider divide by 2 divide by 3 divide by 4 divide by 5 and divide by 6 is bypassed This limits the frequency of the clock source to lt 1600 MHz due to the maximum input frequency allowed at the channel dividers Configuration and Register Settings For clock distribution applications where the external clock is lt 1600 MHz the register settings shown in Table 25 should be used Table 25 Settings for Clock Distribution lt 1600 MHz AD9516 1 Table 26 Settings for Using Internal PLL with External VCO lt 1600 MHz Register Function 0 1 1 lt 0 gt 1b Bypass the VCO divider as source for distribution section 0x10 lt 1 0 gt 00b PLL normal operation PLL on along with other appropriate PLL settings in 0x10 to Ox1E An external VCO VCXO requires an external loop filter that must be connected between CP and the tuning pin of the VCO VCXO This loop filter determines the loop bandwidth and stability of the PLL Make sure to select the proper PFD polarity for the VCO VCXO being used Table 27 Setting the PFD Polarity Register Function Register Function 0 10 lt 1 0 gt 01b PLL asynchronous power down PLL off 0 1 1 lt 0 gt 1b Bypass the VCO divider as so
124. that the deglitching feature be disabled 0x1C lt 7 gt Reference Divider R The reference inputs are routed to the reference divider R R a 14 bit counter can be set to any value from 0 to 16383 by writing to 0x11 and 0x12 Both R 0 and R 1 give divide by 1 The output of the R divider goes to one of the PFD inputs to be compared to the VCO frequency divided by the N divider The frequency applied to the PFD must not exceed the maximum allowable frequency which depends on the antibacklash pulse setting see Tabl 2 The R co htet has its own 4 R counter can be reset using the shared reset bit of the R A and B counters It may also be reset by a SYNC operation VCXO VCO Feedback Divider N P A B R The N divider is a combination of a prescaler P and two counters A and B The total divider value is N Px B where the value of P can be 2 4 8 16 or 32 Prescaler The prescaler of the AD9516 allows for two modes of operation a fixed divide FD mode of 1 2 or 3 and dual modulus DM mode where the prescaler divides by P and P 1 2 and 3 4 and 5 8 and 9 16 and 17 or 32 and 33 The prescaler modes of operation are given in Table 53 0x16 lt 2 0 gt Not all modes are available at all frequencies see Table 2 When operating the AD9516 in dual modulus mode P P 1 the equation used to relate input reference frequency to VCO output frequency is fvco frer R x P x B A frer x N R
125. the dividers also have DCC enabled by default but this function can be disabled if desired by setting the DCCOFF bit of the channel A coarse phase offset or delay is alsospregrammable see the Phase Offset or Coarse Time Delay Divider 3 np Does 4 section The Channekdividers operate up 18 600 MHz The features and settings of the dividers are selected by programming the appropriate setup and control registers see Table 51 and Table 52 through Table 61 Table 39 Setting Division Dx for Divider 3 Divider 4 Divider M N Bypass DCCOFF 3 3 1 0x199 lt 7 4 gt 0x199 lt 3 0 gt 0x19C lt 4 gt 0 190 lt 0 gt 3 2 0x19B lt 7 4 gt 0x19B lt 3 0 gt Ox19C 5 0 190 lt 0 gt 4 41 0 19 lt 7 4 gt 0 19 lt 3 0 gt 0x1A1 lt 4 gt Ox1A2 0 4 2 0 1 0 lt 7 4 gt 0x1A0 lt 3 0 gt Ox1A1 lt 5 gt 0x1A2 lt 0 gt Channel Frequency Division Divider 3 and Divider 4 The division for each channel divider is set by the bits in the registers for the individual dividers X Y 3 1 3 2 4 1 and 4 2 Number of Low Cycles Mxy 1 Number of High Cycles Nxy 1 When both X 1 and 2 are bypassed Dx 1x 1 1 When only 2 is bypassed Dx Nx 2 x 1 When both X 1 and X2 are not bypassed Dx 2 x Nx2 Mx 2 Rev 0 Page 44 of 84 By cascading the dividers channel division up to 1024 can be obtained However not all integer v
126. tion CMOS Outputs at 206 MHz 1 6 2 2 w PLL on internal VCO 2476 MHz VCO divider 2 all channel dividers on six LVPECL outputs 619 MHz eight CMOS outputs 10 pF load 206 MHz all fine delay on maximum current does not include power dissipated in external resistors Full Operation LVDS Outputs at 206 MHz 1 6 2 3 w PLL on internal VCO 2476 MHz VCO divider 2 all channel dividers on six LVPECL outputs 619 MHz four LVDS outputs 206 MHz all fine delay on maximum current does not include power dissipated in external resistors PD Power Down 75 185 mW PD pin pulled low does not include power dissipated in terminations PD Power Down Maximum Sleep 31 mW PD pin pulled low PLL power down 0x10 lt 1 0 gt 01b SYNC power down 0x230 lt 2 gt 1b REF for distribution power down 0 230 lt 1 gt 1b Supply 1 5 mW PLL operating typical closed loop configuration POWER DELTAS INDIVIDUAL FUNCTIONS Power delta when a function is enabled disabled VCO Divider 30 mW VCO divider not used REFIN Differential 20 mW All references off to differential reference enabled REF1 REF2 Single Ended 4 mW All references off to REF1 or enabled differential eT reference not egabled VCO 70 mW CLK input selected to VCO PLL 75 mW PLL off to normal operation no reference enabled Channel Divider 30 mW Divider bypassed to divide by 2 to 32 LVPECL Channel Divider Plus Output Driver 160 mW NoLVPECL o
127. tomatic Internal Holdover Mode The holdover function senses the logic level of the LD pin as a condition to enter holdover The signal at LD can be from the DLD ALD or current source LD mode It is possible to disable the LD comparator 0x1D lt 3 gt which causes the holdover function to always sense LD as high If DLD is used it is possible for the DLD signal to chatter some while the PLL is re acquiring lock The holdover function may retrigger thereby preventing the holdover mode from ever terminating Use of the current source lock detect mode is recommended to avoid this situation see the Current Source Digital Lock Detect section Rev 0 Page 38 of 84 Once in holdover mode the charge pump stays in a high impedance state as long as there is no reference clock present As in the external holdover mode the B counter in the N divider is reset synchronously with the charge pump leaving high impedance state on the reference path PFD event This helps align the edges out of the R and N dividers for faster settling of the PLL and to reduce frequency errors during settling Because the prescaler is not reset this feature works best when the B and R numbers are close as this results in a smaller phase difference for the loop to settle out After leaving holdover the loop then re acquires lock and the LD pin must charge if 0x1D lt 3 gt 1 before it can re enter holdover CP high impedance The holdover function always respo
128. tos Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK tak Period of the clock ts Setup time between CS falling edge and SCLK rising edge start of communication cycle tc Setup time between SCLK rising edge and CS rising edge end of communication cycle tui Minimum period that SCLK should be in a Logic High state tio Minimum period that SCLK should be in a Logic Low state tov SCLK to valid SDIG ang SDO 65 Rev 0 Page 55 of 84 AD9516 1 REGISTER MAP OVERVIEW Table 51 Register Map Overview Default Addr Bit 7 Value Hex Parameter MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB Hex Serial Port Configuration 00 Serial Port 500 LSB First Soft Reset Long Long Soft Reset LSB First SDO Active 18 Configuration Active Instruction Instruction 01 Blank 02 to Reserved 03 04 Read Back Blank Read Back 00 Control Active Registers PLL 10 PFD and PFD Charge Pump Current Charge Pump Mode PLL Power Down 7D Charge Pump Polarity 11 R Counter 14 Bit R Divider Bits lt 7 0 gt LSB 01 12 Blank 14 Bit R Divider Bits lt 3 8 gt MSB 00 13 A Counter Blank 6 Bit A Counter 00 14 B Counter 13 Bit B Counter Bits lt 7 0 gt LSB 03 15 Blank 13 Bit B Counter Bits lt 12 8 gt
129. tput forced to low lt 5 gt 1 divider output forced to high 197 lt 4 gt Divider 2 Start High Selects clock output to start high or start low 4 0 start low 4 1 start high 197 3 0 Divider 2 Phase Offset Phase offset Rev 0 Page 75 of 84 AD9516 1 Reg Addr Hex Bit s Name Description 198 lt 1 gt Divider 2 Direct to Output Connect OUT4 and OUTS to Divider 2 or directly to VCO CLK 1 0 OUT4 and OUTS are connected to Divider 2 lt 1 gt 1 If Ox1E1 lt 1 0 gt 10b the VCO is routed directly to OUT4 and OUTS If OX1E1 lt 1 0 gt 006 the CLK is routed directly to OUT4 and OUTS If Ox1E1 lt 1 0 gt 01b there is no effect 198 lt 0 gt Divider 2 DCCOFF Duty cycle correction function 0 0 enable duty cycle correction lt 0 gt 1 disable duty cycle correction Table 58 LVDS CMOS Channel Dividers Reg Addr Hex Bit s Name Description 199 7 4 Low Cycles Divider 3 1 Number of clock cycles of 3 1 divider input during which 3 1 output stays low 199 lt 3 0 gt High Cycles Divider 3 1 Number of clock cycles of 3 1 divider input during which 3 1 output stays high 19 lt 7 4 gt Phase Offset Divider 3 2 Refer to LVDSCMOS channel divider function description 19A lt 3 0 gt Phase Offset Divider 3 1 Refer to LVDSCMOS channel divider function d
130. tput stays high 19F 7 4 Phase Offset Divider 4 2 Refer to LVDSCMOS channel divider function description 19F lt 3 0 gt Phase Offset Divider 4 1 Refer to LVDSCMOS channel divider function description 1A0 lt 7 4 gt Low Cycles Divider 4 2 Number of clock cycles of 4 2 divider input during which 4 2 output stays low 1A0 lt 3 0 gt High Cycles Divider 4 2 Number of clock cycles of 4 2 divider input during which 4 2 output stays high Rev 0 Page 76 of 84 AD9516 1 Reg Addr Hex Bit s Name Description 1A1 lt 5 gt Bypass Divider 4 2 Bypass and power down 4 2 divider logic route clock to 4 2 output 5 0 do not bypass 5 1 bypass 1A1 4 Bypass Divider 4 1 Bypass and power down 4 1 divider logic route clock to 4 1 output 4 0 do not bypass 4 1 bypass 1A1 3 Divider 4 Nosync Nosync 3 0 obey chip level SYNC signal 3 1 ignore chip level SYNC signal 1A1 2 Divider 4 Force High Force Divider 4 output high Requires that nosync also be set 2 0 force low 2 1 force high lt 1 gt Start High Divider 4 2 Divider 4 2 start high low lt 1 gt 0 start low lt 1 gt 1 start high 1A1 lt 0 gt Start High Divider 4 1 Divider 4 1 start high low lt 0 gt 0 tart low lt 0 gt 1 start high 1A2 lt 0 gt Divider 4 DCCOFF Duty cycle correction function 0 0 enable duty cycle correction
131. urce for distribution section CLK selected as the source 0x1E1 lt 1 gt 0b 0 10 lt 7 gt 0 PFD polarity positive higher control voltage produces higher frequency PFD polarity negative higher control voltage produces lower frequency 0 10 lt 7 gt 1 When using the internal PLL with an external VCO lt 1600 MHz the PLL must be turned on UM NAL Rev 0 Page 31 of 84 AD9516 1 REF_SEL vs GND RSET REFMON CPRSET VCP O O DISTRIBUTION REFERENCE REFERENCE SWITCHOVER PLL REFERENCE zm LD LOCK DETECT R PROGRAMMABLE DIVIDER R DELAY REFIN REF1 O REFIN REF2 neg VCO STATUS ieee g Pehle s a PHASE BYPASS OH REGULATOR LDC P P 4 PROGRAMMABLE FREQUENCY CHARGE REGULATOR LDO PRESCALER COUNTERS N DELAY DETECTOR RUME N DIVIDER DIVIDE BY STATUS 2 3 4 5 OR 6 DIVIDE BY O OUTO 11032 LVPECL DIVIDE BY OUT2 11032 LVPECL SERIAL 2 OUT3 CONTROL DIVIDE BY O OUT4 1 32 gt OUT6 OUT6A AT Hed LAT s OUT6 OUT6B DIVIDE BY DIVIDE BY 4 32 1 32 gt OUT7 OUT7A qua OUT OUT7B gt OUTS OUT8A gt gt OUTS OUT8B DIVIDE BY DIVIDE BY 1 32 1 32 09516 1 gt Q OUT9 OUT9A 2 OUT9 OUT9B Figure 44 Clock Distribution or External VCO 1600 MHz Rev 0 Page 32 of 84 06420 028 Phase Locked Loop PLL REF_SEL vs
132. utput on to one LVPECL output on LVPECL Driver 90 mW Second LVPECL output turned on same channel LVDS Channel Divider Plus Output Driver 120 mW No LVDS output on to one LVDS output on LVDS Driver 50 mW Second LVDS output turned on same channel CMOS Channel Divider Plus Output Driver 100 mW Static no CMOS output on to one CMOS output on CMOS Driver Second in Pair 0 mW Static second CMOS output same pair turned on CMOS Driver First in Second Pair 30 mW Static first output second pair turned Fine Delay Block 50 mW Delay block off to delay block enabled maximum current setting Rev 0 Page 14 of 84 AD9516 1 TIMING DIAGRAMS DIFFERENTIAL gt 06420 062 06420 060 lt Figure 2 CLK CLK to Clock Output Timing DIV 1 Figure 4 LVDS Timing Differential DIFFERENTIAL SINGLE ENDED 10pF LOAD 06420 061 06420 063 trp r trp gc trc 1 1 Figure 3 LVPEGE Im Differential Figures CMOS m Single Ended 10 pF Load k Rev 0 Page 15 of 84 AD9516 1 ABSOLUTE MAXIMUM RATINGS Table 18 With Parameter or Pin Respectto Rating VS VS LVPECL GND 0 3 V to 3 6V VCP GND 0 3 V to 45 8 V REFIN REFIN GND 0 3 V to Vs 0 3 V REFIN REFIN 33Vto433V RSET GND 0 3 V to Vs 0 3 V CPRSET GND 0 3 V to Vs 0 3 V CLK CLK GND 0 3 V to Vs 0 3 V CLK CLK 12Vto41 2V SCLK
133. verter SNR performance The input requirements of the ADC differential or single ended logic level termination should be considered when selecting the best clocking converter solution AD9516 1 LVPECL CLOCK DISTRIBUTION The LVPECL outputs of the AD9516 provide the lowest jitter clock signals available from the AD9516 The LVPECL outputs because they are open emitter require a dc termination to bias the output transistors The simplified equivalent circuit in Figure 57 shows the LVPECL output stage In most applications an LVPECL far end Thevenin termination is recommended as shown in Figure 69 The resistor network is designed to match the transmission line impedance 50 Q and the switching threshold Vs 1 3 V VS_LVPECL VS_LVPECL Vs 06420 045 Figure 69 LVPECL Far End Thevenin Termination VS_LVPECL VS_LVPECL 06420 046 Figure 70 LVPECL with Parallel Transmission Line LVDS CLOCK DISTRIBUTION The AD9516 provides four clock outputs OUT6 to OUT that are selectable as either CMOS or LVDS level outputs LVDS is a differential output option that uses a current mode output stage The nominal current is 3 5 mA which yields 350 mV output swing across 100 resistor The LVDS output meets or exceeds all ANSI TIA EIA 644 specifications A recommended termination circuit for the LVDS outputs is shown in Figure 71 vs vs r 4000 DIFFERENTIAL COUPLED 1000 1 q 06420 047
134. with respect to the clock edges inside the AD9516 The delay from the SYNC rising edge to the beginning of synchronized output clocking is between 14 and 15 cycles of clock at the channel divider input plus either one cycle of the VCO divider input see Figure 55 or one cycle of the channel divider input see Figure 56 depending on whether the VCO divider is used Cycles are counted from the rising edge of the signal Another common way to execute the SYNC function is by setting and resetting the soft sync bit at 0x230 0 see Table 52 through Table 61 for details Both setting and resetting of the soft sync bit require an update all registers 0 232 lt 0 gt 1 operation to take effect CHANNEL DIVIDER OUTPUT CLOCKING 1 1 INPUT TO VCO DIVIDER 11 1 1 SYNC PIN l OUTPUT OF CHANNEL DIVIDER 06420 073 Figure 55 SYNC Timing when VCO Divider Is Used CLK or VCO Is Input Rev 0 Page 48 of 84 CHANNEL DIVIDER OUTPUT CLOCKING i INPUT TO CLK IINPUT TO CHANNEL DIVIDER 1 2 3 4 SYNC PIN OUTPUT OF CHANNEL DIVIDER CHANNEL DIVIDER OUTPUT STATIC AD9516 1 CHANNEL DIVIDER OUTPUT CLOCKING 06420 074 Figure 56 SYNC Timing when VCO Divider Is Not Used CLK Input Only SYNC operation brings all outputs that have not been excluded by the NOSYNC bit to a preset condition before allowing the outputs to begin clocking in synchronicity The preset condition tak
135. wn 51 Register Map 60 Serial 52 Application NOtes eere Re aquqa says 79 Serial Control Port Pin Descriptions sss 52 Using the AD9516 Outputs for ADC Clock Applications 79 General Operation of Serial Control 52 LVPECL Clock Distribution see 79 Communication Cycle Instruction Plus Data 52 LVDS Clock Distribution sse 79 b 52 CMOS Clock Distribution seen 80 DC 53 Outline 81 The Instruction Word 16 53 Ordering GUI utto eR REOR 81 MSB LSB First 53 REVISION HISTORY 4 07 Revision 0 Initial Version AL Rev 0 Page 3 of 84 AD9516 1 SPECIFICATIONS Typical typ is given for Vs Vs vreci 3 3 V 5 Vs lt Vo lt 5 25 V Ta 25 4 12 CPrser 5 1 unless otherwise noted Minimum min and maximum max values are given over full Vs and 40 C to 85 C variation POWER SUPPLY REQUIREMENTS Table 1 Parameter Min Max Unit Test Conditions Comments Vs 3 135 33 3 465 V This is 3 3 V 5 Vs_LVPECL 2 375 Vs V This is nominally 2 5 V to 3 3 V 5 Vee Vs 5 25 V This is nominally 3 3 V to 5 0 V 5 RSET Pin Resistor 4 12 kQ Sets interna
136. y from damage that could be caused by certain termination and load configurations when tristated Because this is not a complete power down it can be called sleep mode When the AD9516 is in a PD power down the chip is in the following state The PLL is off asynchronous power down The VCO is off e The CLK input buffer is off e All dividers are off All LVDS CMOS outputs are off e All LVPECL outputs are in safe off mode e serial control port is active and the chip responds to commands Rev 0 Page 50 of 84 If the AD9516 clock outputs must be synchronized to each other a SYNC is required upon exiting power down see the Synchronizing the Outputs SYNC Function section A VCO calibration is not required when exiting power down PLL Power Down The PLL section of the AD9516 can be selectively powered down There are three PLL operating modes set by 0x10 lt 1 0 gt as shown in Table 53 In asynchronous power down mode the device powers down as soon as the registers are updated In synchronous power down mode the PLL power down is gated by the charge pump to prevent unwanted frequency jumps The device goes into power down on the occurrence of the next charge pump event after the registers are updated Distribution Power Down The distribution section can be powered down by writing 0x230 lt 1 gt 1b This turns off the bias to the distribution section If the LVPECL power down mode is norma
137. y the various settings that include the R divider the N divider the PFD polarity only applicable to external the antibacklash pulse width the charge pump current the selection of internal VCO or external and the loop bandwidth These are managed through programmable register settings see Table 51 and Table 53 and by the design of the external loop filter Successful operation and satisfactory PLL loop performance are highly dependant upon proper configuration of the PLL settings The design of the external loop filter is crucial to the proper operation of the PLL A thorough knowledge of PLL theory and design is helpful ADIsimCLK V1 2 or later is a free program that can help with the design and exploration of the capabilities and features of the AD9516 including the design of the PLL loop filter It is available at www analog com clocks Phase Frequency Detector PFD The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them The PFD includes a programmable delay element that controls the width of the antibacklash pulse This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs The antibacklash pulse width is set by 0x17 lt 1 0 gt An important limit to keep in mind is the maximum frequency allowed into the PFD The maximum input frequency t
138. z 100kHz DIV SPAN 1MHz 23 24 2 5 2 6 27 FREQUENCY GHz Figure 15 VCO Tuning Voltage vs Frequency Figure 18 Output Spectrum LVDS 122 88 MHz PFD 15 36 MHz LBW 55 kHz 4 8 2 46 GHz 06420 138 Rev 0 Page 20 of 84 DIFFERENTIAL OUTPUT V DIFFERENTIAL OUTPUT V DIFFERENTIAL OUTPUT V o e o 1 1 1 e gt gt o o o 1 e 0 2 1 gt gt a 15 20 TIME ns Figure 19 LVPECL Output Differential 100 MHz N a i TIME ns Figure 20 LVPECL Output Differential 1600 MHz N a o a N o N a TIME ns Figure 21 LVDS Output Differential 100 MHz DIFFERENTIAL OUTPUT V 06420 014 DIFFERENTIAL OUTPUT V 06420 015 OUTPUT V 06420 016 Rev 0 Page 21 of 84 AD9516 1 o N 1 N 0 4 Au 0 4 0 1 2 TIME ns Figure 22 LVDS Output Differential amp 800 MHz 1 8 0 2 0 20 40 60 80 100 TIME ns Figure 23 CMOS Output 25 MHz TIME ns Figure 24 CMOS Output 250 MHz 06420 017 06420 018 06420 019 AD9516 1

ANALOG DEVICES AD9516-1 handbook

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