Home

ANALOG DEVICES AD2S1210 handbook

1. 00 00 00 cO cO CO 0 CO CO CODES CODE Figure 5 Typical 14 Bit Angular Accuracy Histogram of Codes 512 Samples Figure 8 Typical 10 Bit Angular Accuracy Histogram of Codes 512 Samples Hysteresis Enabled Hysteresis Disabled Rev 0 Page 11 of 36 600 500 400 HITS PER CODE 200 100 0 8 126 127 128 129 130 5 CODES ANGLE Degrees Figure 9 Typical 10 Bit Angular Accuracy Histogram of Codes 512 Samples Hysteresis Enabled ANGLE Degrees ANGLE Degrees TIME ms Figure 10 Typical 16 Bit 10 Step Response a a o EN TIME ms Figure 11 Typical 14 Bit 10 Step Response 07467 010 07467 009 ANGLE Degrees ANGLE Degrees Rev 0 Page 12 of 36 0 0 050 1 00 1 50 2 00 2 50 300 3 50 4 00 4 50 5 00 TIME ms Figure 12 Typical 12 Bit 10 Step Response 0 0 25 0 50 0 75 1 00 1 25 1 50 1 75 2 00 2 25 2 50 TIME ms Figure 13 Typical 10 Bit 10 Step Response 250 225 0 8 16 24 32 40 48 56 64 TIME ms Figure 14 Typical 16 Bit 179 Step Response 72 80 07467 008 07467 007 07467 014 ANGLE Degrees ANGLE Degrees ANGLE Degre
2. 0x92 D7 to DO Read write Address Bit Read Write Ox8E D7 to DO Read write The LOT low threshold register determines the level of hysteresis on the loss of position tracking fault detection Loss of tracking LOT occurs when the internal error signal of the AD2S1210 exceeds the LOT high threshold LOT has hysteresis and is not cleared until the internal error signal is less than the value defined in the LOT low threshold register The LOT low threshold is a 7 bit word Note that the MSB D7 should be set to 0 The range of the LOT high threshold the LSB size and the default value of the LOT high threshold on power up are dependent on the resolu tion setting of the AD2S1210 and are outlined in Table 19 The control register is an 8 bit register that sets the AD2S1210 control modes The default value of the control register on power up is Ox7E Table 22 Control Register Bit Descriptions Bit Description D7 Address data bit D6 Reserved set to 1 D5 Phase lock range 0 360 1 44 D4 0 disable hysteresis 1 enable hysteresis D3 Set Encoder Resolution EnRES1 D2 Set Encoder Resolution EnRESO D1 Set Resolution RES1 DO Set Resolution RESO Rev 0 Page 22 of 36 Address Data Bit The MSB of each 8 bit word written to the AD2S1210 indicates whether the 8 bit word is a register address or data The MSB D7 of each register address defined on the AD2S1210 is high The MSB of each data word
3. Address Bit Read Write 0x91 D7 to DO Read write Address Read Write 0x8D D7 to DO Read write The LOT high threshold register determines the loss of position tracking threshold for the 251210 The LOT high threshold is a 7 bit word Note that the MSB D7 should be set to 0 The range of the LOT high threshold the LSB size and the default value of the LOT high threshold on power up are dependent on the resolution setting of the AD2S1210 and are outlined in Table 19 LOT LOW THRESHOLD REGISTER Table 18 8 Bit Register The excitation frequency register determines the frequency of the excitation outputs of the AD2S1210 A 7 bit frequency control word is written to the register to set the excitation frequency Note that the MSB D7 should be set to 0 Excitation Frequency x 2 FCW 9 f CLKIN where FCW is the frequency control word and fcrxiN is the clock frequency of the AD2S1210 The specified range of the excitation frequency is from 2 kHz to 20 kHz and can be set in increments of 250 Hz To ensure that the AD2S1210 is operated within the ecified frequency d the frequency control word should be a valu For example of 5 kHz hasa at needs to be 2 is given by 5 kHz x 25 W 14 hexadecimal 8 192 MHz The default excitation frequency of AD2S1210 on power up is 10 kHz CONTROL REGISTER Table 21 8 Bit Register Address Bit Read Write
4. The AD2S1210 also provides an internal synthetic reference signal that is phase locked to its sine and cosine inputs Phase errors between the resolver primary and secondary windings can degrade the accuracy of the RDC and are compensated by this synchronous reference signal This also compensates the phase shifts due to temperature and cabling and eliminates the need of an external preset phase compensation circuit SYNTHETIC REFERENCE GENERATION When a resolver undergoes a high rotation rate the RDC tends to act as an electric motor and produces speed voltages along with the ideal sine and cosine outputs These speed voltages are in quadrature to the main signal waveform Moreover nonzero resistance in the resolver windings causes a nonzero phase shift between the reference input and the sine and cosine outputs The combination of speed voltages and phase shift causes a track ing error in the RDC that is approximated by Rotation Rate Error Phase Shift x 6 Reference Frequency To compensate for the described phase error between the resolver reference excitation and the sine cosine signals an internal synthetic reference signal is generated in phase with the refer ence frequency carrier The synthetic reference is derived using the 2 filtered sine and cosine Sena It is generated synthetic reference reduces the phase shift between the refer ence and sine cosine inputs to less than 10 and operates for phase shifts of
5. Table 26 Fault Register Bit Descriptions Bit Description D7 Sine cosine inputs clipped D6 Sine cosine inputs below LOS threshold D5 Sine cosine inputs exceed DOS overrange threshold D4 Sine cosine inputs exceed DOS mismatch threshold D3 Tracking error exceeds LOT threshold D2 Velocity exceeds maximum tracking rate D1 Phase error exceeds phase lock range DO Configuration parity error Rev 0 Page 23 of 36 DIGITAL INTERFACE The angular position and angular velocity are represented by binary data and can be extracted either via a 16 bit parallel interface or via a 4 wire serial interface that operates at clock rates of up to 25 MHz The AD2S1210 programmable functions are controlled using a set of on chip registers Data is written to these registers using either the serial or the parallel interface SOE INPUT The serial output enable pin SOE is held high to enable the parallel interface The SOE pin is held low to enable the serial interface which places Pin DB0 to Pin DB12 in the high imped ance state Pin DB13 is the serial clock input SCLK Pin DB14 is the serial data input SDD Pin DB15 is the serial data output SDO and WR FSYNC is the frame synchronization input SAMPLE INPUT The AD2S1210 operates on a Type II tracking closed loop principle The loop continually tracks the position and velocity of the resolver without the need for external conversion and wait states The position and ve
6. KAAKA 4333898444 P s M RD Deg it wet me toy 14 148 1 1 POSITION VELOCITY FAULT ASSUMES FAULT REGISTER ADDRESS WRITTEN TO PART BEFORE EXITING CONFIGURATION MODE NOTES 1 YX DON T CARE 07467 029 Figure 30 Parallel Port Read Timing Rev 0 Page 26 of 36 1 gt m FoLKIN 1 1 1 1 1 pa the ma ti tg n SAMPLE 3 t _ gt XXN 1 1 gt 1 4 AO A1 m4 lt t t4 r w tuA 1 1 tt e DATA FAULT ADDRESS FAULT DATA NOTES 1 DON T CARE Figure 31 Parallel Port Clear Fault Register ww BDI com Rev 0 Page 27 of 36 07467 030 SERIAL INTERFACE The serial interface is selected by holding the SOE pin low The AD2S1210 serial interface consists of four signals SDO SDI WR FSYNC and SCLK T
7. Rev 0 Page 6 of 36 Parameter Description Limit at Tmn Tmax Unit Delay WR FSYNC rising edge SDO high Z 15 ns min tso Delay from SAMPLE before WR FSYNC falling edge 6 x tx 20 ns ns min t Delay CS falling edge to WR FSYNC falling edge in normal mode 2 ns min and A1 setup time before WR FSYNC falling edge 2 ns min t33 and A1 hold time after WR FSYNC falling edge In normal mode AO 0 A1 0 1 24 x tck 5 ns ns min In configuration mode 0 1 A1 1 8xta 5ns ns min tsa Delay WR FSYNC rising edge to WR FSYNC falling edge 10 ns min Frequency of SCLK input 4 5 V to 5 25 V 20 MHz Vorive 2 7 V to 3 6 V 25 MHz 2 3 V to 2 7 V 15 MHz Temperature ranges are as follows A B grades 40 C to 85 C C D grades 40 C to 125 C 2 A0 and A1 should remain constant for the duration of the serial readback This may require 24 clock periods to read back the 8 bit fault information in addition to the 16 bits of position velocity data If the fault information is not required A0 A1 may be released following 16 clock cycles ww BDI C com Rev 0 Page 7 of 36 ABSOLUTE MAXIMUM RATINGS Table 3 Parameter to AGND to AGND to AGND to DVop AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Analog Output Voltage Swing Input Current
8. Synthetic Reference Generation Configuration o Modes of Operational Register Mapa eet 21 Position Register 21 Velocity Register 21 REVISION HISTORY 8 08 Revision 0 Initial Version LOS Threshold Register 7 ren 21 DOS Overrange Threshold 6 15 6 21 DOS Mismatch Threshold 6 15 6 21 DOS Reset Maximum and Minimum Threshold Registers 22 LOT High Threshold Register aaa 22 LOT Low Threshold Register e 22 Excitation Frequency Register sse 22 Control Register p EE eere EP ER eet pelea 22 Software Reset Register serere 23 Fault Register ER RERO 23 Digital intetfacen aote eR 24 SOE Input ettet 24 SAMPLE Input cct 24 Format eee eene rotis 24 Parallel Interface eit teo aene erre 24 Serial Interface naia ORE etum 28 Incremental Encoder Outputs ses 31 upply Sequencing and Res Circuit Dynamics B E oop nSesffodel 9E M Eee Sources OL Error soU D REC 33 Outline Dimensions ene deneneneueneueteseneiriedm 34 Ordering Guide eme eme iie deeds 34 Rev 0 Page 2 of 36 SPECIFICATIONS DVpp 5 0 V 596 CLKIN 8 192 MHz 2596 EXC EXC frequency 10 kHz to 20 kHz 10 bit 6 KHz to 20
9. sine or cosine falling below or exceeding the LOS and DOS thresholds within two window counter periods For example with an excitation frequency of 10 kHz a fault is detected within 125 us A persistent fault is detected within one window counter period of the reading and clearing the fault register Note that the time latency to detect the occurrence ofa DOS mismatch fault is dependent on the speed of rotation of the resolver The worst case time latency to detect a DOS mismatch fault is the time required for one full rotation of the resolver Loss of Position Tracking ti g LOT has Th icat s that a A occ ER e The internal error signal of the AD2S1210 has exceeded the specified angular threshold This threshold is defined by the user and is set by writing to the internal register Address 0x8D see the Register Map section e The input signal exceeds the maximum tracking rate The maximum tracking rate depends on the resolution defined by the user and the CLKIN frequency LOT is indicated by a logic low on the LOT pin and is not latched LOT has hysteresis and is not cleared until the internal error signal is less than the value defined in the LOT low threshold register Address Ox8E see the Register Map section When the maximum tracking rate is exceeded LOT is cleared only if the velocity is less than the maximum tracking rate and the internal error signal is less than the value defined in the LOT low threshold regist
10. 0 angular error The value E 0 4 is the difference between the angular error of the rotor and the digital angle output of the converter A phase sensitive demodulator some integrators and a compensa tion filter form a closed loop system that seeks to null the error signal When this is accomplished equals the Resolver Angle 0 within the rated accuracy of the converter A Type II tracking loop is used so that constant velocity inputs can be tracked without inherent error FAULT DETECTION CIRCUIT The AD2S1210 fault detection circuit can sense loss of resolver signals out of range input signals input signal mismatch or loss of position tracking however in the event of a fault the position indicated by the AD2S1210 may differ significantly from the actual shaft position of the resolver Monitor Signal The AD2S1210 generates a monitor signal by comparing the angle in the position register to the incoming sine and cosine signals from the resolver The monitor signal is created in a similar fashion to the error signal described in the Resolver to Digital Conversion section The incoming signals 81109 and cos are multiplied by the sin and cos of the output angle respectively and then added together Monitor Al xsin 0 xsin A2 x cos 0 x cos 4 where A1 is the amplitude of the incoming sine signal A1 4215 the amplitude of the incoming cosine signal 2 x cos 015 the r
11. Excitation Frequency Analog output An on board oscillator provides the sinusoidal excitation signal EXC and its complement signal EXC to the resolver The frequency of this reference signal is programmable via the excitation frequency register Excitation Frequency Complement Analog output An on board oscillator provides the sinusoidal excitation signal EXC and its complement signal EXC to the resolver The frequency of this reference signal is programmable via the excitation frequency register Analog Ground This pin is the ground reference points for analog circuitry on the AD2S1210 Refer all analog input signals and any external reference signal to this AGND voltage Connect the AGND pin to the AGND plane of a system The AGND and DGND voltages should ideally be at the same potential and must not be more than 0 3 V apart even on a transient basis Positive Analog Input of Differential SIN SINLO Pair The input range is 2 3 V p p to 4 0 V p p Negative Analog Input of Differential SIN SINLO Pair The input range is 2 3 V p p to 4 0 V p p Analog Supply Voltage 4 75 V to 5 25 V This pin is the supply voltage for all analog circuitry on the AD2S1210 The and voltages ideally should be at the same potential and must not be more than 0 3 V apart even on a transient basis Negative Analog Input of Differential COS COSLO Pair The input range is 2 3 V p p to 4 0 V p p Positive Analog Input of Differential COS COSLO
12. VOLTAGE REFERENCE REFOUT 2 40 2 47 2 53 lour 100 pA Drift 100 ppm C PSRR 60 dB CLKIN XTALOUT Vi Voltage Input Low 0 8 V Vin Voltage Input High 2 0 V LOGIC INPUTS Vi Voltage Input Low 0 8 V Vorive 2 7 V to 5 25 V 0 7 V Vorve 23 V to 2 7 V Vin Voltage Input High 2 0 V Vorve 2 7 V to 5 25 V 1 7 V Vorive 2 3 V to 2 7 V Low Level Input Current Non 10 uA Pull Up Low Level Input Current Pull Up 80 uA RESO RES1 RD WR FSYNC A0 A1 and RESET pins High Level Input Current 10 uA LOGIC OUTPUTS Vo Voltage Output Low 0 4 V Vorve 2 3 V to 5 25 V Vor Voltage Output High 24 V Vorve 2 7 V to 5 25 V 2 0 V Vorive 2 3 V to 2 7 V lozu High Level Three State Leakage 10 loz Low Level Three State Leakage 10 Rev 0 Page 4 of 36 Parameter Min Typ Max Unit Conditions Comments POWER REQUIREMENTS 4 75 5 25 V DVop 4 75 5 25 V Vorive 2 3 5 25 V POWER SUPPLY lavoo 12 mA 35 mA lovpp 2 mA Temperature ranges are as follows A B grades 40 C to 85 C C D grades 40 C to 125 C 2 The voltages SIN SINLO COS and COSLO relative to AGND must always be between 0 15 V and AVpp 0 2 V 3 All specifications within the angular accuracy parameter are tested at constant velocity that is zero acceleration The velocity accuracy specification includes velocity offset and dynamic ripple 5 For example when RESO 0 and RES1 1
13. the position output has a resolution of 12 bits The velocity output has a resolution of 11 bits with the MSB indicating the direction of rotation In this example with a CLKIN frequency of 8 192 MHz the velocity LSB is 0 488 rps that is 1000 rps 2 5 The clock frequency of the AD2S1210 can be supplied with a crystal an oscillator or directly from a DSP microprocessor digital output When using a single ended clock signal directly from the DSP microprocessor the XTALOUT pin should remain open circuit and the logic levels outlined under the logic inputs parameter in Table 1 apply ww BDI C com Rev 0 Page 5 of 36 TIMING SPECIFICATIONS AV pp DVpp 5 0 V 5 Ta Tmn to Tmax unless otherwise noted Table 2 Parameter Description Limit at Twin Tmax Unit Frequency of clock input 6 144 MHz min 10 24 MHz max tck Clock period 1 faw 98 ns min 163 ns max ti and A1 setup time before RD CS low 2 ns min t Delay CS falling edge to WR FSYNC rising edge 22 ns min t Address data setup time during a write cycle 3 ns min ta Address data hold time during a write cycle 2 ns min ts Delay WR FSYNC rising edge to CS rising edge 2 ns min te Delay CS rising edge to CS falling edge 10 ns min t Delay between writing address and writing data 2 X tck 20 ns min ts and A1 hold time after WR FSYNC rising edge 2 ns min to Delay between successive write cycles 6 x tck 20 ns min tio Delay between risin
14. 44 If additional phase lock range is required Bit D5 in the control register can be set to zero to expand the phase lock range to 360 see the Control Register section CONNECTING THE CONVERTER Ground is connected to the AGND and DGND pins see Figure 26 A positive power supply of 5 V dc 5 15 connected to the AVpp and DVpr pins with typical values for the decoupling capacitors being 10 nF and 4 7 These capacitors are then placed as close to the device pins as possible and are connected to both AVpp and DVpp The pin is connected to the supply voltage of the microprocessor The voltage applied to the Vprive input controls the voltage of the parallel and serial interfaces Vpnivz can be set to 5 V 3 V or 2 5 V Typical values for the Vprive decoupling capacitors 10 nF and 4 7 uF Typical values for the oscillator decoupling capacitors are 20 pF whereas typical values for the reference decoupling capacitors are 10 nF and 10 pE Rev 0 Page 18 of 36 Figure 27 shows a suggested buffer circuit Capacitor C1 may be used in parallel with Resistor R2 to filter out any noise that may 1 exist on the EXC and EXC outputs Care should be taken when selecting the cutoff frequency of this filter to ensure that phase shifts of the carrier caused by the filter do not exceed the phase lock range of the AD2S1210 io The gain of the circuit is nF Carrier Gain R2 RI x 1 1 R2xC1xw 7 and R2 R
15. Pair The input range is 2 3 V p p to 4 0 V p p Reference Bypass Connect reference decoupling capacitors at this pin Typical recommended values are 10 uF and 0 01 pF Voltage Reference Output Resolution Select 0 Logic input RESO in conjunction with RES1 allows the resolution of the AD2S1210 to be programmed Refer to the Configuration of AD2S1210 section Rev 0 Page 10 of 36 TYPICAL PERFORMANCE CHARACTERISTICS 25 C AVpp DVpp 5 V SIN SINLO 3 15 COS COSLO 3 15 V CLKIN 8 192 MHz unless otherwise noted 400 200 350 180 160 300 140 250 120 100 150 89 60 100 40 50 20 0 0 HITS PER CODE 5 e HITS PER CODE 07467 003 07467 006 CODE CODE Figure 3 Typical 16 Bit Angular Accuracy Histogram Of Codes 512 Samples Figure 6 Typical 12 Bit Angular Accuracy Histogram of Codes 512 Samples Hysteresis Disabled 600 500 400 HITS PER CODE 100 07467 017 CODES 07467 004 GODE Figure 7 Typical 12 Bit Angular Accuracy Histogram of Codes 512 Samples Figure 4 Typical 14 Bit Angular Accuracy Histogram of Codes 512 Samples Hysteresis Enabled Hysteresis Disabled 60 600 50 500 40 400 a o 8 30 x 300 5 2 T 20 T 200 10 100 0 0 BESESSSZ2S95999599295995959929928 2 2045 2046 2047 2048 2049 Bo 00 00 00
16. converter are valid The AD2S1210 can be configured to emulate a 256 line a 1024 line a 4096 line or a 16 384 line encoder For example if the AD2S1210 is configured for 12 bit resolution one revolu tion produces 1024 A and B pulses Pulse A leads Pulse B for increasing angular rotation that is clockwise direction The resolution of the encoder emulation outputs of the AD2S1210 is generally configured to match the resolution of the digital output However the encoder emulation outputs of the AD2S1210 can also be configured to have a lower resolution than the digital outputs For example if the AD2S1210 is configured for 16 bit resolu tion then the encoder emulation outputs can also be configured for 14 bit 12 bit or 10 bit resolution However the resolution of the encoder emulation outputs cannot be higher than the resolution of the digital output If the AD2S1210 is configured such that the resolution of the encoder emulation outputs is higher than the resolution of the digital outputs the AD2S1210 internally overrides this configuration In this event the resolu tion of the encoder outputs is set to match the resolution of the digital outputs The resolution of the encoder emulation can be programmed by writing to Bit D control registe The north position passes through zero is set internally for 90 and is defined relative to the A cycle Figure 36 details the relationship between A B and NM z 0746
17. e form the complete loop gespo Integratorl and fen functi C 10 3 10 Compensation filter transfer function C z 11 0 1 RDC open loop transfer function G z k1xk2xI z x C z 12 Table 28 RDC System Response Parameters RDC dosed loop transfer function G z BOSCO 13 The closed loop magnitude and phase responses are that ofa second order low pass filter see Figure 11 and Figure 12 To convert G z into the s plane an inverse bilinear transforma tion is performed by substituting the following equation for z 2 where t is the sampling period 1 4 096 MHz 244 ns Substitution yields the open loop transfer function G s T st iss ta _ 2 1 2 a AES 20 09 This transformation produces the best matching at low frequencies f lt At such frequencies within the closed loop bandwidth of the AD2S1210 the transfer function can be simplified to cde 16 57 where t l a 17 Xd _ t 14 D 2 pb k2 1 a uvm 5 Solving for each value gives ti 5 and K as outlined in Table 29 Parameter Description 10 bit resolution 12 bit resolution 14 bit resolution 16 bit resolution k1 nominal ADC gain 1 8 2 5 1 8 2 5 1 8 2 5 1 8 2 5 k2 Error gain 6x 106 x 21 18 x 106 x 2x 82x 10 x 2x 66 x 106 x 2x a Compensator zero coefficient 8187 8192 4095 4096 8191 8192 3
18. ideally should be at the same potential and must not be more than 0 3 V apart even on a transient basis Clock Input A crystal or oscillator can be used at the CLKIN and XTALOUT pins to supply the required clock frequency of the AD2S1210 Alternatively a single ended clock can be applied to the CLKIN pin The input frequency of the AD2S1210 is specified from 6 144 MHz to 10 24 MHz Crystal Output When using a crystal or oscillator to supply the clock frequency to the AD2S1210 apply the crystal across the CLKIN and XTALOUT pins When using a single ended clock source the XTALOUT pin should be considered a no connect pin Serial Output Enable Logic input This pin enables either the parallel or serial interface The serial interface is selected by holding the SOE pin low and the parallel interface is selected by holding the SOE pin high Sample Result Logic input Data is transferred from the position and velocity integrators to the position and velocity registers after a high to low transition on the SAMPLE signal The fault register is also updated after a high to low transition on the SAMPLE signal Data Bit 15 Serial Data Output Bus When the SOE pin is high this pin acts as DB15 a three state data output pin controlled by CS and RD When the SOE pin is low this pin acts as SDO the serial data output bus controlled by CS and WR FSYNC The bits are clocked out on the rising edge of SCLK Data Bit 14 Serial Data Input Bus When the SOE pin
19. or have a number of shorted turns LOS is indicated by both the DOS and LOT pins latching as logic low outputs The DOS and LOT pins are reset to a no fault state when the user enters configuration mode and reads the fault register The LOS condition has priority over both the DOS and LOT conditions as shown in Table 6 To determine the cause of the LOS fault detection the user must read the fault register Address OxFF see the Register Map section When a loss of signal is detected due to the resolver inputs sine or cosine falling below the specified LOS sine cosine threshold the electrical angle through which the resolver may rotate before the LOS can be detected the AD2S1210 is referred to as the LOS angular latency This is defined by the specified LOS sine cosine threshold set by the user and the maximum amplitude of the input signals being applied to the AD2S1210 The worst case angular latency can be calculated as follows Rev 0 Page 16 of 36 Angular Latency LOS threshold 2x Arc cos n 5 max sine cosine amplitude The preceding equation is based on the worst case angular error which can be seen by the AD2S1210 before an LOS fault is indicated This occurs if one of the resolver input signals either sine or cosine is lost while the remaining signal is at its peak amplitude for example if the sine input is lost while the input angle is 90 The worst case angular latency is twice th
20. position of the rotor shaft relative to the stator The resolver therefore produces two output voltages S3 S1 S2 S4 modulated by the sine and cosine of shaft angle Resolver format signals refer to the signals derived from the output of a resolver as shown in Equation 1 Figure 25 illustrates the output format 07467 024 Figure 25 Electrical Resolver Representation Rev 0 Page 15 of 36 THEORY OF OPERATION RESOLVER TO DIGITAL CONVERSION The AD2S1210 operates on a Type II tracking closed loop principle The output continually tracks the position of the resolver without the need for external conversion and wait states As the resolver moves through a position equivalent to the least significant bit weighting the output is updated by one LSB The converter tracks the shaft angle 0 by producing an output angle that is fed back and compared to the input angle 0 and the resulting error between the two is driven towards 0 when the converter is correctly tracking the input angle To measure the error 53 S1 is multiplied by cos and S2 S4 is multiplied by sino to give E sin t x sin 0 cos for S3 S1 E sin t x cos 0 sin for S2 54 The difference is taken giving E sin at x sin 0 cos cos 0 sin 2 This signal is demodulated using the internally generated synthetic reference yielding sin cos cos O sin Equation 3 is eq t i whid equal to E
21. therefore recommended that when initial configuration of the AD2S1210 is complete the fault address should be written to the AD2S1210 before leaving configuration mode This simplifies the reading and clearing of the fault register in normal operation because it is now possible to access the position velocity and fault information by toggling the A0 and 1 pins without requiring additional register addressing V ma WR XXXXXXXXXXXXAXXAKA lt t 1 1 et XXXXXXXXXXXXXXXC ADDRESS XXXXKXKKXKX DATA XXXKXXKKKKKKEKKEKKEKKEKKKX ADDRESS NOTES DON T CARE 2 RD SHOULD BE HELD HIGH WHEN WRITING TO THE AD2S1210 07467 027 Figure 28 Parallel Port Write Timing Configuration Mode Rev 0 Page 25 of 36 A0 A1 gt E 7 gt r lt tus Cs LAAXAAXAAXAAXAAX t5 14 1 lua 1 lt uA 1 1 1 1 RD n 1 ete 1 1 1 1 1 1 DB0 TO 087 ADDRESS DATA Y ADDRESS DATA NOTES 1 DON T CARE 07467 028 Figure 29 Parallel Port Read Timing Configuration Mode 46 1 1
22. to Any Pin Except Supplies Operating Temperature Range Ambient A B Grades C D Grades Storage Temperature Range Thermal Impedance Thermal Impedance RoHS Compliant Temperature Soldering Reflow ESD 0 3 V to 47 0 V 0 3 V 47 0 V 0 3 V to 0 3 V to 0 3 V 0 3 V to 0 3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 0 3 V to AVop 0 3 V 0 3 V to Vorve 0 3 V ESD CAUTION 0 3 V to Vorve 0 3 V 0 3 V to AVpp 0 3 V 10 mA 40 to 85 C 40 C to 125 C 65 C to 150 C 54 C W 15 C W 260 5 0 C 2 kV HBM Ata ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Transient currents of up to 100 mA do not cause latch up JEDEC 2S2P standard board ww BDI C com Rev 0 Page 8
23. to DO Read write The DOS overrange threshold register determines the degradation of signal threshold of the AD2S1210 The AD2S1210 allows the user to set the DOS overrange threshold to a value between 0 V and 4 82 V The resolution of the DOS overrange threshold is seven bits that is 38 mV Note that the MSB D7 should be set to 0 The default value of the DOS overrange threshold on power up is 4 1 V DOS MISMATCH THRESHOLD REGISTER Table 15 8 Bit Register Address Bit Read Write D7 to DO Read write VELOCITY REGISTER Table 12 16 Bit Register Address Bit Read Write 0x82 D15 to D8 Read only 0x83 D7 to DO Read only The velocity register contains a digital representation of the angular velocity of the resolver input signals The value in the velocity register is updated following a falling edge on the sample input The values are stored in 16 bit twos complement format The The DOS mismatch threshold register determines the signal mismatch threshold of the AD2S1210 The AD2S1210 allows the user to set the DOS mismatch threshold to a value between 0 V and 4 82 V The resolution of the DOS mismatch threshold is seven bits that is 38 mV Note that the MSB D7 should be set to 0 The default value of the DOS mismatch threshold on power up is 380 mV Rev 0 Page 21 of 36 DOS RESET MAXIMUM AND MINIMUM Table 19 LOT High Low Threshold THRESHOLD REGISTERS Tabl
24. 0 400000 600000 800000 1000000 ACCELERATION rps2 07467 019 Figure 23 Typical 10 Bit Tracking Error vs Acceleration C com AL Rev 0 Page 14 of 36 RESOLVER FORMAT SIGNALS V Vp x sin wt R1 2 Va Vs x cos 0 EE 8 3 54 R2 Vp Vs sin 0 A CLASSICAL RESOLVER Vp x sin wt 52 Va Vs x sin wt x cos 0 b S4 R1 R2 er 81 S3 Vp Vs Sin wt x sin 0 07467 023 B VARIABLE RELUCTANCE RESOLVER Figure 24 Classical Resolver vs Variable Reluctance Resolver A resolver is a rotating transformer typically with a primary winding on the rotor and two secondary windings on the stator In the case of a variable reluctance resolver there are no wind ings on the rotor as shown in Figure 24 The primary winding is on the stator as well as the secondary windings but the saliency in the rotor design provides the sinusoidal variation in the secondary coupling with the angular position Either way the resolver output voltages 53 S1 S2 S4 have the same equations as shown in Equation 1 3 51 E sin ot x sin 25 1 0 is the shaft angle Sinot is the rotor excitation frequency Eois the rotor excitation amplitude The stator windings are displaced mechanically by 90 see Figure 24 The primary winding is excited with an ac reference The amplitude of subsequent coupling onto the stator secondary windings is a function of the
25. 2 1 V Vapp X 1 x V 8 40nF 4 Der REF 2 55612 w 8 AD2S1210 where w is the radian frequency of the applied signal Vrer dc voltage is set so that Vour is always a positive value eliminating the need for a negative supply C1 07467 025 EXC EXC O Vin AD8662 Vour 04767 026 connected to a different potential relative to ground if the sine and cosine signals adhere to the recommended specifications A separate screened twisted pair cable is recommended for the Note that because the EXC and EXC outputs are differential analog input pins SIN SINLO COS and COSLO The screens there is an inherent gain of 2x should terminate to either REFOUT or AGND Rev 0 Page 19 of 36 CONFIGURATION OF AD2S1210 MODES OF OPERATION The AD2S1210 has two modes of operation configuration mode and normal mode The configuration mode is used to program the registers that set the excitation frequency the resolution and the fault detection thresholds of the AD2S1210 Configuration mode is also used to read back the information in the fault register The data in the position and velocity registers can also be read back while in configuration mode The AD2S1210 can be operated entirely in configuration mode or when the initial configuration is completed the part can be taken out of configuration mode and operated in normal mode When operating in normal mode the data outputs can provide angula
26. 2 767 32 768 b Compensator pole coefficient 509 512 4085 4096 16 359 16 384 32 757 32 768 Integrator gain 1 1 024 000 1 4 096 000 1 16 384 000 1 65 536 000 Rev 0 Page 32 of 36 Table 29 Loop Transfer Function Parameters vs Resolution fcu 8 192 MHz Resolution Bits t ms t gt ms K sec 10 0 4 42 39 6 108 12 1 91 6 5 x 106 14 2 160 1 6 x 10 16 8 728 92 7 x 10 Note that the closed loop response is described as G s 1 G s By converting the calculation to the s domain it is possible to quantify the open loop dc gain Ka This value is useful to calculate the acceleration error of the loop see the Sources of Error section 5 17 The step response to 10 input step is shown in Figure 10 Figure 11 Figure 12 and Figure 13 The step response to a 179 input step is shown in Figure 14 Figure 15 Figure 16 and Figure 17 In response to a step change in velocity the AD2S1210 exhibits the same response characteristics as it does for a step change in position Figure 18 and Figure 19 in the Typical Performance Characteristics section show the magnitude and phase responses ofthe WANN for each resolution setti SOURCES OF ERROR Acceleration A tracking converter employing a Type II servo loop does not have a lag in velocity There is however an error associated with acceleration This error can be quantified using the acceleration constant Ka of the converter Input
27. 7 035 Figure 36 A B and NM Timing for Clockwise Rotation The inclusion of A and B outputs allows the AD2S1210 with resolver solution to replace optical encoders directly without the need to change or upgrade existing application software SUPPLY SEQUENCING AND RESET The AD2S1210 requires an external reset signal to hold the RESET input low until is within the specified operating range of 4 5 V to 5 5 V The RESET pin must be held low for a minimum of 10 after is within the specified range shown as trsr in Figure 37 Applying a RESET signal to the AD2S1210 initializes the output position to a value of 0x000 degrees output through the parallel serial and encoder interfaces and causes LOS to be indicated LOT and DOS pins pulled low as shown in Figure 37 Failure to apply the correct power up reset sequence may result in an incorrect position indication After a rising edge on the RESET input the device must be allowed at least trrack ms see Figure 37 for the internal circuitry to stabil ize and the tracking loop to settle to the step change of the input position For the duration of fault indications may occur on the LOT and DOS pins due to the step response caused by the RESET The duration of trrack is dependent on the converter resolution as outlined in Table 27 After trracx the fault register should be read and cleared as outlined in the Clearing the Fault Register section The time req
28. AD2S1210 clock The internal clock is generated by dividing the externally applied CLKIN frequency by 2 for example when using a CLKIN frequency of 8 192 MHz the internal AD2S1210 clock is 4 096 MHz The AD2S1210 conti nuously stores the minimum and maximum magnitude of the monitor signal in internal registers The values stored in these internal registers are compared to the LOS and DOS thresholds configured by the user at set intervals This interval known as the window counter period is dependent on the excitation frequency configured by the user It is set to ensure that two window counter periods include at least one full period of the excitation frequency applied to the resolver The window counter period is defined in terms of internal clock cycles The window counter periods for the range of excitation frequencies on the AD2S1210 are outlined in Table 5 Table 5 Window Counter Period vs Excitation Frequency Range CLKIN 8 192 MHz Number of Window Excitation Frequency Internal Clock Counter Period Range Cycles ps 2 kHz lt Exc Freq lt 4 kHz 1065 260 4 kHz lt Exc Freq lt 8 kHz 554 135 25 8 kHz lt Exc Freq lt 20 kHz 256 62 5 1 CLKIN 8 192 MHz The window counter period scales with clock frequency and can be calculated by multiplying the number of internal clock cycles by the period of the internal clock frequency that is CLKIN 2 The AD2S1210 detects an LOS or DOS due to the resolver inputs
29. ANALOG DEVICES FEATURES Complete monolithic resolver to digital converter 3125 rps maximum tracking rate 10 bit resolution 2 5 arc minutes of accuracy 10 12 14 16 bit resolution set by user Parallel and serial 10 bit to 16 bit data ports Absolute position and velocity outputs System fault detection Programmable fault detection thresholds Differential inputs Incremental encoder emulation Programmable sinusoidal oscillator on board Compatible with DSP and SPI interface standards 5 V supply with 2 3 V to 5 V logic interface 40 C to 125 C temperature rating APPLICATIONS DC and ac servo motor control Encoder emulation Electric power steering Electric vehicl Integrated altern Automotiv GENERAL DESCRIPTION The AD2S1210 is a complete 10 bit to 16 bit resolution tracking resolver to digital converter integrating an on board program mable sinusoidal oscillator that provides sine wave excitation for resolvers The converter accepts 3 15 V p p 2796 input signals in the range of 2 kHz to 20 kHz on the sine and cosine inputs A Type II servo loop is employed to track the inputs and convert the input sine and cosine information into a digital representation of the input angle and velocity The maximum tracking rate is 3125 rps Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of p
30. Acceleration 18 Tracking Error Conversely Input Acceleration Tracking Error 19 a The units of the numerator and denominator must be consistent The maximum acceleration of the AD2S1210 is defined by the maximum acceptable tracking error in the users application For example if the maximum acceptable tracking error is 5 then the maximum acceleration is defined as the acceleration that creates an output position error of 5 that is when LOT is indicated An example of how to calculate the maximum acceleration in a 12 bit application with a maximum tracking error of 5 is K sec x 5 Maximum Acceleration KG 90 300 rps com A Figu ure 23 pical Characteristics section show the tracking error vs acceleration response of the AD2S1210 for each resolution setting Rev 0 Page 33 of 36 OUTLINE DIMENSIONS 0 08 COPLANARITY VIEWA ROTATED 90 CCW TOP VIEW PINS DOWN VIEWA C LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS 026 BBC Figure 39 48 Lead Low Profile Quad Flat Package LQFP 051706 A ST 48 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD2S1210ASTZ 40 C to 85 C 48 Lead LQFP ST 48 AD2S1210BSTZ 40 C to 85 48 Lead LOFP ST 48 AD2S1210CSTZ 40 C to 125 C 48 Lead LOFP ST 48 AD2S1210DSTZ 40 C to 125 C 48 Lead LQFP ST 48 17 RoHS Compliant Pa
31. YD XV V SETS 999 XX OLD NOTES 1 XX DON T CARE Figure 33 Serial Interface Write Timing Configuration Mode feLkin CLKIN A0 A1 XXAXAXAXY i A WR FSYNC N QUUUUUUUUUUP CAXXXAXXXAX SDO OLD DATA DATA 1 DATA2 NOTES 1 XX DON T CARE Figure 34 Serial Interface Read Timing Configuration Mode Rev 0 Page 29 of 36 07467 032 07467 033 I gt feLkin tig tie SAMPLE o 2 0 tg cs AX tule WRIFSYNE YOU N aa at POSITION I I POSITION VELOCITY FAULT ASSUMES FAULT REGISTER ADDRESS WRITTEN TO PART BEFORE EXITING CONFIGURATION MODE NOTES 1 CARE Figure 35 Serial Interface Read Timing ww BDI C com Rev 0 Page 30 of 36 07467 034 INCREMENTAL ENCODER OUTPUTS The A B and NM incremental encoder emulation outputs are free running and are valid if the resolver format input signals applied to the
32. at is the maximum tracking rate increases as the resolution is decreased The option of disabling the hysteresis allows the user to oversample the position output and to achieve a higher resolution output within the specified bandwidths through external averaging The hysteresis function can be enabled or disabled through setting Bit D4 in the control register Hysteresis is enabled by default on power up Set Encoder Resolution The resolution of the encoder outputs of the AD2S1210 can be set to the same resolution as the digital output or it can also be set to a lower resolution For example when the resolution of the AD2S1210 position outputs is set to 16 bits the resolution of the encoder outputs may be set to 14 12 or 10 bits This allows the user to take advantage of the lower bandwidth and improved performance of the 16 bit resolution setting without requiring external divide down of the A quad B encoder outputs The default resolution of the encoder outputs on power up is 16 bits Refer to the Incremental Encoder Outputs section Table 23 Encoder Resolution Settings EnRESO EnRES1 Resolution Bits 0 0 10 0 1 12 1 0 14 1 1 16 Set Resolution In normal mode the resolution of the digital output is selected using the RESO and RESI input pins see Table 9 In configuration mode the resolution is selected by setting the RESO and RESI bits in the control register When switching between normal mode and co
33. atents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Variable Resolution 10 Bit to 16 Bit R D Converter with Reference Oscillator FUNCTIONAL BLOCK DIAGRAM REFERENCE PINS CRYSTAL REFERENCE INTERNAL gd o OSCILLATOR CLOCK DAC GENERATOR INPUTS TYPE Il FAULT FROM TRACKING LOOP DETECTION DETECTION RESOLVER OUTPUTS DATA I O ENCODER EMULATION OUTPUTS MULTIPLEXER z ex 95 a 3i 2 07467 001 PRODUCT HIGHLIGHTS 1 Ratiometric tracking conversion The Type II tracking loop provides continuous output position data without conversion delay It also provides noise immunity and tolerance of harmonic distortion on the reference and input signals 2 System fault detection A fault detection circuit can sense loss of resolver signals out of range input signals input signal mismatch or loss of position tracking The fault detection threshold levels can be individually programmed by the user for optimization within a particular application 3 Inputsignal range The sine and cosine inputs can accept differential input voltages of 3 15 V p p 27 4 Programmable excitation frequency Excitation frequency is easily programmable to a number of standard f
34. d on the SDI pin and again latched into the part using the WR FSYNC input The MSB of the 8 bit write indicates whether the 8 bit word is a register address MSB set high or the data to be written MSB set low Figure 33 shows the timing specifications to follow when writing to the configuration registers Reading from the AD2S1210 in Configuration Mode To read back data stored in one of the on chip registers including the fault register the user must first place the AD2S1210 into configuration mode using the A0 and A1 inputs The 8 bit address of the register to be read should then be written to the part as described in the Writing to the AD2S1210 section This transfers the relevant data to the output register In configuration mode the output shift register is eight bits wide Data is shifted out of the device as an 8 bit word under the control of the serial clock input SCLK The timing diagram for this operation is shown in Figure 34 When reading back data from any of the read write registers see Table 10 the 8 bit word consists of the seven bits of data in the relevant register D6 to DO and an error bit D7 If the error bit is returned high this indicates that the data read back from the device does not match the configuration data written to the device in the previous write cycle To read back the angular position or velocity data while in configuration mode a falling edge of the SAMPLE input is required to u
35. e Register Name Address Data Register Position 0x80 D15toD8 Read only 0x81 D7 to DO Read only Velocity 0x82 D15to D8 Read only 0x83 D7 to DO Read only LOS Threshold 0x88 D7 to DO Read write DOS Overrange 0x89 D7 to DO Read write Threshold DOS Mismatch 07 to DO Read write Threshold DOS Reset Max Ox8B D7 to DO Read write Threshold DOS Reset Min 0 8 D7 to DO Read write Threshold LOT High Threshold 0 80 07 00 Read write LOT Low Threshold Ox8E D7 to DO Read write Excitation Frequency 0x91 D7 to DO Read write Control 0x92 D7 to DO Read write Soft Reset OxFO D7 to DO Write only Fault OxFF D7 to DO Read only maximum velocity that the AD2S1210 can track for each resolution is specified in Table 1 For example the maximum tracking rate of the AD2S1210 at 16 bits resolution with an 8 192 MHz input clock is 125 rps A velocity of 125 rps results in Ox7FFF being stored in the velocity register a velocity of 125 rps results in 0x8000 being stored in the velocity register The value stored in the velocity register is 16 bits regardless of resolution At lower resolutions the LSBs of the 16 bit digital output should be ignored For example at 10 bit resolution Data D15 to Data Bit 06 provide valid data D5 to DO should be ignored The maximum tracking rate of the AD2S1210 at 10 bit resolution with an 8 192 MHz input clock is 2500 rps A velocity of 2500 rps results in Ox1FF being stored in Bit D15 to Bit D6 of t
36. e worst case angular error Signal Degradation Detection The AD2S1210 indicates that a degradation of signal DOS has occurred for two separate conditions e When either resolver input sine or cosine exceeds the specified DOS sine cosine threshold This threshold is defined by the user and is set by writing to the internal register Address 0x89 see the Register Map section e When the amplitudes of the input signals sine and cosine mismatch by more than the specified DOS sine cosine mismatch threshold This threshold is defined by the user and is set by writing to the internal register Address 0x8A see the Register Map section The AD2S1210 stores the minimum andr maximumsmag nce D tWeenthe tor signal im i Th axi i Wann DOS misma a urred Th minimum and maximum internal registers must be defined by the user at Address 0x8C and Address 0x8B respectively see the Register Map section DOS is indicated by a logic low on the DOS pin When DOS is indicated the output is latched low until the user enters configura tion mode and reads the fault register The DOS condition has priority over the LOT condition as shown in Table 6 To deter mine the cause of the DOS fault detection the user must read the fault register Address OxFF see the Register Map section Time Latency for LOS and DOS Detection Note that the monitor signal is generated on the active edge of the internal
37. e 16 8 Bit Registers Address Bit Read Write 0 88 D7 to DO Read write 0x8C D7 to DO Read write LOT Low LOT High Resolution Range LSB Size Default Default Bits Degrees Degrees Degrees Degrees 10 Oto 45 0 35 2 5 12 5 12 01018 0 14 1 0 5 0 14 0109 0 09 0 5 2 5 16 0109 0 09 0 5 2 5 The AD2S1210 continuously stores the minimum and maximum magnitude of the monitor signal in internal registers The differ ence between the minimum and maximum is calculated to determine if a DOS mismatch has occurred The initial values for the minimum and maximum internal registers must be defined by the user When the fault register is cleared the registers that store the maximum and minimum amplitudes of the monitor signal are reset to the values stored in the DOS reset maximum and minimum threshold registers The resolution of the DOS reset maximum and minimum thresholds is seven bits each that is 38 mV Note that the MSB D7 should be set to 0 To ensure correct operation it is recommended that the DOS reset minimum threshold register be set to at least 1 LSB less than the DOS overrange threshold and the DOS reset maximum threshold register be set to at least 1 LSB greater than the LOS threshold register The default value of the DOS reset minimum threshold register and the DOS reset maximum threshold register are 3 99 V and 2 28 V Table 17 EXCITATION FREQUENCY REGISTER Table 20 8 Bit Register
38. e Fault Register The LOT pin and or the DOS pin of the AD2S1210 are taken low to indicate that a fault has been detected The AD2S1210 is capable of detecting eight separate fault conditions To determine which condition triggered the fault indication the user is required to enter configuration mode and read the fault register To reset the fault indicators an additional SAMPLE pulse is required This ensures that any faults that may occur between the initial sampling and subsequent reading of the fault register are captured Therefore to read and clear the fault register the following sequence of events is required high to low transition of the SAMPLE input 2 The SAMPLE input should be held low for tis ns and then can be returned high 3 The AD2S1210 should be put into configuration mode that is AO and A1 are both set to logic high 4 The fault register should be read as described in the Reading from the AD2S1210 in Configuration Mode section 5 A second high to low transition of the SAMPLE input clears the fault indications on the DOS and or LOT pins 6 Note that in the event ofa persistent fault the fault indica tors are reasserted within the specified fault time latency Figure 31 shows the timing specifications to follow when clearing the fault register Note that the last valid register address written to the AD2S1210 prior to exiting configuration mode is again valid when reentering configuration mode It is
39. e part into configuration mode The data from the fault register and the remaining on chip registers can be accessed in configuration mode Table 8 Configuration Mode Settings AO Al Result 0 0 Normal mode position output 0 1 Normal mode velocity output 1 0 Reserved 1 1 Configuration mode 50 REST Inputs In norm ne re 0 ut is selected using th Sli 2 ion mode e resolution is selected the RESI bits in the control register When switching between normal mode and configuration mode it is the responsibility of the user to ensure that the resolution set in the control register matches the resolution set by the RESO and RESI input pins Failure to do so may result in incorrect data on the outputs caused by the differences between the resolution settings Table 9 Resolution Settings Typical Min Excitation Max Excitation Resolution Bandwidth Frequency Frequency 10 Bits 4100 Hz 10 kHz 20 kHz 12 Bits 1700 Hz 6 kHz 20 kHz 14 Bits 900 Hz 3 kHz 12 kHz 16 Bits 250 Hz 2 kHz 10 kHz Resolution Position LSB Velocity LSB RESO RES1 Bits Arc min rps 0 0 10 21 1 4 88 0 1 12 5 3 0 488 1 0 14 1 3 0 03 1 1 16 0 3 0 004 1 CLKIN 8 192 MHz The velocity LSB size and maximum tracking rate scale linearly with the CLKIN frequency Rev 0 Page 20 of 36 REGISTER MAP Table 10 Register Map Register Register Read Writ
40. e valid Incremental Encoder Emulation Output B Logic output This output is free running and is valid if the resolver format input signals applied to the converter are valid North Marker Incremental Encoder Emulation Output Logic output This output is free running and is valid if the resolver format input signals applied to the converter are valid Direction Logic output This output is used in conjunction with the incremental encoder emulation outputs The DIR output indicates the direction of the input rotation and is high for increasing angular rotation Reset Logic input The AD2S1210 requires an external reset signal to hold the RESET input low until Voo is within the specified operating range of 4 75 V to 5 25 V Loss of Tracking Logic output LOT is indicated by a logic low on the LOT pin and is not latched Refer to the Loss of Position Tracking Detection section Degradation of Signal Logic output Degradation of signal DOS is detected when either resolver input sine or cosine exceeds the specified DOS sine cosine threshold or when an amplitude mismatch occurs between the sine and Logic cosine input voltage edslay a logi n the DOS pin Refer to the Signal DegradationsDetection 5 nction with AO allows Te 1210 S Refer to the onfig rationof AD Mode Select 0 Logic input AO in conjunction with A1 allows the mode of the AD2S1210 to be selected Refer to the Configuration of AD2S1210 section
41. er LOT can be indicated for step changes in position such as after a RESET signal is applied to the AD2S1210 It is also useful as a built in test to indicate that the tracking converter is functioning properly The LOT condition has lower priority than both the DOS and LOS conditions as shown in Table 6 The LOT and DOS conditions cannot be indicated using the LOT and DOS pins at the same time However both condi tions are indicated separately in the fault register To determine the cause of the LOT fault detection the user must read the fault register Address OxFF see the Register Map section Rev 0 Page 17 of 36 Table 6 Fault Detection Decoding Order of Condition Priority Loss of Signal LOS Degradation of Signal DOS Loss of Tracking LOT No Fault Sine Cosine Input Clipping The AD2S1210 indicates that a clipping error has occurred if any of the resolver input pins SIN SINLO COS or COSLO are clipping the power rail or ground rail of the AD2S1210 The clipping fault is indicated if the input amplitudes are less than 0 15 V or greater then AV 0 2 V for more than 4 Sine cosine input clipping error is indicated by both the DOS and LOT pins latching as logic low outputs Sine cosine input clipping error is also indicated by Bit D7 of the fault register being set high The DOS and LOT pins are reset to a no fault state when the user enters configuration mode and reads the fault register Config
42. es 250 07467 013 TIME ms Figure 15 Typical 14 Bit 179 Step Response 175 a N a o 0 1 2 3 4 5 6 7 8 9 10 TIME ms 07467 012 Figure 16 Typical 12 Bit 179 Step Response 225 1 2 3 4 5 TIME ms 07467 011 Figure 17 Typical 10 Bit 179 Step Response 0 10 BIT 14 BIT 15 12 81 16 BIT MAGNITUDE dB 5 1 10 100 1k 10k 100k FREQUENCY Hz 07467 015 Figure 18 Typical System Magnitude Response PHASE dB 07467 016 FREQUENCY Hz Figure 19 Typical System Phase Response 10 TRACKING ERROR Degrees 0 500 1000 1500 2000 2500 ACCELERATION rps 07467 022 Figure 20 Typical 16 Bit Tracking Error vs Acceleration Rev 0 Page 13 of 36 TRACKING ERROR Degrees TRACKING ERROR Degrees 10 10 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 ACCELERATION rps2 Figure 21 Typical 14 Bit Tracking Error vs Acceleration 0 20000 60000 100000 140000 180000 ACCELERATION rps2 Figure 22 Typical 12 Bit Tracking Error vs Acceleration 07467 021 07467 020 10 N a TRACKING ERROR Degrees 0 20000
43. esolver angle is the angle stored in the position register Note that Equation 4 is shown after demodulation with the Carrier Signal sinwt removed Also note that for matched input signal that is a no fault condition Al A2 When 1 A2 and the converter is tracking 0 the monitor signal output has a constant magnitude of Al Monitor A x sin 0 cos 1 which is independent of shaft angle When A1 z A2 the monitor signal magnitude varies between A1 and A2 at twice the rate of shaft rotation The monitor signal is used as described in the following sections to detect degradation or loss of input signals Loss of Signal Detection The AD2S1210 indicates that a loss of signal LOS has occurred for four separate conditions e When either resolver input sine or cosine falls below the specified LOS sine cosine threshold This threshold is defi eus igset to internal register A 2 88Xseelthe Re Wh resolver i pins 8 LO COS or COSLO are disconnected from the sensor e When any of the resolver input pins SIN SINLO COS or COSLO are clipping the power rail or ground rail of the AD2S1210 Refer to the Sine Cosine Input Clipping section e When a configuration parity error has occurred Refer to the Configuration Parity Error section A loss of signal is caused if either of the stator windings of the resolver sine or cosine are open circuit
44. g edge of WR FSYNC and falling edge of RD ns min tn Delay CS falling edge to RD falling edge ns min Enable delay RD low to data valid in configuration mode 4 5 V to 5 25 V ns min 2 7 V to 3 6 V ns min 2 3 V to 2 7 V ns min tis RD aisi s min s min 1148 s min Delay between rising edge of RD and falling edge of WR FSYNC ns min tis SAMPLE pulse width 2x tex 20 ns min 117 Delay from SAMPLE before RD CS low 6 x tc 20 ns min tis Hold time RD before RD low 2 ns min Enable delay RD CS low to data valid Vorive 4 5 V to 5 25 V 17 ns min 2 7 V to 3 6 V 21 ns min 2 3 V to 2 7 V 33 ns min RD pulse width 6 ns min and A1 set time to data valid when RD CS low Vorive 4 5 V to 5 25 V 36 ns min 2 7 V to 3 6 V 37 ns min 2 3 V to 2 7 V 29 ns min Delay WR FSYNC falling edge to SCLK rising edge 3 ns min toa Delay WR FSYNC falling edge to SDO release from high Z Vorive 4 5 V to 5 25 V 16 ns min Vorive 2 7 V to 3 6 V 26 ns min 2 3 V to 2 7 V 29 ns min t24 Delay SCLK rising edge to DBx valid Vorive 4 5 V to 5 25 V 24 ns min 2 7 V to 3 6 V 18 ns min 2 3 V to 2 7 V 32 ns min t25 SCLK high time 0 4 X tck ns min SCLK low time 0 4 x tck ns min t27 SDI setup time prior to SCLK falling edge 3 ns min t28 SDI hold time after SCLK falling edge 2 ns min
45. he SDI is used for transferring data into the on chip registers whereas the SDO is used for accessing data from the on chip registers including the position velocity and fault registers SCLK is the serial clock input for the device and all data transfers either on SDI or SDO take place with respect to this SCLK signal WR FSYNC is used to frame the data The falling edge of WR FSYNC takes the SDI and SDO lines out of a high impedance state A rising edge on WR FSYNC returns the SDI and SDO to a high impedance state The input is not required for the serial interface and should be held low SDO Output In normal mode of operation data is shifted out of the device as a 24 bit word under the control of the serial clock input SCLK The data is shifted out on the rising edge of SCLK The timing diagram for this operation is shown in Figure 32 SDI Input The SDI input is used to address the on chip registers and as a daisy chain input in configuration mode The data is shifted into the part on the falling edge of SCLK The timing diagram for this operation is shown in Figure 32 Writing to the The on chip registers e 5 12860 ca sing the serial interface To write to one of the registers the user must first place the 0251210 into configuration mode using the A0 and A1 inputs The 8 bit address should be written to the AD2S1210 using the SDI pin and latched using the rising edge of the WR FSYNC input The data can then be presente
46. he velocity register a velocity of 2500 rps results in Ox3FF being stored in Bit D15 to Bit D6 of the velocity register In this 10 bit example the LSB size of the velocity output is 4 88 rps LOS THRESHOLD REGISTER Table 13 8 Bit Register Address Bit Read Write 0x88 D7 to DO Read write POSITION REGISTER Address i 0x80 D15 to D8 0x81 D7 to DO Read only Read only The position register contains a digital representation of the angular position of the resolver input signals The values are stored in 16 bit binary format The value in the position register is updated following a falling edge on the SAMPLE input Note that with hysteresis enabled see the Control Register section at lower resolutions the LSBs of the 16 bit digital output are set to zero For example at 10 bit resolution Data Bit D15 to Data Bit D6 provide valid data D5 to D0 are set to zero With hysteresis disabled the value stored in the position register is 16 bits regardless of resolution At lower resolutions the LSBs of the 16 bit digital output can be ignored For example at 10 bit resolution Data Bit D15 to Data Bit D6 provide valid data D5 to DO can be ignored The LOS threshold register determines the loss of signal threshold D7 should be set to 0 The A value of the LOS reso on power up is 2 2 V DOS OVERRANGE THRESHOLD REGISTER Table 14 8 Bit Register Address Bit Read Write 0x89 D7
47. ications to follow when writng to the configura tion registers Note that the RD input should be held high when writing to the AD2S1210 Reading from the AD2S1210 The following data can be read back from the AD2S1210 e Angular position e Angular velocity e Fault register data e Status of on chip registers The angular position and angular velocity data can be read back in either normal mode or configuration mode To read the status of the fault register or the remaining on chip registers the part must be put into configuration mode Reading from the AD2S1210 in Configuration Mode read back data stored in one of the on chip registers including the fault register the user must first place the AD2S1210 into configuration mode using the A0 and A1 inputs The 8 bit address of the register to be read should then be written to the part as described in the Writing to the AD2S1210 section This transfers the relevant data to the output register The data can then be read using the RD input as described previously When reading back data from any of the read write registers see Table 10 the 8 bit word consists of the seven bits of data in the relevant register D6 to and an error bit D7 If the error bit is returned high this indicates tha match th config ite cy If the user wants to read back the angular position or velocity data while in configuration mode a falling edge of the SAMPLE input is requ
48. ired to update the information in the position and velocity registers The data in these registers can then be read back by addressing the required register and reading back the data as described previously Figure 29 shows the timing specifications to follow when reading from the configuration registers Reading from the AD2S1210 in Normal Mode To read back position or velocity data from the AD2S1210 the information stored in the position and velocity registers should first be updated using the SAMPLE input A high to low transition on the SAMPLE input transfers the data from the position and velocity integrators to the position and velocity registers The fault register is also updated on the high to low transition of the SAMPLE input The status of the A0 and A1 inputs determines whether the position or velocity data is transferred to the output register The CS pin must be held low to transfer the selected data to the output register Finally the RD input is used to read the data from the output register and to enable the output buffer The output buffer is enabled when CS and RD are held low The data pins return to a high impedance state when RD returns to a high state If the user is reading data continuously RD can be reapplied a minimum of t ns after it was released The timing requirements for the read cycle are shown in Figure 30 Note that the WR FSYNC input should be high when RD is low Rev 0 Page 24 of 36 Clearing th
49. is high this pin acts as DB14 a three state data output pin controlled by CS and RD When the SOE pin is low this pin acts as SDI the serial data input bus controlled by CS and WR FSYNC The bits are clocked in on the falling edge of SCLK Rev 0 Page 9 of 36 Pin No 13 14 to 17 18 20 21to 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 DB13 SCLK DB12 to DB9 Vorive DB8 DB7 to DBO A EXC EXC AGND SIN SINLO COSLO COS REFBYP REFOUT RESO PER Description Data Bit 13 Serial Clock In parallel mode this pin acts as DB13 a three state data output pin controlled by CS and RD In serial mode this pin acts as the serial clock input Data Bit 12 to Data Bit 9 Three state data output pins controlled by CS and RD Logic Power Supply Input The voltage supplied at this pin determines at what voltage the interface operates Decouple this pin to DGND The voltage range on this pin is 2 3 V to 5 25 V and may be different to the voltage range at and DVpp but should never exceed either by more than 0 3 V Data Bit 8 Three state data output pin controlled by CS and RD Data Bit 7 to Data Bit 0 Three state data input output pins controlled by CS RD and WR FSYNC Incremental Encoder Emulation Output A Logic output This output is free running and is valid if the resolver format input signals applied to the converter ar
50. it 900 2800 Hz 1200 2200 Hz CLKIN 8 192 MHz 14 bit 400 1500 Hz 600 1200 Hz CLKIN 8 192 MHz 16 bit 100 350 Hz 125 275 Hz CLKIN 8 192 MHz Rev 0 Page 3 of 36 Parameter Min Typ Max Unit Conditions Comments Tracking Rate 10 bit 3125 rps CLKIN 10 24 MHz 2500 CLKIN 8 192 MHz 12 bit 1250 rps CLKIN 10 24 MHz 1000 CLKIN 8 192 MHz 14 bit 625 rps CLKIN 10 24 MHz 500 CLKIN 8 192 MHz 16 bit 156 25 rps CLKIN 10 24 MHz 125 CLKIN 8 192 MHz Acceleration Error 10 bit 30 arc min At 50 000 rps CLKIN 8 192 MHz 12 bit 30 arc min At 10 000 rps CLKIN 8 192 MHz 14 bit 30 arc min At 2500 rps CLKIN 8 192 MHz 16 bit 30 arc min At 125 rps CLKIN 8 192 MHz Settling Time 10 Step Input 10 bit 0 6 0 9 ms To settle to within 2 158 CLKIN 8 192 MHz 12 bit 22 3 1 ms To settle to within 2 LSB CLKIN 8 192 MHz 14 bit 6 5 9 0 ms To settle to within 2 LSB CLKIN 8 192 MHz 16 bit 27 5 40 ms To settle to within 2 LSB CLKIN 8 192 MHz Settling Time 179 Step Input 10 bit 1 5 2 2 ms To settle to within 2 158 CLKIN 8 192 MHz 12 bit 4 75 6 0 ms To settle to within 2 LSB CLKIN 8 192 MHz 14 bit 10 5 14 7 ms To settle to within 2 158 CLKIN 8 192 MHz 16 bit 45 66 ms To settle to within 2 LSB CLKIN 8 192 MHz EXC EXC OUTPUTS Voltage 32 4 0 typi to 2 Center VNM 2 4 2 53 C Frequency 2 20 kHz EXC EXC DC Mismatch 30 mV EXC EXC AC Mismatch 100 mV THD 58 dB First five harmonics
51. kHz 12 bit 3 kHz to 12 kHz 14 bit 2 kHz to 10 kHz 16 bit TA Tmn to Tmax unless otherwise noted Table 1 Parameter Min Typ Max Unit Conditions Comments SINE COSINE INPUTS Voltage Amplitude 23 3 15 4 0 Vp p Sinusoidal waveforms differential SIN to SINLO COS to COSLO Input Bias Current 8 25 Vin 4 0 V p p CLKIN 8 192 MHz Input Impedance 485 kQ Vin 4 0 V p p CLKIN 8 192 MHz Phase Lock Range 44 44 Degrees Sine cosine vs EXC output Control Register D3 0 Common Mode Rejection 20 arcsec V 10 Hz to 1 MHz Control Register D4 0 ANGULAR ACCURACY Angular Accuracy 2 5 1 LSB 5 115 D grades 5 1 LSB 10 1LSB arcmin A C grades Resolution 10 12 14 16 Bits No missing codes Linearity INL 10 bit 1 LSB B D grades 2 LSB A C grades 12 bit 2 LSB B D grades 4 LSB A C grades 14 bit 4 LSB B D grades 8 LSB A C grades 16 bit 1 LSB B D grades 32 es Linearity MANN 0 9 LSB Repeatabil VELOCITY OUTPUT Velocity Accuracy 10 bit 2 LSB B D grades zero acceleration 4 LSB A C grades zero acceleration 12 bit 2 LSB B D grades zero acceleration 4 LSB A C grades zero acceleration 14 bit 4 LSB B D grades zero acceleration 8 LSB A C grades zero acceleration 16 bit 16 LSB B D grades zero acceleration 32 LSB A C grades zero acceleration Resolution 9 11 13 15 Bits DYNAMNIC PERFORMANCE Bandwidth 10 bit 2000 6500 Hz 2900 5300 Hz CLKIN 8 192 MHz 12 b
52. locity registers are external to the loop and are updated with a high to low transition of the SAMPLE signal This pin must be held low for at least tis ns to guarantee correct latching of the data DATA FORMAT The digital angle e resolver shaft as a 10 bit to 16 bit unsigned b digital velocity data is a 10 bit to 16 bit twos complement word which represents the velocity of the resolver shaft rotating in either a clockwise or a counterclockwise direction PARALLEL INTERFACE The parallel interface is selected holding the SOE pin high The chip select pin CS must be held low to enable the interface Writing to the 251210 The on chip registers of the AD2S1210 are written to in parallel mode using an 8 bit parallel interface D7 to DO and the WR FSYNC pin The MSB of each 8 bit word written to the AD2S1210 indicates whether the 8 bit word is a register address or data The MSB D7 of each register address defined on the AD2S1210 is high see the Register Map section The MSB of each data word written to the AD2S1210 is low To write to one of the registers the user must first place the AD2S1210 into configura tion mode using the A0 and A1 inputs Then the 8 bit address should be written to the AD2S1210 using Pin DB7 to Pin DBO and latched using the rising edge of the WR FSYNC input The data can then be presented on Pin DB7 to Pin DBO and again latched into the part using the WR FSYNC input Figure 28 shows the timing specif
53. mode and read the fault register To reset the fault indicators an additional SAMPLE pulse is required This ensures that any faults that may occur between the initial sampling and subsequent reading of the fault register are captured Therefore to read and clear the fault register the following sequence of events is required Ahigh to low transition of the SAMPLE input 2 Hold the SAMPLE input low for tis ns and then it can be returned high 3 Put the AD2S1210 into configuration mode that is AO and A1 are both set to logic high 4 Read the fault register as described in the Reading from the AD2S1210 in Configuration Mode section 5 A second high to low transition of the SAMPLE input clears the fault indications on the DOS and or LOT pins Note that in the event of a persistent fault the fault indicators are reasserted within the specified fault time latency Rev 0 Page 28 of 36 SCLK soo X X X sp 1 3 00 Figure 32 Serial Interface Timing Diagram 07467 031 CLKIN st P lt ts 1 t t cs 1 t la t P iA fg II 1 WR FSYNC AAA AAA DDRESS AA AAA 1 ANI AY ini
54. nfiguration mode it is the responsibility of the user to ensure that the resolution set in the control register matches the resolution set by the RESO and RESI input pins The default resolution of the digital output on power up is 12 bits SOFTWARE RESET REGISTER Table 24 8 Bit Register Address Bit Read Write OxFO D7 to DO Write only Addressing the software reset register that is writing the 8 bit address 0xF0 of the software reset register to the AD2S1210 serito initiate a soft war are reinitializes the excitation pe II tracking loop The red in the onfiguration registers is not overwritten by a software reset However it should be noted that the data in the fault register is reset In an application that uses two or more resolver to digital converters which are both driven from the same clock source the software reset can be used to synchronize the phase of the excitation frequencies across the converters FAULT REGISTER Table 25 8 Bit Register Address Bit Read Write OxFF D7 to DO Read only The AD2S1210 has the ability to detect eight separate fault condi tions When a fault occurs the DOS and or the LOT output pins are taken low By reading the fault register the user can determine the cause of the triggering of the fault detection output pins Note that the fault register bits are active high that is the fault bits are taken high to indicate that a fault has occurred
55. of 36 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS o Q o AD2S1210 DVpp 5 TOP VIEW CLKIN Not to Scale SAMPLE DB15 SDO 11 DB14 SDI 12 20121122 m m a a DB9 Vorive DGND DB7 X DB12 DB11 DB10 2 DB13 SCLK 07467 002 Figure 2 Pin Configuration Table 4 Pin Function Descriptions Pin No 1 10 11 12 RES1 CS RD WR FSYNC DGND CLKIN XTALOUT SOE SAMPLE DB15 SDO DB14 SDI mem Description Resolution Sele the SOE pin is low the RD pin should be held high Edge Triggered Logic Input When the SOE pin is high this pin acts as a frame synchronization signal and input enable for the parallel data inputs DB7 to DBO The input buffer is enabled when CS and WR FSYNC are held low When the SOE pin is low the WR FSYNC pin acts as a frame synchronization signal and enable for the serial data bus Digital Ground These pins are ground reference points for digital circuitry on the AD2S1210 Refer all digital input signals to this DGND voltage Both of these pins can be connected to the AGND plane of a system The DGND and AGND voltages should ideally be at the same potential and must not be more than 0 3 V apart even on a transient basis Digital Supply Voltage 4 75 V to 5 25 V This is the supply voltage for all digital circuitry on the AD2S1210 The and DVpp voltages
56. pdate the information in the position and velocity registers Reading from the AD2S1210 in Normal Mode To read back position or velocity data from the AD2S1210 the information stored in the position and velocity registers should first be updated using the SAMPLE input A high to low transition on the SAMPLE input transfers the data from the position and velocity integrators to the position and velocity registers The fault register is also updated on the high to low transition of the SAMPLE input The status of the A0 and A1 inputs determines whether the position or velocity data is transferred to the output register In normal mode the output shift register is 24 bits wide The 24 bit word consists of 16 bits of angular data position or velocity data followed by the 8 bit fault register data Data is read out MSB first Bit 23 on the SDO pin Bit 23 through Bit 8 correspond to the angular information The angular position data format is unsigned binary with all 0s corresponding to 0 degrees and all information If the user does not require the fault information the WR FSYNC can be pulled high after the16 SCLK rising edge Clearing the Fault Register The LOT pin and or the DOS pin of the AD2S1210 are taken low to indicate that a fault has been detected The AD2S1210 is capable of detecting eight separate fault conditions To determine which condition triggered the fault indication the user is required to enter configuration
57. r position or angular velocity data The A0 and A1 inputs are used to determine whether the AD2S1210 is in configuration mode and to determine whether the position or velocity data is supplied to the output pins see Table 8 Setting the Excitation Frequency The excitation frequency of the AD2S1210 is set by writing a frequency control word to the excitation frequency register Address 0x91 see the Register Map section FCW Excitation Frequency FCW x fus where FCW ist 1 frequency of the 2 0 The specified range of the excitation frequency is from 2 kHz to 20 kHz and can be set in increments of 250 Hz To achieve the angular accuracy specifications in Table 1 the excitation frequency should be selected as outlined in Table 7 Table 7 Recommended Excitation Frequency vs Resolution fcu 8 192 MHz Note that the recommended frequency range for each resolution and bandwidth as outlined in Table 7 are defined for a clock frequency of 8 192 MHz The recommended excitation frequency range scales with the clock frequency of the AD2S1210 The default excitation frequency of the AD2S1210 is 10 kHz when operated with a clock frequency of 8 192 MHz AO A1 Inputs The AD2S1210 allows the user to read the angular position or the angular velocity data directly from the parallel outputs or through the serial interface The required information can be selected using the A0 and A1 inputs These inputs should also be used to put th
58. requencies between 2 kHz and 20 kHz 5 Triple format position data Absolute 10 bit to 16 bit angular position data is accessed via either a 16 bit parallel port or a 4 wire serial interface Incremental encoder emulation is in standard A quad B format with direction output available 6 Digital velocity output 10 bit to 16 bit signed digital velocity accessed via either a 16 bit parallel port or a 4 wire serial interface One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2008 Analog Devices Inc All rights reserved TABLE OF CONTENTS Features e aaa LR uer 1 Applications ise itte te RC RUND 1 Functional Block Diagram eere 1 General Description usa eterne 1 Product Highlights 1 eene 1 Revision History 2 Specifications ecce etiem ee eene ede 3 Timing Specifications a 6 Absolute Maximum Ratings asa 8 ESD Caution ioco ua ies 8 Pin Configuration and Function 9 Typical Performance Characteristics sss 11 Resolver Format Signals 15 Theory of Operation 16 Resolver to Digital Conversion see 16 Detection Circuit seniri n et es 16 On Board Programmable Sinusoidal Oscillator 18
59. rt WNN Rev 0 Page 34 of 36 BDTI C comi NOTES ww BDI C com NOTES ww BDI C com 2008 Analog Devices Inc All rights reserved Trademarks and AN ALOG registered trademarks are the property of their respective owners DEVICES Rev 0 Page 36 of 36
60. uired to read and clear the fault register is indicated as traurr and is defined by the interface speed of the DSP microprocessor used in the application Note Table 27 vs Resolution fcu 8 1 Resolution Bits trrack ms 10 10 12 20 14 25 16 60 T RESET trrack lt ae trAuLT cor XXE a os Figure 37 Power Supply Sequencing and Reset 07457 036 Rev 0 Page 31 of 36 CIRCUIT DYNAMICS LOOP RESPONSE MODEL ACCELERATION VELOCITY siwcostooKUP LOOKUP c a 07467 037 Figure 38 RDC System Response EM Diagram The RDC is a mixed signal device that uses two ADCs to digitize signals from the resolver and a Type II tracking loop to convert these to digital position and velocity words The first gain stage consists of the ADC gain on the sine cosine inputs and the gain of the error signal into the first integrator The first integrator generates a signal proportional to velocity The compensation filter contains a pole and a zero that are used to provide phase margin and reduce high frequency noise gain The second integrator is the same as the first and generates the position output from the velocity signal The sin cos lookup has unity gain The values for the k1 k2 a b and c parameters are outlined in Table 28 The following equations outline the transfer functions of the individual blocks as shown in Figure 38 whi
61. uration Parity Error The AD2S1210 includes a number of user programmable registers that allow the user to configure the part Each read write register on the AD2S1210 is programmed with seven bits of informa tion by the user The 8 bit is reserved as a parity error bit In the AD2S1210 i occurred Config and LOT pins latching as logic low outputs Configuration parity error is also indicated by Bit DO of the fault register being set high In the event that a parity error occurs it is recommended that the user reset the part using the RESET pin Phase Lock Error The AD2S1210 indicates that a phase lock error has occurred if the difference between the phase of the excitation frequency and the phase of the sine and cosine signals exceeds the specified phase lock range Phase lock error is indicated by a logic low on the LOT pin and is not latched Phase lock error is also indicated by Bit D1 of the fault register being set high ON BOARD PROGRAMMABLE SINUSOIDAL OSCILLATOR An on board oscillator provides the sinusoidal excitation signal EXC to the resolver as well as its complemented signal EXC The frequency of this reference signal is programmable to a number of standard frequencies between 2 kHz and 20 kHz The amplitude of this signal is 3 6 V p p and is centered on 2 5 V The reference excitation output of the AD2S1210 needs an external buffer amplifier to provide gain and the additional current to drive a resolver
62. written to the AD2S1210 is low Note that when a data word is written to the AD2S1210 the 5 is internally reconfigured as a parity bit When reading data from any of the read write registers see Table 10 the parity of Bit D6 to Bit DO is recalculated and compared to the previously stored parity bit The MSB ofthe 8 bit output is used to indicate whether a configuration error has occurred If the MSB is returned high this indicates that the data read back from the device does not match the configuration data written to the device in the previous write cycle Phase Lock Range The phase lock range allows the AD2S1210 to compensate for phase errors between the excitation frequency and the sine cosine inputs The recommended mode of operation is to use the default phase lock range of 44 If additional phase lock range is required a range of 360 can be set However in this mode of operation the AD2S1210 should be reset following a loss of signal error Failure to do so may result in a 180 error in the angular output data Hysteresis The 25191 e the output g register When operating in a noisy environment this can be used to prevent flicker the LSB On the AD2S1210 the maximum tracking rate is defined by the bandwidth Each resolution setting is internally configured with a different bandwidth as outlined in Table 1 The maximum tracking rate and the bandwidth are inversely proportional to the resolution th

ANALOG DEVICES AD2S1210 handbook

Contents

Download Pdf Manuals

Related Search

Related Contents