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ANALOG DEVICES ADE7753 handbook(1)

1. 16 Zero Crossing Detection 17 Period Measuremient uoe tee ptite e tm 18 Power Supply Monitor sentent 18 Line Voltage Sag Detection sse 18 Peak Detection 4 1 YAY LA J Ld A I9 ADE7753 Interrupts eee art b 20 Temperature Measurement sse 21 ADE7753 Analog to Digital Conversion 21 Channel AD P PI ESTA titi Eai 22 Channel 2 AD esent REDE REROE Ie OR IEEE ERR 24 Phase Compensation c ssssssesesssoiviesssrseressnesrsotsvenesesssevenescvenvisniee 26 Active Power Calculation senes 27 Energy Calculation eei ep Ip REUS 28 Power Offset Calibration 30 REVISION HISTORY 6 04 Changed from Rev 0 to Rev A Changes IEC Standards sse 1 Changes to Phase Error Between Channels Definition 7 Changes to Figure24 nunueni tenir direi rita tg 13 Changes to CH2OS Register sse 16 Change to the Period Measurement Section 18 Change to Temperature Measurement Section 21 Changes to Figure 69 sse 31 Energy to Frequency Conversion sse 30 Line Cycle Energy Accumulation Mode 32 Positive Only Accumulation Mode sss 32 No L ad Threshold etti 32 Reactive Power Calculation sse 33 Sign of
2. Table 1 Parameter Spec Unit Test Conditions Comments ENERGY MEASUREMENT ACCURACY Active Power Measurement Error CLKIN 3 579545 MHz Channel 1 Range 0 5 V Full Scale Channel 2 300 mV rms 60 Hz gain 2 Gain 1 0 1 96 typ Over a dynamic range 1000 to 1 Gain 2 2 0 1 96 typ Over a dynamic range 1000 to 1 Gain 4 0 1 96 typ Over a dynamic range 1000 to 1 Gain 8 0 1 96 typ Over a dynamic range 1000 to 1 Channel 1 Range 0 25 V Full Scale Gain 1 0 1 96 typ Over a dynamic range 1000 to 1 Gain 2 0 1 96 typ Over a dynamic range 1000 to 1 Gain 4 0 1 96 typ Over a dynamic range 1000 to 1 Gain 8 0 2 96 typ Over a dynamic range 1000 to 1 Channel 1 Range 0 125 V Full Scale Gain 1 0 1 96 typ Over a dynamic range 1000 to 1 Gain 2 0 1 96 typ Over a dynamic range 1000 to 1 Gain 4 0 2 96 typ Over a dynamic range 1000 to 1 Gain 8 0 2 96 typ Over a dynamic range 1000 to 1 Active Power Measurement Bandwidth 14 kHz Phase Error 1 between Channels 0 05 max Line Frequency 45 Hz to 65 Hz HPF on AC Power Supply Rejection AVpp DVpo z SV 175 mV rins 120 Hz Output Frequency Variation dF 0 25 typ Channel 1 20 mV rms gain J 6 range 0 5 V Channel 2 300 mV rms 60 Hz gain 1 DC Power Supply Rejection AVop DVoo 5 V 250 mV dc Output Frequency Variation CF 0 3 typ Channel 1 20 mV rms 60 Hz gain 16 range 0 5 V Channel 2 300 mV rms 60 Hz gain 1 IRMS Measurement Error 0 5 typ Over a dynamic
3. YES RESET THE INTERRUPT STATUS READ REGISTER ADDR 0x0C YES READ LINE accus iad EE ADDR 0x04 T i CALCULATE APOS SEE EQUATION 49 ee pgs WRITE APOS VALUE TO THE APOS REGISTER ADDR 0x11 02875 A 009 Figure 83 Calibrating Watt Offset with an Accurate Source For this example Meter Constant MeterConstant imp Wh 3 2 Line Voltage Vnomina 220 V Line Frequency fi 50 Hz CF Numerator CFNUM 0 CF Denominator CFDEN 489 Base Current In 10A Half Line Cycles Used at Base Current LINECYCus 2000 Period Register Reading PERIOD 8959 Clock Frequency CLKIN 3 579545 MHz Expected LAENERGY Register Value at Base Current from the Watt Gain section LAENERGY ig expected 19186 Minimum Current Ium 40 mA Number of Half Line Cycles used at Minimum Current LINECYCumm 35700 Active energy Reading at Minimum Current LAENERGYimin nominal 1395 LAENERG Yimineexpected INT Dum x LAENERGY ppexpected PANETT ane 53 Ig LINECYC p LAENERG Yimin expected INT 99 9185 25700 INT 1369 80 1370 10 2000 where LAENERGY peexpectea is the expected LAENERGY reading at I from the watt gain calibration LINECYCim is the number of half line cycles that energy is accumulated over when measuring at Imn More line cycles could be required at the minimum current to minimize the effect of quantization error on the offset calibration For example if a test c
4. FULL SCALE CURRENT 02875 0 006 02875 0 010 Figure 9 Active Energy Error as a Percentage of Reading Gain 8 over Figure 6 Active Energy Error as a Percentage of Reading Gain 1 over Temperature with External Reference and Integrator Off Power Factor with Internal Reference and Integrator Off 0 4 0 6 GAIN 8 0 3 INTEGRATOR OFF INTERNAL REFERENCE 0 4 85 C PF 1 Hl 1 40 C PF 1 0 2 0 1 s a es 0 P E B 01 MM J amp ou T 0 2 0 4 0 3 0 4 0 6 0 1 1 10 100 0 1 1 10 100 FULL SCALE CURRENT FULL SCALE CURRENT 02875 0 008 02875 0 011 Figure 7 Active Energy as a Percentage of Reading Gain 8 over Figure 10 Active Energy Error as a Percentage of Reading Gain 8 over Temperature with Internal Reference and Integrator Off Power Factor with External Reference and Integrator Off 0 8 0 5 GAIN 8 INTEGRATOR OFF 0 4 oe INTERNAL REFERENCE 0 3 0 4 0 2 g 02 25 C PF 1 S ia oc o o o 4 4 TT wW 0 2 25 C PF 0 5 704 _a0 c PF 0 5 I 485 C PF 0 5 0 6 0 1 1 10 100 FULL SCALE CURRENT FULL SCALE CURRENT 02875 0 009 02875 0 012 Figure 11 Reactive Ene
5. 02875 0 084 ADE7753 INTERRUPT STATUS REGISTER 0xOB RESET INTERRUPT STATUS REGISTER 0x0C INTERRUPT ENABLE REGISTER 0x0A The status register is used by the MCU to determine the source of an interrupt request IRQ When an interrupt event occurs in the ADE7753 the corresponding flag in the interrupt status register is set to logic high If the enable bit for this flag is Logic 1 in the interrupt enable register the IRQ logic output goes active low When the MCU services the interrupt it must first carry out a read from the interrupt status register to determine the source of the interrupt Table 13 Interrupt Status Register Reset Interrupt Status Register and Interrupt Enable Register Bit Interrupt Location Flag Description 0 AEHF Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the active energy register i e the AENERGY register is half full 1 SAG Indicates that an interrupt was caused by a SAG on the line voltage 2 CYCEND Indicates the end of energy accumulation over an integer number of half line cycles as defined by the content of the LINECYC register see the Line Cycle Energy Accumulation Mode section 3 WSMP Indicates that new data is present in the waveform register 4 ZX This status bit reflects the status of the ZX logic ouput see the Zero Crossing Detection section 5 TEMP Indicates that a temperature conversion result is available
6. CFDEN SET Irgsr Ip Vtest Vnom PF 1 SET HALF LINECYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR 0x1C SET MODE FOR LINE CYCLE ACCUMULATION ADDR 0x09 0x0080 ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR 0x0A 0x04 RESET THE INTERRUPT STATUS READ REGISTER ADDR 0x0C E YES RESET THE INTERRUPT STATUS READ REGISTER ADDR 0x0C YES READ LINE ACCUMULATION ENERGY ADDR 0x04 CALCULATE WGAIN SEE EQUATION 47 WRITE WGAIN VALUE TO THE WGAIN REGISTER ADDR 0x12 2 S amp E ge E S S Figure 81 Calibrating Watt Gain Using an Accurate Source Equation 47 describes the relationship between the expected LAENERGY value and the LAENERGY measured in the test condition LAENERGY ppexpc WGAIN INT Brerpected x 212 47 LAENERGY g nominal The nominal LAENERGY reading LAENERGY mona is the LAENERGY reading with the test current applied The expected LAENERGY reading is calculated from the following equation LAENERGY expected CF ig expected X Accumulation Time s CFNUM 1 CFDEN 1 INT 48 x WDIV where CFisexpectea Hz is calculated from Equation 34 accumula tion time is calculated from Equation 37 and the line period is determined from the PERIOD register according to Equation 38 For this example Meter Constant MeterConstant imp Wh 3 2 Test Current Ih 10A Line Voltage Vnominal 220 V Line Frequency fi 50 Hz Half Line Cycles LINECYCi 20
7. OxFF 0x0 OxFF OxFF 0x0 0x0 0x0 0x0 0x0 NNN CC Power Gain Adjust This is a 12 bit register The active power calculation can be calibrated by writing to this register The calibration range is 50 of the nominal full scale active power The resolution of the gain adjust is 0 0244 LSB see the Calibrating an Energy Meter Based on the ADE7753 section Active Energy Divider Register The internal active energy register is divided by the value of this register before being stored in the AENERGY register CF Frequency Divider Numerator Register The output frequency on the CF pin is adjusted by writing to this 12 bit read write register see the Energy to Frequency Conversion section CF Frequency Divider Denominator Register The output frequency on the CF pin is adjusted by writing to this 12 bit read write register see the Energy to Frequency Conversion section Channel 1 RMS Value Current Channel Channel 2 RMS Value Voltage Channel Channel 1 RMS Offset Correction Register Channel 2 RMS Offset Correction Register Apparent Gain Register Apparent power calculation can be calibrated by writing to this register The calibration range is 50 of the nominal full scale real power The resolution of the gain adjust is 0 02444 LSB Apparent Energy Divider Register The internal apparent energy register is divided by the value of this register before being stored in the VAENERGY register Line Cycle Energ
8. and the contents represent one more than the desired number of full line cycles For example when the sag cycle SAGCYC 7 0 contains 0x04 the SAG pin goes active low at the end of the third line cycle for which the line voltage Channel 2 signal falls below the threshold if the DISSAG bit in the mode register is Logic 0 As is the case when zero crossings are no longer detected the sag event is also recorded by setting the SAG flag in the interrupt status register If the SAG enable bit is set to Logic 1 the IRQ logic output goes active low see the ADEZ753 Interrupts section The SAG pingoeSildgidhigh again when the absolute value of the signal on NAA Jexceedsthe sag level set in the sag level register This is shown in Figure 43 when the SAG pin goes high again during the fifth line cycle from the time when the signal on Channel 2 first dropped below the threshold level Sag Level Set The contents of the sag level register 1 byte are compared to the absolute value of the most significant byte output from LPF1 after it is shifted left by one bit thus for example the nominal maximum code from LPF1 with a full scale signal on Channel 2 is 0x2518 see the Channel 2 Sampling section Shifting one bit left gives 0x4A30 Therefore writing 0x4A to the SAG level register puts the sag detection level at full scale Writing 0x00 or 0x01 puts the sag detection level at 0 The SAG level register is compared to the most significant
9. Output Impedance 3 4 kQ min Temperature Coefficient 30 ppm C typ CLKIN All specifications CLKIN of 3 579545 MHz Input Clock Frequency 4 MHz max 1 MHz min LOGIC INPUTS RESET DIN SCLK CLKIN and CS Input High Voltage Vinx 24 V min DVpp 5 V 1096 Input Low Voltage Vint 0 8 V max DVpp 5 V 1096 Input Current lin 3 yA max Typically 10 nA Vin 0 V to DVpp Input Capacitance Cin 10 pF max LOGIC OUTPUTS 5 J SAG and IRQ ng Opentdrain outputs 1 0 k Mi udfesistor Output High Voltage Vou V min Source 5 MA i Output Low Voltage VoL 0 4 V max Isink 0 8 mA ZX and DOUT Output High Voltage Vou 4 V min Isource 5 MA Output Low Voltage Vor 0 4 V max Isink 0 8 MA CF Output High Voltage Vou 4 V min Isource 5 mA Output Low Voltage Vor 1 V max Isink 7 mA POWER SUPPLY For specified performance AVDD 4 75 V min 5V 596 5 25 V max 5V 4 596 DVDD 4 75 V min 5V 596 5 25 V max 5V 4 596 Albo 3 mA max Typically 2 0 mA Dibo 4 mA max Typically 3 0 mA 1 See the plots in the Typical Performance Characteristics section See the Terminology section for explanation of specifications 3See the Analog Inputs section 2 1V 02875 0 002 Figure 2 Load Circuit for Timing Specifications Rev A Page 4 of 60 TIMING CHARACTERISTICS ADE7753 AVpp DVpp 5 V 5 AGND DGND 0 V on chip reference CLKIN 3 579545 MHz XTAL Tmn to Tmax 40 C to 85 C Table 2 Parameter Spec Unit Test Condit
10. SAMPLING SIGNAL _ FILTER FREQUENCY NOISE o 2 447 894 FREQUENCY kHz HIGH RESOLUTION SIGNAL OUTPUT FROM DIGITAL LPF i l Pd l NOISE l do 2 447 894 FREQUENCY kHz 02875 0 047 Figure 48 Noise Reduction Due to Oversampling and Noise Shaping in the Analog Modulator Rev A Page 21 of 60 ADE7753 Antialias Filter Figure 47 also shows an analog low pass filter RC on the input to the modulator This filter is present to prevent aliasing Aliasing is an artifact of all sampled systems Aliasing means that frequency components in the input signal to the ADC which are higher than half the sampling rate of the ADC appear in the sampled signal at a frequency below half the sampling rate Figure 49 illustrates the effect Frequency components arrows shown in black above half the sampling frequency also know as the Nyquist frequency i e 447 kHz are imaged or folded back down below 447 kHz This happens with all ADCs regardless of the architecture In the example shown only frequencies near the sampling frequency i e 894 kHz move into the band of interest for metering i e 40 Hz to 2 kHz This allows the use of a very simple LPF low pass filter to attenuate high frequency near 900 kHz noise and prevents distortion in the band of interest For conventional current sensors a simple RC filter single pole LPF with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 894 kHz s
11. 0 E IRMSOS 11 0 Le Be VAGAIN 11 0 VRMSOS 11 0 h e REGISTERS AND SERIAL INTERFACE 24V REFERENCE AGND REFiyouT CLKIN CLKOUT U S Patents 5 745 323 5 760 617 5 862 069 5 872 469 others pending Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 02875 A 001 DIN DOUTSCLK CS iRG One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved ADE7753 TABLE OF CONTENTS Specifications ivo XL RETIRER UNA RSEN TRY EE 3 Timing Characteristics sssseeeenee netten 5 Absolute Maximum Ratings eeeeeeeeeentententnns 6 ESD Caution ie eoe RR 6 Termin logy iine EE TEENE 7 Pin Configuration and Function Descriptions s 8 Typical Performance Characteristics sss 10 Theory of Op ration t RI ass 15 Analog Inp uts nte n ORERNC EUER 15 di dt Current Sensor and Digital Integrator
12. 1 due to the external transducer To cancel the lead 0 1 in Channel 1 a phase lead must also be introduced into Channel 2 0 18 The resolution of the phase adjustment allows the introduction 0 16 of a phase lead in increment of 0 048 The phase lead is achieved 0 14 by introducing a time advance into Channel 2 A time advance of 4 48 us is made by writing 2 0x0B to the time delay block thus reducing the amount of time delay by 4 48 us or equiva PHASE Degrees e e lently a phase lead of approximately 0 1 at line frequency of 0 08 60 Hz 0x0B represents 2 because the register is centered with 0 0 06 at OxOD 0 04 0 02 40 45 50 55 60 65 70 FREQUENCY Hz 02875 0 058 Figure 59 Combined Phase Response of the HPF and Phase Compensation 40 Hz to 70 Hz Rev A Page 26 of 60 54 56 58 60 62 64 66 FREQUENCY Hz 02875 0 059 Figure 60 Combined Gain Response of the HPF and Phase Compensation ACTIVE POWER CALCULATION Power is defined as the rate of energy flow from source to load It is defined as the product of the voltage and current wave forms The resulting waveform is called the instantaneous power signal and is equal to the rate of energy flow at every instant of time The unit of power is the watt or joules sec Equation 9 gives an expression for the instantaneous power sig
13. 39 show the magnitude and phase response of the digital integrator 10 GAIN dB S e 102 103 FREQUENCY Hz 02875 0 036 Figure 36 Combined Gain Response of the Digital Integrator and Phase Compensator Rev A Page 16 of 60 PHASE Degrees GAIN dB hob f PHASE Degrees 88 0 88 5 89 0 89 5 90 0 90 5 102 103 FREQUENCY Hz 02875 0 037 Figure 37 Combined Phase Response of the Digital Integrator and Phase Compensator ira o o a o 40 45 50 55 60 65 70 FREQUENCY Hz 02875 0 038 Figure 38 Combined Gain Response of the Digital Integrator and Phase Compensator 40 Hz to 70 Hz 40 45 50 55 60 65 70 FREQUENCY Hz pasao Figure 39 Combined Phase Response of the Digital Integrator and Phase Compensator 40 Hz to 70 Hz ADE7753 Note that the integrator has a 20 dB dec attenuation and an approximately 90 phase shift When combined with a di dt sensor the resulting magnitude and phase response should be a flat gain over the frequency band of interest The di dt sensor has a 20 dB dec gain associated with it It also generates signifi cant high frequency noise therefore a more effective anti aliasing filter is needed to avoid noise due to aliasing see the Antialias Filter section When the di
14. ADE7753 Serial Interface section should be reviewed first before reviewing the interrupt timing As previously described when the IRQ output goes low the MCU ISR must read the interrupt status register to determine the source of the interrupt When reading the status register contents the IRQ output is set high on the last falling edge of SCLK of the first byte transfer read interrupt status register command The IRQ output is held high until the last bit of the next 15 bit transfer is shifted out interrupt status register contents see Figure 45 If an interrupt is pending at this time the IRQ output goes low again If no interrupt is pending the IRQ output stays high TEMPERATURE MEASUREMENT The ADE7753 also includes an on chip temperature sensor A temperature measurement can be made by setting Bit 5 in the mode register When Bit 5 is set logic high in the mode register the ADE7753 initiates a temperature measurement on the next zero crossing When the zero crossing on Channel 2 is detected the voltage output from the temperature sensing circuit is connected to ADCI Channel 1 for digitizing The resulting code is processed and placed in the temperature register TEMP 7 0 approximately 26 us later 24 CLKIN cycles If enabled in the interrupt enable register Bit 5 the IRQ output goes active low when the temperature conversiomis fiished The contents of the temper MM are signed twos complement with a resolution of app
15. AENERGY RAENERGY LAENERGY VAENERGY RVAENERGY LVAENERGY LVARENERGY MODE IROEN STATUS RSTSTATUS CH10S CH20S GAIN PHCAL APOS R R W R W R W R W R W 24 24 24 24 24 24 24 24 16 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x000C 0x40 0x0 0x0 0x00 0x0 0x0 0x0D 0x0 Waveform Register This read only register contains the sampled waveform data from either Channel 1 Channel 2 or the active power signal The data source and the length of the waveform registers are selected by data Bits 14 and 13 in the mode register see the Channel 1 Sampling and Channel 2 Sampling sections Active Energy Register Active power is accumulated integrated over time in this 24 bit read only register see the Energy Calculation section Same as the active energy register except that the register is reset to 0 following a read operation Line Accumulation Active Energy Register The instantaneous active power is accumulated in this read only register over the LINCYC number of half line cycles Apparent Energy Register Apparent power is accumulated over time in this read only register Same as the VAENERGY register except that the register is reset to 0 following a read operation Line Accumulation Apparent Energy Register The instantaneous real power is accumulated in this read only register over the LINECYC number of half line cy
16. Channel 1 current and the power calculation is not affected by this offset The offsets can be removed by performing an offset calibration see the Analog Inputs section Gain Error The difference between the measured ADC output code minus the offset and the ideal output code see the Channel 1 ADC and Channel 2 ADC sections It is measured for each of the input ranges on Channel 1 0 5 V 0 25 V and 0 125 V The difference is expressed as a qe of the ideal code Rev A Page 7 of 60 ADE7753 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DOUT SCLK cs CLKOUT CLKIN IRQ SAG ZX CF 02875 0 005 Figure 5 Pin Configuration SSOP Package Table 4 Pin Function Descriptions Pin No Mnemonic Description 1 RESET Reset Pin for the ADE7753 A logic low on this pin holds the ADCs and digital circuitry including the serial interface in a reset condition 2 DVDD Digital Power Supply This pin provides the supply voltage for the digital circuitry in the ADE7753 The supply voltage should be maintained at 5 V 5 for specified operation This pin should be decoupled to DGND with a 10 uF capacitor in parallel with a ceramic 100 nF capacitor 3 AVDD Analog Power Supply This pin provides the supply voltage for the analog circuitry in the ADE7753 The supply should be maintained at 5 V 5 for specified operation Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper d
17. GAIN 8 GAIN 8 INTEGRATOR OFF 0 8 INTEGRATOR ON INTERNAL REF 40 C PF 0 5 INTERNAL REFERENCE 0 6 0 4 02 85 C PF 0 5 S tc 0 T Q 25 C PF 20 1 5 0 2 04 0 6 25 C PF 0 5 0 8 1 0 0 1 1 10 100 FULL SCALE CURRENT FULL SCALE CURRENT 02875 0 020 02875 0 024 Figure 22 Reactive Energy Error as a Percentage of Reading Gain 8 over Figure 19 IRMS Error as a Percentage of Reading Gain 8 with Power Factor with Internal Reference and Integrator On Internal Reference and Integrator Off 1 0 0 8 INTEGRATOR ON 0 6 40 C PF 0 0 4 0 2 25 C PF 0 ERROR ERROR 85 C PF 0 0 1 1 10 100 FULL SCALE CURRENT FULL SCALE CURRENT 02875 0 022 02875 0 025 Figure 23 Reactive Energy Error as a Percentage of Reading Gain 8 over Figure 20 Active Energy Error as a Percentage of Reading Gain 8 over Temperature with Internal Reference and Integrator On Power Factor with Internal Reference and Integrator On Rev A Page 12 of 60 ADE7753 GAIN 8 GAIN 1 INTEGRATOR ON EXTERNAL REFERENCE IN
18. Logic 1 see the Interrupt Status Register section If the enable bit for this interrupt in the interrupt enable register is Logic 1 then the IRQ logic output goes active low The flag bits in the status register are set irrespective of the state of the enable bits To determine the source of the interrupt the system master MCU should perform a read from the status register with reset RSTSTATUS 15 0 This is achieved by carrying out a read from Address 0x0C The IRQ output goes logic high on completion of the interrupt status register read command see the Interrupt Timing section When carrying out a read with reset the ADE7753 is designed to ensure that no interrupt events are missed If an interrupt event occurs just as the status register is being read the event is not lost and the IRQ logic output is guaranteed to go high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt See the next section for a more detailed description IRQ MCU PROGRAM SEQUENCE GLOBAL INTERRUPT MASK SET CLEAR MCU INTERRUPT FLAG STATUS WITH RESET 0x05 Using the ADE7753 Interrupts with an MCU Figure 46 shows a timing diagram with a suggested implemen tation of ADE7753 interrupt management using an MCU At time ti the IRQ line goes active low indicating that one or more interrupt events have occurred in the ADE7753 The IRQ logic output should be ti
19. Reactive Power Calculation sss 34 Apparent Power Calculation sse 34 Apparent Energy Calculation sse 35 Line Apparent Energy Accumulation sss 36 Energies Scaling rite ti tede ient 37 Calibrating an Energy Meter Based on the ADE7753 37 CERIN Frequeney 5 2 nini ia ot esee een 47 Suspending ADE7753 Functionality ss 47 Checksum Register a ertt 47 ADEZ753 Serial Interface 3 j lipatvstpaetvatistbanai eae 48 ADEZ753 RegIStets ii e e rete iatu rente ta teb utes snak 51 ADE7753 Register Descriptions eee 54 Communications Register eee 54 Mode Register 0x09 sese 54 Interrupt Status Register 0x0B Reset Interrupt Status Register 0x0C Interrupt Enable Register 0x0A 56 CH1OS Register OXOD oe eeeeeseeseeseeseeseesesseseseeseeaeeneeneesesees 57 Outline DimensiQhs tti etes 58 Ordering Guide em 58 Changes to Figure 71 eere teret Sosro 33 Changes to the Apparent Energy Section sss 36 Changes to Energies Scaling Section sss 37 Changes to Calibration Section sse 37 8 03 Revision 0 Initial Version Rev A Page 2 of 60 SPECIFICATIONS ADE7753 AVpp DVpp 5 V 5 AGND DGND 0 V on chip reference CLKIN 3 579545 MHz XTAL Tmn to Tmax 40 C to 85 C
20. THE REFERENCE METER OUTPUT CALCULATE PHCAL SEE EQUATION 59 WRITE PHCAL VALUE TO THE PHCAL REGISTER ADDR 0x10 02875 A 010 Figure 84 Calibrating Phase Using a Reference Meter For this example CF 96 Error at PF 5 Inductive ERRORcrunpr 5 0 215 PERIOD Register Reading PERIOD 8959 Then PHCAL is 11 using Equations 57 through 59 Error 0 215 100 0 00215 a Phase Error eS wee 0 07 45 PHCAL t 0 07 x sox00 2 13 11 09 PHCAL can be expressed as follows PHCAL 43 2n Note that PHCAL is a signed twos complement register TE Ars Error PERIOD 0x0D 62 Setting the PHCAL register to 11 provides a phase correction of 0 08 to correct the phase lead 360 Phase Correction PHCAL 0x0D x PERIOD Phase Correction 11 0x0D x Si AR 0 08 8960 Rev A Page 43 of 60 ADE7753 Calibrating Phase with an Accurate Source Example With an accurate source line cycle accumulation is a good method of calibrating phase error The value of LAENERGY must be obtained at two power factors PF 1 and PF 0 5 inductive SET hesr lb Vest Vnom PF 0 5 SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR 0x1C SET MODE FOR LINE CYCLE ACCUMULATION ADDR 0x09 0x0080 ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR 0x0A 0x04 RESET THE INTERRUPT STATUS READ REGISTER ADDR 0x0C YES READ LI
21. Voltage to DGND 0 3 V to DVDD 0 3 V device reliability Digital Output Voltage to DGND 0 3 V to DVDD 0 3 V Operating Temperature Range Industrial 40 C to 85 C Storage Temperature Range 65 C to 150 C Junction Temperature 150 C 20 Lead SSOP Power Dissipation 450 mW Osa Thermal Impedance 112 C W Lead Temperature Soldering Vapor Phase 60 sec 215 C Infrared 15 sec 220 C 1 N AL MWN i ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features WARNING SI proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Sprit Ate electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance ESD SENSITIVE DEVICE degradation or loss of functionality Rev A Page 6 of 60 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7753 is defined by the following formula Energy Register ADE7753 True Energy True Energy Percentage Error x 100 Phase Error between Channels The digital integrator and the high pass filter HPF in Channel 1 have a non ideal phase response To offset this phase response and equalize the phase response between channels two phase correction networks are placed in Channel 1 one for the digital integ
22. accessible through a read to the active energy register AENERGY 23 0 A read to the RAENERGY register returns the content of the AENERGY register and the upper 24 bits of the internal register are cleared As shown in Figure 65 the active power signal is accumulated in an internal 49 bit signed register The active power signal can be read from the waveform register by setting MODE 14 13 0 0 and setting the WSMP bit Bit 3 in the interrupt enable register to 1 Like the Channel 1 and Channel 2 waveform sampling modes the waveform date is available at sample rates of 27 9 kSPS 14 kSPS 7 kSPS or 3 5 kSPS see Figure 52 Figure 66 shows this energy accumulation for full scale signals sinusoidal on the analog inputs The three curves displayed illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are 0x7FF 0x000 and 0x800 The watt gain register is used to carry out power calibration in the ADE7753 As shown the fastest integration time occurs when the watt gain register is set to maximum full scale i e OX7FF AENERGY 28 0 i err Dr re WGAIN Ox7FF C WGAIN 0x000 WGAIN 0x800 Ox3F FFFF 0x00 0000 TIME minutes 0x40 0000 0x80 0000 02875 0 065 Figure 66 Energy Register Rollover Time for Full Scale Power Minimum and Maximum Power Gain Note that the energy register contents rolls over to full
23. as Channel 1 The Channel 2 waveform sample is a 16 bit word and sign extended to 24 bits For normal operation the differential voltage signal between V2P and V2N should not exceed 0 5 V With maximum voltage input 0 5 V at PGA gain of 1 the output from the ADC swings between 0x2852 and 0xD7AE 10 322d However before being passed to the wave form register the ADC output is passed through a single pole low pass filter with a cutoff frequency of 140 Hz The plots in Figure 54 show the magnitude and phase response of this filter PHASE Degrees 101 102 103 FREQUENCY Hz 02875 0 053 Figure 54 Magnitude and Phase Response of LPF1 The LPF1 has the effect of attenuating the signal For example if the line frequency is 60 Hz then the signal at the output of LPF1 is attenuated by about 8 0 919 0 73 dB 5 Inc Note LPF1 does not affect the active power calculation The signal processing chain in Channel 2 is illustrated in Figure 55 Rev A Page 24 of 60 2 42V x1 x2 x4 REFERENCE x8 x16 ADE7753 V2P GAIN 7 5 4 ACTIVE AND REACTIVE vaia ENERGY CALCULATION V2N VRMS CALCULATION AND WAVEFORM ANALOG v SAMPLING INPUT RANGE LPF OUTPUT PEAK SAG ZX 0 5V 0 25 0 125 WORD RANGE 62 5mV 31 25mV 0x2852 ov 0x2581 0x0000 OxDAE8 OxD7AE 02875 0 054 Figure 55 ADC and Signal Processing in Channel 2 VOLTAGE SIGNAL V t 0x2518
24. bit twos complement VRMSOS register is not enough the voltage channel offset register CH2OS can be used to correct the VRMS offset Current rms compensation is performed before the square root IRMS IRMS0 32768 x IRMSOS 66 where IRMSO0 is the rms measurement without ffset c rrection The current rms calculation is linear from full scale to full scale 100 J To calibrate this offset two IRMS measurements are required for example at I and Imax 50 Imax is set at half of the full scale analog input range so the smallest linear IRMS reading is at Imax 50 1 I x IRMS 1 7 x IRMS IRMSOS ee um TURMSI 67 32768 L I where IRMS and IRMS are rms register values without offset correction for input I and I5 respectively ADE7753 Apparent Energy Apparent energy gain calibration is provided for both meter to meter gain adjustment and for setting the VAh LSB constant VAENERGY 68 VAGAIN VADIV 1 VAENERGY inia X 1 EE VADIV is similar to the CFDEN for the watt hour calibration It should be the same across all meters and determines the VAh LSB constant VAGAIN is used to calibrate individual meters Apparent energy gain calibration should be performed before rms offset correction to make most efficient use of the current test points Apparent energy gain and watt gain compensation require testing at I while rms and watt offset correction require a lower test current App
25. byte of a waveform sample after the shift left and detection is made when the contents of the sag level register are greater PEAK DETECTION The ADE7753 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value Figure 44 illustrates the behavior of the peak detection for the voltage channel Both Channel 1 and Channel 2 are monitored at the same time ADE7753 V2 VPKLVL 7 0 H p ef PKV RESET LOW WHEN RSTSTATUS REGISTER IS READ PKV INTERRUPT FLAG BIT 8 OF STATUS REGISTER READ RSTSTATUS REGISTER 02875 0 088 Figure 44 ADE7753 Peak Level Detection Figure 44 shows a line voltage exceeding a threshold that is set in the voltage peak register VPKLVL 7 0 The voltage peak event is recorded by setting the PKV flag in the interrupt status register If the PKV enable bit is set to Logic 1 in the interrupt mask register the IRQ logic output goes active low Similarly the current peak event is recorded by setting the PKI flag in the interrupt status register see the ADE7753 Interrupts section Peak Level Set The contents of the VPKLVL and IPKLVL registers are respectively compared to the absolute value of Channel 1 and Channel 2 after they are multiplied by 2 Thus for example the nomira irm code po the Channel 1 ADC with a full scale Signal is 0x28 M ECf sedthe Channel 1 Sampling section Multiplying by 2 gives 0x5
26. data on the next falling edge of SCLK All remaining bits of register data are shifted in on the falling edge of subsequent SCLK pulses see Figure 92 As explained earlier the data write is initiated by a write to the communications register followed by the data During a data write operation to the ADE7753 data is transferred to all on chip registers one byte at a time After a byte is transferred into the serial port there is a finite time before it is transferred to one of the ADE7753 on chip registers Although another byte transfer to the serial port can start while the previous byte is being transferred to an on chip register this second byte transfer ADE7753 should not finish until at least 4 us after the end of the previous byte transfer This functionality is expressed in the timing specification ts see Figure 92 If a write operation is aborted during a byte transfer CS brought high then that byte cannot be written to the destination register Destination registers can be up to 3 bytes wide see the ADE7753 Register Description tables Therefore the first byte shifted into the serial port at DIN is transferred to the MSB most significant byte of the destination register If for example the addressed register is 12 bits wide a 2 byte data transfer must take place The data is always assumed to be right justified therefore in this case the four MSBs of the first byte would be ignored and the four LSBs of the first byte
27. external voltage reference Alternatively the meter can be calibrated at multiple temperatures Real time compensation can be achieved easily by using the on chip temperature sensor CHANNEL 1 ADC Figure 51 shows the ADC and signal processing chain for Channel 1 In waveform sampling mode the ADC outputs a signed twos complement 24 bit data word at a maximum of 27 9 kSPS CLKIN 128 With the specified full scale analog input signal of 0 5 V or 0 25 V or 0 125 V see the Analog Inputs section the ADC produces an output code that is approximately between 0x2851EC 2 642 412d and 0xD7AE14 2 642 412d see Figure 51 Rev A Page 22 of 60 2 42V 1 21V 0 6V x8 x16 REFERENCE AIN 2 vip _ GAINT2 0 O ut pads Caer O VIN 4 0 5V 0 25V 0 125V 62 5mV 0x2851EC 31 3mV 15 6mV ov 0x00000 OxD7AEA4 ANALOG ADC OUTPUT INPUT WORD RANGE RANGE WHEN DIGITAL INTEGRATOR IS ENABLED FULL SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A 20dB DECADE OxE631F8 GAIN 4 3 DIGITAL INTEGRATOR ADE7753 CURRENT RMS IRMS CALCULATION WAVEFORM SAMPLE REGISTER ACTIVE AND REACTIVE POWER CALCULATION CHANNEL 1 50Hz CURRENT WAVEFORM DATA RANGE AFTER INTEGRATOR 50Hz 0x1EF73C 0x000000 CHANNEL 1 CURRENT WAVEFORM DATA RANGE OxE108C4 CHANNEL 1 60Hz CURRENT WAVEFORM DATA RANGE AFTER INTEGRATOR 60Hz 0x19CE08 0x00000
28. given load condition AENERGY expect AENERGY oia X 2 2 CFexpected Hz CFnominai X CFNUM 1 f WGAIN 41 CFDEN 41 222 When calibrating with a reference meter WGAIN is adjusted until CF matches the reference meter pulse output If an accurate source is used to calibrate WGAIN is modified until the active energy accumulation rate yields the expected CF pulse rate The steps of designing and calibrating the active energy portion of a meter with either a reference meter or an accurate source are outlined in the following examples The specifications for this example are Meter Constant MeterConstant imp Wh 3 2 Base Current Ib 10A Maximum Current Imax 60 A Line Voltage V nominat 220 V Line Frequency fi 50 Hz accurate source is to Calculate the F denominator CFDEN This is d neby comparing the expected CF pulse output to the nominal CF output with the default CFDEN 0x3F and CFNUM 0x3F and when the base current is applied The first step in calibrationywith fra a reference meter or an The expected CF output for this meter with the base current applied is 1 9556 Hz using Equation 34 CF a expected Hz 3 200imp Whx 10 Ax 220 V x cos 1 9556 Hz 3600s h 9 Alternatively CFexpectea can be measured from a reference meter pulse output if available CFexpectea Hz CF 42 The maximum CF frequency measured without any frequency division and with ac inputs at full scale is
29. in the ADE7753 i e ADCs and reference This pin should be tied to the analog ground plane or the quietest ground reference in the system This quiet ground reference should be used for all analog circuitry for example anti aliasing filters current and voltage transducers etc To keep ground noise around the ADE7753 to a minimum the quiet ground plane should connected to the digital ground plane at only one point It is acceptable to place the entire device on the analog ground plane 9 REFin our Access to the On Chip Voltage Reference The on chip reference has a nominal value of 2 4 V 8 and a typical temperature coefficient of 30 ppm C An external reference source can also be connected at this pin In either case this pin should be decoupled to AGND with a 1 uF ceramic capacitor 10 DGND Digital Ground Reference This pin provides the ground reference for the digital circuitry in the ADE7753 i e multiplier filters and digital to frequency converter Because the digital return currents in the ADE7753 are small it is acceptable to connect this pin to the analog ground plane of the system However high bus capacitance on the DOUT pin could result in noisy digital current which could affect performance 11 CF Calibration Frequency Logic Output The CF logic output gives active power information This output is intended to be used for operational and calibration purposes The full scale output frequency can be adjusted by writing to the C
30. scale negative 0x800000 and continues to increase in value when the power or energy flow is positive see Figure 66 Conversely if the power is negative the energy register underflows to full scale positive 0x7FFFFF and continues to decrease in value By using the interrupt enable register the ADE7753 can be configured to issue an interrupt IRQ when the active energy register is half full positive or negative or when an overflow or underflow occurs Rev A Page 29 of 60 ADE7753 Integration Time under Steady Load As mentioned in the last section the discrete time sample period T for the accumulation register is 1 1 us 4 CLKIN With full scale sinusoidal signals on the analog inputs and the WGAIN register set to 0x000 the average word value from each LPF2 is OXCCCCD see Figure 61 The maximum positive value that can be stored in the internal 49 bit register is 2 or OxFFFEFFFEFFFF before it overflows The integration time under these conditions with WDIV 0 is calculated as follows _ OxFFFF FFFF FFFF 0xCCCCD Time x 1 12 us 375 8 s 6 26 min 15 When WDIV is set to a value different from 0 the integration time varies as shown in Equation 16 Time Timewpry o xWDIV 16 POWER OFFSET CALIBRATION The ADE7753 also incorporates an active power offset register APOS 15 0 This is a signed twos complement 16 bit register that can be used to remove offsets in the active power calculation see
31. this by not accumulating energy if the multiplier output is below the no load threshold This threshold is 0 00196 of the full scale output frequency of the multiplier Compare this value to the IEC1036 specification which states that the meter must start up with a load equal to or less than 0 496 Ib This standard translates to 016796 of the full scale output frequency of the multiplier Rev A Page 32 of 60 REACTIVE POWER CALCULATION Reactive power is defined as the product of the voltage and current waveforms when one of these signals is phase shifted by 90 The resulting waveform is called the instantaneous reactive power signal Equation 25 gives an expression for the instanta neous reactive power signal in an ac system when the phase of the current channel is shifted by 90 v t J2v sin wt 0 23 i t J21 sin ot i t J2 Isin or 3 24 where 0 is the phase difference between the voltage and current channel V is the rms voltage Iis the rms current Rp t v t x i t 25 Rp t VI sin 0 VI sin 2o 0 90 DEGREE PHASE SHIFT INSTANTANEOUS REACTIVE i i POWER SIGNAL Rp t FROM CHANNEL 2 ADC LINECYC 15 0 ADE7753 The average reactive power over an integral number of lines n is given in Equation 26 nT RP Rp t dt VI sin 0 26 nT 5 where T is the line cycle period RP is referred to as the reactive power Note that the reactive power is equal to the
32. this register Same as Channel 1 Peak Register except that the register contents are reset to 0 after read Channel 2 Peak Register The maximum input value of the voltage channel since the last read of the register is stored in this register Same as Channel 2 Peak Register except that the register contents are reset to 0 after a read Temperature Register This is an 8 bit register which contains the result of the latest temperature conversion see the Temperature Measurement section Rev A Page 52 of 60 ADE7753 Address Name R W No Bits Default Type Description 0x27 PERIOD R 16 0x0 U Period of the Channel 2 Voltage Channel Input Estimated by Zero Crossing Processing The MSB of this register is always zero 0x28 Reserved 0x3C 0x3D TMODE R W 8 U Test Mode Register Ox3E CHKSUM R 6 0x0 U Checksum Register This 6 bit read only register is equal to the sum of all the ones in the previous read see the ADE7753 Serial Read Operation section 0x3F DIEREV R 8 U Die Revision Register This 8 bit read only register contains the revision number of the silicon 1 Type decoder U unsigned S signed by twos complement method and S signed by sign magnitude method Rev A Page 53 of 60 ADE7753 ADE7753 REGISTER DESCRIPTIONS All ADE7753 functionality is accessed via the on chip registers Each register is accessed by first writing to the communications registe
33. written to the ADE7753 would be the four MSBs of the 12 bit word Figure 93 illustrates this example cs lee te SCLK m te COMMAND BYTE UERUUUI PEUT wong CAP nnmnnnneuuu Pm WBA CRESCE C2 GB MO CO EN MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE 6 02875 0 081 Figure 92 Serial Interface Write Timing ato ee A Ast aeo poss Anar gir Koen Ka ae x ues poss cc MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE 02875 0 082 Figure 93 12 Bit Serial Write Operation Rev A Page 49 of 60 ADE7753 ADE7753 Serial Read Operation During a data read operation from the ADE7753 data is shifted out at the DOUT logic output on the rising edge of SCLK As is the case with the data write operation a data read must be preceded with a write to the communications register With the ADE7753 in communications mode ie CS logic low an 8 bit write to the communications register first takes place The MSB of this byte transfer is a 0 indicating that the next data transfer operation is a read The LSBs of this byte contain the address of the register that is to be read The ADE7753 starts shifting out of the register data on the next rising edge of SCLK see Figure 94 At this point the DOUT logic output leaves its high impedance state and starts driving the data bus All remaining bits of register data are shifted out on subsequent SCLK rising edges The serial interface also enters communications mode
34. 0 FREQUENCY RESPONSE WHEN DISABLED THE OUTPUT WILL NOT BE FURTHER ATTENUATED 02875 0 052 Figure 51 ADC and Signal Processing in Channel 1 Channel 1 Sampling The waveform samples can also be routed to tlie Waveform register MODE 14 13 130 tdibe read by the system master MCU In waveform sampling mode the WSMP bit Bit 3 in the interrupt enable register must also be set to Logic 1 The active apparent power and energy calculation remain uninterrupted during waveform sampling When in waveform sampling mode one of four output sample rates can be chosen by using Bits 11 and 12 of the mode register WAVSEL1 0 The output sample rate can be 27 9 kSPS 14 kSPS 7 kSPS or 3 5 kSPS see the Mode Register 0X09 section The interrupt request output IRQ signals a new sample availability by going active low The timing is shown in Figure 52 The 24 bit waveform samples are transferred from the ADE7753 one byte eight bits at a time with the most significant byte shifted out first The 24 bit data word is right justified see the ADE7753 Serial Interface section The interrupt request output IRQ stays low until the interrupt routine reads the reset status register see the ADE7753 Interrupts section RG 2 o sck UU UL LL READ FROM WAVEFORM om __ ofolofor nex DOUT ses 4 CHANNEL 1 DATA 24 BITS 02875 0 050 Figure 52 Waveform Sampling Channel 1 Channel 1 RMS Calculation
35. 0 0x000 then the output frequency can be set to 6 1 Hz by writing OxFF to the CFDEN register The output frequency has a slight ripple at a frequency equal to twice the line frequency This is due to imperfect filtering of the instantaneous power signal to generate the active power signal see the Active Power Calculation section Equation 9 from the Active Power Calculation section gives an expression for the instantaneous power signal This is filtered by LPF2 which has a magnitude response given by Equation 17 IB Es 17 f2 1 Rev A Page 30 of 60 ADE7753 The active power signal output of LPF2 can be rewritten as Since the average value of a sinusoid is 0 this ripple does not contribute to the energy calculation over time However the ripple can be observed in the frequency output especially at su ewe VI cen sD 18 higher output frequencies The ripple gets larger asa percentage 2f 2 of the frequency at larger loads and higher output frequencies 1 EJ The reason is simply that at higher output frequencies the integration or averaging time in the energy to frequency conversion process is shorter As a consequence some of the sinusoidal ripple is observable in the frequency output Choosing From Equation 13 a lower output frequency at CF for calibration can significantly reduce the ripple Also averaging the output frequency by using a longer gate time for the counter achieves the same results E ud
36. 00 CF Numerator CFNUM 0 CF Denominator CFDEN 489 Energy Reading at Base Current LAENERGY 3x nominal 17174 Period Register Reading PERIOD 8959 Glock Frequency A L 3 579545 MHz GF peas Calculated to be 1 9556 Hz according to Equation 34 LAENERGY oyeaa is calculated to be 19186 using Equation 48 CF atexpected Hz 3 200 imp Whx 220 Vx10 A 3600 s h x cos 1 9556 Hz LAENERGY nested CFip oxpecied X LINECYC yg 2x PERIOD x8 CLKIN CFNUM 1 CFDEN 1 INT xWDIV LAENERGY nexa 1 9556 x 2000 2 x 8959 x 8 3 579545 x 10 t2 1 489 1 INT INT 19186 4 19186 WGAIN is calculated to be 480 using Equation 47 WGAIN INT 22186 1 52 480 17174 Note that WGAIN is a signed twos complement register Rev A Page 40 of 60 With WDIV and CFNUM set to 0 LAENERGY can be expressed as LAENERGY napa INT CF 1p expected X LINECYC jg 2x PERIOD x8 CLKIN x CFDEN 1 The calculated Wh LSB ratio for the active energy register using Equation 39 is 6 378 x 10 1 Wh ooo e TO sp 3200imp Wh Watt Offset Offset calibration allows outstanding performance over a wide dynamic range for example 1000 1 To do this calibration two measurements are needed at unity power factor one at I and the other at the lowest current to be corrected Either calibration frequency or line cycle accumulation measurements can be used to determine the energy offset Gain calibration
37. 0A3D8 Therefore writing 0x50 to the IPKLVL register for example puts the Channel 1 peak detection level at full scale and sets the current peak detection to its least sensitive value Writing 0x00 puts the Channel 1 detection level at 0 The detection is done by comparing the contents of the IPKLVL register to the incoming Channel 1 sample The IRQ pin indicates that the peak level is exceeded if the PKI or PKV bits are set in the interrupt enable register IRQEN 15 0 at Address 0x0A Peak Level Record The ADE7753 records the maximum absolute value reached by Channel 1 and Channel 2 in two different registers IPEAK and VPEAK respectively VPEAK and IPEAK are 24 bit unsigned registers These registers are updated each time the absolute value of the waveform sample from the corresponding channel is above the value stored in the VPEAK or IPEAK register The contents of the VPEAK register correspond to 2x the maximum absolute value observed on the Channel 2 input The contents of IPEAK represent the maximum absolute value observed on the Channel 1 input Reading the RSTVPEAK and RSTIPEAK registers clears their respective contents after the read operation Rev A Page 19 of 60 ADE7753 ADE7753 INTERRUPTS ADE7753 interrupts are managed through the interrupt status register STATUS 15 0 and the interrupt enable register IRQEN 15 0 When an interrupt event occurs in the ADE7753 the corresponding flag in the status register is set to
38. 0x3 2 Calibrating Watt Gain Using an Accurate Source Example The CFDEN value calculated using Equation 44 should be written to the CFDEN register before beginning calibration and zero should be written to the CFNUM register First the line accumulation mode and the line accumulation interrupt should be enabled Next the number of half line cycles for the energy accumulation is written to the LINECYC register This sets the accumulation time Reset the interrupt status register and wait for the line cycle accumulation interrupt The first line cycle accumulation results may not have used the accumulation time set by the LINECYC register and should be discarded After resetting the interrupt status register the following line cycle readings will be valid When LINECYC half line cycles have elapsed the IRQ pin goes active low and the nominal LAENERGY with the test current applied can be read This LAENERGY value is compared to the expected LAENERGY value to deter mine the WGAIN value If apparent energy gain calibration is performed at the same time LVAENERGY can be read directly after LAENERGY Both registers should be read before the next interrupt is issued on the IRQ pin Refer to the Apparent Energy Calculation section for more details Figure 81 details the steps that calibrate the watt gain using an accurate source Rev A Page 39 of 60 ADE7753 CALCULATE CFDEN VALUE FOR DESIGN WRITE CFDEN VALUE TO CFDEN REGISTER ADDR 0x15
39. 23 KHz For this example the nominal CF with the test current Iv applied is 958 Hz In this example the line voltage and maximum current scale half of their respective analog input ranges The line voltage and maximum current should not be fixed at the maximum analog inputs to account for occurrences such as spikes on the line E 43 CF pomina Hz 23 kHz x yy x y x 7 MAX CF x nominay Hz 23 kHz x WA x y x10 0 958 Hz Rev A Page 38 of 60 The nominal CF on a sample set of meters should be measured using the default CFDEN CFNUM and WDIV to ensure that the best CFDEN is chosen for the design With the CFNUM register set to 0 CFDEN is calculated to be 489 for the example meter CF 1 CEDEN INT IB nominal 1 44 IB expected CFDEN INT 22 1 490 1 489 1 9556 This value for CFDEN should be loaded into each meter before calibration The WGAIN and WDIV registers can then be used to finely calibrate the CF output The following sections explain how to calibrate a meter based on ADE7753 when using a reference meter or an accurate source Calibrating Watt Gain Using a Reference Meter Example The CFDEN and CFNUM values for the design should be written to their respective registers before beginning the calibration steps shown in Figure 80 When using a reference meter the ERROR in CF is measured by comparing the CF output of the ADE7753 meter with the pulse output of the reference meter with the same
40. 5096 Each LSB scales the power output by 0 0244 Figure 64 shows the maximum code in hex output range for the active power signal LPF2 Note that the output range changes depending on the contents of the watt gain register The minimum output range is given when the watt gain register contents are equal to 0x800 and the maximum range is given by writing 0x7FF to the watt gain register This can be used to calibrate the active power or energy calculation in the ADE7753 0x13333 2 POSITIVE E OxCCCD POWER O 0x6666 0x00000 a OxF999A iad w gt NEGATIVE oxF 5 0xF3333 POWER lt 0xECCCD M 0x000 Ox7FF Ox800 7 WWGAIN 11 0 ACTIVE POWER CALIBRATION RANGE 02875 0 062 Figure 64 Active Power Calculation Output Range ENERGY CALCULATION As stated earlier power is defined as the rate of energy flow This relationship can be expressed mathematically in Equation 12 dE P dt 12 where P is power E is energy Conversely energy is given as the integral of power E ra 13 Rev A Page 28 of 60 1 INSTANTANEOUS v POWER SIGNAL p t VOLTAGE SIGNAL v t 0x19999A 0x000000 APOS 15 0 53 2 6 277 24 ADE7753 FOR WAVEFORM SAMPLING 0x19999 FOR WAVEFORM ACCUMULATIOIN OxCCCCD 02875 0 064 Figure 65 Active Power Signal Processing The ADE7753 achieves the integration of the active power signal by continuously accumulating the activ
41. 753 As shown the fastest integration time occurs when the VAGAIN register is set to maximum full scale i e OX7FF VAENERGY 23 0 ACTIVE POWER N SIGNAL P APPARENT POWER ARE ACCUMULATED INTEGRATED IN THE APPARENT ENERGY REGISTER TIME nT 02875 0 074 Figure 75 ADE7753 Apparent Energy Calculation VAENERGY 23 0 OxFF FFFF VAGAIN 0x7FF VAGAIN 0x000 VAGAIN 0x800 0x80 0000 0x40 0000 0x20 0000 0x00 0000 TIME minutes 02875 0 075 6 26 12 52 18 78 25 04 Figure 76 Energy Register Rollover Time for Full Scale Power Maximum and Minimum Power Gain Rev A Page 35 of 60 ADE7753 Note that the apparent energy register is unsigned see Figure 76 By using the interrupt enable register the ADE7753 can be con figured to issue an interrupt IRQ when the apparent energy register is half full or when an overflow occurs The half full interrupt for the unsigned apparent energy register is based on 24 bits as opposed to 23 bits for the signed active energy register Integration Times under Steady Load As mentioned in the last section the discrete time sample period T for the accumulation register is 1 1 us 4 CLKIN With full scale sinusoidal signals on the analog inputs and the VAGAIN register set to 0x000 the average word value from apparent power stage is OxAD055 see the Apparent Power Calculation section The maximum value that can be stored
42. ADDR 0x07 CALCULATE WGAIN SEE EQUATION 47 WRITE WGAIN VALUE TO ADDR 0x12 CALCULATE VAGAIN SEE EQUATION 69 WRITE VGAIN VALUE TO ADDR 0x1A 02875 A 004 Figure 87 Active Apparent Gain Calibration Reactive Energy To create a VAR pulse an impulse VARh constant must be Reactive energy is only available in line accumulation mode in determined The 1 f attenuation correction factor is determined the ADE7753 The accumulated reactive energy over LINECYC by comparing the nominal reactive energy accumulation rate to number of half line cycles is stored in the VARENERGY register the expected value The attenuation correction factor is multi plied by the contents of the LVARENERGY register with the In the ADE7753 a low pass filter at 2 Hz on the current channel ADE7753 in line accumulation mode is implemented for the reactive power calculation This provides the 90 degree phase shift needed to calculate the reactive power This filter introduces 1 f attenuation in the reactive energy accumulated Compensation for this attenuation can be done externally in a microcontroller The microcontroller can use the LVARENERGY register in order to produce a pulse output similar to the CF pulse for reactive energy Rev A Page 46 of 60 The impulse LSB ratio used to convert the value in the LVARENERGY register into a pulse output can be expressed in terms of impulses VARh and VARh LSB VARCF imp LSB imp VARhxVARh LSB Er
43. AENERGY 23 0 represents the upper 24 bits of this internal register This discrete time accumulation or summation is equivalent to integration in continuous time Equation 31 expresses the relationship oo Apparent Energy Lim S Apparent Power nT xT 31 T0 m where n is the discrete time sample number T is the sample period The discrete time sample period T for the accumulation register in the ADE7753 is 1 1 us 4 CLKIN Figure 75 shows this discrete time integration or accumulation The apparent power signal is continuously added to the internal register This addition is a signed addition even if the apparent energy remains theoretically always positive ADE7753 The 49 bits of the internal register are divided by VADIV If the value in the VADIV register is 0 then the internal active energy register is divided by 1 VADIV is an 8 bit unsigned register The upper 24 bits are then written in the 24 bit apparent energy register VAENERGY 23 0 RVAENERGY register 24 bits long is provided to read the apparent energy This register is reset to 0 after a read operation Figure 76 shows this apparent energy accumulation for full scale signals sinusoidal on the analog inputs The three curves displayed illustrate the minimum time it takes the energy register to roll over when the VAGAIN registers content is equal to 0x7FE 0x000 and 0x800 The VAGAIN register is used to carry out an apparent power calibration in the ADE7
44. ANALOG DEVICES FEATURES High accuracy supports IEC 60687 61036 61268 and IEC 62053 21 62053 22 62053 23 On chip digital integrator enables direct interface to current sensors with di dt output Active reactive and apparent energy sampled waveform current and voltage rms Less than 0 1 error in active energy measurement over a dynamic range of 1000 to 1 at 25 C Positive only energy accumulation mode available On chip user programmable threshold for line voltage surge and SAG and PSU supervisory Digital calibration for power phase and input offset On chip temperature sensor 3 C typical SPI compatible serial interface Pulse output with programmable frequency Interrupt request pin IRQ and status register Reference 2 4 V with external overdrive capability Single 5 V supply low power 25 mW typical GENERAL DESCRIPTION The ADE7753 features proprietary ADCs and DSR forhigh accuracy over large variations UP WV conditions and time The ADE7753 incorporates two second order 16 bit X A ADCs a digital integrator on CH1 reference circuitry temperature sensor and all the signal processing required to perform active reactive and apparent energy measurements line voltage period measurement and rms calculation on the Single Phase Multifunction Metering IC with di dt Sensor Interface ADE7753 voltage and current The selectable on chip digital integrator provides direct interface to di dt current sensors such a
45. DISABLE NOT USED 02875 0 086 Figure 97 Channel 1 Offset Register TY DiI C NAD Rev A Page 57 of 60 ADE7753 OUTLINE DIMENSIONS N e e NN iy eo 9o to o 20 11 10 om za Aj CO oio 1 85 175 2 00 MAX 65 rere Ls oosmint 55 eI 0o38 N DE 0 95 0 22 SEATING gt 0 75 gt COPLANARITY PLANE 0 55 0 10 COMPLIANT TO JEDEC STANDARDS MO 150AE Figure 98 20 Lead Shrink Small Outline Package SSOP ORDERING GUIDE Model Package Description Package Option 7 D oe Range ADE7753ARS gt t A SS P Vi RS 20 48 C to 85 C ADE7753ARSRL 20 Lead SSOP RS 20 40 C to 85 C ADE7753ARSZ 20 Lead SSOP RS 20 40 C to 85 C ADE7753ARSZRL 20 Lead SSOP RS 20 40 C to 85 C EVAL ADE7753EB Evaluation Board Z Pb free part Rev A Page 58 of 60 ADE7753 NOTES ww BDI C conh ALI ADE7753 NOTES VW D i AL 2004 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www analo g com 15 5 La DEVICES Rev A Page 60 of 60
46. ENERGY IS HALF FULL TEMPERATURE DATA READY PK RESET CHANNEL 1 SAMPLE ABOVE IPKLVL END OF SOFTWARE HARDWARE RESET PKV AEOF CHANNEL 2 SAMPLE ABOVE VPKLVL ACTIVE ENERGY REGISTER OVERFLOW 02875 A 013 Figure 96 Interrupt Status Interrupt Enable Register Rev A Page 56 of 60 ADE7753 CH10S REGISTER 0x0D The CH1OS register is an 8 bit read write enabled register The MSB of this register is used to switch on off the digital integrator in Channel 1 and Bits 0 to 5 indicates the amount of the offset correction in Channel 1 Table 14 summarizes the function of this register Table 14 CH1OS Register Bit Bit Location Mnemonic Description 0to5 OFFSET The six LSBs of the CH1OS register control the amount of dc offset correction in Channel 1 ADC The 6 bit offset correction is sign and magnitude coded Bits 0 to 4 indicate the magnitude of the offset correction Bit 5 shows the sign of the offset correction A 0 in Bit 5 means the offset correction is positive and a 1 indicates the offset correction is negative 6 Not Used This bit is unused 7 INTEGRATOR This bit is used to activate the digital integrator on Channel 1 The digital integrator is switched on by setting this bit This bit is set to be 0 on default 7 6 54 3 2 1 0 o 0 0 of o 0 o o appr oxo DIGITAL INTEGRATOR SELECTION SIGN AND MAGNITUDE CODED 1 ENABLE OFFSET CORRECTION BITS 0
47. F Fr 3 58MHz Y TO FREQUENCY COUNTER CT TURN RATIO 1800 1 CHANNEL 2 GAIN 1 GAIN 1 CH1 RB 1 100 8 Tem PS2501 1 02875 0 030 Figure 30 Test Circuit for Performance Curves with Integrator Off Rev A Page 14 of 60 THEORY OF OPERATION ANALOG INPUTS The ADE7753 has two fully differential voltage input channels The maximum differential input voltage for input pairs VIP VIN and V2P V2N is 0 5 V In addition the maximum signal level on analog inputs for VIP VIN and V2P V2N is 0 5 V with respect to AGND Each analog input channel has a programmable gain amplifier PGA with possible gain selections of 1 2 4 8 and 16 The gain selections are made by writing to the gain register see Figure 32 Bits 0 to 2 select the gain for the PGA in Channel 1 and the gain selection for the PGA in Channel 2 is made via Bits 5 to 7 Figure 31 shows how a gain selection for Channel 1 is made using the gain register GAIN 7 0 oo o o oo 0 0 GAIN K SELECTION OFFSET ADJUST 50mV efe ofofofo 0 0 CH10S 7 0 BITS 0 to 5 SIGN MAGNITUDE CODED OFFSET CORRECTION BIT 6 NOT USED BIT 7 DIGITAL INTEGRATOR ON 1 OFF 0 DEFAULT OFF 02875 0 031 Figure 31 PGA in Channel 1 In addition to the PGA Channel 1 also has a full scale input range selection for the ADC The ADC analog input range selection is also made using the gain register see Fi
48. FDEN and CFNUM registers see the Energy to Frequency Conversion section Rev A Page 8 of 60 ADE7753 Pin No Mnemonic Description 12 13 14 15 16 17 18 19 20 ZX CLKIN CLKOUT DOUT DIN Voltage Waveform Channel 2 Zero Crossing Output This output toggles logic high and logic low at the zero crossing of the differential signal on Channel 2 see the Zero Crossing Detection section This open drain logic output goes active low when either no zero crossings are detected or a low voltage threshold Channel 2 is crossed for a specified duration see the Line Voltage Sag Detection section Interrupt Request Output This is an active low open drain logic output Maskable interrupts include active energy register rollover active energy register at half level and arrivals of new waveform samples see the ADE7753 Interrupts section Master Clock for ADCs and Digital Signal Processing An external clock can be provided at this logic input Alternatively a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7753 The clock frequency for specified operation is 3 579545 MHz Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit Refer to the crystal manufacturer s data sheet for load capacitance requirements A crystal can be connected across this pin and CLKIN as described for Pin 15 to p
49. Figure 65 An offset could exist in the power calculation due to crosstalk between channels on the PCB or in the IC itself The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed i i The 256 LSBs APOS 0x0100 written to the active power offset register are equivalent to 1 LSB in the waveform sample register Assuming the average value output from LPF2 is OxCCCCD 838 861d when inputs on Channels 1 and 2 are both at full scale At 60 dB down on Channel 1 1 1000 of the Channel 1 full scale input the average word value output from LPF2 is 838 861 838 861 1 000 One LSB in the LPF2 output has a measurement error of 1 838 861 x 100 0 11996 of the average value The active power offset register has a resolution equal to 1 256 LSB of the waveform register therefore the power offset correction resolution is 0 00047 LSB 0 119 256 at 60 dB ENERGY TO FREQUENCY CONVERSION ADE7753 also provides energy to frequency conversion for calibration purposes After initial calibration at manufacturing the manufacturer or end customer often verify the energy meter calibration One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency which is proportional to the energy or active power under steady load conditions This output frequency can provide a simple single wire optically isolated interface to external calibrat
50. NE ACCUMULATION ENERGY ADDR 0x04 CALCULATE PHCAL SEE EQUATION 59 WRITE PHCAL VALUE TO THE PHCAL REGISTER ADDR 0x10 02875 A 011 Figure 85 Calibrating Phase with an Accurate Source For this example Meter Constant MeterConstant imp Wh 3 2 Line Voltage V nominal 220 V Line Frequency fi 50 Hz CF Numerator CFNUM 0 CF Denominator CFDEN 489 Base Current Ib 10A Half Line Cycles Used at Base Current LINECYCi 2000 PERIOD Register PERIOD 8959 Expected Line Accumulation at Unity Power Factor from Watt Gain Section LAENERGY weeexpected 19186 Active Energy Reading at PF 5 inductive LAENERGY r pr 5 9613 The error using Equation 56 is 9613 19186 191867 Phase Error Arcsin e 0 07 V3 Using Equation 59 PHCAL is calculated to be 11 Error 0 0021 PHCAL Int 007 x 5220300 2 15 1 Note that PHCAL is a signed twos complement register The phase lead is corrected by 0 08 when the PHCAL register is set to 11 360 Phase Correction PHCAL 0x0D x PERIOD Phase Correction 11 0x0D x sie 0 08 8960 VRMS and IRMS Calibration VRMS and IRMS are calculated by squaring the input in a digital multiplier v2 t 4D V sin dir x JAN T V V xcosQot 63 The square of the rins v lue iVextfacted from v t by a low pass filter The square root of the output of this low pass filter gives the rms value An
51. SB depends on the gain setting i e 1 2 4 8 or 16 Table 6 shows the correctable offset span for each of the gain settings and the LSB weight mV for the offset correction registers The maximum value that can be written to the offset correction registers is 31d see Figure 34 Figure 34 shows the relationship between the offset correction register contents and the offset mV on the analog inputs for a gain setting of 1 In order to perform an offset adjustment the analog inputs should be first connected to AGND and there should be no signal on either Channel 1 or Channel 2 A read from Channel 1 or Channel 2 using the waveform register indicates the offset in the channel This offset can be canceled by writing an equal and opposite offset value to the Channel 1 offset register or an equal value to the Channel 2 offsetregister The offset correction can be confirmed by performing another read Note when adjusting the offset of Chann l 1 one shotild disable the digital integrator and the HPF Table 6 Offset Correction Range Channels 1 and 2 Gain Correctable Span LSB Size 1 50 mV 1 61 mV LSB 2 37 mV 1 19 mV LSB 4 30 mV 0 97 mV LSB 8 26 mV 0 84 mV LSB 16 24 mV 0 77 mV LSB CH10S 5 0 ox1F 01 1111b SIGN 5 BITS OmV isomy OFFSET ADJUST 11 1111b SIGN 5 BITS 02875 0 034 Ox3F Figure 34 Channel 1 Offset Correction Range Gain 1 The current and voltage rms offsets c
52. TERNAL REFERENCE m 2 wW FREQUENCY Hz FULL SCALE VOLTAGE 02875 0 026 02875 0 029 Figure 24 Active Energy Error as a Percentage of Reading Gain 8 over Figure 27 VRMS Error as a Percentage of Reading Gain 1 with Power Factor with Internal Reference and Integrator On External Reference 8 INTEGRATOR ON INTERNAL REFERENCE 6 o E T 4 2 0 15 12 9 6 3 0 3 6 FULL SCALE CURRENT CH1 OFFSET 0p5V_1X mV 02875 0 087 02875 0 027 Figure 25 Active Energy Error as a Percentage of Reading Gain 8 over Figure 28 Channel 1 Offset Gain 1 Power Supply with Internal Reference and Integrator On 0 5 GAIN 8 0 4 INTEGRATOR ON TERNAL REFERENCE 0 3 0 2 0 1 FULL SCALE CURRENT 02875 0 028 Figure 26 IRMS Error as a Percentage of Reading Gain 8 with Internal Reference and Integrator On Rev A Page 13 of 60 ADE7753 i gt 10 F di dt CURRENT TOSPIBUS USED ONLY FOR CALIBRATION 1000 1ko VIN U4 ul ADE7753 SO vi 22pF FT 3 58MHz V7 22pF Y 110V HMM e NOT CONNECTED CHANNEL 1 GAIN 8 FREQUENCY CHANNEL 2 GAIN 1 COUNTER PS2501 1 02875 A 012 Figure 29 Test Circuit for Performance Curves with Integrator On W T I gt 1OuF CURRENT TRANSFORMER 1kQ CALIBRATION S VIN U4 a ADE7753 C862 TO SPI BUS USED ONLY FOR v1 22p
53. VRMOS 11 0 0x0 sgn 29 28 OxDAEB pen VRMS 23 0 LPF1 LPF3 CHANNEL 2 x 0x17D338 0x00 02875 0 0055 Figure 56 Channel 2 RMS Signal Processing Channel 2 has only one analog input range 0 5 V differential Like Channel 1 Channel 2 has aPG Arwitlr gain sel amp ctiong of 1 2 4 8 and 16 For energy nieasutem nt the output of the AIDC is passed directly to the multiplier and is not filtered An HPF is not required to remove any dc offset since it is only required to remove the offset from one channel to eliminate errors due to offsets in the power calculation When in waveform sampling mode one of four output sample rates can be chosen by using Bits 11 and 12 of the mode register The available output sample rates are 27 9 kSPS 14 kSPS 7 kSPS or 3 5 kSPS see the Mode Register 0x09 section The interrupt request output IRQ signals that a sample is available by going active low The timing is the same as that for Channel 1 as shown in Figure 52 Channel 2 RMS Calculation Figure 56 shows the details of the signal processing chain for the rms calculation on Channel 2 The Channel 2 rms value is processed from the samples used in the Channel 2 waveform sampling mode The rms value is slightly attenuated because of LPF1 Channel 2 rms value is stored in the unsigned 24 bit VRMS register The update rate of the Channel 2 rms measurement is CLKIN 4 With the specified full scale ac analog input signal of 0 5 V t
54. YC register can hold a maximum value of 65 535 In other words the line energy accumulation mode can be used to accumulate active energy for a maximum duration over 65 535 half line cycles At 60 Hz line frequency it translates to a total duration of 65 535 120 Hz 546 seconds POSITIVE ONLY ACCUMULATION MODE In positive only accumulation mode the energy accumulation is done only for positive power ignoring any occurrence of negative power above or below the no load threshold as shown in Figure 70 The CF pulse also reflects this accumulation method when in this mode The ADE7753 is placed in positive only accumulation mode by setting the MSB of the mode register MODE 15 The default setting for this mode is off Transitions in the direction of power flow going from negative to positive or positive to negative set the IRQ pin to active low if the interrupt enable register is enabled The interrupt status registers PPOS and PNEG show which transition has occurred see the ADE7753 register descriptions in Table 10 ACTIVE ENERGY NO LOAD THRESHOLD ACTIVE POWER NO LOAD THRESHOLD T7 gt 77 ag 1 1 1 1 1 1 1 1 IRQ PPOS PNEG PPOS PNEG PPOS PNEG INTERRUPT STATUS REGISTERS 02875 0 069 Figure 70 Energy Accumulation in Positive Only Accumulation Mode NO LOAD THRESHOLD The ADE7753 includes a no load threshold feature on the active energy that eliminates any creep effects in the meter The ADE7753 accomplishes
55. ading Gain 8 over Temperature with External Reference and Integrator Off 0 5 0 4 0 3 0 2 ERROR 10 100 FULL SCALE CURRENT 02875 0 017 Figure 16 Reactive Energy Error as a Percentage of Reading Gain 8 over Power Factor with External Reference and Integrator Off 0 3 0 2 ff 5 25V GAIN 8 INTEGRATOR OFF 0 1 INTERNAL REFERENCE g tc 0 o W 5 0V 0 1 4 75V 0 2 0 3 0 1 1 10 100 FULL SCALE CURRENT 02875 0 018 Figure 17 Active Energy Error as a Percentage of Reading Gain 8 over Power Supply with Internal Reference and Integrator Off Rev A Page 11 of 60 ADE7753 GAIN 8 INTEGRATOR OFF EXTERNAL REFERENCE S tc e tc tc Ww LINE FREQUENCY Hz FULL SCALE CURRENT 02875 0 019 02875 0 023 Figure 18 Active Energy Error as a Percentage of Reading Gain 8 over Figure 21 Active Energy Error as a Percentage of Reading Gain 8 over Frequency with External Reference and Integrator Off Temperature with Internal Reference and Integrator On 1 0
56. again as soon as the read has been completed At this point the DOUT logic output enters a DIN a s COMMAND BYTES y BYTE TE high impedance state on the falling edge of the last SCLK pulse The read operation can be aborted by bringing the CS logic input high before the data transfer is complete The DOUT output enters a high impedance state on the rising edge of CS When an ADE7753 register is addressed for a read operation the entire contents of that register are transferred to the serial port This allows the ADE7753 to modify its on chip registers without the risk of corrupting data during a multibyte transfer Note that when a read operation follows a write operation the read command i e write to communications register should not happen for at least 4 us after the end of the write operation If the read command is sent within 4 us of the write operation the last byte of the write operation could be lost This timing constraint is given as timing specification t te TE MOST SIGNIFICANT BYTE A EAST SIGNIFICANT BYTE SIGNIFICANT BYTE 02875 0 083 Figure 94 Serial Interface Read Timing Rev A Page 50 of 60 ADE7753 REGISTERS Table 10 Summary of Registers by Address ADE7753 Address Name R W No Bits Default Type Description 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 Ox0A OxOB OxOC OxOD OxOE OxOF 0x10 Ox11 WAVEFORM
57. alculated more accurately because of this precise timing control and provide all the information needed for reactive power and power factor calculation At the end of an energy calibration cycle the CYCEND flag in the interrupt status register is set If the CYCEND mask bit in the interrupt mask register is enabled the IRQ output also goes active low Thus the IRQ line can also be used to signal the end of a calibration The line apparent energy accumulation uses the same signal path as the apparent nergy accu two registers is equivalent To The LSB size of these LVAENERGY REGISTER IS UPDATED EVERY LINECYC ZERO CROSSINGS WITH THE TOTAL APPARENT ENERGY DURING THAT DURATION LVAENERGY 23 0 02875 0 076 Energy Calibration of 60 ENERGIES SCALING The ADE7753 provides measurements of active reactive and apparent energies These measurements do not have the same scaling and thus cannot be compared directly to each other Table 8 Energies Scaling PF 1 PF 0 707 PF 0 Integrator On at 50 Hz Active Wh Wh x 0 707 0 Reactive 0 Wh x 0 508 Wh x 0 719 Apparent Wh x 0 848 Wh x 0 848 Wh x 0 848 Integrator Off at 50 Hz Active Wh Wh x 0 707 0 Reactive 0 Wh x 0 245 Wh x 0 347 Apparent Wh x 0 848 Wh x 0 848 Wh x 0 848 Integrator On at 60 Hz Active Wh Wh x 0 707 0 Reactive 0 Wh x 0 610 Wh x 0 863 Apparent Wh x 0 827 Wh x 0 827 Wh x 0 827 Integrator Off at 60 Hz Active Wh Wh x 0 707 0 R
58. an be adjusted with the IRMSOS and VRMSOS registers see Channel 1 RMS Offset Compensation and Channel 2 RMS Offset Compensation sections di dt CURRENT SENSOR AND DIGITAL INTEGRATOR A di dt sensor detects changes in magnetic field caused by ac current Figure 35 shows the principle of a di dt current sensor MAGNETIC FIELD CREATED BY CURRENT DIRECTLY PROPORTIONAL TO CURRENT EMF ELECTROMOTIVE FORCE INDUCED BY CHANGES IN MAGNETIC FLUX DENSITY di dt 02875 0 035 Figure 35 Principle of a di dt Current Sensor The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current The changes in the magnetic flux density passing through a conductor loop generate an electromotive force EMF between the two ends of the loop The EMF is a voltage signal which is proportional to the di dt of the current The voltage output from the di dt current sensor is determined by the mutual inductance between the current carrying conductor and the di dt sensor The current signal needs to be recovered from the di dt signal before it gan b tus amp d Ain integrator is therefore necessary to restore the signal to a form The ADE7753 fias a b tlt ir digital integrator to recover the current signal from the di dt sensor The digital integrator on Channel 1 is switched off by default when the ADE7753 is powered up Setting the MSB of CH10OS register turns on the integrator Figure 36 to Figure
59. ant Minimum Current Imm 40 mA Load at Minimum Current Win 9 6 W CF Error at Minimum Current ERRORcrumn 1 3 CF Numerator CFNUM 0 CF Denominator CFDEN 489 Clock Frequency CLKIN 3 579545 MHz MeterConstant imp Wh 3 2 Using Equation 49 APOS is calculated to be 522 for this example CF Absolute Error CFimin nominat CFinNGxpected 50 CF Absolute Error MeterConstant imp Wh 3600 ERRORcrumm x Wm X 51 CF Absolute Error 0 C eos 3 200 _ 0 000110933 Hz 100 3600 Then AENERGY Error Rate LSB s a CF Absolute Error Boe E 52 ECENUM 1 AENERGY Error Rate LSB s 0 000110933 x D 0 05436 Using Equation 49 APOS is 522 0 05436 x 22 APOS t _ 3 579545 x 10 522 APOS can be represented as follows with CFNUM and WDIV set at 0 APOS ERROR cr quy X Win I imp Wh CFDEN 1 235 CLKIN Rev A Page 41 of 60 ADE7753 Calibrating Watt Offset with an Accurate Source Example The LAENERGY expected at Imin is 1370 using Equation 53 Figure 83 is the flowchart for watt offset calibration with an accurate source SET Itest Imn Vrest Vnom PF 1 SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR 0x1C SR See SET MODE FOR LINE CYCLE ACCUMULATION ADDR 0x09 0x0080 E eee ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR 0x0A 0x04 o RESET THE INTERRUPT STATUS READ REGISTER ADDR 0x0C
60. arent energy gain calibration can be done at the same time as the watt hour gain calibration using line cycle accumulation In this case LAENERGY and LVAENERGY the line cycle accumulation apparent energy register are both read following the line cycle accumulation interrupt Figure 87 shows a flowchart for calibrating active and apparent energy simultaneously LVAENERGY VAGAIN INT TORE j x n 69 a DWAENERGY 1p nominal LVAENERGY dissi INT 0 o x Accumulation time s 70 B constant x 3600s h The accumulation time is determined from Equation 37 and the line period can be determined from the PERIOD register accord ing to Equation 38 The VAh represented by the VAENERGY register is VAh VAENERGY x VAh LSB constant 71 The VAh LSB constant can be verified using this equation Accumulation time s VS 3600 yj VAh hy sp Constant IVAENERGY Rev A Page 45 of 60 ADE7753 CALCULATE CFDEN VALUE FOR DESIGN WRITE CFDEN VALUE TO CFDEN REGISTER ADDR 0x15 CFDEN SET Irgsr lb Vrest Vnom PF 1 SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR 0x1C SET MODE FOR LINE CYCLE ACCUMULATION ADDR 0x09 0x0080 ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR 0x0A 0x04 RESET THE INTERRUPT STATUS READ REGISTER ADDR 0x0C NO YES RESET THE INTERRUPT STATUS READ REGISTER ADDR 0x0C TY ALI YES READ LINE ACCUMULATION ENERGY ACTIVE ENERGY ADDR 0x04 APPARAENT ENERGY
61. ase error can be obtained from either CF or LAENERGY measurements LAENERGY Pras S LAENERGY g expected 2 LAENERG Yip expected Error 56 If watt gain and offset calibration have been performed there should be 096 error in CF at unity power factor and then Error 9S5ERRORcras pr 5 100 57 The phase error is 58 Phase Error Arcsin 2d 43 The relationship between phase UM ndithe PHOAL phase correction register is PHCAL PERIOD INT Phase Error x 360 0x0D 59 The expression for PHCAL can be simplified using the assumption that at small x Arcsin x x The delay introduced in the voltage channel by PHCAL is Delay PHCAL 0x0D x 8 CLKIN 60 The delay associated with the PHCAL register is a time delay if PHCAL 0x0D is positive but represents a time advance if this quantity is negative There is no time delay if PHCAL 0x0D The phase correction is in the opposite direction of the phase error 360 Phase Correction PHCAL 0x0D x 61 PERIOD ADE7753 Calibrating Phase Using a Reference Meter Example A power factor of 0 5 inductive can be assumed if the pulse output rate of the reference meter is half of its PF 1 rate Then the ERROR between CF and the pulse output of the reference meter can be used to perform the preceding calculations SET hesr lb Vrest Vnom PF 0 5 MEASURE THE ERROR BETWEEN THE CF OUTPUT AND
62. ber of half cycles as shown in Figure 71 SIGN OF REACTIVE POWER CALCULATION Note that the average reactive power is a signed calculation The phase shift filter has 90 phase shift when the integrator is enabled and 90 phase shift when the integrator is disabled Table 7 summarizes the relationship between the phase differ ence between the voltage and the current and the sign of the resulting VAR calculation Table 7 Sign of Reactive Power Calculation Angle Integrator Sign Between 0 to 90 Off Positive Between 90 to 0 Off Negative Between 0 to 90 On Positive Between 90 to 0 On i i Negative JJ APPARENT POWER CALCULATION The apparent power is defined as the maximum power that can be delivered to a load Vims and Ims are the effective voltage and current delivered to the load the apparent power AP is defined as Vrms X Ims The angle 0 between the active power and the apparent power generally represents the phase shift due to non resistive loads For single phase applications 0 represents the angle between the voltage and the current signals see Figure 72 Equation 28 gives an expression of the instantaneous power signal in an ac system with a phase shift APPARENT REACTIVE POWER ACTIVE POWER 02875 0 071 Figure 72 Power Triangle v t NER V Sin t i t J2 I ms Sin t 0 27 p t v t xi t p t Vins rms cos 0 x Vis rms cos 20t 9 28 The apparent
63. cles Line Accumulation Reactive Energy Register The instantaneous reactive power is accumulated in this read only register over the LINECYC number of half line cycles Mode Register This is a 16 bit register through which most of the ADE7753 functionality is accessed Signal samplewates filter enabling and calibration fnod s are sel cted by ying this register The contents can bexead at anytime seethe Mode Register 0x9 section Interrupt Enable Register ADE7753 interrupts can be deactivated at any time by setting the corresponding bit in this 16 bit enable register to Logic 0 The status register continues to register an interrupt event even if disabled However the IRQ output is not activated see the ADE7753 Interrupts section Interrupt Status Register This is an 16 bit read only register The status register contains information regarding the source of ADE7753 interrupts the see ADE7753 Interrupts section Same as the interrupt status register except that the register contents are reset to 0 all flags cleared after a read operation Channel 1 Offset Adjust Bit 6 is not used Writing to Bits 0 to 5 allows offsets on Channel 1 to be removed see the Analog Inputs and CH10S Register OxOD sections Writing a Logic 1 to the MSB of this register enables the digital integrator on Channel 1 a Logic 0 disables the integrator The default value of this bit is O Channel 2 Offset Adjust Bits 6 and 7 are not used Writing to Bit
64. cribes the ul of each bit in the register Table 12 Mode Register Bit Bit Default Location Mnemonic Value Description 0 DISHPF 0 HPF high pass filter in Channel 1 is disabled when this bit is set 1 DISLPF2 0 LPF low pass filter after the multiplier LPF2 is disabled when this bit is set 2 DISCF 1 Frequency output CF is disabled when this bit is set 3 DISSAG 1 Line voltage sag detection is disabled when this bit is set 4 ASUSPEND 0 By setting this bit to Logic 1 both ADE7753 A D converters can be turned off In normal operation this bit should be left at Logic 0 All digital functionality can be stopped by suspending the clock signal at CLKIN pin 5 TEMPSEL 0 Temperature conversion starts when this bit is set to 1 This bit is automatically reset to 0 when the temperature conversion is finished 6 SWRST 0 Software Chip Reset A data transfer should not take place to the ADE7753 for at least 18 us after a software reset 7 CYCMODE 0 Setting this bit to Logic 1 places the chip into line cycle energy accumulation mode 8 DISCH1 0 ADC 1 Channel 1 inputs are internally shorted together 9 DISCH2 0 ADC 2 Channel 2 inputs are internally shorted together 10 SWAP 0 By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the analog inputs V1P and V1N are connected to ADC 2 12 11 DTRT1 0 00 These bits are used to select the waveform register update rate DTRT 1 DTRTO Update Rate 0 0 27 9
65. dc component of the instantaneous reactive power signal Rp t in Equation 25 This is the relationship used to calculate reactive power in the ADE7753 The instantaneous reactive power signal Rp t is generated by multiplying Channel 1 and Channel 2 In this case the phase of Channel 1 is shifted by 90 The dc component of the instantaneous reactive power signal is then extracted by a low pass filter in order to obtain the reactive power informa tion Figure 71 shows the signal processing in the reactive power calculation in the ADE7753 ACCUMULATE REACTIVE ENERGY IN INTERNAL REGISTER AND UPDATE 0 THE LVARENERGY REGISTER LVARENERGY 23 0 AT THE END OF LINECYC HALF LINE CYCLES 23 02875 0 070 Figure 71 Reactive Power Signal Processing Rev A Page 33 of 60 ADE7753 The features of the line reactive energy accumulation are the same as the line active energy accumulation The number of half line cycles is specified in the LINECYC register LINECYC is an unsigned 16 bit register The ADE7753 can accumulate reactive power for up to 65535 combined half cycles At the end of an energy calibration cycle the CYCEND flag in the interrupt status register is set If the CYCEND mask bit in the interrupt mask register is enabled the IRQ output also goes active low Thus the IRQ line can also be used to signal the end of a cali bration The ADE7753 accumulates the reactive power signal in the LVARENERGY register for an integer num
66. defined as Root mean squafe rms rj of a continuous signal V t is Q For time sampling signals rms calculation involves squaring the signal taking the average and obtaining the square root VRMS Vins rms 3 The ADE7753 simultaneously calculates the rms values for Channel 1 and Channel 2 in different registers Figure 53 shows the detail of the signal processing chain for the rms calculation on Channel 1 The Channel 1 rms value is processed from the samples used in the Channel 1 waveform sampling mode The Channel 1 rms value is stored in an unsigned 24 bit register IRMS One LSB of the Channel 1 rms register is equivalent to one LSB of a Channel 1 waveform sample The update rate of the Channel 1 rms measurement is CLKIN 4 Rev A Page 23 of 60 ADE7753 CURRENT SIGNAL i 1 0x2851EC 0x00 OxD7AE14 HPF1 CHANNEL 1 ai 69 D 4 02875 0 0051 sgn 225 226 927 IRMSOS 11 0 laus t 217 216 ad 0x1C82B3 0x00 IRMS Figure 53 Channel 1 RMS Signal Processing With the specified full scale analog input signal of 0 5 V the ADC produces an output code that is approximately 2 642 412d see the Channel 1 ADC section The equivalent rms value of a full scale ac signal are 1 868 467d 0x1C82B3 The current rms measurement provided in the ADE7753 is accurate to within 1 for signal input between full scale and full scale 100 The conversion from the register value to amps must be done e
67. e errors The ADE7753 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors Because the compensation is in time this technique should be used only for small phase errors in the range of 0 1 to 0 5 Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics CHANNEL 2 DELAY REDUCED BY 4 48us 0 1 LEAD AT 60Hz DELAY BLOCK 4 48us LSB OBh IN PHCAL 5 0 v2 p PHCAL 5 0 100us TO 34us 60Hz lt 02875 0 056 v1 gt 60Hz Figure 57 Phase Calibration The phase calibration register PHCAL 5 0 is a twos comple ment signed single byte register thathas values ranging from 0x21 31d to 0x1F 31d EM i PHASE Degrees The register is centered at OxOD so that writing 0x0D to the register gives 0 delay By changing the PHCAL register the time delay in the Channel 2 signal path can change from 102 12 us to 439 96 us CLKIN 3 579545 MHz One LSB is equivalent FREQUENCY Hz 02875 0 087 to 2 22 us CLKIN 8 time delay or advance A line frequency of Figure 58 Combined Phase Response of the HPF and 60 Hz gives a phase resolution of 0 048 at the fundamental i e Phase Compensation 10 Hz to 1 kHz 360 x 2 22 us x 60 Hz Figure 57 illustrates how the phase compensation is used to remove a 0 1 phase lead in Channel
68. e power signal in an internal nonreadable 49 bit energy register The active energy register AENERGY 23 0 represents the upper 24 bits of this internal register This discrete time accumulation or summation is equivalent to integration in continuous time Equation 14 expresses the relationship E pat Lim 2 p nT xT 14 where n is the discrete time sample humberd T is the sample period The discrete time sample period T for the accumulation register in the ADE7753 is 1 1us 4 CLKIN As well as calculating the energy this integration removes any sinusoidal components that might be in the active power signal Figure 65 shows this discrete time integration or accumulation The active power signal in the waveform register is continuously added to the internal active energy register This addition is a signed addition therefore negative energy is subtracted from the active energy contents The exception to this is when POAM is selected in the MODE 15 0 register In this case only positive energy contributes to the active energy accumulation see the Positive Only Accumulation Mode section The output of the multiplier is divided by WDIV If the value in the WDIV register is equal to 0 then the internal active energy register is divided by 1 WDIV is an 8 bit unsigned register After dividing by WDIV the active energy is accumulated in a 49 bit internal energy accumulation register The upper 24 bits of this register are
69. eactive 0 Wh x 0 204 Wh x 0 289 Apparent Wh x 0 827 Wh x 0 827 Wh x 0 827 CALIBRATING AN ENERGY METER BASED ON THE ADE7753 TAN T The ADE7753 provides gain and offset compensation for active and apparent energy calibration Its phase compensation corrects phase error in active apparent and reactive energy If a shunt is used offset and phase calibration may not be required A reference meter or an accurate source can be used to calibrate the ADE7753 WATT VA GAIN CALIBRATION RMS CALIBRATION ADE7753 When using a reference meter the ADE7753 calibration output frequency CF is adjusted to match the frequency output of the reference meter A pulse output is only provided for the active energy measurement in the ADE7753 If it is desired to use a reference meter for calibrating the VA and VAR then additional code would have to be written in a microprocessor to produce a pulsed output for these quantities Otherwise VA and VAR calibration require an accurate source The ADE7753 provides a line cycle accumulation mode for calibration using an accurate source In this method the active energy accumulation rate is adjusted to produce a desired CF frequency The benefit of using this mode is that the effect of the ripple noise in the active energy is eliminated Up to 65535 half line cycles can be accumulated thus providing a stable energy value to average The accumulation time is calculated from the line cycle period mea
70. ecoupling The typical performance graphs show the power supply rejection performance This pin should be decoupled to AGND with a 10 uF capacitor in parallel witi a Ceramic 109 hF capacitor a 4 5 V1P VIN analog Inputs for Channel 1 This channel is intended for use with a di dt m transducer such as a Rogowski Coil or another current sensor S ch as a Shunt or current transformer CT These inputs are fully differential voltage inputs with maximum differential input signal levels of 0 5 V 0 25 V and 0 125 V depending on the full scale selection see the Analog Inputs section Channel 1 also has a PGA with gain selections of 1 2 4 8 or 16 The maximum signal level at these pins with respect to AGND is 0 5 V Both inputs have internal ESD protection circuitry and in addition an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage 6 7 V2N V2P Analog Inputs for Channel 2 This channel is intended for use with the voltage transducer These inputs are fully differential voltage inputs with a maximum differential signal level of 0 5 V Channel 2 also has a PGA with gain selections of 1 2 4 8 or 16 The maximum signal level at these pins with respect to AGND is 0 5 V Both inputs have internal ESD protection circuitry and an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage 8 AGND Analog Ground Reference This pin provides the ground reference for the analog circuitry
71. ed to a negative edge triggered external interrupt on the MCU On detection of the negative edge the MCU should be configured to start executing its interrupt service routine ISR On entering the ISR all interrupts should be disabled by using the global interrupt enable bit At this point the MCU external interrupt flag can be cleared to capture interrupt events that occur during the current ISR When the MCU interrupt flag is cleared a read from the status register with reset is carried out This causes the IRQ line to be reset logic high t2 see the Interrupt Timing section The status register contents are used to determine the source of the interrupt s and therefore the appropriate action to be taken If a subsequent interrupt event occurs during the ISR that event is recorded by the MCU external interrupt flag being set again ts On returning from the ISR the global interrupt mask is cleared same instruction cycle and the external interrupt flag causes the MCU to jump to its ISR once a gain This ensures that the MCU does not miss any external interrupts MCU INTERRUPT is AT T READ ISR RETURN GLOBAL INTERRUPT MASK RESET ISR ACTION BASED ON STATUS CONTENTS 02875 0 044 Figure 45 ADE7753 Interrupt Management DOUT READ STATUS REGISTER COMMAND IRQ STATUS REGISTER CONTENTS 02875 0 045 Figure 46 ADE7753 Interrupt Timing Rev A Page 20 of 60 Interrupt Timing The
72. ee Figure 49 The 20 dB per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensors However for a di dt sensor such as a Rogowski coil the sensor has a 20 dB per decade gain This neutralizes the 20 dB per decade attenuation produced by one simple LPF Therefore when using a di dt _ sensor care should be taken to offsetythe 20 dByper decade gain One simple approach is to cascade Mi RG filt rs to produce the 40 dB per decade attenuation needed ALIASING EFFECTS l SAMPLING IMAGE FREQUENCY FREQUENCIES 0 2 447 894 FREQUENCY kHz 02875 0 048 Figure 49 ADC and Signal Processing in Channel 1 Outline Dimensions ADC Transfer Function The following expression relates the output of the LPF in the Z A ADC to the analog input signal level Both ADCs in the ADE7753 are designed to produce the same output code for the same input signal level Code ADC 3 0492 x t x 262 144 1 OUT Therefore with a full scale signal on the input of 0 5 V and an internal reference of 2 42 V the ADC output code is nominally 165 151 or 2851Fh The maximum code from the ADC is 262 144 this is equivalent to an input signal level of 0 794 V However for specified performance it is recommended that the full scale input signal level of 0 5 V not be exceeded ADE7753 Reference Circuit Figure 50 shows a simplified version of the reference output circuitry The nominal reference vol
73. egrated to calculate energy see the Energy Calculation section 0 dB 4 Dc N e e 1 3 10 30 100 FREQUENCY Hz Figure 62 Frequency Response of LPF2 Rev A Page 27 of 60 ADE7753 x i UPPER 24 BITS ARE CURRENT APOS 15 0 ACCESSIBLE THROUGH CHANNEL LPF2 AENERGY 23 0 AENERGY 23 0 REGISTER VOLTAGE i CHANNEL 1 1 48 0 ACTIVE POWER a SERAL E 4 WAVEFORM REGISTER OUTPUTS FROM THE LPF2 ARE VALUES OUTPUT LPF2 TIME nT ACCUMULATED INTEGRATED IN THE INTERNAL ACTIVE ENERGY REGISTER 02875 0 063 Figure 63 ADE7753 Active Energy Calculation Figure 63 shows the signal processing chain for the active power calculation in the ADE7753 As explained the active power is calculated by low pass filtering the instantaneous power signal Note that when reading the waveform samples from the output of LPF2 the gain of the active energy can be adjusted by using the multiplier and watt gain register WGAIN 11 0 The gain is adjusted by writing a twos complement 12 bit word to the watt gain register Equation 11 shows how the gain adjustment is related to the contents of the watt gain register Eum Output WGAIN Acte Power x4l4 MOM 11 2 For example when Ox7FF is written to the watt gain register the power output is scaled up by 5096 0x7FF 2047d 2047 2 0 5 Similarly 0x800 2048d signed twos complement and power output is scaled by
74. ered 73 VARCF nominal VARCF inspected VARConstant imp VARR x Viominal X Ip xsin 74 3600s h LVARENERGY g x PERIODso 4z VARCFistnina 75 Accumulation time s x PERIOD where the accumulation time is calculated from Equation 37 The line period can be determined from the PERIOD register according to Equation 38 Then VAR can be determined from the LVARENERGY register value LVARENERGY s x VARh LSB x PERIODs0 4z VARh 76 PERIOD VAR LVARENERGY x VARh LSB 3600s h PERIODs0 Accumulation time s x PERIOD The PERIODsow PERIOD factoringthe preceding VAR equatidns is the correction factor for the 1 AUM attenuation of the low pass filter The PERIODsox term refers to the line period at calibration and could represent a frequency other than 50 Hz CLKIN FREQUENCY In this data sheet the characteristics of the ADE7753 are shown when CLKIN frequency is equal to 3 579545 MHz However the ADE7753 is designed to have the same accuracy at any CLKIN frequency within the specified range If the CLKIN frequency is not 3 579545 MHz various timing and filter characteristics need to be redefined with the new CLKIN frequency For example the cutoff frequencies of all digital filters such as LPF1 LPF2 or HPF1 shift in proportion to the change in CLKIN frequency according to the following equation CLKIN Frequency 78 New Frequency Original Frequency x Pto dgio THEY 3 579545 MHz The change
75. f bits from the modulator the low pass filter can produce 24 bit data words that are proportional to the input signal level The A converter uses two techniques to achieve high resolution from what is essentially a 1 bit conversion technique The first is oversampling Oversampling means that the signal is sampled at a rate frequency which is many times higher than the bandwidth of interest For example the sampling rate in the ADE7753 is CLKIN A 894 kHz and the band of interest is 40 Hz to 2 kHz Oversampling has the effect of spreading the quantization noise noise due to sampling over a wider bandwidth With the noise spread more thinly over a wider bandwidth the quantization noise in the band of interest is lowered see Eigure 48 How amp ver oversampling alone is not efficient enough to improve the signal to noise ratio SNR in the band of interest For example an oversampling ratio of 4 is required just to increase the SNR by only 6 dB 1 bit To keep the oversampling ratio at a reasonable level it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies In the 2 A modulator the noise is shaped by the integrator which has a high pass type response for the quantization noise The result is that most of the noise is at the higher frequencies where it can be removed by the digital low pass filter This noise shaping is shown in Figure 48 ANTILALIAS piGirAL FILTER RC
76. ge 17 of 60 ADE7753 The zero crossing detection also drives the ZX flag in the interrupt status register An active low in the IRQ output also appears if the corresponding bit in the interrupt enable register is set to Logic 1 The flag in the interrupt status register as well as the IRQ output are reset to their default values when the interrupt status regis ter with reset RSTSTATUS is read Zero Crossing Timeout The zero crossing detection also has an associated timeout register ZXTOUT This unsigned 12 bit register is decremented 1 LSB every 128 CLKIN seconds The register is reset to its user programmed full scale value every time a zero crossing is detected on Channel 2 The default power on value in this register is OxFFF If the internal register decrements to 0 before a zero crossing is detected and the DISSAG bit in the mode register is Logic 0 the SAG pin goes active low The absence of a zero crossing is also indicated on the IRQ pin if the ZXTO enable bit in the interrupt enable register is set to Logic 1 Irrespective of the enable bit setting the ZXTO flag in the interrupt status register is always set when the internal ZXTOUT register is decremented to 0 see the ADE7753 Interrupts section The ZXOUT register can be written read by the user and has an _ address of 1Dh see the ADE7 53ySerial Interface Section The resolution of the register is 128 L seconds per LSB Thus the maximum delay for an interru
77. gital integrator is switched off the ADE7753 can be used directly with a conventional current sensor such as a current transformer CT or with a low resistance current shunt ZERO CROSSING DETECTION The ADE7753 has a zero crossing detection circuit on Channel 2 This zero crossing is used to produce an external zero crossing signal ZX and it is also used in the calibration mode see the Calibrating an Energy Meter Based on the ADE7753 section The zero crossing signal is also used to initiate a temperature measurement on the ADE7753 see the Temperature Measurement section Figure 40 shows how the zero crossing signal is generated from the output of LPF1 V2p d 63 TO 63 FS vel MULTIPLIER V2N zx LPF1 T 3ap 140Hz 2 32 60Hz LN 02875 0 040 Figure 40 Zero Crossing Detection on Channel 2 The ZX signal goes logic high on a positive going zero crossing and logic low on a negative going zero crossing on Channel 2 The zero crossing signal ZX is generated from the output of LPF1 LPF1 has a single pole at 140 Hz at CLKIN 3 579545 MHZ As a result there is a phase lag between the analog input signal V2 and the output of LPF1 The phase response of this filter is shown in the Channel 2 Sampling section The phase lag response of LPF1 results in a time delay of approximately 1 14 ms 60 Hz between the zero crossing on the analog inputs of Channel 2 and the rising or falling edge of ZX Rev A Pa
78. gure 32 As mentioned previously the maximum differential input voltage is 0 5 V However by using Bits 3 and 4 in the gain register the maximum ADC input voltage can be set to 0 5 V 0 25 V or 0 125 V This is achieved by adjusting the ADC reference see the ADE7753 Reference Circuit section Table 5 summarizes the maximum differential input signal level on Channel 1 for the various ADC range and gain selections ADE7753 Table 5 Maximum Input Signal Levels for Channel 1 Max Signal ADC Input Range Selection Channel 1 05V 0 25V 0 125 V 0 5 V Gain 1 0 25 V Gain 2 Gain 1 0 125 V Gain 4 Gain 2 Gain 1 0 0625 V Gain 8 Gain 4 Gain 2 0 0313 V Gain 16 Gain 8 Gain 4 0 0156 V Gain 16 Gain 8 0 00781 V Gain 16 GAIN REGISTER CHANNEL 1 AND CHANNEL 2 PGA CONTROL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 ADDR OAH PGA 2 GAIN SELECT L__ PGA 1 GAIN SELECT 0002 x1 0002 x1 001 x2 001 x2 010 x4 010 x4 011 2 x8 011 x8 100 x 16 100 x 16 CHANNEL 1 FULL SCALE SELECT REGISTER CONTENTS 00 0 5V SHOW POWER ON DEFAULTS 01 0 25V 10 0 125V 02875 0 032 Figure 32 ADE7753 Analog Gain Register Channel 2 by writing to the offset correction registers CH1OS and CH2OS respectively These registers allow channel offsets in the range 20 mV to 50 mV depending on the gain setting to be removed Channel 1 and 2 offset registers are sign magn
79. he output from the LPF1 swings between 0x2518 and OxDAES at 60 Hz see the Channel 2 ADC section The equivalent rms value of this full scale ac signal is approximately 1 561 400 0z17D338 in the VRMS register The voltage rms measure ment provided in the ADE7753 is accurate to within 0 5 for signal input between full scale and full scale 20 The conversion from the register value to volts must be done externally in the microprocessormising avolts LSB constant Since the low pass filtering used for calctlating the rms value is imperfect there is some ripple noise from 20 term present in the rms measure ment To minimize the noise effect in the reading synchronize the rms reading with the zero crossings of the voltage input Channel 2 RMS Offset Compensation The ADE7753 incorporates a Channel 2 rms offset compensation register VRMSOS This is a 12 bit signed register that can be used to remove offset in the Channel 2 rms calculation An offset could exist in the rms calculation due to input noises and dc offset in the input samples The offset calibration allows the contents of the VRMS register to be maintained at 0 when no voltage is applied One LSB of the Channel 2 rms offset is equivalent to one LSB of the rms register Assuming that the maximum value from the Channel 2 rms calculation is 1 561 400d with full scale ac inputs then one LSB of the Channel 2 rms offset represents 0 06496 of measurement error at 60 dB down of ful
80. he communications register COMMUNICATIONS DINO REGISTER REGISTER ADDRESS DECODE I 02875 0078 Figure 89 Addressing ADE7753 Registers via the Communications Register The communications register is an 8 bit wide register The MSB determines whether the next data transfer operation is a read or a write The six LSBs contain the address of the register to be accessed see the Communications Register section for a more detailed description Figure 90 and Figure 91 show the data transfer sequences for a read and write operation respectively On completion of a data transfer read or write the ADE7753 once again enters communications mode A data transfer is complete when the LSB of the ADE7753 register being addressed for a write or a read is transferred to or from the ADE7753 cs a sc FU UU UU UUU mnn COMMUNICATIONS REGISTER WRITE DIN ___ 0 0 ADDRESS i DOUT MULTIBYTE READ DATA 02875 0 079 Figure 90 Reading Data from the ADE7753 via the Serial Interface se Annnnnnn nnne COMMUNICATIONS REGISTER WRITE DN i o ADDREss MULTIBYTE READ DATA 02875 0 080 Figure 91 Writing Data to the ADE7753 via the Serial Interface The serial interface of the ADE7753 is made up of four signals SCLK DIN DOUT and CS The serial clock for a data transfer is applied at the SCLK logic input This logic input has a Schmitt trigger input structure that allows slow rising and falling clock edges
81. i tude coded A negative number is applied to the Channel 1 offset register CH1OS for a negative offset adjustment Note that the Channel 2 offset register is inverted A negative number is applied to CH2OS for a positive offset adjustment It is not necessary to perform an offset correction in an energy measure ment application if HPF in Channel 1 is switched on Figure 33 shows the effect of offsets on the real power calculation As seen from Figure 33 an offset on Channel 1 and Channel 2 contributes a dc component after multiplication Because this dc component is extracted by LPF2 to generate the active real power infor mation the offsets contribute an error to the active power calculation This problem is easily avoided by enabling HPF in Channel 1 By removing the offset from at least one channel no error component is generated at dc by the multiplication Error terms at cos wt are removed by LPF2 and by integration of the active power signal in the active energy register AENERGY 23 0 see the Energy Calculation section Itis also possible to adjust mobs errors on Channel 1 and Rev A Page 15 of 60 ADE7753 DC COMPONENT INCLUDING ERROR TERM IS EXTRACTED BY THE LPF FOR REAL x POWER CALCULATION Vos x los Vx I FREQUENCY RAD S 02875 0 033 Figure 33 Effect of Channel Offsets on the Real Power Calculation The contents of the offset correction registers are 6 bit sign and magnitude coded The weight of the L
82. in the apparent energy register before it overflows is 2 or OxFEFFFF The average word value is added to the internal register which can store 2 or OXFFFEFFFE FFFF before it overflows Therefore the integration time under these conditions with VADIV 0 is calculated as follows OxFFFF FFFF FFFF 0xD055 Time x 1 2 us 888 s 12 52 min 32 When VADIV is set to a value different from 0 the integration time varies as shown in Equation 33 Time Timewpiv o x VADIV cr APPARENT POWER FROM CHANNEL 2 ADC ZERO CROSSING CALIBRATION DETECTION CONTROL LINECYC 15 0 Figure 77 ADE7753 Apparent Rev A Page 36 LINE APPARENT ENERGY ACCUMULATION The ADE7753 is designed with a special apparent energy accumulation mode which simplifies the calibration process By using the on chip zero crossing detection the ADE7753 accumulates the apparent power signal in the LVAENERGY register for an integral number of half cycles as shown in Figure 77 The line apparent energy accumulation mode is always active The number of half line cycles is specified in the LINCYC register which is an unsigned 16 bit register The ADE7753 can accumulate apparent power for up to 65535 combined half cycles Because the apparent power is integrated on the same integral number of line cycles as the line active energy register these two values can be compared easily The active energy and the apparent energy are c
83. in the temperature register 6 RESET Indicates the end of a reset for both software or hardware reset The corresponding enable bit has no function in the interrupt enable register i e this status bit is set at the end of a reset but it cannot be enabled to cause an interrupt 7 AEOF Indicates that the active energy register has overflowed 8 PKV Indicates that waveform sample from Channel 2 has exceeded the VPKLVL value 9 PKI Indicates that waveform sample from Channel 1 has exceeded the IPKLVL value A VAEHF Indicates that an interrutywas eaused by thE Oto 1 transition of th MSB ef the apparent energy register i e the VAEWERGY register is half full ji B VAEOF Indicates that the apparent energy registerhas overflowed C ZXTO Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the specified number of line cycles see the Zero Crossing Timeout section D PPOS Indicates that the power has gone from negative to positive E PNEG Indicates that the power has gone from positive to negative F RESERVED Reserved 15 14 13 12 11 10 9 8 7 6 5 4 olo o ololo ol o DBDDBDBDBED ADDR 0x0A 0x0B 0x0C RESERVED E Dam AEHF ACTIVE ENERGY HALF FULL PNEG SAG POWER POSITIVE TO NEGATIVE SAG ONLINE VOLTAGE PPOS CYCEND POWER NEGATIVE TO POSITIVE END OF LINECYC HALF LINE CYCLES ZXTO WSMP ZERO CROSSING TIMEOUT WAVEFORM SAMPLES DATA READY VAEOF zx VAENERGY OVERFLOW ZERO CROSSING VAEHF TEMPL VA
84. ion equipment Figure 67 illustrates the energy to frequency conversion in the ADE7753 CFNUM 11 0 DFC 48 0 AENERGY 48 0 Ee 11 0 CFDEN 11 0 02875 0 066 CF Figure 67 ADE7753 Energy to Frequency Conversion A digital to frequency converter DFC is used to generate the CF pulsed output The DFC generates a pulse each time 1 LSB in the active energy register is accumulated An output pulse is generated when CFDEN 1 CFNUM 1 number of pulses are generated at the DFC output Under steady load conditions the output frequency is proportional to the active power The maximum output frequency with ac input signals at full scale and CFNUM 0x00 and CFDEN 0x00 is approximately 23 kHz The ADE7753 incorporates two registers CFNUM 11 0 and CFDEN 11 0 to set the CF frequency These are unsigned 12 bit registers which can be used to adjust the CF frequency to a wide range of values These frequency scaling registers are 12 bit registers which can scale the output frequency by 1 2 to 1 witha step ofur if the value 0 is written to men these registers the value 1 would be applied to the register The ratio CFNUM 1 CFDEN 1 should be smaller than 1 to ensure proper operation If the ratio of the registers CFNUM 1 CFDEN 1 is greater than 1 the register values would be adjusted to a ratio CFNUM 1 CFDEN 1 of 1 For example if the output frequency is 1 562 kHz while the contents of CFDEN are
85. ions Comments Write Timing ti 50 ns min CS falling edge to first SCLK falling edge t 50 ns min SCLK logic high pulse width t3 50 ns min SCLK logic low pulse width t4 10 ns min Valid data setup time before falling edge of SCLK ts 5 ns min Data hold time after SCLK falling edge te 400 ns min Minimum time between the end of data byte transfers t 50 ns min Minimum time between byte transfers during a serial write ts 100 ns min CS hold time after SCLK falling edge Read Timing to 4 us min Minimum time between read command i e a write to communication register and data read tio 50 ns min Minimum time between data byte transfers during a multibyte read tu 30 ns min Data access time after SCLK rising edge following a write to the communications register ti 100 ns max Bus relinquish time after falling edge of SCLK 10 ns min ti 100 ns max Bus relinquish time after rising edge of CS 10 ns min 1 J 1 Sample tested during initial release M M anyiredesign ot process change that could affect this parameter Allinputsigin 10 to 90 and timed from a voltage level of 1 6 V See Figure 3 Figure 4 and the ADE7753 Serial Interface section 3 Minimum time between read command and data read for all registers except waveform register which is to 500 ns min Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0 8 V or 2 4 V 5 Derived from the mea
86. is equal to 0x800 and the maximum range is given by writing 0x7FF to the apparent power gain register This can be used to calibrate the apparent power or energy calculation in the ADE7753 Rev A Page 34 of 60 APPARENT POWER 100 FS APPARENT POWER 150 FS APPARENT POWER 50 FS i 0x103880 0xAD055 0x5682B 0x00000 VAGAIN 11 0 APPARENT POWER CALIBRATION RANGE VOLTAGE AND CURRENT CHANNEL INPUTS 0 5V GAIN 02875 0 073 Figure 74 Apparent Power Calculation Output Range Apparent Power Offset Calibration Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value see Channel 1 RMS Calculation and Channel 2 RMS Calculation sections The Channel 1 and Channel 2 rms values are then multiplied together in the apparent power signal processing Since no additional offsets are created in the multiplication of the rms values there is no specific offset compensation in the apparent power signal processing The offset compensation of the apparent power measurement is done by calibrating each individual rms measurement APPARENT ENERGY CALCULATION gy The apparent energy is given as the integral of thejapparent power J Apparent Energy Apparent Power t dt 30 The ADE7753 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 48 bit register The apparent energy register V
87. kSPS CLKIN 128 0 1 14 kSPS CLKIN 256 1 0 7 kSPS CLKIN 512 1 1 3 5 kSPS CLKIN 1024 Rev A Page 54 of 60 ADE7753 Bit Bit Default Location Mnemonic Value Description 14 13 WAVSEL1 0 00 These bits are used to select the source of the sampled data for the waveform register WAVSEL1 0 Length Source 0 0 24 bits active power signal output of LPF2 0 1 Reserved 1 0 24 bits Channel 1 1 1 24 bits Channel 2 15 POAM 0 Writing Logic 1 to this bit allows only positive power to be accumulated in the ADE7753 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C STSTSTSTSTSTSTSTST TS IST ADDR 0x09 POAM ew L DISHPF POSITIVE ONLY ACCUMULATION DISABLE HPF1 IN CHANNEL 1 WAVSEL DISLPF2 WAVEFORM SELECTION FOR SAMPLE MODE DISABLE LPF2 AFTER MULTIPLIER 00 LPF2 01 RESERVED DISCF 10 CH1 DISABLE FREQUENCY OUTPUT CF 11 CH2 DISSAG DTRT DISABLE SAG OUTPUT WAVEFORM SAMPLES OUTPUT DATA RATE 00 27 9kSPS CLKIN 128 ASUSPEND 01 14 4kSPS CLKIN 256 SUSPEND CH1 AND CH2 ADCs 10 7 2kSPS CLKIN 512 11 3 6kSPS CLKIN 1024 TEMPSEL START TEMPERATURE SENSING SWAP SWAP CH1 AND CH2 ADCs a SWRST SOFTWARE CHIP RESET DISCH2 SHORT THE ANALOG INPUTS ON KAN L 2 I DISCH1 SHORT THE ANALOG INPUTS ON CHANNEL 1 CYCMO NOTE REGISTER CONTENTS SHOW POWER ON DEFAULTS Figure 95 Mode Register Rev A Page 55 of 60 LINE CYCLE ENERGY ACCUMULATION MODE
88. l scale VRMS VRMS VRMSOS 6 where VRMSv is the rms measurement without offset correction The voltage rms offset compensation should be done by testing the rms results at two non zero input levels One measurement can be done close to full scale and the other at approximately full scale 10 The voltage offset compensation can be derived from these measurements If the voltage rms offset register does not have enough range the CH2OS register can also be used Rev A Page 25 of 60 ADE7753 PHASE COMPENSATION When the HPF is disabled the phase error between Channel 1 and Channel 2 is 0 from dc to 3 5 kHz When HPF is enabled Channel 1 has the phase response illustrated in Figure 58 and Figure 59 Also shown in Figure 60 is the magnitude response of the filter As can be seen from the plots the phase response is ve 4 almost 0 from 45 Hz to 1 kHz This is all that is required in typical energy measurement applications However despite being internally phase compensated the ADE7753 must work with transducers which could have inherent phase errors For example a phase error of 0 1 to 0 3 is not uncommon for a current transformer CT These phase errors can vary from part to part and they must be corrected in order to perform accurate power calculations The errors associated with phase mismatch are particularly noticeable at low power factors The ADE7753 provides a means of digitally calibrating these small phas
89. nal in an ac system v t V2 xV sin or j 2 i t V2 x I sin wt 8 where Vis the rms voltage Iis the rms current P t v t x i t p t VI VI cos 20t 9 The average power over an integral number of line cycles n is given by the expression in Equation 10 1 nT where T is the line cycle period P is referred to as the active or real power Note that the active power is equal to the dc component of the instantaneous power signal p t in Equation 8 i e VI This is the relationship used to calculate active power in the ADE7753 ADE7753 The instantaneous power signal p t is generated by multiplying the current and voltage signals The dc component of the instantaneous power signal is then extracted by LPF2 low pass filter to obtain the active power information This process is illustrated in Figure 61 INSTANTANEOUS POWER SIGNAL 0x19999A p t vxi vxixcos 2ot ACTIVE REAL POWER SIGNAL v x i vi OxCCCCD 0x00000 ndi CURRENT NC y i t 2 2xixsin ot a 2 VOLTAGE v t 2 2xvxsin ot 02875 0 060 Figure 61 Active Power Calculation Since LPF2 does not have an ideal brick wall frequency response see Figure 62 the active power signal has some ripple due to the instantaneous power signal This ripple is sinusoidal and has a frequency equal to twice the line frequency Because the ripple ig AUI in nature it is removed when the active power signal is int
90. of CLKIN frequency does not affect the timing characteristics of the serial interface because the data transfer is synchronized with serial clock signal SCLK But one needs to observe the read write timing of the serial data transfer see the ADE7753 timing characteristics in Table 2 Table 9 lists various timing changes that are affected by CLKIN frequency ADE7753 Table 9 Frequency Dependencies of the ADE7753 Parameters Parameter CLKIN Dependency Nyquist Frequency for CH 1 and CH 2 ADCs CLKIN 8 PHCAL Resolution Seconds per LSB 4 CLKIN Active Energy Register Update Rate Hz CLKIN 4 Waveform Sampling Rate per Second WAVSEL1 0 00 CLKIN 128 01 CLKIN 256 10 CLKIN 512 11 CLKIN 1024 Maximum ZXTOUT Period 524 288 CLKIN SUSPENDING ADE7753 FUNCTIONALITY The analog and the digital circuit can be suspended separately The analog portion of the ADE7753 can be suspended by setting the ASUSPEND bit Bit 4 of the mode register to logic high see the Mode Register 0x9 section In suspend mode all wave form samples from the ADCs are set to 0 The digital circuitry can be halted by stopping the CLKIN input and maintaining a logic high or low on the CLKIN pin The ADE7753 can be reactivated by restoring the CLKIN input and setting the ASUSPEND bit to logic low CHECKSUM REGISTER The ADE7753 has a d ecksu register CHECKSUM 5 0 to ensure the data bits feceiyed if the last serial read operation are not corrup
91. offset correction is provided to cancel noise and offset contributions from the input There is ripple noise from the 2w term because the low pass filter does not completely attenuate the signal This noise can be minimized by synchronizing the rms register readings with the zero crossing of the voltage signal The IRQ output can be configured to indicate the zero crossing of the voltage signal This flowchart demonstrates how VRMS and IRMS readings are synchronized to the zero crossings of the voltage input SET INTERRUPT ENABLE FOR ZERO CROSSING ADDR 0x0A 0x0010 RESET THE INTERRUPT STATUS READ REGISTER ADDR 0x0C NO YES READ VRMS OR IRMS ADDR 0x17 0x16 RESET THE INTERRUPT STATUS READ REGISTER ADDR 0x0C 02875 A 003 Figure 86 Synchronizing VRMS and IRMS Readings with Zero Crossings Rev A Page 44 of 60 Voltage rms compensation is done after the square root VRMS VRMS0 VRMSOS 64 where VRMSO is the rms measurement without offset correction VRMS is linear from full scale to full scale 20 To calibrate the offset two VRMS measurements are required for example at V nomina and V nomina 10 V nominat is set at half of the full scale analog input range so the smallest linear VRMS reading is at V sonisa 10 V xVRMS V gt xVRMS V Vj VRMSOS 65 where VRMS and VRMS are rms register values without offset correction for input V and V respectively If the range of the 12
92. power is defined as Vrms x I ms This expression is independent from the phase angle between the current and the voltage Figure 73 illustrates the signal processing in each phase for the calculation of the apparent power in the ADE7753 APPARENT POWER SIGNAL P Irms CURRENT RMS SIGNAL i t Ox1C82B3 pS 0x00 VOLTAGE RMS SIGNAL v t 0x17D338 7 0x00 Figure 73 Apparent Power Signal Processing MULTIPLIER OxADO55 Vrms 02875 0 072 The gain ofthe appaxent energy Can be adjusted by using the multiplier and VAGAIN register WAGAIN 11 0 The gain is adjusted by writing a twos complement 12 bit word to the VAGAIN register Equation 29 shows how the gain adjustment is related to the contents of the VAGAIN register OutputVAGAIN Amorem Power x f magn 29 2 For example when 0x7FF is written to the VAGAIN register the power output is scaled up by 50 0x7FF 2047d 2047 2 0 5 Similarly 0x800 2047d signed twos complement and power output is scaled by 50 Each LSB represents 0 024496 of the power output The apparent power is calculated with the current and voltage rms values obtained in the rms blocks of the ADE7753 Figure 74 shows the maximum code hexadeci mal output range of the apparent power signal Note that the output range changes depending on the contents of the apparent power gain registers The minimum output range is given when the apparent power gain register content
93. pply monitor has built in hysteresis and filtering which give a high degree of immunity to false triggering due to noisy supplies ov ADE7753 POWER ON INACTIVE INACTIVE ACTIVE INACTIVE STATE SAG 02875 0 042 Figure 42 On Chip Power Supply Monitor As seen in Figure 42 the trigger level is nominally set at 4 V The tolerance on this trigger level is about 5 The SAG pin can also be used as a power supply monitor input to the MCU The SAG pin goes logic low when the ADE7753 is in its inactive state The power supply and decoupling for the part should be such that the ripple at AVDD does not exceed 5 V 5 as specified for normal operation LINE VOLTAGE SAG DETECTION In addition to the detection of the loss of the line voltage signal zero crossing the ADE7753 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value for a number of line cycles This condition is illustrated in Figure 43 Rev A Page 18 of 60 CHANNEL 2 FULL SCALE Hp p 477 7 7 7 3 n SAGLVL 7 0 ttr do 4 7 ARE SAG RESET HIGH WHEN CHANNEL 2 EXCEEDS SAGLVL 7 0 SAGCYC 7 0 0x04 PES 3 LINE CYCLES SAG 02875 0 043 Figure 43 ADE7753 Sag Detection Figure 43 shows the line voltage falling below a threshold that is set in the sag level register SAGLVL 7 0 for three line cycles The quantities 0 and 1 are not valid for the SAGCYC register
94. pt is 0 15 second 128 CLKIN x 2 Figure 41 shows the mechanism of the zero crossing timeout detection when the line voltage stays at a fixed dc level for more than CLKIN 128 x ZXTOUT seconds 12 BIT INTERNAL REGISTER VALUE ZXTOUT CHANNEL 2 ZXTO DETECTION BIT 02875 0 041 Figure 41 Zero Crossing Timeout Detection PERIOD MEASUREMENT The ADE7753 also provides the period measurement of the line The period register is an unsigned 16 bit register and is updated every period The MSB of this register is always zero The resolution of this register is 2 2 ms LSB when CLKIN 3 579545 MHz which represents 0 01396 when the line fre quency is 60 Hz When the line frequency is 60 Hz the value of the period register is approximately 7576d The length of the register enables the measurement of line frequencies as low as 13 9 Hz The period register is stable at 1 LSB when the line is established and the measurement does not change A settling time of 1 8 seconds is associated with this filter before the measurement is stable POWER SUPPLY MONITOR The ADE7753 also contains an on chip power supply monitor The analog supply AVpp is continuously monitored by the ADE7753 If the supply is less than 4 V 596 then the ADE7753 goes into an inactive state that is no energy is accumulated when the supply voltage is below 4 V This is useful to ensure correct device operation at power up and during power down The power su
95. r and then transferring the register data A full description of the serial interface protocol is given in the ADE7753 Serial Interface section COMMUNICATIONS REGISTER The communications register is an 8 bit write only register which controls the serial data transfer between the ADE7753 and the host processor All data transfer operations must begin with a write to the communications register The data written to the communications register determines whether the next operation is a read or a write and which register is being accessed Table 11 outlines the bit designations for the communications register DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W R 0 A5 A4 A3 A2 A1 AO Table 11 Communications Register Bit Bit Location Mnemonic Description 0to5 AO to A5 The six LSBs of the communications register specify the register for the data transfer operation Table 10 lists the address of each ADE7753 on chip register 6 RESERVED This bit is unused and should be set to 0 7 W R When this bit is a Logic 1 the data transfer operation immediately following the write to the communications register is interpreted as a write to the ADE7753 When this bit is a Logic 0 the data transfer operation immediately following the write to the communications register is interpreted as a read operation MODE REGISTER 0x09 T J The ADE7753 functionality is MANAR Writing tothe mode register Table 12 des
96. range 100 to 1 IRMS Measurement Bandwidth 14 kHz VRMS Measurement Error 0 5 typ Over a dynamic range 20 to 1 VRMS Measurement Bandwidth 140 Hz ANALOG INPUTS See the Analog Inputs section Maximum Signal Levels 0 5 V max VIP VIN V2N and V2P to AGND Input Impedance dc 390 k min Bandwidth 14 kHz CLKIN 256 CLKIN 3 579545 MHz Gain Error External 2 5 V reference gain 1 on Channels 1 and 2 Channel 1 Range 0 5 V Full Scale 4 typ V1 0 5 Vdc Range 0 25 V Full Scale 4 typ V1 0 25 V dc Range 0 125 V Full Scale 4 typ V1 0 125 V dc Channel 2 typ V2 0 5 V dc Offset Error 32 mV max Gain 1 Channel 1 13 mV max Gain 16 32 mV max Gain 1 Channel 2 13 mV max Gain 16 WAVEFORM SAMPLING Sampling CLKIN 128 3 579545 MHz 128 27 9 kSPS Channel 1 See the Channel 1 Sampling section Signal to Noise Plus Distortion 62 dB typ 150 mV rms 60 Hz range 0 5 V gain 2 Bandwidth 3 dB 14 kHz CLKIN 3 579545 MHz Footnotes on next page Rev A Page 3 of 60 ADE7753 Parameter Spec Unit Test Conditions Comments Channel 2 See the Channel 2 Sampling section Signal to Noise Plus Distortion 60 dB typ 150 mV rms 60 Hz gain 2 Bandwidth 3 dB 140 Hz CLKIN 3 579545 MHz REFERENCE INPUT REFin out Input Voltage Range 2 6 V max 2 4 V 8 2 2 V min 2 4 V 896 Input Capacitance 10 pF max ON CHIP REFERENCE Nominal 2 4 V at REFiyour pin Reference Error 200 mV max Current Source 10 uA max
97. rator and the other for the HPF The phase correction networks correct the phase response of the corresponding component and ensure a phase match between Channel 1 current and Channel 2 voltage to within 0 1 over a range of 45 Hz to 65 Hz with the digital integrator off With the digital integrator on the phase is corrected to within 0 4 over a range of 45 Hz to 65 Hz Power Supply Rejection This quantifies the ADE7753 measurement error as a percentage of reading when the power supplies are varied For the ac PSR measurement a reading at nominal supplies 5 4 istaken A second reading is obtained with the same inputsignal levels when an ac 175 mV rms 120 Hz signal s intreduced onto the ADE7753 supplies Any error introduced by this ac signal is expressed as a percentage of reading see the Measurement Error definition For the dc PSR measurement a reading at nominal supplies 5 V is taken A second reading is obtained with the same input signal levels when the supplies are varied 5 Any error introduced is again expressed as a percentage of the reading ADC Offset Error The dc offset associated with the analog inputs to the ADCs It means that with the analog inputs connected to AGND the ADCs still see a dc analog input signal The magnitude of the offset depends on the gain and input range selection see the Typical Performance Characteristics section However when HPF1 is switched on the offset is removed from
98. rgy Error as a Percentage of Reading Gain 1 over Figure 8 Active Energy Error as a Percentage of Reading Gain 8 over Power Factor with Internal Reference and Integrator Off Power Factor with Internal Reference and Integrator Off Rev A Page 10 of 60 701 1 10 100 FULL SCALE CURRENT 02875 0 013 Figure 12 Reactive Energy Error as a Percentage of Reading Gain 1 over Power Factor with External Reference and Integrator Off 0 20 0 15 40 C PF 0 0 10 GAIN 8 INTEGRATOR OFF 0 05 25 C PF 0 4 INTERNAL REFERENCE IM PE 0 0 1 1 10 100 FULL SCALE CURRENT 02875 0 014 Figure 13 Reactive Energy Error as a Percentage of Reading Gain 8 over Temperature with Internal Reference and Integrator Off 0 3 GAIN 8 0 2 INTEGRATOR OFF INTERNAL REFERENCE 0 1 40 C PF 0 5 g 25 C PF 0 N 4 0 o tc tc ul 0 1 85 C PF 0 5 425 C PF 0 5 0 2 0 3 0 1 1 10 100 FULL SCALE CURRENT 02875 0 015 Figure 14 Reactive Energy Error as a Percentage of Reading Gain 8 over Power Factor with Internal Reference and Integrator Off ADE7753 FULL SCALE CURRENT 02875 0 016 Figure 15 Reactive Energy Error as a Percentage of Re
99. rovide a clock source for the ADE7753 The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used Chip Select Part of the 4 wire SPI serial interface This active low logic input allows the ADE7753 to share the serial bus with several other devices see the ADE7753 Serial Interface section Serial Clock Input for the Synchronous Serial Interface All serial data transfers are synchronized to this clock see the ADE7753 Serial Interface section The SCLK has a Schmitt trigger input for use with a clock source that has a slow edge transition time for example opto isolator output Data Output for the Serial Interface Data is shifted out at this pin on the rising edge of SCLK This logic output is normally in a high impedance state unless it is driving data onto the serial data bus see the ADE7753 Serial Interface section Data Input for the Serial Interface Data is shifted in at this pin on the falling edge of SCLK see the ADE7753 Serial Interface section IN D ALI Rev A Page 9 of 60 ADE7753 TYPICAL PERFORMANCE CHARACTERISTICS 0 3 GAIN 8 0 2 INTEGRATOR OFF EXTERNAL REFERENCE 0 1 85 C PF 1 u 25 C PF ERROR 0 1 0 1 0 2 N 40 C PF 1 0 3 a 04 0 5 0 3 0 1 1 10 100 FULL SCALE CURRENT
100. roximately 1 5 LSB C The temperature register produces a code of 0x00 when the ambient temperature is approximately 25 C The temperature measurement is uncalibrated in the ADE7753 and has an offset tolerance as high as 25 C ADE7753 ANALOG TO DIGITAL CONVERSION The analog to digital conversion in the ADE7753 is carried out using two second order X A ADCs For simplicity the block diagram in Figure 47 shows a first order Z A ADC The converter is made up of the Z A modulator and the digital low pass filter MCLK 4 ANALOG LOW PASS FILTER INTEGRATOR d dm LA n ps COMPARATOR DIGITAL LOW PASS FILTER 02875 0 046 Figure 47 First Order X A ADC ADE7753 A x A modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock In the ADE7753 the sampling clock is equal to CLKIN 4 The 1 bit DAC in the feedback loop is driven by the serial data stream The DAC output is subtracted from the input signal If the loop gain is high enough the average value of the DAC out put and therefore the bit stream can approach that of the input signal level For any given input value in a single sampling interval the data from the 1 bit ADC is virtually meaningless Only when a large number of samples are averaged is a meaningful result obtained This averaging is carried out in the second part of the ADC the digital low pass filter By averaging a large number o
101. s Rogowski coils eliminating the need for an external analog integrator and resulting in excellent long term stability and pre cise phase matching between the current and voltage channels The ADE7753 provides a serial interface to read data and a pulse output frequency CF which is proportional to the active power Various system calibration features i e channel offset correction phase calibration and power calibration ensure high accuracy The part also detects short duration low or high voltage variations The positive only accumulation mode gives the option to accumulate energy only when positive power is detected An internal no load threshold ensures that the part does not exhibit any creep when there is no load The zero crossing output ZX produces a pulse that is synchronized to the zero crossing point of the line voltage This signal is used internally in the line cycle active and apparent energy accumulation modes which enables faster calibration hesinterraptsstdtus register T the nature of the interrupt and the interrupt enable register controls which event produces an output on the IRQ pin an open drain active low logic output The ADE7753 is available in a 20 lead SSOP package FUNCTIONAL BLOCK DIAGRAM AVDD RESET O INTEGRATOR 0 xm DVDD DGND U fat He WGAIN 11 0 ADE7753 LPF2 CFNUM 11 0 LE 0 HPF1 SENSOR PHCAL 5
102. s O to 5 of this register allows any offsets on Channel 2 to be removed see the Analog Inputs section Note that the CH2OS register is inverted To apply a positive offset a negative number is written to this register PGA Gain Adjust This 8 bit register is used to adjust the gain selection for the PGA in Channels 1 and 2 see the Analog Inputs section Phase Calibration Register The phase relationship between Channel 1 and 2 can be adjusted by writing to this 6 bit register The valid content of this twos compliment register is between Ox1D to 0x21 At a line frequency of 60 Hz this is a range from 2 06 to 0 7 see the Phase Compensation section Active Power Offset Correction This 16 bit register allows small offsets in the active power calculation to be removed see the Active Power Calculation section Rev A Page 51 of 60 ADE7753 Address Name R W No Bits Default Type Description 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 Ox1A Ox1B Ox1C Ox1D Ox1E Ox1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 WGAIN WDIV CFNUM CFDEN IRMS VRMS IRMSOS VRMSOS VAGAIN VADIV LINECYC ZXTOUT SAGCYC SAGLVL IPKLVL VPKLVL IPEAK RSTIPEAK VPEAK RSTVPEAK TEMP R W R W R W R W R W R W R W R W R W 12 24 24 0x0 0x0 0x3F 0x3F 0x0 0x0 0x0 0x0 0x0 0x0 OxFFFF OxFFF
103. should be performed prior to offset calibration Offset calibration is performed by determining the active energy error rate Once the active energy error rate has been determined the value to write to the APOS register to correct the offset is calculated AENERGY Error Rate x 25 gt QUERI P j The AENERGY registers update at a rate of CLKIN 4 The twos complement APOS register provides a fine adjustment to the active power calculation It represents a fixed amount of power offset to be adjusted every CLKIN 4 The 8 LSBs of the APOS register are fractional such that one LSB of APOS represents 1 256 of the least significant bit of the internal active energy register Therefore one LSB of the APOS register represents 2 of the AENERGY 23 0 active energy register APOS 49 The steps involved in determining the active energy error rate for both line accumulation and reference meter calibration options are shown in the following sections Calibrating Watt Offset Using a Reference Meter Example Figure 82 shows the steps involved in calibrating watt offset with a reference meter SET ItEst mins Vrest Vnom PF 1 MEASURE THE ERROR BETWEEN THE CF OUTPUT AND THE REFERENCE METER OUTPUT AND THE LOAD IN WATTS CALCULATE APOS SEE EQUATION 49 WRITE APOS VALUE TO THE APOS REGISTER ADDR 0x11 02875 A 008 Figure 82 Calibrating Watt Offset Using a Reference Meter ADE7753 For this example Meter Const
104. sured by the ADE7753 in the PERIOD register and the number of half line cycles in the accumulation fixed by the LINECYC register Current and voltage rms offset calibration removes any apparent energy offset A gain calibration is also provided for apparent energy Figure 79 shows an optimized calibration flow for active energy rms and apparent energy Activerandiappafent energy jg calibrations can take place concurrently with a readjof tHe accumulated apparent energy register following that of the accumulated active energy register Figure 78 shows the calibration flow for the active energy portion of the ADE7753 WATT GAIN CALIBRATION WATT OFFSET CALIBRATION PHASE CALIBRATION 02875 A 005 Figure 78 Active Energy Calibration The ADE7753 does not provide means to calibrate reactive energy gain and offset The reactive energy portion of the ADE7753 can be calibrated externally through a MCU WATT OFFSET CALIBRATION PHASE CALIBRATION 02875 A 002 Figure 79 Apparent and Active Energy Calibration Rev A Page 37 of 60 ADE7753 Watt Gain The first step of calibrating the gain is to define the line voltage base current and the maximum current for the meter A meter constant needs to be determined for CF such as 3200 imp kWh or 3 2 imp Wh Note that the line voltage and the maximum current scale to half of their respective analog input ranges in this example The expected CF in Hz is CFexpected Hz MeterConstan
105. sured time taken by the data outputs to change 0 5 V when loaded with the circuit in Figure 2 The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading So am gt th su eU rE a gt te ae M az GOOODCOSS cw ey XX X Xem COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE A aa 02875 0 081 Figure 3 Serial Write Timing fia COMMAND BYTES E U BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE SO E 02875 0 083 Figure 4 Serial Read Timing Rev A Page 5 of 60 are specified with tr tf 5 ns ADE7753 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 3 Parameter Rating AVDD to AGND 03Vto47V Stresses above those listed under Absolute Maximum Ratings DVDD to DGND 03Vto47V may cause permanent damage to the device This is a stress DVDD to AVDD 03Vto403V rating only and functional operation of the device at these or Analog Input Voltage to AGND 6Vto46V any other conditions above those indicated in the operational VIP VIN V2P and V2N section of this specification is not implied Exposure to absolute Reference Input Voltage to AGND 03Vto AVDD 0 3 V maximum rating conditions for extended periods may affect Digital Input
106. t imp Wh x Load W 34 3600s h AERD s where is the angle between I and V and cos 9 is the power factor The ratio of active energy LSBs per CF pulse is adjusted using the CFNUM CFDEN and WDIV registers LAENERGY AccumulationTime s CFNUM 1 CF expected CFDEN 1 35 The relationship between watt hours accumulated and the quantity read from AENERGY can be determined from the amount of active energy accumulated over time with a given load 36 Wh Load W x Acci MIA Tine LSB LAENERGY x3600s h where Accumulation Time can be determined from the value in the line period and the number of half line cycles fixed in the LINECYC register LINECYC jp x Line Period s 7 37 Accumulation time s The line period can be determined from the PERIOD register Line Period s PERIOD x 5 CL KIN 8 The AENERGY Wh LSB ratio can also be expressed in terms of the meter constant CFNUM 1 ny Wh CFDEN 1 m Asp MeterConstant imp Wh Sd In a meter design WDIV CFNUM and CFDEN should be kept constant across all meters to ensure that the Wh LSB constant is maintained Leaving WDIV at its default value of 0 ensures maximum resolution The WDIV register is not included in the CF signal chain so it does not affect the frequency pulse output The WGAIN register is used to finely calibrate each meter Cali brating the WGAIN register changes both CF and AENERGY for a
107. tage at the REFnyour pin is 2 42 V This is the reference voltage used for the ADCs in the ADE7753 However Channel 1 has three input range selections that are selected by dividing down the reference value used for the ADC in Channel 1 The reference value used for Channel 1 is divided down to and of the nominal value by using an internal resistor divider as shown in Figure 50 OUTPUT IMPEDANCE MAXIMUM 6ko LOAD 104A O REFERENCE INPUT TO ADC CHANNEL 1 RANGE SELECT 2 42V 1 21V 0 6V 02875 0 049 Figure 50 ADE7753 Reference Circuit Output The REFmyovr pin can be oyerdriven by an external source for example external 5 V ME Note that the nominal reference value supplied to the s is now 2 5 V not 2 42 V which has the effect of increasing the nominal analog input signal range by 2 5 2 42 x 100 3 or from 0 5 V to 0 5165 V The voltage of the ADE7753 reference drifts slightly with temperature see the ADE7753 Specifications for the temperature coefficient specification in ppm C The value of the temperature drift varies from part to part Since the reference is used for the ADCs in both Channels 1 and 2 any x drift in the reference results in 2x deviation of the meter accuracy The reference drift resulting from temperature changes is usually very small and it is typically much smaller than the drift of other components on a meter However if guaranteed temperature performance is needed one needs to use an
108. ted The 6 bit checksum register is reset before the first bit MSB of the register to be read is put on the DOUT pin During a serial read operation when each data bit becomes available on the rising edge of SCLK the bit is added to the checksum register In the end of the serial read operation the content of the checksum register is equal to the sum of all ones in the register previously read Using the checksum register the user can determine if an error has occurred during the last read operation Note that a read to the checksum register also generates a checksum of the checksum register itself CONTENT OF REGISTER n bytes CHECKSUM REGISTER ADDR 0x3E Figure 88 Checksum Register for Serial Interface Read DOUT O Rev A Page 47 of 60 ADE7753 ADE7753 SERIAL INTERFACE All ADE7753 functionality is accessible via several on chip registers see Figure 89 The contents of these registers can be updated or read using the on chip serial interface After power on or toggling the RESET pin low or a falling edge on CS the ADE7753 is placed in communications mode In communica tions mode the ADE7753 expects a write to its communications register The data written to the communications register determines whether the next data transfer operation is a read or a write and also which register is accessed Therefore all data transfer operations with the ADE7753 whether a read or a write must begin with a write to t
109. test conditions applied to both meters Equation 45 defines thewercentierror with respect to the pulse outputs of both meter n the base current D CES CE ERRORceum 5 TUB 100 45 CF ef IB CALCULATE CFDEN VALUE FOR DESIGN WRITE CFDEN VALUE TO CFDEN REGISTER ADDR 0x15 CFDEN SET Irest lp Vrest Vnom PF 1 MEASURE THE ERROR BETWEEN THE CF OUTPUT AND THE REFERENCE METER OUTPUT CALCULATE WGAIN SEE EQUATION 46 WRITE WGAIN VALUE TO THE WGAIN REGISTER ADDR 0x12 02875 A 006 Figure 80 Calibrating Watt Gain Using a Reference Meter ADE7753 For this example Meter Constant CF Numerator CFNUM 0 CF Denominator CFDEN 489 Error measured at Base Current ERROR crus 3 07 MeterConstant imp Wh 3 2 One LSB change in WGAIN changes the active energy registers and CF by 0 0244 WGAIN is a signed twos complement register and can correct for up to a 50 error Assuming a 3 0796 error WGAIN is 126 ERROR WGAIN INT CFU 46 0 0244 E 0 WGAIN SINT 99 P 0 0244 When CF is calibrated the AENERGY register has the same Wh LSB constant from meter to meter if the meter constant WDIV and the CFNUM CFDEN ratio remain the same The Wh LSB ratio for this meter is 6 378 x 10 using Equation 39 with WDIV at the default value CFNUM 1 why e CHDEN 1 LSB MeterConsta imp Wh xWDIV 1 Wh 490 1 6378x104 LSB 3 200imp Wh 49
110. the line cycle energy accumulation mode the energy calibration can be greatly simplified and the time required to calibrate the meter can be significantly reduced The ADE7753 is placed in line cycle energy accumulation mode by setting Bit 7 CYCMODE in the mode register In line cycle energy accumulation mode the ADE7753 accumulates the active power signal in the LAENERGY register Address 0x04 for an integral number of line cycles as shown in Figure 69 The number of half line cycles is specified in the LINECYC register Address 0x1C The ADE7753 can accumulate active power for up to 65 535 half line cycles Because the active power is integrated on an integral number of line cycles at the end of a line cycle energy accumu lation cycle the CYCEND flag in the interrupt status register is set Bit 2 If the CYCEND enable bit in the interrupt enable register is enabled the IRQ output also goes active low Fhusethe IRQ line can also be used to signal the completion of the line cycle energy accumulation Another calibration cycle cam start as long as the CYCMODE bit in the mode register is set From Equations 13 and 18 nT nT E t Pide e cos 2nft dt 20 1 ES 9 8 9 where n is an integer T is the line cycle period Since the sinusoidal component is integrated over an integer number of line cycles its value is always 0 Therefore nT E va 0 21 0 E t VInT 22 Note that in this mode the 16 bit LINEC
111. to be used All data transfer operations are synchronized to the serial clock Data is shifted into the ADE7753 at the DIN logic input on the falling edge of SCLK Data is shifted out of the ADE7753 at the DOUT logic output en a rising edge of SQLK Fhe i input is the chip select input Thi input is used when multiple devices share the serial Bus A filing edge on C also f sets the serial interface and places the ADE7753 into communications mode The CS input should be driven low for the entire data transfer operation Bringing CS high during a data transfer operation aborts the transfer and places the serial bus in a high impedance state The CS logic input can be tied low if the ADE7753 is the only device on the serial bus However with CS tied low all initiated data transfer operations must be fully completed i e the LSB of each register must be transferred because there is no other way of bringing the ADE7753 back into communications mode without resetting the entire device by using RESET Rev A Page 48 of 60 ADE7753 Serial Write Operation The serial write sequence takes place as follows With the ADE7753 in communications mode i e the CS input logic low a write to the communications register first takes place The MSB of this byte transfer is a 1 indicating that the data transfer operation is a write The LSBs of this byte contain the address of the register to be written to The ADE7753 starts shifting in the register
112. urrent of 40 mA results in an active energy accumulation of 113 after 2000 half line cycles one LSB variation in this reading represents an 0 8 error This measurement does not provide enough resolution to calibrate out a lt 1 offset error However if the active energy is accumulated over 37 500 half line cycles one LSB variation results in 0 05 error reducing the quantization error APOS is 672 using Equations 55 ha 49 LAENERGY Absolute Error LAENERGY mixGonina LAENERGY min expected LAENERGY Absolute Error 1395 1370 25 54 AENERGY Error Rate LSB s LAENERGY Absolute Error M CLKIN 55 LINECYC 2 8x PERIOD AENERGY Error Rate LSB s ZEN 3 579545 x10 0 069948771 35700 2 8x 8959 AENERGY Error Rate x 2 CLKIN APOS 35 APOS 2 069948771x2 a 3 579545 x10 Rev A Page 42 of 60 Phase Calibration The PHCAL register is provided to remove small phase errors The ADE7753 compensates for phase error by inserting a small time delay or advance on the voltage channel input Phase leads up to 1 84 and phase lags up to 0 72 at 50 Hz can be corrected The error is determined by measuring the active energy at Is and two power factors PF 1 and PF 0 5 inductive Some CTs may introduce large phase errors that are beyond the range of the phase calibration register In this case coarse phase compensation has to be done externally with an analog filter The ph
113. x sin 4nfit 19 i where f is the line frequency for example 60 Hz E t VIt vit w 7 From Equation 19 it can be seen that there is a small ripple in the energy calculation due to a sin 2 wt component This is shown graphically in Figure 68 The active energy calculation is shown by the dashed straight line and is equal to V x Ix t The sinusoidal ripple in the active energy calculation is also shown VI 4xnxfi 142x1 8 9 Hz Jenat t 02875 0 067 Figure 68 Output Frequency Ripple OUTPUT FROM LPF2 APOS 15 0 ee ACCUMULATE ACTIVE LPF1 23 0 ENERGY IN INTERNAL LAENERGY 23 0 REGISTER AND UPDATE Gainers ZERO CROSS f peu THE LAENERGY REGISTER ADC DETECTION AT THE END OF LINECYC LINE CYCLES LINECYC 15 0 02875 0 068 Figure 69 Energy Calculation Line Cycle Energy Accumulation Mode Rev A Page 31 of 60 ADE7753 LINE CYCLE ENERGY ACCUMULATION MODE In line cycle energy accumulation mode the energy accumula tion of the ADE7753 can be synchronized to the Channel 2 zero crossing so that active energy can be accumulated over an integral number of half line cycles The advantage of summing the active energy over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0 This eliminates any ripple in the energy calculation Energy is calculated more accurately and in a shorter time because the integration period can be shortened By using
114. xternally in the microprocessor using an amps LSB constant To minimize noise synchronize the reading of the rms register with the zero crossing of the voltage input and take the average of a number of readings Channel 1 RMS Offset Compensation The ADE7753 incorporates a Channel 1 rms offset compensa tion register IRMSOS This is 12 bit WIN Fegister that can be used to remove offset in the Channel Viti Sicalculation An offset could exist in the rms calculation due to input noises that are integrated in the dc component of V t The offset calibration allows the content of the IRMS register to be maintained at 0 when no input is present on Channel 1 One LSB of the Channel 1 rms offset is equivalent to 32 768 LSB of the square of the Channel 1 rms register Assuming that the maximum value from the Channel 1 rms calculation is 1 868 467d with full scale ac inputs then 1 LSB of the Channel 1 rms offset represents 0 4696 of measurement error at 60 dB down of full scale IRMS JIRMS IRMSOS x32768 4 where IRMS is the rms measurement without offset correction To measure the offset of the rms measurement two data points are needed from non zero input values for example the base current Ip and Imax 100 The offset can be calculated from these measurements CHANNEL 2 ADC Channel 2 Sampling In Channel 2 waveform sampling mode MODE 14 13 1 1 and WSMP 1 the ADC output code scaling for Channel 2 is not the same
115. y Accumulation Mode Line Cycle Register This 16 bit register is used during line cycle energy accumulation mode to set the aumberof half line cycles for energy accumulation see the Line Cycle Energy Accumulation Mede SeGtion l Zero Crossing TimeoutJf no zero cfossiggs afe detected on Channel 2 within a time period specified by this 12 bit register the interrupt request line IRQ is activated see the Zero Crossing Detection section Sag Line Cycle Register This 8 bit register specifies the number of consecutive line cycles the signal on Channel 2 must be below SAGLVL before the SAG output is activated see the Line Voltage Sag Detection section Sag Voltage Level An 8 bit write to this register determines at what peak signal level on Channel 2 the SAG pin becomes active The signal must remain low for the number of cycles specified in the SAGCYC register before the SAG pin is activated see the Line Voltage Sag Detection section Channel 1 Peak Level Threshold Current Channel This register sets the level of the current peak detection If the Channel 1 input exceeds this level the PKI flag in the status register is set Channel 2 Peak Level Threshold Voltage Channel This register sets the level of the voltage peak detection If the Channel 2 input exceeds this level the PKV flag in the status register is set Channel 1 Peak Register The maximum input value of the current channel since the last read of the register is stored in

ANALOG DEVICES ADE7753 handbook(1)

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