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ANALOG DEVICES AD7896 handbook

1. 2 7 V S version Note that at 3 0 V operation A B J versions an SCLK of 10 MHz throughput rate of 100 kHz may be acceptable if the required processor setup time is 0 ns this may be possible with an ASIC or FPGA The data must be read in the next 10 ns which is specified as the data hold time t after the SCLK edge The AD7896 counts the serial clock edges to know which bit from the output register should be placed on the SDATA out put To ensure that the part does not lose synchronization the serial clock counter is reset on the falling edge of the CONVST input provided the SCLK line is low The user should ensure that a falling edge on the CONVST input does not occur while a serial data read operation is in progress MICROPROCESSOR MICROCONTROLLER INTERFACE The AD7896 B a 3 wire seri used fi np micr ontr flrs 1 terf processors AG AD 789 accepts an external serial clock and as a result in all interfaces shown here the processor controller is configured as the master providing the serial clock with the AD7896 configured as the slave in the system AD7896 8051 Interface Figure 5 shows an interface between the AD7896 and the 8X51 L51 microcontroller The 8X51 L51 is configured for its Mode 0 serial interface mode The diagram shows the simplest form of the interface where the AD7896 is the only part connected to the serial port of the 8X51 L51 and therefore no decoding of the serial read operations is require
2. CONVST and new data from this conversion is available in the output register of the AD7896 8 us later Once the read opera ion has i place anoth ge allowed before the n ds At CO the settling of the track ifie f ith t PA e ersion is initiated of 10 MHz 5 V operation the le hronghput ti time for the part is 8 us conversion time plus 1 6 us read time plus 0 4 us acquisi tion time This results in a minimum throughput time of 10 us equivalent to a throughput rate of 100 kHz A serial clock of less than 10 MHz can be used but this will in turn mean that the throughput time will increase The read operation consists of 16 serial clock pulses to the output shift register of the AD7896 After 16 serial clock pulses the shift register is reset and the SDATA line is three stated If there are more serial clock pulses after the 16th clock the shift register will be moved on past its reset state However the shift register will be reset again on the falling edge of the CONVST signal to ensure that the part returns to a known state every conversion cycle As a result a read operation from the output register should not straddle across the falling edge of CONVST as the output shift register will be reset in the middle of the read operation and the data read back into the microprocessor will appear invalid The throughput rate of the part can be increased by reading data during conversion If the data is read during conversio
3. ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN ww BOLLC CcO0M Narrow Body R 8 Dimensions shown in millimeters and inches 5 00 0 1968 Haso 01800 8 5 4 00 0 1574 6 20 0 2440 3 80 0 1497 T1 a 5 80 0 2284 yo SJ 1 27 0 0500 0 50 0 0196 yx BSC 1 75 0 0688 e 0 25 0 0099 0 25 0 0098 1 35 0 0532 0 10 0 0040 y Y LAN 0 51 0 0201 ye 8 lle COPLANARITY 2 rime 0 31 0 0122 0 25 0 0098 0 1 27 0 0500 010 PLANE 0 17 0 0067 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLV AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV C 13 AD7896 Revision History Location Page 7 03 Data Sheet changed from REV B to REV C Changes to SPECIFICATIONS suicida dees Woes bark eee dae l a 2 Changes to Figure Li a ee een a 3 Edits to ORDERING GUIDE i Fee ee a 4 Added ESD Warning u 2 Rs an ll ARE RL 4 Updated OUTLINE DIMENSIONS arene l a IE a I e a E 13 14 REV C ww BDI C com AD ww BDI C Com AD
4. V 2 4 2 4 2 4 2 4 Vpp 5 V 10 Input Low Voltage Vint 0 8 0 8 0 8 0 8 V max Input Current In 10 10 10 10 HA max Vin 0 V to Vpp Input Capacitance Ciy 10 10 10 10 pF max LOGIC OUTPUTS Output High Voltage Voy 2 4 2 4 2 4 2 4 V min Isource 400 pA Output Low Voltage Vor 0 4 0 4 0 4 0 4 V max IsinR 1 6 mA Output Coding Straight Natural Binary CONVERSION RATE Conversion Time Mode 1 Operation 8 8 8 8 5 Us max Mode 2 Operation 14 14 14 14 5 us max Track and Hold Acquisition Time 1 5 1 5 1 5 1 5 Us max REV C AD7896 Test Conditions Parameter A Version B Version J Version S Version Unit Comments POWER REQUIREMENTS Vop 2 7 5 5 2 7 5 5 2 7 5 5 2 7 5 5 V min max Ipp 4 4 4 4 mA max Digital Input Y DGND Vpp 2 7V t03 6V 5 5 5 5 mA max Digital Inputs Y DGND Vop 5V1 10 Power Dissipation 10 8 10 8 10 8 10 8 mW max Vpp 2 7 V Typically 9 mW Power Down Mode Digital Inputs Y DGND Ipp 25 C 5 5 5 typ 5 HA max Vpp 2 7 V to 3 6 V Tun to Tax 15 15 75 75 HA max Vop 2 7 V to 3 6 V Ipp 25 C 50 50 50 50 HA max Vpp 5 V 10 Tmn to Tmax 150 150 500 500 HA max Vpp 5 V 10 Power Dissipation 25 C 13 5 13 5 13 5 13 5 uW max Vpp 2 7 V NOTES Temperature ranges are as follows A B Versions 40 C to 85 C J Version 0 C to 70 C S Version 55 C to 125 C Applies to Mode 1 operation See the section on Operating Modes 3See Terminology Sample tested 25 C t
5. o 40 10 100 1000 SAMPLING RATE IN Hz Figure 13 Power vs Sample Rate in Auto Power Down Mode REV C AD7896 OUTLINE DIMENSIONS 8 Lead Plastic Dual In Line Package PDIP N 8 Dimensions shown in inches and millimeters 8 Lead Ceramic Dual In Line Package CERDIP Q 8 Dimensions shown in inches and millimeters 0 375 9 53 0 005 0 13 0 055 1 40 0 365 9 27 MIN MAX u 0 355 9 02 ji ol b ki 5 0 295 7 49 0 310 7 87 0 285 7 24 0 220 5 59 1 a 0 275 6 98 r 0 325 8 26 E gt je 0 310 Gan 0 100 2 54 BSC 0 100 2 54 0 300 7 62 0 150 3 81 0 405 pd ce 29 MAX 0 320 8 13 BSC gt gt 0 135 3 43 E 9060 1 52 i 0 290 7 37 M 0 180 iois 9 120 8 05 0 200 5 08 0 015 0 38 4 57 0 38 MAX si 0 015 0 38 0 200 5 08 IN Ti 150 3 81 0 150 3 81 SEATING 0 010 0 25 0 125 3 18 0 130 3 30 30 PLANE 0 008 0 20 0 023 0 58 58 Di pl a a N 0 015 0 38 0 110 2 79 0 060 1 52 0 014 0 36 Je gati PLANE il 0 008 0 20 0 022 0 56 0 050 1 27 0 018 0 46 0 045 1 14 CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETERS DIMENSIONS 0 014 0 36 IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLV AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO 095AA CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE
6. ANALOG DEVICES 2 7V to 5 5 V 12 Bit 8 jus ADC in 8 Lead SOIC PDIP AD7896 FEATURES 100 kHz Throughput Rate Fast 12 Bit Sampling ADC with 8 ps Conversion Time 8 Lead PDIP and SOIC Single 2 7 V to 5 5 V Supply Operation High Speed Easy to Use Serial Interface On Chip Track and Hold Amplifier Analog Input Range Is 0 V to Supply High Input Impedance Low Power 9 mW Typ GENERAL DESCRIPTION The AD7896 is a fast 12 bit ADC that operates from a single 2 7 V to 5 5 V supply and is housed in small 8 lead PDIP and 8 lead SOIC packages The part contains an 8 he successive approximation ADC an on chip traq serial interface port clock input and a serial data output with the external serial clock accessing the serial data from the part In addition to the traditional dc accuracy specifications such as linearity full scale and offset errors the AD7896 is also speci fied for dynamic performance parameters including harmonic distortion and signal to noise ratio The part accepts an analog input range of 0 V to Vpp and operates from a single 2 7 V to 5 5 V supply consuming only 9 mW typical The Vpp input is also used as the reference for the part so that no external reference is required The AD7896 features a high sampling rate mode and for low power applications a proprietary automatic power down mode where the part automatically goes into power down once conver sion is complete and wakes up before the ne
7. a fast 12 bit ADC that operates from a single 2 7 V to 5 5 V supply It provides the user with a track and hold ADC and serial interface logic functions on a single chip The ADC section of the AD7896 consists of a conven tional successive approximation converter based on an R 2R ladder structure The internal reference for the AD7896 is derived from Vpp which allows the part to accept an analog input range of 0 V to Vpp The AD7896 has two operating modes the high sampling mode and the auto sleep mode where the part automatically goes into sleep after the end of conversion These modes are discussed in more detail in the Timing and Control section A major advantage of the AD7896 is that it provides all of the preceding functions in an 8 lead package PDIP or SOIC This offers the user considerable space saving advantages over alterna tive solutions The AD7896 consumes only 9 mW typical making it ideal for battery powered applications Conversion is initiated on the AD7896 by pulsing the CONVST input On the falling edge of CONVST the on chip track and hold goes from track to hold mode and the conversion sequence is started The conversion clock for the part is generated inter nally using a laser trimmed clock oscillator circuit Conversion time for the AD7896 is 8 us in the high sampling mode 14 us for the auto sleep mode and the track and hold acquisition time is 1 5 us To obtain optimum performance from the part t
8. agram of Figure 6 With the BUSY line from the AD7896 connected to the Port PC2 of the 68HC11 L11 the BUSY line can be polled by the 68HC11 L11 10 The BUSY line can be connected to the IRQ line of the 68HC11 L11 if an interrupt driven system is preferred These two options are shown in the diagram The serial clock rate from the 68HC11 L11 is limited to signifi cantly less than the allowable input serial clock frequency with which the AD7896 can operate As a result the time to read data from the part will actually be longer than the conversion time of the part This means that the AD7896 cannot run at its maximum throughput rate when used with the 68HC11 L11 PC2 OR ma 68HC11 L11 AD7896 Figure 6 AD7896 to 68HC11 L11 Interface AD7896 ADSP 2103 ADSP 2105 Interface An interface circuit between the AD7896 and the ADSP 2103 ADSP 2105 DSP processor is shown in Figure 7 In the interface shown the RFSI output from the ADSP 2103 ADSP 2105s SPORTI serial port is used to gate the serial clock SCLKI of the ADSP 2103 ADSP 2105 before it is applied to the SCLK input of the AD7896 The RFSI output is configured tive high operation The BWSY li AD7896 is connected e JRQ of 3 ABSP 2105 so that at thefend o is genegated telling the 21 on The inter face ensures a noncontinuous clock for the AD7896 s serial clock input with only 16 serial clock pulses provided and the serial clock line of the AD7896 remainin
9. case the BUSY will be the best indicator for when the conversion is complete Even though the part is in sleep mode data can still be read from the part The read operation consists of 16 clock cycles as in Mode 1 operation For the fastest serial clock of 10 MHz at 5 V operation the read operation will take 1 6 us which must be complete at least 400 ns before the falling edge of the next CONVST to allow the track and hold amplifier to have enough time to settle This mode is very useful when the part is converting at a slow rate as the power consumption will be significantly reduced from that of Mode 1 operation t4 40ns MIN 400ns MIN gt SCLK ld tconvert a CONVERSION IS INITIATED AND TRACK AND HOLD GOES INTO HOLD 8us LATER CONVERSION ENDS chi READ READ tuoi dii OPERATION SHOULD END 400ns SERIAL PRIOR TO NEXT SHIFT FALLING EDGE OF REGISTER CONVST IS RESET Figure 2 Mode 1 Timing Operation Diagram for High Sampling Performance jet CONVST Le tconvert 144s gt I PART CONVERSION CONVERSION WAKES IS INITIATED ENDS UP TRACK AND 14us LATER HOLD GOES INTO HOLD t 6ps WAKE UP TIME N 5 io ia SUE f 4 SERIAL READ READ OPERATION OUTPUT OPERATION SHOULD END 400ns SERIAL PRIORTO NEXT SHIFT FALLING EDGE OF REGISTER IS RESET CONVST Figure 3 Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated REV AD7896 Serial Interface The se
10. d t2 ts 40ns MIN t4 60ns MAX ts 10ns MIN tg 50ns MAX 5V A B VERSIONS gt t ke SCLK 1 P 1 2 3 gt t 4 THREE STATE wi 5 6 15 16 re Eu 4 LEADING ZEROS THREE STATE DOUT O P DB1 DB10 Figure 4 Data Read Operation REV C AD7896 To chip select the AD7896 in systems where more than one device is connected to the 8X51 L51 serial port a port bit configured as an output from one of the 8X51 L51 parallel ports can be used to gate on or off the serial clock to the AD7896 A simple AND function on this port bit and the serial clock from the 8X51 L51 will provide this function The port bit should be high to select the AD7896 and low when it is not selected The end of conversion is monitored by using the BUSY signal which is shown in the interface diagram of Figure 5 with the BUSY line from the AD7896 connected to the Port P1 2 of the 8X51 L51 so the BUSY line can be polled by the 8X51 L51 The BUSY line can be connected to the INTI line of the 8X51 L51 if an interrupt driven system is preferred These two options are shown on the diagram Note also that the AD7896 outputs the MSB first during a read operation while the 8X51 L51 expects the LSB first Therefore the data that is read into the serial buffer needs to be rearranged before the correct data format from the AD7896 appears in the accumulator The serial clock rate from the 8X51 L51 is limited to signifi cantly less than the all
11. d Acquisition Time Track and hold acquisition time is the time required for the output of the track and hold amplifier to reach its final value within 1 2 LSB after the end of conversion the point at which the track and hold returns into track mode It also applies to a situation where there is a step input change on the input voltage applied to the selected Vw input of the AD7896 It means that the user must wait a the duration of the tnaekzand held tion time after nfor aft to Viy before st sion operates to specifica Signal to Noise Distortion Ratio This is the measured ratio of signal to noise distortion at the output of the ADC The signal is the rms amplitude of the fun damental Noise is the sum of all nonfundamental signals up to half the sampling frequency fs 2 excluding dc The ratio is dependent on the number of quantization levels in the digitiza tion process the more levels the smaller the quantization noise The theoretical signal to noise distortion ratio for an ideal N bit converter with a sine wave input is given by Signal to Notse Distortion 6 02N 1 76 dB Thus for a 12 bit converter this is 74 dB Total Harmonic Distortion Total harmonic distortion THD is the ratio of the rms sum of harmonics to the fundamental For the AD7896 it is defined as MARZARZAZIZZZA Y THD dB 20 log where V is the rms amplitude of the fundamental and V2 V3 Va Vs and Ve are the r
12. ee eee eee 220 C Extended S Version 55 C to 125 C ESD iris bind nenne gt 4000 V Storage Temperature Range 65 C to 150 C Stresses above those listed under Absolute Maximum Ratings may cause perma Junction Temperature O A 150 C nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ORDERING GUIDE Temperature Linearity SNR Package Model Range Error LSB dB Option AD7896AN 40 C to 85 C 70 N 8 AD7896BN 40 C to 85 C 1 2 70 N 8 AD7896AR 40 C to 85 C 70 R 8 AD7896AR REEL 40 C to 85 C 1 70 R 8 AD7896AR REEL7 40 C to 85 C del 70 R 8 AD7896BR E 70 R 8 7 R 2 1 2 70 8 J 8 AD7896JR REEL 0 C to 70 C 1 70 R 8 AD7896SQ 55 C to 125 C 70 Q 8 EVAL AD7896CB Evaluation Board N PDIP Q CERDIP R SOIC CAUTION accumulate on the human body and test equipment and can discharge w ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily ithout detection Although the WARN N G l el AD7896 features proprietary ESD protection circuitry permanent damage may occur on devices precautions are recommended ESD SENSITIVE DEVICE subjected to high energ
13. ers for the part are 1 4 LSB while the typical DNL errors are 1 2 LSB Noise In an ADC noise exhibits itself as code uncertainty in de appli cations and as the noise floor in an FF T for example in ac applications In a sampling ADC like the AD7896 all informa tion about the analog input appears in the baseband from dc to 1 2 the sampling frequency The input bandwidth of the track and hold exceeds the Nyquist bandwidth and therefore an antialiasing filter should be used to remove unwanted signals above fs 2 in the input signal in applications where such signals exist REV C Figure 9 shows a histogram plot for 8192 conversions of a de input using the AD7896 with a 3 3 V supply The analog input was set at the center of a code transition It can be seen that almost all the codes appear in the one output bin indicating very good noise performance from the ADC The rms noise performance for the AD7896 for the plot below was 111 UV f sampLe 95kHz fsc k 8 33MHz AIN CENTERED ON CODE 1005 RMS NOISE 0 138 LSB OCCURRENCE 1005 1006 CODE Figure 9 Histogram of 8192 Conversions of a DC Input The same data is presented in Figure 10 as in Figure 9 except that in this case the output data read for the device occurs during conversion This has the effect of injecting noise onto the die while bit decisions are being made and this increases the oise FO by the AD7896 m plot for 8192 conve
14. g low between data transfers The SDATA line from the AD7896 is connected to the DRI line of the ADSP 2103 ADSP 2105 serial port The timing relationship between the SCLK1 and RFS1 outputs of the ADSP 2103 ADSP 2105 are such that the delay between the rising edge of the SCLKI and the rising edge of an active high RFS1 is up to 30 ns There is also a requirement that data must be set up 10 ns prior to the falling edge of the SCLK1 to be read correctly by the ADSP 2103 ADSP 2105 The data access time for the AD7896 is 60 ns 5 V A B versions from the rising edge of its SCLK input Assuming a 10 ns propaga tion delay through the external AND gate the high time of the SCLK1 output of the ADSP 2105 must be gt 30 60 10 10 ns i e 2110 ns This means that the serial clock fre quency with which the interface of Figure 7 can work is limited to 4 5 MHz However there is an alternative method that allows for the ADSP 2105 SCLKI to run at 5 MHz which is the max serial clock frequency of the SCLK1 output The arrangement is where the first leading zero of the data stream from the AD7896 cannot be guaranteed to be clocked into the ADSP 2105 due to the combined delay of the RES signal and the data access time of the AD7896 In most cases this is acceptable as there will still be three leading zeros followed by the 12 data bits For the ADSP 2103 the SCLK1 frequency will need to be limited to lt 4 MHz to account for the 100 ns data access ti
15. gt larger spread of codes with ti ef his e n i easing to 279 UV Be serial clock edges appear ipa dai to the bit trials of the conversion process It is possible to achieve the same level of performance when reading during conversion as when reading after conver sion depending on the relationship of the serial clock edges to the bit trial points 8000 7000 f sampLE 95kHz f seLk 8 33MHz AIN CENTERED ON 6000 CODE 1005 RMS NOISE 0 346 LSB w W 5000 E E 4000 D 8 8 3000 2000 1000 p 1004 1005 1006 CODE Figure 10 Histogram of 8192 Conversions with Read during Conversion 11 AD7896 Dynamic Performance Mode 1 Only With a combined conversion and acquisition time of 9 5 us the AD7896 is ideal for wide bandwidth signal processing applications These applications require information on the ADC s effect on the spectral content of the input signal Signal to noise distortion total harmonic distortion peak harmonic or spurious noise and intermodulation distortion are all specified Figure 11 shows a typical FFT plot of a 10 kHz 0 V to 3 3 V input after being digi tized by the AD7896 operating at a 102 4 kHz sampling rate The signal to noise distortion ratio is 71 5 dB and the total harmonic distortion is 82 4 dB fsampLe 102 4kHz fin 10kHz SNR 71 54dB THD 82 43dB 0 10240 20480 30720 40960 51200 FREQUENCY H
16. han the other bits is due to the internal architecture of the part Sixteen clock pulses must be provided to the part to access the full conversion result will be valid for a i time to allow the bie to be read on the falling edge of SCLK and then the SDATA line is disabled three stated After this last bit has been clocked out the SCLK input should remain low until the next serial data read opera tion If there are extra clock pulses after the 16th clock the AD7896 will start over again with outputting data from its out put register and the data bus will no longer be three stated even when the clock stops Provided the serial clock has stopped before the next falling edge of CONVST the AD7896 will continue to operate correctly with the output shift register being reset on the falling edge of CONVST However the SCLK line must be low when CONVST goes low in order to reset the output shift register correctly The serial clock input does not need to be continuous during the serial read operation The 16 bits of data four leading zeros and 12 bit conversion result can be read from the AD7896 in a number of bytes However the SCLK input must remain low between the two bytes The maximum SCLK frequency is 10 MHz for 5 V operation giving a throughput of 100 kHz and at 2 7 V the maximum SCLK frequency is less than 10 MHz to allow for the longer data access time t4 60 ns 5 V 100 ns 2 7 V A B J versions 70 ns 5 V 110 ns
17. he read operation should not occur during the conversion or to operate at t sheet speci 1 CIRCUIT DESCRIPTION Analog Input Section The analog input range for the AD7896 is 0 V to Vpp The Vin pin drives the input to the track and hold amplifier directly This allows for a maximum output impedance of the circuit driving the analog input of 1 kQ This ensures that the part will be settled to 12 bit accuracy in the 1 5 us acquisition time This input is benign with dynamic charging currents The designed code transitions occur on successive integer LSB values i e FS 1 LSB Output coding is straight 1 LSB 2 LSB 3 LSB natural binary with 1 LSB FS 4096 3 3 V 4096 0 81 mV The ideal input output transfer function is shown in Table I Table I Ideal Input Output Code Table for the AD7896 Analog Input Code Transition FSR 1 LSB 3 299194 111 110tolll 111 FSR 2 LSB 3 298389 111 101to111 110 FSR 2 3 LSB 3 297583 111 100to 111 101 AGND 3 LSB 0 002417 000 010to 000 011 AGND 2 LSB 0 001611 000 001to 000 010 AGND 1 LSB 0 000806 000 000 to 000 001 NOTES FSR is full scale range and is 3 3 V with Vpp 3 3 V 21 LSB FSR 4096 0 81 mV with Vpp 3 3 V Track and Hold Section The track and hold amplifier on the analog input of the AD7896 allows the ADC to accurately convert an input sine wave of full scale amplitude to 12 bit accuracy The i
18. me of the AD7896 at 3 V REV C AD7896 An alternative scheme is to configure the ADSP 2103 ADSP 2105 such that it accepts an external noncontinuous serial clock In this case an external noncontinuous serial clock is provided that drives the serial clock inputs of both the ADSP 2103 ADSP 2105 and the AD7896 In this scheme the serial clock frequency is limited to 10 MHz by the AD7896 RFS1 ADSP 2103 ADSP 2105 AD7896 Figure 7 AD7896 to ADSP 2103 ADSP 2105 Interface AD7896 DSP56002 L002 Interface Figure 8 shows an interface circuit between the AD7896 and the DSP56002 L002 DSP processor The DSP56002 L002 is con figured for normal mode asynchronous operation with gated clock It is also set up for a 16 bit word with SCK as gated clock output In this mode the DSP56002 L002 provides 16 serial clock pulses to the AD7896 in a serial read operation The DSP56002 L002 assumes valid data on the first falling edge of SCK so the interface is simply 2 wire as shown in Figure 8 The BUSY line from the AD7896 is connected to the MODA IRQA input F the DSP56002 L002 s 2 generated rsi n operation eX gonver MODA IRQA DSP56002 L002 Figure 8 AD7896 to DSP56002 L002 Interface AD7896 PERFORMANCE Linearity The linearity of the AD7896 is determined by the on chip 12 bit DAC This is a segmented DAC that is laser trimmed for 12 bit integral linearity and differential linearity Typical relative accu racy numb
19. ms amplitudes of the second through the sixth harmonics Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum up to fs 2 and excluding dc to the rms value of the fundamental Normally the value of this specification is deter mined by the largest harmonic in the spectrum but for parts where the harmonics are buried in the noise floor it will be a noise peak Intermodulation Distortion With inputs consisting of sine waves at two frequencies fa and fb any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m n 0 1 2 3 etc Intermodulation distortion terms are those for which neither m nor n are equal to zero For example the second order terms include fa fb and fa fb while the third in terms include 2fa fb 2fa fb fa 2fb and The AD7 input freqtiencie et In thi ondor in frequency a the i sine waves wide the third order terms are usually at a frequency close to the input frequencies As a result the second and third order terms are specified sepa rately The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dB REV C AD7896 CONVERTER DETAILS The AD7896 is
20. n a throughput time of 8 us conversion time plus 1 5 us acquisi tion time is achieved when a 10 MHz 5 V operation serial clock is being used This minimum throughput time of 9 5 us is achieved with a slight reduction in performance from the AD7896 The advantage of this arrangement is that when the serial clock is significantly lower than 10 MHz the throughput time for this arrangement will be significantly less than the throughput time where the data is read after conversion The signal to noise distortion number is likely to degrade by less than 1 dB while the code flicker from the part will also increase see the AD7896 Performance section AD7896 OPERATING MODES Mode 1 Operation High Sampling Performance The timing diagram in Figure 2 is for optimum performance in Operating Mode 1 where the falling edge of CONVST starts the conversion and puts the track and hold amplifier into its hold mode This falling edge of CONVST also causes the BUSY signal to go high to indicate that a conversion is taking place The BUSY signal goes low when the conversion is complete which is 8 us max after the falling edge of CONVST and new data from this conversion is available in the output register of the AD7896 A read operation accesses this data This read operation consists of 16 clock cycles and the length of this read operation depends on the serial clock frequency For the fastest throughput rate with a serial clock of 10 MHz at 5 V
21. nput bandwidth of the REV C track and hold is greater than the Nyquist rate of the ADC even when the ADC is operated at its maximum throughput rate of 100 KHz i e the track and hold can handle input frequencies in excess of 50 kHz The track and hold amplifier acquires an input signal to 12 bit accuracy in less than 1 5 us The operation of the track and hold is essentially transparent to the user With the high sampling operating mode the track and hold amplifier goes from its tracking mode to its hold mode at the start of conversion i e the rising edge of CONVST The aperture time for the track and hold i e the delay time between the external CONVST signal and the track and hold actually going into hold is typi cally 15 ns At the end of conversion on the falling edge of BUSY the part returns to its tracking mode The acquisition time of the track and hold amplifier begins at this point For the auto shutdown mode the rising edge of CONVST wakes up the part and the track and hold amplifier goes from its tracking mode to its hold mode 6 us after the rising edge of CONVST provided that the CONVST high time is less than 6 us Once again the part returns to its tracking mode at the end of conver sion when the BUSY signal goes low Timing and Control Figure 2 shows the timing and control sequence required to obtain optimum performance from the AD7896 In the sequence shown conversion is initiated on the falling edge of
22. o ensure compliance gt This 14 us includes the wake up time from standby This wake up time is timed from the rising edge of CONVST whereas conversion is timed from the falling edge of CONVST for narrow CONVST pulsewidth the conversion time is effectively the wake up time plus conversion time hence 14 us This can be seen from Figure 3 Note that if the CONVST pulsewidth is greater than 6 us the effective conversion time will increase beyond 14 us Specifications subject to change without notice TIMING CHARACTERISTICS Von 2 7 V to 5 5 V AGND DGND 0 V ni s min e t3 40 40 45 ns min SCLK Low Pulsewidth ty Data Access Time after Falling Edge of SCLK 60 60 70 nsmax Vpp 5 V 10 100 100 110 nsmax Vpp 2 7 V to 3 6 V ts 10 10 10 ns min Data Hold Time after Falling Edge of SCLK te 504 504 504 ns max Bus Relinquish Time after Falling Edge of SCLK NOTES Sample tested at 25 C to ensure compliance All input signals are measured with tr tf 1 ns 10 to 90 of V pp and timed from a voltage level of 1 4 V The SCLK maximum frequency is 10 MHz Care must be taken when interfacing to account for the data access time t 4 and the setup time required for the user s processor These two times will determine the maximum SCLK frequency that the user s system can operate with See Serial Interface section for more information 3 Measured with the load circuit of Figure 1 and defined as the
23. ology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD7896 SPECIFICATIONS Voo 2 7 V to 5 5 V AGND DGND 0 V All specifications Tyjy to Tmax unless otherwise noted Test Conditions Parameter A Version B Version J Version S Version Unit Comments DYNAMIC PERFORMANCE Signal to Noise Distortion Ratio 25 C 70 70 70 typ 70 dB min fin 10 kHz Sine Wave SAMPLE 100 kHz Tmn to Tmax 70 dB min Total Harmonic Distortion THD l 80 80 80 typ 80 dB max fin 10 kHz Sine Wave SAMPLE 100 kHz Peak Harmonic or Spurious Noise l 80 80 80 typ dB max fin 10 kHz Sine Wave SAMPLE 100 kHz Intermodulation Distortion IMD fa 9 kHz fb 9 5 kHz fsAMPLE 100 KHz Second Order Terms 80 80 80 typ 80 dB max Third Order Terms 80 80 80 typ 80 dB max DC ACCURACY Resolution 12 12 12 12 Bits Minimum Resolution for Which No Missing Codes Are Guaranteed 12 12 12 12 Bits Relative Accuracy 1 2 LSB max Differential Nonlinearity 1 1 1 1 LSB max Positive Full Scale Error 3 11 5 13 13 LSB max Unipolar Offset Error 4 5 4 LSB max Vpp 5 V 10 4 3 5 4 LSB max Vpp 2 7 V to 3 6 V ANALOG INPUT Input Voltage Range 0 to Vpp Oto Vpp 0to Vpp 0 to Vpp V Input Current 5 LOGIC INPU Input High Voltag 0 0 V in Vp to 3 6
24. opera tion the read operation will take 1 6 us The read operation must be complete at least 400 ns before the falling edge of the next CONVST which gives a total time of 10 us for the full throughput time equivalent to 100 kHz This mode of opera tion should be used for high sampling applications Mode 2 Operation Auto Sleep after Conversion The timing diagram in Figure 3 is for optimum performance in Operating Mode 2 where the part automatically goes into sleep mode once BUSY goes low after conversion and wakes up tconvert 84S before the next conversion takes place This is achieved by keeping CONVST low at the end of conversion whereas it was high at the end of conversion for Mode 1 operation The rising edge of CONVST wakes up the part This wake up time is 6 us at which point the track and hold amplifier goes into its hold mode The conversion takes 8 us after this provided the CONVST has gone low giving a total of 14 us from the rising edge of CONVST to the conversion being complete which is indicated by the BUSY going low Note that since the wake up time from the rising edge of CONVST is 6 us when the CONVST pulsewidth is greater than 6 us the conversion will take more than the 14 us shown in the diagram from the rising edge of CONVST This is because the track and hold amplifier goes into its hold mode on the falling edge of CONVST and then the conversion will not be complete for a further 8 us In this
25. owable input serial clock frequency with which the AD7896 can operate As a result the time to read data from the part will actually be longer than the conversion time of the part This means that the AD7896 cannot run at its maximum throughput rate when used with the 8X51 L51 Figure 5 AD7896 to 8X51 L51 Interface AD7896 68HC11 L11 Interface An interface circuit between the AD7896 and the 68HC11 L11 microcontroller is shown in Figure 6 For the interface shown the 68HC11 L11 SPI port is used and the 68HC11 L11 is con figured in its single chip mode The 68HC11 L11 is configured in the master mode with its CPOL bit set to a Logic 0 and its CPHA bit set to a Logic 1 As with the previous interface the diagram shows the simplest form of the interface where the AD7896 is the only part connected to the serial port of the 68HC11 L11 and therefore no decoding of the serial read operations is required Once again to chip select the AD7896 in systems where more than one device is connected to the 68HC11 L11 serial port a port bit configured as an output from one of the 68HC11 L11 parallel ports can be used to gate on or off the serial clock to the AD7896 A simple AND function on this port bit and the serial clock from the 68HC11 L11 will provide this function The port bit should be high to select the AD7896 and low when it is not selected The end of conversion is monitored by using the BUSY signal which is shown in the interface di
26. rial interface to the AD7896 consists of three wires a serial clock input SCLK the serial data output SDATA and a conversion status output BUSY This allows for an easy to use interface to most microcontrollers DSP processors and shift registers Figure 4 shows the timing diagram for the read operation to the AD7896 The serial clock input SCLK provides the clock source for the serial interface Serial data is clocked out from the SDATA line on the falling edge of this clock and is valid on both the rising and falling edges of SCLK The advantage of having the data valid on both the rising and falling edges of the SCLK is to give the user greater flexibility in interfacing to the part and so that a wider range of microprocessor and microcontroller inter faces can be accommodated This also explains the two timing figures ty and t that are quoted on the diagram The time t speci fies how long after the falling edge of the SCLK that the next data bit becomes valid whereas the time t specifies how long after the falling edge of the SCLK that the current data bit is valid for The first leading zero is clocked out on the first rising edge of SCLK note that the first zero may be valid on the first falling edge of SCLK even though the data access time is specified at 60 ns 5 V A B J versions only for the other bits and the SCLK high time will be 50 ns with a 10 MHz SCLK The reason that the first bit will be clocked out faster t
27. time required for an output to cross 0 8 V or 2 V Derived from the measured time taken by the data outputs to change 0 5 V when loaded with the circuit of Figure 1 The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor This means that the time t quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances Figure 1 Load Circuit for Access Time and Bus Relinquish Time REV C AD7896 ABSOLUTE MAXIMUM RATINGS PDIP Package Power Dissipation 450 mW Ta 25 C unless otherwise noted Ora Thermal Impedance 125 C W Vppto AGND Sena 0 3 V to 7 V fic Thermal Impedance LL 50 C W Vpp t0 DGND israele 0 3 V to 7 V Lead Temperature Soldering 10 sec 260 C Analog Input Voltage to AGND 0 3 V to Vpp 0 3 V SOIC Package Power Dissipation 450 mW Digital Input Voltage to DGND 0 3 V to Vpp 0 3 V Oy Thermal Impedance 4 160 C W Digital Output Voltage to DGND 0 3 V to Vpp 0 3 V Bic Thermal Impedance oo o ooococomooo o 75 C W Operating Temperature Range Lead Temperature Soldering Commercial J Version 04 0 C to 70 C Vapor Phase 60 sec LL 215 C Industrial A B Versions 40 C to 85 C Infrared 15 sec eee eee e
28. wed by the 12 bits of conversion data On the 16th falling edge of SCLK the SDATA line is held for the data hold timegan ee data coding is straight bina d hold goes into its hold mode and conversion is initiated If CONVST is low at th end of conversion the part goes into power down mode In this case the rising edge of CONVST wakes up the part The BUSY pin is used to indicate when the part is doing a conversion The BUSY pin goes high on the falling edge of CONVST and returns low when the conversion is complete AD7896 TERMINOLOGY Relative Accuracy This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function The end points of the transfer function are zero scale which is Viy AGND 1 2 LSB a point 1 2 LSB below the first code transi tion 00 000 to 00 001 and full scale which is V AGND Vpp 1 2 LSB a point 1 2 LSB above the last code transition 11 110to11 111 Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC Unipolar Offset Error This is the deviation of the first code transition 00 000 to 00 001 from the ideal Vyn voltage AGND 1 LSB Positive Full Scale Error This is the deviation of the last code transition 11 110 to 11 111 from the ideal Win AGND Vpp 1 LSB after the offset error has been adjusted out Track and Hol
29. xt conversion cycle The part is available in a small 8 lead 0 3 wide plastic or hermetic dual in line package PDIP and in an 8 lead small outline IC SOIC Patent Pending REV C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies FUNCTIONAL BLOCK DIAGRAM VoD AD7896 TRACK AND HOLD p OUTPUT REGISTER crock DGND BUSY TONVST AGND SCLK SDATA PRODUCT HIGHLIGHTS 1 Complete 12 bit ADC in an 8 Lead Package The AD7896 contains an 8 us ADC a track and hold ampli ran control pa and a high speed serial interface all in an i reference for the Low The AD7896 operates from a single 2 7 V to 5 5 V supply and consumes only 9 mW typical The automatic power down mode where the part goes into power down once conversion is complete and wakes up before the next con version cycle makes the AD7896 ideal for battery powered or portable applications 3 High Speed Serial Interface The part provides high speed serial data and serial clock lines allowing for an easy 2 wire serial interface arrangement One Techn
30. y electrostatic discharges Therefore proper ESD to avoid performance degradation or loss of functionality 4 REV C AD7896 PIN CONFIGURATION Vin 1 o 8 BUSY v AD7896 TONVST vol TOP VIEW z AGND 3 Not to Scale 6 DGND SCLK 4 5 SDATA PIN FUNCTION DESCRIPTIONS Mnemonic Description Vin Analog Input The analog input range is 0 V to Vpp Vop Positive supply voltage 2 7 V to 5 5 V AGND Analog Ground Ground reference for track and hold comparator and DAC SCLK Serial Clock Input An external serial clock is applied to this input to obtain serial data from the AD7896 A new serial data bit is clocked out on the falling edge of this serial clock Data is guaranteed valid for 10 ns after this falling edge so data can be accepted on the falling edge when a fast serial clock is used The serial clock input should be taken low at the end of the serial data transmission SDATA Serial Data Output Serial data from the AD7896 is provided at this output The serial data is clocked BUSY out by the falling edge of SCLK but the data can also be read on the falling edge of the SCLK This is possible because data bit N is valid for a specified time after the falling edge of the SCLK data hold time and can be read before data bit N 1 becomes valid a specified time after the falling edge of SCLK data access time see Figure 4 Sixteen bits of serial data are provided with four leading zeros follo
31. z Figure 11 AD7896 FF e the Terminology section is related to the resolution or number of bits in the converter Rewriting the formula below gives a mea sure of performance expressed in effective number of bits N N SNR 1 76 6 02 where SNR is the signal to noise distortion ratio The effective number of bits for a device can be calculated from its measured signal to noise distortion ratio Figure 12 shows a typical plot of effective number of bits versus frequency for the AD7896 from dc to fsamprinc 2 The sampling frequency is 102 4 kHz The plot shows that the AD7896 converts an input sine wave of 51 2 kHz to an effective numbers of bits of 11 25 which equates to a signal to noise distortion level of 69 dB 2 12 00 11 75 11 50 EFFECTIVE NUMBER OF BITS 11 25 11 00 o 25 6 51 2 INPUT FREQUENCY kHz Figure 12 Effective Number of Bits vs Frequency Power Considerations In the automatic power down mode the part can be operated at a sample rate that is considerably less than 100 kHz In this case the power consumption will be reduced and will depend on the sample rate Figure 13 shows a graph of the power con sumption versus sampling rates from 10 Hz to 1 kHz in the automatic power down mode The conditions are 2 7 V supply 25 C serial clock frequency of 8 33 MHz and the data was read after conversion 200 N o POWER nW ao

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