Home

ANALOG DEVICES AD7722 handbook

Contents

1. Figure 20 Single Ended to Differential Analog Input Circuit for Bipolar Mode Operation REV B The 1 nF capacitors at each ADC input store charge to aid the amplifier settling as the input is continuously sampled A resistor in series with the drive amplifier output and the 1 nF input capacitor may also be used to create an antialias filter Clock Generation The AD7722 contains an oscillator circuit to allow a crystal or an external clock signal to generate the master clock for the ADC The connection diagram for use with the crystal is shown in Figure 21 Consult the crystal manufacturer s recommendation for the load capacitors AD7722 XTAL CLKIN Figure 21 Crystal Oscillator Connection An external clock must be free of ringing and have a minimum rise time of 5 ns Degradation in performance can result as high edge rates increase coupling that can generate noise in the sampling process The connection diagram for an external clock source Figure 22 shows a series damping resistor connected between the clock output and the clock input to the AD7722 Figure 22 External Clock Oscillator Connection A low phase noise clock should be used to generate the ADC sampling clock because sampling clock jitter effectively modulates the input signal and raises the noise floor The sampling clock generator should be isolated from noisy digital circuits grounded and heavily decoupled to the analog ground plane
2. matty in t IIN huh il T U hi init adic WA TTA iii ET AIN 90kHz CLKIN 12 5 MHz SNR 89 6dB S N D 89 6dB SFDR 108 0dB Ji hu Mi Ni Ji nf I ih TA T TT Wii T ul LL 1 TH 20 40 60 80 98 FREQUENCY kHz TPC 15 16K Point FFT 13 AD7722 CIRCUIT DESCRIPTION The AD7722 ADC employs a Z A conversion technique that converts the analog input into a digital pulse train The analog input is continuously sampled by a switched capacitor modulator at twice the rate of the clock input frequency 2 x fcr xn The digital data that represents the analog input is in the ones density of the bit stream at the output of the X A modulator The modu lator outputs a bit stream at a data rate equal to for In Due to the high oversampling rate which spreads the quantization noise from 0 to fcr x 2 the noise energy contained in the band of interest is reduced Figure 9a To reduce the quantization noise further a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the band of interest Figure 9b The digital filter that follows the modulator provides three main functions The filter performs sophisticated averaging on the 1 bit samples from the output of the modulator while removing the large out of band quantization noise Figure 9c Lastly the digital filter reduces the data rate from fc x at the input of the filter to fci gm 64 at the output of the filter The
3. 104 6875 kHz Due to the sampling nature of the digital filter the filter does not provide any rejection at integer multiples of its input sampling frequency The filter response in Figure 10a shows the unattenu ated frequency bands occurring at n x Let Km Where n 1 2 3 At these frequencies there are frequency bands f gp wide fz ag is the 3 dB bandwidth of the digital filter on either side of n x Lr Km Where noise passes unattenuated to the output Out of band signals coincident with any of the filter images are aliased into the pass band However due to the AD7722 s high oversampling ratio these bands occupy only a small fraction of the spectrum and most broadband noise is filtered This means that the antialias filtering requirements in front of the AD7722 are considerably reduced versus a conventional converter with no on chip filtering Figure 10b shows the frequency response of an filter passes It may also be necessary in some applications to provide analog filtering in front of the AD7722 to ensure that differential noise signals outside the band of interest do not saturate the analog modulator 0dB TfeLkin 2fcLKIN SfcLKIN Figure 10a Digital Filter Frequency Response OUTPUT DATA RATE ANTIALIAS FILTER RESPONSE 0dB REGUIRED ATTENUATION fcLkn 64 CLKIN Figure 10b Frequency Response of Antialias Filter REV B AD7722 APPLYING THE AD7722 Analog Input Range The AD7722 uses d
4. 6875 kHz to 12 395 MHz Vin VinC UNI Ving UNI Vint Vin and Vin D D Offset between REF1 and REF2 REF1 AGND Applied to REF1 or REF2 Guaranteed Monotonic REF 2 Is an Ideal Reference REF1 AGND Unipolar Mode Bipolar Mode Test Conditions Comments Min Vom 2 5 V Vin Vin 1 25 V p p or VinC 1 25 V Vin 0 V to 2 5 V Input Bandwidth 0 kHz 90 625 kHz Input Bandwidth 0 kKHz 100 kHz for xm 14 MHz Input Bandwidth 0 kHz 90 625 kHz Input Bandwidth 0 kKHz 100 kHz for xm 14 MHz Input Bandwidth 0 kHz 90 625 kHz Input Bandwidth 0 kHz 100 kHz feri 14 MHz Vin 0 V Vin 0 V to 2 5 V Input Bandwidth 0 kHz 90 625 kHz Input Bandwidth 0 kHz 97 65 kHz Input Bandwidth 0 kHz 97 65 kHz 86 84 5 84 5 83 84 5 83 16 A Version Typ 2 47 60 Ha EE lre 2 5 Max Unit Bits LSB LSB mV FSR mV FSR LSB C LSB C LSB C REV B AD7722 A Version Parameter Test Conditions Comments Typ Maz Unit LOGIC INPUTS Excluding CLKIN Vinu Input High Voltage 2 0 V Viis Input Low Voltage 0 8 V CLOCK INPUT CLKIN Vinu Input High Voltage Vin Input Low Voltage ALL LOGIC INPUTS Im Input Current Vin 0 V to DVpp Cym Input Capacitance LOGIC OUTPUTS Vou Output High Voltage Iour 200 UA Vor Output Low Voltage Iour 1 6 mA POWER SUPPLIES AVpp AVpp1 DV nn Ipp Total from AVpp and DVpp Power Consumption NOTES 1Operating temperat
5. RESET Timing Serial and Parallel Mode ag __ JAJU t34 lt SYNC RESET UNI 1 t37 UNI 0 G 8192 ter 8192 tex 8192 to x E 1 8199 to 512 tai 512 tor x e 512 teak neg mer LIII Figure 8 Calibration Timing Serial and Parallel Mode tz REV B 7 AD7722 PIN FUNCTION DESCRIPTIONS Mnemonic Pin No Description AVppi AGNDI AV nn AGND DVpp DGND REF 1 REF2 Vin Vin UNI CLKIN XTAL P S CAL RESET SYNC 14 10 20 23 9 13 15 19 21 25 20 39 6 28 22 Clock Logic Power Supply Voltage for the Analog Modulator 5 V 5 Clock Logic Ground Reference for the Analog Modulator Analog Power Supply Voltage 5 V 5 Ground Reference for Analog Circuitry Digital Power Supply Voltage 5 V 5 Ground Reference for Digital Circuitry Reference Input Output REF1 connects through 3 KQ to the output of the internal 2 5 V reference and to the input of a buffer amplifier that drives the 2 Amodulator This pin can also be overdriven with an external reference 2 5 V Reference Input Output REF2 connects to the output of an internal buffer amplifier used to drive the Z A modulator When REF2 is used as an input REF1 must be connected to AGND Positive Terminal of the Differential Analog Input Negative Terminal of the Differential Analog Input Analog Input Range Select Input UNI selects the analog input range for either bipolar or un
6. The sampling clock generator should be referenced to the analog ground plane in a split ground system However this is not always possible because of system constraints In many cases the sampling clock must be derived from a higher frequency multipurpose system clock that is generated on the digital ground plane If the clock signal is passed between its origin on a digital ground plane to the AD7722 on the analog ground plane the ground noise between the two planes adds directly to the clock and will produce excess jitter The jitter can cause degradation in the signal to noise ratio and can also produce unwanted harmonics This can be remedied somewhat by transmitting the sampling clock signal as a differential one using either a small RF trans former or a high speed differential driver and receiver such as the PECL In either case the original master system clock should be generated from a low phase noise crystal oscillator AD7722 Varying the Master Clock Although the AD7722 is specified with a master clock of 12 5 MHz the AD7722 operates with clock frequencies up to 15 MHz and as low as 300 kHz The input sample rate output word rate and frequency response of the digital filter are directly proportional to the master clock frequency For example reducing the clock frequency to 5 MHz leads to an analog input sample rate of 10 MHz an output word rate of 78 125 KSDS a pass band frequency of 36 25 kHz a cutoff frequency of
7. allowable maximum input span When an overflow condition is detected DVAL is set low for 64 CLKIN cycles one output period and the output data is clipped to either positive or negative full scale depending on the sign of the overflow After the next convolution is completed 64 CLKIN cycles if the overflow condition does not exist DVAL goes high to indicate that a valid output is available Otherwise DVAL will remain low until the overflow condition is eliminated The second stage digital filter can overflow as a result of overflow from the first stage The overflow condition is detected when the second stage filter calculates a conversion result that exceeds either plus or minus full scale 1 e below 32 768 or above 32 767 in bipolar mode When the overflow is detected DVAL is set low and the output register is updated with either positive or negative full scale depending on the sign of the overload After the next convolution is completed DVAL returns high if the next conversion result is within the full scale range As with all high order 2 A modulators large overloads on the analog input can cause the modulator to go unstable The nals as high as the output is clipped to eithef positive or negative full scale depending on the polarity of the overload The modulator is reset to a stable state and the digital filter sequencer counter is reset DVAL is set low for a minimum of 8192 CLKIN cycles while the modulator settles
8. are synchronized Ensure that the supplies are settled before applying the RESET SYNC pulse 8 REV B AD7722 PIN CONFIGURATION 44 Lead MQFP S 44B O PAA Q L oo 2 0 Oo mq a m maa D 82582 ses ee PRG LBB aL AAA aa a3 a2 a1 jao 39 38 37 36 35 34 DGND DB2 1 S 33 DGND DB13 DGND DB1 IDENTIFIER 132 DGND DB14 DGND DB0 3 31 DGND DB15 CFMT DRDY 4 30 SYNC DVALIRD 5 AD7722 291 CS DGND 6 TOP VIEW 28 DGND UNI Not to Scale CAL P S 8 26 AGND AGND 9 25 AGND AGND1 110 24 REF2 CLKIN 11 29 AVpp 12 13 14 15 16 17 18 19 20 21 22 d A Z A T F amp F F A Aaa Ff a Z 9 Z W Z Z 6 Z H K 2287575952 PARALLEL MODE PIN FUNCTION DESCRIPTIONS Mnemonic Pin No Descrip WA AA E R nn DVAL RD T Ad ingit tis evel 9 I itive logicinput The RD oa S se AY g edgg of CLKIN This digital inpuweanabefused in Conjunt ith a fron gt device Ret nut data bus is enabled when the rising edge of CLKIN senses a logic oi level on RD if CS is also low When RD is sensed high the output data bits DB15 DBO will be high impedance Data Ready Logic Output A falling edge indicates a new output word is available to be read from the output data register DRDY will return high upon completion of a read operation If a read operation does not occur between output updates DRDY will pulse high for two CLKIN cycles before the next output update DRDY also indica
9. h 25 C CLKIN 12 5 MHz AIN 20 kHz Bipolar Mode Vw 0 V to 2 5 V Viy 1 25 V unless otherwise noted 40 30 20 10 0 0 50 100 150 200 250 300 0 20 40 60 80 100 INPUT LEVEL dB OUTPUT DATA RATE kSPS INPUT FREQUENCY kHz TPC 1 S N D and SFDR vs TPC 2 SN D vs Output TPC 3 SNR THD and SFDR Analog Input Level Sample Rate vs Input Frequency 2 0 50 100 150 200 250 300 50 0 50 100 INPUT FREQUENCY kHz OUTPUT DATA RATE kSPS TEMPERATURE C TPC 4 SNR THD and SFDR TPC 5 SHN D vs Output TPC 6 SNR vs Temperature vs Input Frequency Sample Rate Ao ae ee uy a i hint DNL ERROR LSB 116 50 25 0 25 50 75 100 0 20000 40000 65535 TEMPERATURE C CODE TPC 7 THD vs Temperature TPC 8 Histogram of Output TPC 9 Differential Nonlinearity Codes with DC Input 12 REV B INL ERROR LSB CLKIN 12 5MHz SNR 90 108 S N D 89 2dB SFDR 99 5dB THD 96 6dB 2ND 100 9dB 3RD 106 0dB 4TH 99 5dB LE gt nga H RT E T ici i T IO B TT Ru XTAL 12 288MHz SNR 89 0dB S N D 87 8dB SFDR 94 3dB THD 93 8dB 2ND 94 3dB 3RD 108 5dB 4TH 105 7dB iM re TEN JI WW 1 N LAM RHA 20 40 60 80 96 FREQUENCY kHz TPC 12 16K Point FFT REV B AD7722 0 2 5 5 0 7 5 10 0 CLKIN FREQUENCY MHz TPC 13 Power Consumption vs CLKIN Frequency AIN 90kHz XTAL 12 288MHz SNR 88 1dB S N D 88 1dB SFDR 103 7dB
10. is low SDO is valid on the rising edge of SCO if SFMT is high When CFMT is logic high SDO is valid on the rising edge of SCO if SFMT is low SDO is valid on the falling edge of SCO if SFMT is high Time Slot Logic Input The logic level on TSI sets the active state of the DOE pin With TSI set logic high DOE will enable the SDO output buffer when it is a logic high and vice versa TSI is used when two AD7722s are connected to the same serial data bus When using a single ADC connect TSI to DGND Data Output Enable Logic Input The DOE pin controls the three state output buffer of the SDO pin The active state of DOE is determined by the logic level on the TSI pin When the DOE logic level equals the level on the TSI pin the serial data output SDO is active Otherwise SDO will be high impedance SDO can be three state after a serial data transmission by connecting DOE to FSO This input is useful when two AD7722s are connected to the same serial data bus When using a single ADC to ensure SDO is active connect DOE to DGND so that it equals the logic level of TSI Serial Data Format Logic Input The logic level on the SFMT pin selects the format of the FSO signal A logic low makes the FSO output a pulse one SCO cycle wide occurring every 32 SCO cycles With SFMT set to a logic high the FSO signal is a frame pulse that is active low for the duration of the 16 data bit transmission he FSI in When the C serial output gh transit
11. 38 77 kHz and a stop band frequency of 41 875 kHz SYSTEM SYNCHRONIZATION AND CONTROL The AD7722 digital filter contains a sequencer block that controls the digital interface and all the control logic needed to operate the digital filter A 14 bit cycle counter Keeps track of where the filters are in their overall operating cycle and decodes the digital interface signals to the AD7722 The cycle counter has a number of important transition points In particular the bottom six bits control the convolution counter that decimates by 64 to the update rate of the output data register The counter s top bit is used to provide ample time 8192 CLKIN cycles to allow the modulator and digital filter to settle as the AD7722 sequences through its autocalibration process The counter increments on the rising edge of the signal at the CLKIN pin and all of the digital I O signals are synchronous with this clock The upper bit of this counter also controls when DVAL or DRDY indicates that valid data is available in the output data register after a SYNC RESET CAL or initial FSI During normal operation the delay_o versi should not be c CLKIN cycles digital filter SYNC Input The SYNC input provides a synchronization function for use in parallel or serial mode SYNC allows the user to start gathering samples of the analog input from a known point in time This allows a system using multiple AD7722s operated from a common master clock to be sy
12. AD7722 output data rate fs is a little over twice the signal bandwidth which guarantees that there is no loss of data in the signal band Digital filtering has certain advantages over analog filtering First since digital filtering occurs after the A D conversion it can remove noise injected during the conversion process Analog filtering cannot remove noise injected during conversion Second the digital filter combines low pass band ripple with_a steep roll off while also maintain QUANTIZATION NOISE foLkin 2 BAND OF INTEREST NOISE SHAPING for wan 2 BAND OF INTEREST CEKIN DIGITAL FILTER CUTOFF FREQUENCY WHICH EQUALS 97 65kHz 12 5MHz foLkin 2 m BAND OF INTEREST C Figure 9 X A ADC 14 The AD7722 employs two finite impulse response FIR filters in series The first filter is a 384 tap filter that samples the output of the modulator at fcr kin The second filter is a 151 tap half band filter that samples the output of the first filter at fo mai 22 and decimates by 2 The implementation of this filter architecture results in a filter with a group delay of 42 conversions 84 conver sions for settling to a full scale step The digital filter provides 6 dB of attenuation at a frequency fc_xn 128 one half its output rate With a clock frequency of 12 5 MHz the digital filter has a pass band frequency of 90 625 kHz a cutoff frequency is 96 92 kHz and a stop band frequency of
13. ANALOG DEVICES FEATURES 16 Bit 2 A ADC 64x Oversampling Ratio Up to 220 kSPS Output Word Rate Low Pass Linear Phase Digital Filter Inherently Monotonic On Chip 2 5 V Voltage Reference Single Supply 5 V High Speed Parallel or Serial Interface GENERAL DESCRIPTION at an output word rate of 195 3 kHz The analog input is continuously sampled by an analog modula tor eliminating the need for external sample and hold circuitry The modulator output is processed by two finite impulse response FIR digital filters in series The on chip filtering reduces the external antialias requirements to first order in most cases The group delay for the filter is 215 5 us while the settling time for a step input is 431 us The sample rate filter corner frequency and output word rate are set by an external clock that is nominally 12 5 MHz Use of a single bit DAC in the modulator guarantees excellent linearity and dc accuracy Endpoint accuracy is ensured on chip by calibration This calibration procedure minimizes the zero scale and full scale errors REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademar
14. EF2 to AGND The external capacitor provides the charge required for the dynamic load presented at the REF2 pin SWITCHED CAP DAC REF CLKIN g a o8 Figure 17 REF2 Equivalent Input Circuit The AD780 is ideal to use as an external reference with the AD7722 Figure 18 shows a suggested connection diagram AD7722 Figure 18 External Reference Circuit Connection REV B AD7722 Input Circuits Figures 19 and 20 show two simple circuits for bipolar mode operation Both circuits accept a single ended bipolar signal source and create the necessary differential signals at the input to the ADC The circuit in Figure 19 creates a 0 V to 2 5 V signal at the Vin pin to form a differential signal around an initial bias of 1 25 V For single ended applications best THD performance is obtained with Vyn set to 1 25 V rather than 2 5 V The input to the AD7722 can also be driven differentially with a complementary input as shown in Figure 20 In this case the input common mode voltage is set to 2 5 V The 2 5 V p p full scale differential input is obtained with a 1 25 V p p signal at each input in antiphase This configuration minimizes the required output swing from the amplifier circuit and is useful for single supply applications DIFFERENTIAL INPUT 2 5V p p Figure 19 Single Ended Analog Input Circuit for Bipolar Mode Operation 12pF Vin DIFFERENTIAL INPUT 2 5V p p COMMON MODE VOLTAGE 2 5V
15. Gee oes AE 20 C W Lead Temperature Soldering Vapor Phase 60 SEC wA 215 C Taare 36C IIIA IAA 220 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional opera tion of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Transient currents up to 100 mA will not cause SCR latch up ww BDI C com AD CAUTIONS ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily WARNING accumulate on the human body and test equipment and can discharge without detection S S Although the AD7722 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD E ee ieee ae precautions are recommended to avoid performance degradation or loss of functionality 4 REV B Parameter CLKIN Freguency CLKIN Period tcLK L Lt x CLKIN Low Pulse Width CLKIN High Pulse Width CLKIN Rise Time CLKIN Fall Time FSI Low Time FSI Setup Time FSI Hold Time CLKIN to SCO Delay SCO Period SCO Transition to FSO High Delay SCO Transition to FSO Low Delay SCO Transition to SDO Valid Delay SCO Transition from FSI SDO Enable Delay Time SDO Di
16. LES cum J ANN SCO CFMT 0 32 SCO CYCLES J a a a SFMT 0 Sco VALID DATA FOR 16 SCO CYCLES ZERO FOR LAST 16 SCO CYCLES VALID Figure 2a Generalized Serial Mode Timing FSI Logic Low or High TSI DOE 64 CKLIN CYCLES cum D PUA UMA LT SCO CFMT 0 32 SCO CYCLES FSO ST 16 Sco cyoLes SFMT 1 LOW FOR 16 SCO CYCLES HIGH FOR LAST 16 SCO CYCLES e e SCO VALID DATA FOR 16 SCO CYCLES ZERO FOR LAST 16 SCO CYCLES ST16sco CYCLES VALID VALID lhd Figure 2b Generalized Serial Mode Timing FSI Logic Low or High TSI DOE hr WL Z t4 to gt CLKIN R O G rA o p ty tio Figure 3 Serial Mode Timing for Clock Input Frame Sync Input and Serial Clock Output Fs LULL ipia OL t42 SFMT LOGIC FSO LOW 0 L tia sno fois ma X ms Ha 1 SCO t42 t11 SFMT LOGIC Fso LOW FOR HIGH 1 D15 D0 gt Ha sno fois X ov A Ds Figure 4 Serial Mode Timing for Frame Sync Input Frame Sync Output Serial Clock Output and Serial Data Output CFMT Logic Low TSI DOE 6 REV B AD7722 SDO Figure 5 Serial Mode Timing for Data Output Enable and Serial Data Output TSI Logic Low DBO DB15 VALID DATA Figure 6 Parallel Mode Read Timing t30 CLKIN MIN SYNC RESET Dr 9 1 E AY ova WAI DRDY tog AT OLYT AL tog lt Figure 7 SYNC and
17. VAL goes high whenever a calcula tion is performed on the average of eight conversion results 512 CLKIN cycles and then returns low See Figure 8 In bipolar mode an additional measurement is required since zero scale is not the same as FS Therefore calibration in bipolar mode requires an additional 512 8192 CLKIN cycles Zero scale is similarly determined by shorting both analog inputs to AGND Then the inputs are internally reconfigured to apply FS and FS Vpgp 2 and VpgF 2 to determine the gain correction factor After the calibration registers have been loaded with new values the inputs of the modulator are switched back to the input pins However correct data is available at the interface only after the modulator and filter have settled to the new input values Should the part see a rising edge on the SYNC or RESET pin during a calibration cycle the calibration cycle is discontinued and a synchronization operation or reset will be performed The calibration registers are static They need to be updated only if unacceptable drifts in analog offsets or gain are expected After power up a RESET is not mandatory since power on reset circuitry clears the offset and gain registers Care must be taken to ensure that the CAL pin is held low during power up Before REV B initiating a calibration routine ensure that the supplies and reference input have settled and that the voltage on the analog input pins is be
18. ame the output data transmission to an external device An output data transmission is 32 SCO cycles in duration The serial data shifts out of the SDO pin MSB first LSB last for a duration of 16 SCO cycles For the next 16 SCO cycles SDO outputs zeros Two control inputs SFMT and CFMT select the format for the serial data transmission FSO is either a pulse approximately one SCO cycle in duration or a square wave with a period of 32 SCO cycles depending on the state of the SFMT The logic level applied to SFMT also determines if the serial data is valid on the rising or falling edge of the SCO The clock format pin CFMT simply switches the phase of SCO for the selected FSO format With a logic low level on SFMT and CFMT set low Figure 4 FSO pulses high for one SCO cycle at the beginning of a d transmission frame oes_low on the SDO pin on the SCO fallimg e With a logic high level on SFMT and CFMT set low Figure 4 the data on the SDO pin is available after the falling edge of SCO and can be latched on the SCO rising edge FSO goes low at the beginning of a data transmission frame when the MSB is available and returns high after 16 SCO cycles The frame sync input FSI can be used if the AD7722 conver sion process must be synchronized to an external source FSI is an optional signal if FSI is grounded or tied high frame syncs are internally generated Frame sync allows the conversion data presented to the serial
19. amental signals and harmonics to half the sampling rate ferKw 128 excluding dc The ADC is evaluated by applying a low noise low distortion sine wave signal to the input pins By generating a fast Fourier transform FFT plot the S N D data can then be obtained from the output spectrum Total Harmonic Distortion THD THD is the ratio of the rms sum of the harmonics to the rms value of the fundamental THD is defined as SORT V2 V 4V V Ve Vi THD 20 log where V is the rms amplitude of the fundamental and V2 V3 Vi Vs and V are the rms amplitudes of the second through sixth harmonics The THD is also derived from the FFT plot of the ADC output spectrum Spurious Free Dynamic Range SFDR Defined as the difference in dB between the peak spurious or har monic component in the ADC output spectrum up to fcrkm 128 and excluding dc and the rms value of the fundamental Normally the value of this specification will be determined by the largest harmonic in the output spectrum of the FFT For input signals With inputs consisting of sine waves at two frequencies fa and fb any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m n 0 1 2 3 and so on Intermodulation distortion terms are those for which neither m nor n is equal to zero For example the second order terms include fa fb and fa fb while the third order terms include 2fa f
20. b 2fa fb fa 2fb and fa 2fb Testing is performed using the CCIF standard where two input frequencies near the top end of the input bandwidth are used In this case the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies As a result the second and third order terms are specified separately The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamental expressed in dB REV B Pass Band Ripple The frequency response variation of the AD7722 in the defined pass band frequency range Pass Band Frequency The frequency up to which the frequency response variation is within the pass band ripple specification Cutoff Frequency The frequency below which the AD7722 s frequency response will not have more than 3 dB of attenuation Stop Band Frequency The frequency above which the AD7722 s frequency response will be within its stop band attenuation Stop Band Attenuation The AD7722 s frequency response will not have less than 90 dB of attenuation in the stated frequency band Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function The endpoints of the transfer functi
21. com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD7722 SPEGIFIGATIONS AVop Vun 9 V 5 DVpp 5 V 5 AGND AGND1 DGND 0 V UNI Logic Low or High feig 12 5 MHz fs 195 3 kKSPS REF2 2 5 V Ty Tyn to Tua unless otherwise noted Parameter DYNAMIC SPECIFICATIONS Bipolar Mode UNI Ving Signal to Noise Distortion Total Harmonic Distortion Spurious Free Dynamic Range Unipolar Mode UNI Vint Signal to Noise Distortion Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion AC CMRR Digital Filter Response Pass Band Ripple Cutoff Frequency Stop Band Attenuation ANALOG INPUTS Full Scale Input Span Bipolar Mode Unipolar Mode Absolute Input Voltage Input Sampling Capacitance Input Sampling Rate Differential Input CLOCK vi VYA AY CLKIN Mark Space Ratio REFERENCE REF 1 Output Voltage REF1 Output Voltage Drift REF1 Output Impedance Reference Buffer Offset Voltage Using Internal Reference REF2 Output Voltage REF2 Output Voltage Drift Using External Reference REF2 Input Impedance External Reference Voltage Range STATIC PERFORMANCE Resolution Differential Nonlinearity Integral Nonlinearity After Calibration Offset Error Gain Error Without Calibration Offset Error Gain Error Offset Error Drift Gain Error Drift Vin Vin 2 5 V p p Vom 1 25 V to 3 75 V 20 kHz 0 kHz to 90 625 kHz 104
22. curacy suffers if the input capacitor is switched away too early An alternative circuit configuration for driving the differential inputs to the AD7722 is shown in Figure 15 Vin AD7722 Vin C 2 7nF Figure 15 Differential Input with Antialiasing A capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by one input to be effectively supplied by the other input This minimizes undesir able charge transfer from the analog inputs to and from ground The series resistor isolates the operational amplifier from the current spikes created during the sampling process and provides a pole for antialiasing The 3 dB cutoff frequency fs gp of the antialias filter is given by Equation 1 and the attenuation of the filter is given by Equation 2 1 PaB Attenuation 20 log 1 1 2 The choice of the filter cutoff frequency will depend on the amount of roll off that is acceptable in the pass band of the digital filter and the required attenuation at the first image frequency For example when operating the AD7722 with a 12 5 MHz clock with the typical values of R and C of 100 Q and 2 7 nF shown in Figure 15 the 3 dB cutoff frequency f gp creates less than 1 dB of in band 90 625 kHz roll off and provides about 36 dB attenuation at the first image frequency The capacitors used for the input antialiasing circuit must have low dielectric absorption to av
23. e AD7722 operates as the master with the DSP operating as the slave The AD7722 outputs its own serial clock SCO to transmit the digital word on the SDO pin to a DSP The DSP s serial interface is synchronized to the data transmission provided by the FSO signal Since the serial data clock from the AD7722 is always one half the CLKIN frequency DSPs that can accept relatively high serial clock frequencies are required The ADSP 21xx family of DSPs can operate with a maximum serial clock of 13 824 MHz the DSP56002 allows a maximum serial clock of 13 3 MHz the TMS320C5x 57 accepts a maximum serial clock of 10 989 MHz REV B AD7722 cuan LY nel aS dug Tey AAA Ses FSO MASTER FSI SLAVE 4 DOE MASTER AND SLAVE SDO MASTER d 16 lt NOTE 1 THE STATE OF FSI CANNOT BE CHANGED 4 CLKIN CYCLES BEFORE A FSO EDGE Figure 25 Timing for 2 Channel Multiplexed Operation To interface the AD7722 to other DSPs the master clock Grounding and Layout frequency of the AD7722 can be reduced so that the SCO The analog and digital power supplies to the AD7722 are indepen frequency equals the maximum allowable frequency of the serial dent and separately pinned out to minimize coupling between clock input to the DSP When the AD7722 is operated with a analog and digital sections within the device The AD7722 should lower CLKIN frequency lt 10 MHz DSPs such as the be treated as an analog component and grounded a
24. e digital filter output and the result is multiplied by the gain correction factor to obtain an offset and gain corrected final result The calibration cycle is controlled by internal logic and the user need only initiate the cycle A calibration is initiated when the rising edge of CLKIN senses a high level on the CAL input There is an uncertainty of up to 64 CLKIN cycles before the calibration cycle actually begins because the current conversion must complete before calibration commences The calibration values loaded into the registers only apply for the particular analog input mode bipolar unipolar selected when initiating the calibration cycle On changing to a different analog input mode a new calibration must be performed During the calibration cycle in unipolar mode the offset of the analog modulator is evaluated the differential inputs to the modulator are shorted internally to AGND Once calibration begins DVAL goes low and DRDY goes high indicating there is invalid data in the output register After 8192 CLKIN cycles when the modulator and digital filter f output results s i The gain correction factor can then be de e by internally switching the inputs to FS VgRer2 The positive input of the modulator is switched to the reference voltage and the negative input to AGND Again when the modulator and digital filter settle the average of the eight output results is used to calculate the gain correction factor D
25. e ee are Se eee ok Be re a Be ee Wa 2 Changes to ABSOLUTE MAXIMUM RATINGS 4 Changes tO ORDERING GUIDE iii 6556 teikts isr riar KAA R EE ESAN L E see Es 4 Changes to PIN FUNCTION DESCRIPTIONS 8 Changes to PARALLEL MODE PIN FUNCTION DESCRIPTIONS 9 Changes to SERIAL MODE PIN FUNCTION DESCRIPTIONS 10 Changes to Differential Inputs SECHONS Kai AAA 15 T WAN Bi SA REV B C01185 0 10 03 B
26. evices are synchronized Ensure that the supplies are settled before applying the RESET SYNC pulse Chip select is a level sensitive logic input CS enables the output data register for parallel mode read operation The CS logic level is sensed on the rising edge of CLKIN The output data bus is enabled when the rising edge of CLKIN senses a logic low level on CS if RD is also low When CS is sensed high the output data bits DB15 DB0 will be high impedance In serial mode tie CS to a logic low Synchronization Logic Input SYNC is an asynchronous input When using more than one AD7722 operated from a common master clock SYNC allows each ADC s X A modulator to simultaneously sample its analog input and update its output data register A rising edge resets the AD7722 digital filter sequencer counter to zero After a SYNC conversion data is not valid until after the digital filter settles see Figure 7 DVAL goes low in the serial mode When the rising edge of CLKIN senses a logic low on SYNC or RESET the reset state is released in parallel mode DRDY goes high After the reset state is released DVAL returns high after 8192 CLKIN cycles 128 x 64 fer km in parallel mode DRDY returns low after one additional convolution cycle of the digital filter 64 CLKIN periods when valid data is ready to be read from the output data register When operating with more than one AD7722 a RESET SYNC should be issued follow ing power up to ensure the devices
27. icroprocessor or a modern microcontroller such as the MC68HC16 or 8xC251 AD7722 DSP uC DBO DB15 DO D15 74xx16374 74xx16244 DRDY ADDR cs RD RD INTERRUPT Figure 23 Parallel Interface Connection With CS and RD tied permanently low the data output bits are always active When the DRDY output goes high for two CLKIN cycles the rising edge of DRDY is used to latch the conversion data before a new conversion result is loaded into the output data register The falling edge of DRDY then sends an appro priate interrupt signal for interface control Alternatively if buffers are used instead of latches the falling edge of DRDY provides the necessary interrupt when a new output word is available from the AD7722 19 AD7722 SERIAL INTERFACE The AD7722 s serial data interface port allows easy interfacing to industry standard digital signal processors The AD7722 operates solely in the master mode providing three serial data output pins for transfer of the conversion results The serial data clock output SCO serial data output SDO and frame sync output FSO are all synchronous with CLKIN SCO freguency is always one half the CLKIN freguency FSO is continuously output at the conversion rate of the ADC Trg 64 The generalized timing diagrams in Figure 2 show how the AD7722 may be used to transmit its conversion results Serial data shifts out of the SDO pin synchronous with SCO The FSO is used to fr
28. ifferential inputs to provide common mode noise rejection i e the converted result will correspond to the differential voltage between the two inputs The absolute voltage on both inputs must lie between AGND and AVpp In unipolar mode the full scale analog input range Vin Vin is 0 V to Varra The output code is straight binary in the unipolar mode with 1 LSB 38 uV The ideal transfer function is shown in Figure 11 In bipolar mode the full scale input range is VppF 2 The bipolar mode allows complementary input signals As another example in bipolar mode Vn can be connected to a dc bias voltage to allow a single ended input on Vin t equal to Vpras VppF 2 In bipolar mode the output code is twos complement with 1 LSB 38 uV The ideal transfer function is shown in Figure 12 OUTPUT CODE VRer2 1LSB DIFFERENTIAL INPUT VOLTAGE V NLA Vin Figure 11 Unipolar Mode Transfer Function OUTPUT CODE VpeEFo 2 1 LSB ov DIFFERENTIAL INPUT VOLTAGE V n Vin Figure 12 Bipolar Mode Transfer Function REV B Differential Inputs The analog input to the modulator is a switched capacitor design The analog signal is converted into charge by highly linear sampling capacitors A simplified equivalent circuit diagram of the analog input is shown in Figure 13 A signal source driving the analog input must be able to provide the charge onto the sampling capacitors every half CLKIN cycle and set
29. in DOE controls SDO s output buffer When the logic level on DOE matches the state of the TSI pin the SDO output buffer drives the serial dataline otherwise the output of the buffer goes high impedance The serial format pin SFMT is set high to choose the frame sync output format The clock format pin CFMT is set high so that serial data is made available on SDO after the rising edge of SCO and can be latched on the SCO falling edge e master controls the DOE input of both the master and slave one ADC s SDO is active while the other is high impedance Figure 25 When the master transmits its conversion result during the first 16 SCO cycles of a data transmission frame the low level on DOE sets the slave s SDO high impedance Once the master completes transmitting its conversion data its FSO goes high and triggers the slave s FSI to begin its data transmission frame Following power up of the two devices once the supplies have settled a synchronous RESET SYNC pulse should be issued to both ADCs to ensure synchronization After a RESET SYNC has been issued FSI can be applied to the master ADC to allow continuous synchronization between the processor and the ADCs For continuous synchronization FSI should not be applied within four CLKIN cycles before an FSO master edge See Figure 25 Serial Interfacing to DSPs In serial mode the AD7722 can be interfaced directly to several industry standard DSPs In all cases th
30. interface to be a filtered and decimated result derived from a known point in time FSI can be applied once after power up or it can be a periodic signal synchronous to CLKIN occurring every 64 CLKIN cycles When FSI is applied for the first time or if a low to high transition is detected that is not synchronized to the output word rate the next 127 conversions should be considered invalid while the digital filter accumulates new samples Figure 4 shows how the frame sync signal resets the serial output interface and how the AD7722 will begin to output its serial data transmission frame A common frame sync signal can be applied to two or more AD7722s to synchronize them to a common master clock 2 Channel Multiplexed Operation Three additional serial interface control pins DOE TSI and CFMT are provided The connection diagram in Figure 24 shows how they are used to allow the serial data outputs of two AD7722s to easily share one serial data line Since a serial data transmission frame lasts 32 SCO cycles two AD7722s can share a single data line by alternating transmission of their 16 bit output data onto one SDO pin 20 aster device is selected bW setting connectingfits TSI pin tied hi m the master s AD7722 MASTER CFMT SFMT TSI FROM CONTROL LOGIC AD7722 SLAVE FSI DOE CLKIN SDO TO HOST CFMT SCO PROCESSOR Figure 24 Connection for 2 Channel Multiplexed Operation The data output enable p
31. ion thk L ots fre d ister resets SCO and transmits the conversion kanis Synchronization starts R and the next 127 conversions are invalid In serial mode DVAL remains high FSI inputs applied synchronous to the output data rate do not alter the serial data transmission If FSI is tied to either a logic high or low the AD7722 will generate FSO outputs controlled by the logic level on SFMT ing S Serial Data Clock Output The serial clock output is synchronous to the CLKIN signal and hasa frequency one half the CLKIN frequency A data transmission frame is 32 SCO cycles long Serial Data Output The serial data is shifted out MSB first synchronous with the SCO A serial data transmission lasts 32 SCO cycles After the LSB is output trailing zeros are output for the remaining 16 SCO cycles Frame Sync Output This output indicates the beginning of a word transmission on the SDO pin Depending on the logic level of the SFMT pin the FSO signal is either a positive pulse approximately one SCO period wide or a frame pulse which is active low for the duration of the 16 data bit trans mission see Figure 4 In serial mode these pins should be tied to DGND 10 REV B AD7722 TERMINOLOGY Signal to Noise Plus Distortion Ratio S N D S N D is the measured signal to noise plus distortion ratio at the output of the ADC The signal is the rms magnitude of the fundamental Noise plus distortion is the rms sum of all nonfund
32. ipolar operation A logic low input selects unipolar operation A logic high input selects bipolar operation Clock Input Master clock signal for the device The CLKIN pin interfaces the AD7722 internal oscillator circuit to an external crystal or an external clock A parallel resonant fundamental frequency microprocessor grade crystal and a 1 MQ resistor should be connected between the CLKIN and XTAL WA with two Ka B from each pin to ground Alternatively the CLKIN pin can be driye atible clock The AD7722 as specified gwth auclock input guencyof 1 YA OSoillator STALE pin Gonnects occa Moff man extern Parallel Serial Interface Select Input A logic high configures as output data interface for parallel mode operation The serial mode operation is selected with the P S set to a logic low Calibration Logic Input A logic high input for a duration of one CLKIN cycle initiates a calibration sequence for the device gain and offset error Reset Logic Input RESET is used to clear the offset and gain calibration registers RESET is an asynchronous input RESET allows the user to set the AD7722 to an uncalibrated state if the device had been previously calibrated A rising edge also resets the AD7722 X A modulator by shorting the integrator capacitors in the modulator In addition RESET functions identically to the SYNC pin described below When operating with more than one AD7722 a RESET SYNC should be issued following power up to ensure the d
33. ks are the property of their respective owners 16 Bit 195 kSPS CMOS gt A ADC AD7 722 FUNCTIONAL BLOCK DIAGRAM DGND DVpp AGND AVpp REF1 Q 2 5V _ REF2 REFERENCE es a eee J Vin 16 BIT A D CONVERTER 5 A FIR Vin O MODULATOR FILTER eae See J PS CLOCK O XTAL CALO CIRCUITRY O CLKIN RESET O da UNI SYNCO ODB15 CS O ODB14 DVAURD O DB13 CFMT DRDY DB12 DBO C 6 DB11 DB10 Q DB9 FSO o DB3 DB4 DB5 DB6 DB7 DB8 TSI DOE SFMT FSI SCO SDO onversion data is al at the output register through a flex CO ible serial port or a parallel port This offers 3 wire high speed interfacing to digital signal processors The serial interface operates in an internal clocking master mode whereby an internal serial data clock and framing pulse are device outputs Additionally two AD7722s can be configured with the serial data outputs connected together Each converter alternately transmits its conver sion data on a shared serial data line The part provides an accurate on chip 2 5 V reference A reference input output function is provided to allow either the internal reference or an external system reference to be used as the reference source for the part The AD7722 is available in a 44 lead MQFP package and 1s specified over the industrial temperature range of 40 C to 85 C One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog
34. nchronized so that each ADC updates its output register simultaneously The SYNC input resets the digital filter without affecting the contents of the calibration registers In a system using multiple AD7722s a common signal to their sync input will synchronize their operation On the rising edge of SYNC the digital filter sequencer counter is reset to zero The filter is held in a reset state until a rising edge on CLKIN senses SYNC low A SYNC pulse one CLKIN cycle long can be applied synchronous to the falling edge of CLKIN This way on the next rising edge of CLKIN SYNC is sensed low the filter is taken out of its reset state and multiple parts start to gather input samples In serial mode DVAL remains low for 8192 CLKIN cycles to allow the modulator and digital filter to settle In parallel mode DRDY remains high for an additional 64 CLKIN cycles when valid data is loaded into the output register After a SYNC conver sion data is not valid until the digital filter settles see Figure 7 18 DVAL The DVAL pin when used in the serial mode indicates if invalid data may be present at the ADC output There are four events that can cause DVAL to be deasserted and they have different impli cations for how long the results should be considered invalid DVAL is set low if there is an overflow condition in the first stage of the digital filter The overflow can result from an analog input signal nearly twice the
35. nd decoupled TMS320C20 C25 and DSP56000 1 round pins should o the analog a RS All t Figures 26 be sol ize series induc several DS SLEDOE tance pled to the analog SFMT CF be permanently hardwired ee E S place surface together to S DGND or DVpp Alternatively SEMT or mount capacitor as EE as possible to ie device ideally right CFMT can be tied either high or low to configure the serial data YP against the device pins interface for the particular format required by the DSP The The printed circuit board that houses the AD7722 should use frame synchronization signal FSI can be applied from the user s separate ground planes for the analog and digital interface system control logic circuitry All converter power pins should be decoupled to the analog ground plane and all interface logic circuit power pins should be decoupled to the digital ground plane This facili AD7722 tates the use of ground planes which can physically separate sensitive analog components from the noisy digital system Digital and analog ground planes should only be joined in one place and should not overlap to minimize capacitive coupling between them Separate power supplies for AVpp and DVpp are also highly desirable The digital supply pin DVpp should be powered from a separate analog supply but if necessary DVpp may share its power connection to AVpp see the connection diagram in Figure 29 The 10 Q resistor in series with the DVpp pin is required t
36. o dampen the effects of the fast switching currents into the digital section of the AD7722 The ferrite is also recommended to filter high frequency signals from corrupting the analog power supply A minimum etch technique is generally best for ground planes because it gives the best shielding Noise can be minimized by paying attention to the system layout and preventing different signals from interfering with each other High level analog signals should be separated from low level analog signals and both should be kept away from digital signals In waveform sampling and reconstruction systems the sampling clock CLKIN is as vulner Figure 28 AD7722 to TMS320C20 TMS320C25 able to noise as any analog signal CLKIN should be isolated from TMS320C50 Interface REV B 21 AD7722 the analog and digital systems Fast switching signals like clocks should be shielded with their associated ground to avoid radiating noise to other sections of the board and clock signals should never be routed near the analog inputs Avoid running digital lines under the device as these will couple noise onto the die The analog ground plane should be allowed to run under the AD7722 to shield it from noise coupling The power supply lines to the AD7722 should use as large a trace as possible preferably a plane to provide a low impedance path and reduce the effects of glitches on the power supply line Avoid crossover of digital and analog signals Traces
37. oid distortion Film capacitors such as polypropylene polystyrene or polycarbonate are suitable If ceramic capacitors are used they must have NPO dielectric Applying the Reference The reference circuitry used in the AD7722 includes an on chip 2 5 V band gap reference and a reference buffer circuit The block diagram of the reference circuit is shown in Figure 16 The inter nal reference voltage is connected to REF1 through a 3 KQ resistor and is internally buffered to drive the analog modulator s switched cap DAC REF2 When using the internal reference connect 100 nF between REF1 and AGND If the internal reference is 16 required to bias external circuits use an external precision op amp to buffer REFI 1v gt COMPARATOR REFERENCE BUFFER peal 100nF 2 5V REFERENCE AD7722 SWITCHED CAP DAC REF REF2 24 Figure 16 Reference Circuit Block Diagram The AD7722 can operate with its internal reference or an external reference can be applied in two ways An external reference can be connected to REF overdriving the internal reference However there will be an error introduced due to the offset of the internal buffer amplifier For the lowest system gain errors when using an external reference REF1 is grounded disabling the internal buffer and the external reference is connected to REF2 In all cases since the REF2 voltage connects to the analog modulator a 100 nF capacitor must connect directly from R
38. on are minus full scale a point 0 5 LSB below the first code transition 100 00to 100 01 in bipolar mode 000 00 to 000 01 in unipolar mode and plus full scale a point 0 5 LSB above the last code transition Ol1 10to 011 111n bipolar mode 111 10to 111 11 in unipolar mode The error is expressed in LSB Differential Nonlinearity Mane is d difference betwes ey and the ideal 1 LSB both input oak Si kane kia EES variation of a ground level is specified as a common mode rejection ratio CMRR is the ratio of gain for the differential signal to the gain for the common mode signal Unipolar Offset Error Unipolar offset error is the deviation of the first code transition 00 000 to 00 001 from the ideal differential voltage Vin Vin 0 5 LSB when operating in the unipolar mode Bipolar Offset Error This is the deviation of the midscale transition code 111 11 to 000 00 from the ideal differential voltage Vin Vin 0 5 LSB when operating in the bipolar mode Gain Error The first code transition should occur at an analog value 1 2 LSB above full scale The last transition should occur for an analog value 1 1 2 LSB below the nominal full scale Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions AD7722 Typical Performance Characteristics AVio DVpp 5 0 V
39. on opposite sides of the board should run at right angles to each other This will reduce the effects of feedthrough through the board 22 Figure 29 Power Supply Decoupling ww BDI C com AD REV B AD7722 OUTLINE DIMENSIONS 44 Lead Metric Quad Flat Package MQFP S 44B Dimensions shown in millimeters 1 03 0 88 2 45 0 73 MAX 5 17 SEATING 20 8 PLANE COPLANARITY TOP VIEW 0 10 PINS DOWN 2 10 2 00 0 25 MAK 1 96 E COMPLIANT TO JEDEC STANDARDS MS 022 AA 1 ww BDTI C conn REV B 23 AD7722 Revision History Location Page 10 03 Data Sheet changed from REV A to REV B Change to ORDERING GUIDE itimie Ki IA Ee eho eS AAA Eee ee wee 4 Ien lacer Geg And IIIA E R IIIA IKIWA IIIA E A 7 Changes to PIN PUNC TION DESCRIPTIONS mii iii 8 Text added to 2 Channel Multiplexed Operation section 20 ep laced PICUte KAIKA ee OE oe oes Ee ee OES ES eee ee eee AA 21 Changes to text in 2 Channel Multiplexed Operation section 21 Chances tO Pieu 2 0 5 eo aux die ae oe ae a ee AAA ee ne Se a eae he ee Oe ee eo oe ee ee eee 22 Change to OUTLINE DIMENSIONS wai Geen AHAAA AAA 23 5 03 Data Sheet changed from REV 0 to REV A Figures and PCs Ren umbered a 662 8446 a 666 0660 46 oe RRR 2S de ow EOD SEAS ee ewe ee es 645 ok UNIVERSAL Changes to SPECIFICATIONS a4 eas be 4 AINA eo eek eS or ee we So
40. out and the digital filter accumu lates new samples DVAL returns high to indicate that valid data is available from the serial output register 8192 CLKIN cycles after the overload condition is removed Lastly DVAL also indicates when valid data is available at the serial interface after initial power up or upon completion of a CAL RESET or SYNC sequence Reset Input The AD7722 RESET input controls the digital filter the same as the SYNC input described previously Additionally it resets the modulator by shorting its integrator capacitors and clears the on chip calibration registers so that the conversion results are not corrected for offset or gain error Power On Reset A power on reset function is provided to reset the AD7722 internal logic after initial power up On power up the offset and gain calibration registers are cleared REV B AD7722 Offset and Gain Calibration A calibration of offset and gain errors can be performed in both serial and parallel modes by initiating a calibration cycle During this cycle offset and gain registers in the filter are loaded with values representing the dc offset of the analog modulator and a modulator gain correction factor The correction factors are determined by an on chip microcontroller measuring the conver sion results for three different input conditions minus full scale FS plus full scale FS and midscale In normal operation the offset register is subtracted from th
41. sable Delay Time DRDY High Time Conversion Time DRDY to CS Setup Time CS to RD Setup Time RD Pulse Width Data Access Time after RD Falling D Bus Relin 1S ising CS to RD RD to DRD i SYNC RESET Input Pulse Width DVAL Low Delay from SYNC RESET SYNC RESET Low Time after CLKIN Rising DRDY High Delay after SYNC RESET Low DRDY Low Delay after SYNC RESET Low DVAL High Delay after SYNC RESET Low CAL Setup Time CAL Pulse Width Calibration Delay from CAL High Unipolar Input Calibration Time UNI 0 4 Bipolar Input Calibration Time UNI 1 4 Conversion Results Valid UNI 0 Conversion Results Valid UNI 1 NOTES Guaranteed by design ram Bp AVop 5 V 5 DVop 5 V 5 AGND DGND 0 V CL 50 pF Th Twin to Tuay TIMING SPECIFICATIONS faxy 12 5 MHz SFMT Logic Low or High CFMT Logic Low or High Min ty t2 t3 t4 ts te t7 tg t t t t t t t t t 9 10 11 12 13 14 15 16 17 Frame sync is initiated on falling edge of CLKIN With RD synchronous to CLKIN tz can be reduced up to 1 tet K See Figure 8 Specifications subject to change without notice REV B Typ Max tc x 10 50 8192 64 8192 2 64 3 x 8192 2 x 512 4 x 8192 3 x 512 3 x 8192 2 x 512 64 4x 8192 3 x 512 64 AD7722 TCLK TCLK TCLK LLK tcLK LLK LLK tcLK tcLK AD7722 64 CKLIN CYC
42. tes when conversion results are available after a SYNC or RESET sequence and when completing a self calibration CFMT DRDY DGND DB15 Data Output Bit MSB DGND DB14 Data Output Bit DGND DB13 Data Output Bit DGND DB12 Data Output Bit DGND DBI11 Data Output Bit DGND DB10 Data Output Bit FSO DB9 Data Output Bit SDO DB8 Data Output Bit SCO DB7 Data Output Bit FSI DB6 Data Output Bit SFMT DB5 Data Output Bit DOE DB4 Data Output Bit TSI DB3 Data Output Bit DGND DB2 Data Output Bit DGND DBI1 Data Output Bit DGND DBO0 Data Output Bit LSB REV B 9 AD7722 Mnemonic DVAL RD CFMT DRDY TSI DB3 DOE DB4 SEMT DB5 FSI DB6 SCO DB7 SDO DB8 FSO DB9 DGND DB0 DGND DB1 DGND DB2 DGND DB10 DGND DB11 DGND DB12 DGND DB13 DGND DB14 DGND DB15 Pin No SERIAL MODE PIN FUNCTION DESCRIPTIONS Description Data Valid Logic Output A logic high on DVAL indicates that the conversion result in the output data register is an accurate digital representation of the analog voltage at the input to the A modu lator The DVAL pin is set low for 8 192 CLKIN cycles if the analog input is overranged and after initiating CAL SYNC or RESET Serial Clock Format Logic Input The clock format pin selects whether the serial data SDO is valid on the rising or falling edge of the serial clock SCO When CFMT is logic low SDO 1s valid on the falling edge of SCO if SFMT
43. tle to the required accuracy within the next half cycle AD7722 2pF AC GROUND CLKIN da B pa l PB Figure 13 Analog Input Equivalent Circuit Since the AD7722 samples the differential voltage across its analog inputs low noise performance is attained with an input circuit that provides low common mode noise at each input The amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the AD7722 When a capacitive load is switched onto the output of an op amp the amplitude will momentarily d he op amp will try to can be connected betwe n the amplifier and the input to the AD7722 as shown in Figure 14 The external capacitor at each input aids in supplying the current spikes created during the sampling process The resistor in this diagram as well as creating the pole for the antialiasing isolates the op amp from the transient nature of the load Vin AD7722 ANALOG INPUT Vin Figure 14 Simple RC Antialiasing Circuit The differential input impedance of the AD7722 switched capacitor input varies as a function of the CLKIN frequency given by the equation 15 AD7722 Even though the voltage on the input sampling capacitors may not have enough time to settle to the accuracy indicated by the resolu tion of the AD7722 as long as the sampling capacitor charging follows the exponential curve of RC circuits only the gain ac
44. tween the supply voltages DATA INTERFACING The AD7722 offers a choice of serial or parallel data interface options to meet the requirements of a variety of system configu rations In parallel mode multiple AD7722s can be easily configured to share a common data bus Serial mode is ideal when it is required to minimize the number of data interface lines connected to a host processor In either case careful attention to the system configuration is required to realize the high dynamic range available with the AD7722 Consult the recommendations in the Power Supply Grounding and Layout section The following recommendations for parallel interfacing also apply for the system design in serial mode Parallel Interface When using the AD7722 place a buffer latch adjacent to the converter to isolate the converter s data lines from any noise that may be on the data bus Even though the AD7722 has three state outputs use of an isolation latch represents good design practice This arrangement will inject a small amount of digital noise on the AD7722 ground plane these currents should be quite small and can be minimized by ensuring that the converter input output does not drive a large fanout they normally can t by design Minimizing the fanout on the AD7722 s digital port will also keep the converter logic transi tions relatively free from ringing and these potent i The s aa the parallel terfa 2 terface with the system data bus of a m
45. ure range is 40 C to 85 C A Version Measurement Bandwidth 0 5 x fs Input Level 0 05 dB Ta 25 C to 85 C T Tmn to Tmax Applies after calibration at temperature of interest Gain error excludes reference error The ADC gain is calibrated w r t the voltage on the REF2 pin Specifications subject to change without notice ww BDI C com AD REV B 3 AD7722 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Ta 25 C unless otherwise noted DVpp to DOND acs an kinini aa 0 3 V to 7 V Package Package AVpp AVpp to AGND 0 3 V to 7 V Model Temperature Description Option AVpp AVpp to DVDD 1 V to 1 V AD7722AS 40 C to 85 C 144 Lead MQFP S 44B AGND AGNDI to DGND 0 3 V to 0 3 V EVAL AD7722CB Evaluation Board Digital Inputs to DGND 0 3 V to DVpp 0 3 V Digital Outputs to DGND 0 3 V to DVpp 0 3 V Vnt Vin to AGND 0 3 V to AVpp 0 3 V REFI to AGND 0 3 V to AVpp 0 3 V REF2 to AGND 0 3 V to AVpp 0 3 V DGND AGND1 AGND2 0 3 V Input current to any pin except the supplies 10 mA Operating Temperature Range 40 C to 85 C Storage Temperature Range 65 C to 150 C Joncuon Temperate AKIWA 150 C oo a a Bn Thermal Impedance ii ii 72 C W Figure 1 Load Circuit for Timing Specifications Oye Thermal pee anes KIA

Download Pdf Manuals

Related Search

ANALOG DEVICES AD7722 handbook ad717x_connect_analog_input ad7717-2 ad7203 digital to analog converter ad7715-2 ad7177-2 analog devices p/n ad8479 ad7175-2

Related Contents

SATA Hard disk installation 和RAID function Reference Manual                    

Copyright © All rights reserved.