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ANALOG DEVICES AD9237 Manual

1. DNC DO NOT CONNECT 05455 003 Figure 3 Pin Configuration Pin Number Mnemonic Description 1 MODE2 SHA Gain Select and Power Scaling Control see Table 8 2 CLK Clock Input Pin 3 OE Output Enable Pin Active Low 4 PDWN Power Down Eunction Selection see Table 9 5 GC Gray Gode Control Active High 6 DNC Not Onnett 7 to 14 17 to 20 15 16 21 22 23 24 25 26 27 32 28 31 29 30 DO LSB to D11 MSB DGND DRVDD OTR MODE SENSE VREF REFB REFT AVDD AGND VIN VIN Data Output Bits Digital Output Ground Digital Output Driver Supply Must be decoupled to DGND with a minimum 0 1 uF capacitor Recommended decoupling is 0 1 uF in parallel with 10 pF Out of Range Indicator Data Format and Clock Duty Cycle Stabilizer DCS Mode Selection see Table 10 Reference Mode Selection see Table 7 Voltage Reference Input Output see Table 7 Differential Reference Must be decoupled to REFT with a minimum 10 pF capacitor Differential Reference Analog Power Supply Must be decoupled to AGND with a minimum 0 1 pF capacitor Recommended decoupling is 0 1 uF in parallel with 10 pF Analog Ground Analog Input Pin Analog Input Pin Rev 0 Page 8 of 28 TERMINOLOGY Analog Bandwidth Full Power Bandwidth The analog input frequency at which the spectral power of the fundamental frequency as determined by the FFT
2. 5 LFCSP Evaluation Board see 22 Timing 6 Outline Dimensions entiende eie eH berries 28 Absolute Maximum Ratings sentent 7 Ordering Guide ette tt 28 ESD Caution 7 Pin Configuration and Funttion 1 8 REVISION HISTORY 10 05 Revision 0 Initial Version Rev 0 Page 2 of 28 AD9237 SPECIFICATIONS DC SPECIFICATIONS AVDD 3 V DRVDD 2 5 V maximum sample rate 2 V differential input 0 5 dBFS input 1 0 V internal reference Tw to Tmax unless otherwise noted Table 1 AD9237BCP 20 AD9237BCP 40 AD9237BCP 65 Parameter Min Typ Max Min Unit RESOLUTION 12 12 12 Bits ACCURACY No Missing Codes Guaranteed 12 12 12 Bits Offset Error 1 30 1 95 1 30 1 95 1 30 1 95 FSR Gain Error 0 70 2 10 0 75 2 10 1 05 2 25 FSR Differential Nonlinearity DNL 0 70 0 95 0 70 0 95 1 00 0 70 1 25 LSB Integral Nonlinearity INL 0 90 1 35 0 90 1 35 0 90 2 00 LSB TEMPERATURE DRIFT Offset Error 2 2 2 Gain Error 12 12 12 INTERNAL VOLTAGE REFERENCE Output Voltage Error 1 V Mode 5 25 5 25 5 25 mV Load Regulation 1 0 mA 0 8 0 8 0 8 mV Output Voltage Error 0 5 V Mode 2 5 2 5 2 5 mV Load Regulation 0 5 mA 0 1 0 1 0 1 mV Reference Input Resistance 7 7 7 INPUT REFERRED NOISE ST
3. 50 164 50 ecd 4ed 3SN AGOONS L93410 V 3SN qauadans v 15 319019 SNISSVdA8 ind 370 3rior 3101 SI E Figure 50 LFCSP Evaluation Board Schematic Clock Input Rev 0 Page 25 of 28 AD9237 Figure 53 LFCSP Evaluation Board Layout Ground Plane 0 0 lh e XD 05455 056 05455 057 LM 05455 058 Rev 0 Page 26 of 28 ANALOG DEVICES 2002 USA 2409215 9409235 89409236 2409237 5409245 2204325 0240455 J65MSPS 180 5 EJ105MSPS 79 ING CONTROLS 5 LAT DR2 y RUN E 9 E25 0 CH Figure 56 LFCSP Evaluation Board Layout Secondary Silkscreen 05455 059 05455 060 05455 061 Table 12 LFCSP Evaluation Board Bill of Materials AD9237 Recommended Vendor Supplied Item Qty Omit Reference Designator Device Package Value Part Number by ADI 1 18 C1 C5 C7 C8 C9 C11 C12 Chip Capacitors 0603 0 1 uF C13 C15 C16 C31 C33 C34 C36 C37 C41 C43 C47 9 C6 C17 C18 C27 C28 C35 C42 C44 C45 2 8 C2 C3 C4 C10 C20 Tantalum Capacitors TAJD 10 uF C22 C25 C29 2 C24 C46 3 8 C14
4. 05455 007 Figure 7 Equivalent CLK PDWN Input Circuit AD9237 TYPICAL PERFORMANCE CHARACTERISTICS AVDD 3 0 V DRVDD 2 5 V maximum sample rate with DCS disabled Ta 25 2 V differential input 0 5 dBFS VREF 1 0 V internal FFT length 16 K unless otherwise noted AMPLITUDE dBFS SNR SFDR dBc E 05455 008 60 10 0 12 5 15 0 17 5 FREQUENCY MHz CLOCK FREQUENCY MSPS Figure 8 AD9237 20 10 MHz FFT Figure 11 AD9237 20 SNR SFDR vs Clock Frequency with fin 10 MHz 05455 011 N 90 SNR 66 8dBc SFDR z 83 1dBc SNR SFDR AMPLITUDE dBFS 05455 009 05455 012 0 2 4 6 8 10 12 14 16 18 20 20 2 30 35 40 FREQUENCY MHz CLOCK FREQUENCY MSPS Figure 9 AD9237 40 20 MHz FFT Figure 12 AD9237 40 SNR SFDR vs Clock Frequency with fin 20 MHz 90 SNR 66 0dBc SFDR 78 6dBc 85 80 75 SNR SFDR dBc 70 AMPLITUDE dBFS 65 05455 013 40 45 50 55 60 FREQUENCY MHz CLOCK FREQUENCY MSPS Figure 10 AD9237 65 70 MHz FFT Figure 13 AD9237 65 SNR SFDR vs Clock Frequency with fin 35 MHz a Rev 0 Page 11 of 28 AD9237 SNR 65 6dBc SFDR 67 1dBc SFDR DCS 5 DIS
5. 819 99 00 WOLLO NO 008 3 19NIS eza D 5558 m 39N3H3d3H AS 0 XVW AL 39N3H3H3H AL TVNHINI 8 39V 10A 1VNH31X3 V 3O0N3H343H Figure 48 LFCSP Evaluation Board Schematic Analog Inputs and DUT Rev 0 Page 23 of 28 AD9237 U1 74LVTH162374 HEADER 40 CLKLAT DAC MSB ORX D13X GND D12X D11X DRVDD D10X D9X GND D8X D7X D6X D5X GND D3X DRVDD D2X D1X LSB GND CLKLAT DAC R38 R39 1kQ TO USE AMPLIFIER VAMP POWER DOWN SHOWN RIGHT USE R40 OR R41 C44 C24 REMOVE R12 R3 R18 R42 C6 C18 VAMP GND R17 C17 R19 00 0 1nF 500 GND GND R34 5 1 2kQ Figure 49 LFCSP Evaluation Board Schematic Digital Path Rev 0 Page 24 of 28 AD9237 280 95750 bea sea 153 53 293 2 00 258 aiot ova Lv Dro 979 OL SHOLSIS3H HLO8 SAOWSY 40135 AV130 31V5 SMOHS JILYWAHOS yoya 311000 airo 029 289 022 mm 98XDAPZ sn SNISSVdA8 SNISSVdA8 SNISSVdA8 HOLV1 193 093 miro 19 009 62 er
6. FS FS 1 2 LSB 0 0000 0000 0001 0 0000 0000 0000 0 0000 0000 0000 FS 1 2 LSB FS 1 2LSB 5 Figure 45 OTR Relation to Input Voltage and Output Data Table Data og Input Is MODE Voltage Data Format Duty Cycle Stabilizer AVDD Twos Complement Disabled 2 3 AVDD Twos Complement Enabled 1 3 AVDD Offset Binary Enabled AGND Default Offset Binary Disabled Out of Range OTR An out of range condition exists when the analog input voltage is beyond the input range of the ADC The OTR pin is a digital output that is updated along with the data output corresponding to the particular sampled input voltage Therefore the OTR pin has the same pipeline latency as the digital data OTR is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range as shown in Figure 45 OTR remains high until the analog input returns to within the input range and another conversion is OTR MSB 0 0 Within range 0 1 Within range 1 0 Underrange 1 1 Overrange MSB OVER 1 OTR UNDER 1 8 MSB 5 Figure 46 Overrange Underrange Logic Digital Output Enable Function OE The AD9237 has three state ability The OE pin is internally pulled down to AGND by a 70 resistor If the OE pin is low the output data drivers are enabled If the OE pin is high the output data drivers are placed in a high impedance st
7. Rev 0 Page 4 of 28 AD9237 AD9237BCP 20 AD9237BCP 40 AD9237BCP 65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit SPURIOUS FREE DYNAMIC RANGE SFDR finput 2 4 MHz 88 0 83 5 85 5 dBc 9 7 MHz 724 87 5 dBc finput 19 6 MHz 72 2 82 4 dBc finput 34 2 MHz 69 4 80 1 dBc finpur 70 MHz 80 5 77 9 74 9 dBc WORST HARMONIC SECOND OR THIRD finput 2 4 MHz 88 0 83 5 85 5 dBc finput 9 7 MHz 724 87 5 dBc finput 19 6 MHz 72 2 82 4 dBc finput 34 2 MHz 69 4 80 1 dBc finpur 70 MHz 80 5 77 9 74 9 WORST OTHER SPUR finput 2 4 MHz 90 90 90 finput 9 7 MHz 734 90 finput 19 6 MHz 73 1 90 dBc finput 34 2 MHz 72 0 90 dBc finpur 70 MHz 90 90 90 dBc SWITCHING SPECIFICATIONS Table 4 4 i AD9237BCP 20 AD9237BCP 40 PEE Parameter Min Typ Typ Max in Typ Max Unit CLK INPUT PARAMETERS Maximum Conversion Rate 20 40 65 MSPS Minimum Conversion Rate 1 1 1 MSPS CLK Period 50 0 25 0 15 4 ns CLK Pulse Width High 15 0 8 8 6 2 ns CLK Pulse Width Low 15 0 8 8 6 2 ns DATA OUTPUT PARAMETERS Output Delay teo 3 5 3 5 3 5 ns Pipeline Delay Latency 8 8 8 Cycles Output Enable Time 6 6 6 ns Output Disable Time 3 3 3 ns Aperture Delay t4 1 0 1 0 1 0 ns Aperture Uncertainty Jitter t 0 5 0 5 0 5 ps rms Wake Up Time Sleep Mode 3 0 3 0 3 0 ms Wake Up Time Standby Mode 3 0 3 0 3 0
8. C30 C32 Chip Capacitors 0603 0 001 uF C38 C39 C40 C48 C49 4 1 C19 Chip Capacitor 0603 15 pF 5 1 C26 Chip Capacitors 0603 10 pF 2 C21 C23 6 41 E2 to E36 E43 E44 E50 to E53 Headers EHOLE Jumper Blocks 2 E1 E45 1031 02 ND 4 H1 H2 H3 H4 MTHOLE 7 2 1 2 SMA Connectors 50 SMA 8 1 L1 Inductor 0603 10nH Coilcraft 0603CS 10NXGBU 9 1 P2 Terminal Block TB6 Wieland 25 602 2653 0 25 530 0625 0 10 1 P12 Header Dual HEADER40 Digi Key 52131 20 0 20 Pin RT Angle 11 5 R3 R12 R23 R28 Rx GhipyResistors 0603 00 6 816 RY n 627 R37 R42 7 12 2 R4 R15 I Resistors i 0603 330 13 19 R5 to R8 R13 R20 R21 Chip Resistors 0603 1 R24 to R26 R30 to R32 R36 R43 to R47 2 R38 R39 14 2 R10 R11 Chip Resistors 0603 360 15 1 R29 Chip Resistors 0603 500 1 R19 16 12 RP1 RP2 Resistor Pack R 742 2200 Digi Key CTS 742C163220JTR 17 1 T1 ADT1 1WT AWT1 1T Mini Circuits 18 1 U1 74LVTH162374 TSSOP 48 CMOS Register 19 1 04 AD9237BCP ADC DUT LFCSP 32 Analog Devices Inc X 20 1 U5 74VCX86M SOIC 14 Fairchild 21 1 PCB AD92XXBCP PCB PCB Analog Devices Inc X 22 1 U3 AD8351 Op Amp MSOP 8 Analog Devices Inc X 23 1 T2 M A COM 1 1 13 1 1TX M A COM ETC1 1 13 Transformer 24 1 R2 Chip Resistor 0603 SELECT 25 3 R14 R18 R35 Chip Resistors 0603 250 26 4 R1 R9 R40 R41 Chip Resistors 0603 10 kQ 27 1 R34 Chip Resistor 1 2 28 1 R33 Chip Resistor 1000 Total 118 40 These items ar
9. xoa xia xva xsa xoa dn 9 ASQGNVIS 74 3 5022 330 1OH1NOO OLNV 2 NIVO VHS 8 NO 1 2 NIVO VHS 2 NO H3A Od 1 VHS 9 330 1041405 H3MOd NIVO VHS 9 xcia 080 9990 085 5 H 552 v LY NO 819 ANO ike 220 m C m 9 I 1 1913 21 1VNOILdO n ora 61 05 12 22 ec xeia 93 10H LIN vH 93 10H LWN 93 10H LIN 9310H LIN a te A asn H3AO 80 330 371949 ALNG AYVNIE 13330 7 NO 31949 13330 NO 319492 ALnG dWOO 2 2 330 31942 ALNA dINOD 1 123135 T rj NEX 1MI LLOV So airo 99 V LY QHVOS NO 38 its Q InOHS ANO ERN LLO 219 229 49
10. 4 VREF 0 5 V 135 185 135 158 rms VREF 1 0V 070 i 0 70 4 050 LSB rms ANALOG INPUT Input Span VREF 0 5 MODE2 0 V 1 1 1 V p p VREF 1 0 V MODE2 0 V 2 2 2 V p p VREF 0 5 V MODE2 AVDD 2 2 2 V p p VREF 1 0 V MODE2 AVDD 4 4 4 V p p Input Capacitance 7 7 7 pF POWER SUPPLIES Supply Voltages AVDD 2 7 3 0 3 6 2 7 3 0 3 6 2 7 3 0 3 6 V DRVDD 2 25 2 5 3 6 2 25 2 5 3 6 2 25 2 5 3 6 V Supply Current IAVDD 30 5 45 5 64 5 mA IDRVDD 3 0 4 5 5 5 mA PSRR 0 01 0 01 0 01 FSR POWER CONSUMPTION DC Input 85 135 190 mW Sine Wave Input 100 120 150 180 210 270 mW Power Down Mode 1 1 1 mW Standby Power 20 20 20 mW 1 Gain error and gain temperature coefficient are based on the ADC only with a fixed 1 0 V external reference 2 Measured at maximum clock rate fn 2 4 MHz full scale sine wave with approximately 5 pF loading on each output bit 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND Refer to Figure 4 for the equivalent analog input structure Measured with dc input at maximum clock rate Rev 0 Page 3 of 28 AD9237 DIGITAL SPECIFICATIONS Table 2 AD9237BCP 20 AD9237BCP 40 AD9237BCP 65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit LOGIC INPUTS High Level Input Voltage 2 0 2 0 2 0 V Low Level Input Voltage 0 8 0 8 0 8 V High Level Input Current 10 10 10 10 10 10 Low Level Input Current 10 1
11. 46 MHz SNR 67 2dBFS SFDR 88 3dBFS AMPLITUDE dBc 05455 021 0 5 10 15 20 FREQUENCY MHz Figure 21 AD9237 40 Two Tone FFT 45 MHz 46 MHz SNR 66 9dBFS SFDR 84 1dBFS AMPLITUDE dBFS 05455 094 0 5 10 15 20 25 30 FREQUENCY MHz Figure 22 AD9237 65 Two Tone FFT fini 69 MHz fw 70 MHz Rev 0 Page 13 of 28 SNR SFDR dBc and dBFS 05455 024 30 25 20 15 10 INPUT AMPLITUDE AIN Figure 23 AD9237 65 Two Tone SNR SFDR vs Analog Input with 45 MHz fw 46 MHz 1 o SNR SFDR dBc and dBFS 05455 025 30 25 20 15 10 INPUT AMPLITUDE AIN Figure 24 AD9237 40 Two Tone SNR SFDR vs Analog Input with 45 MHz fw 46 MHz o SNR SFDR dBc and dBFS 05455 098 30 25 20 15 10 INPUT AMPLITUDE AIN 1 o Figure 25 AD9237 65 Two Tone SNR SFDR vs Analog Input with 69 MHz 70 MHz AD9237 100 SNR 67 1dBFS SFDR 87 3dBFS o H5 m a 5 2 5 5 5 5 2 0 5 10 15 20 30 25 20 15 10 6 5 FREQUENCY MHz INPUT AMPLITUDE AIN Figure 26 AD9237 40 Two Tone FFT Figure 29 AD92
12. a changing clock and the part does not have enough power to operate properly 190 170 AD9237 65 150 130 POWER mW 110 90 05455 096 10 20 30 40 50 60 6 SAMPLE RATE MSPS Figure 44 Total Power vs Sample Rate with Power Scaling Enabled a The MODE2 pin is a multilevel input that controls the span factor and power scaling modes The MODE2 pin is internally pulled down to AGND by a 70 kQ resistor The input threshold and corresponding mode selections are outlined in Table 8 Table 8 MODE2 Selection MODE2 Voltage Span Factor Power Scaling AVDD 1 Disabled 2 3 AVDD 1 Enabled 1 3 AVDD 2 Enabled AGND Default 2 Disabled PDWNipiu is m ltileye input 4 controls the power states The input threshold values and corresponding power states are outlined in Table 9 Table 9 PDWN Selection PDWN Voltage Power State Power mW AVDD Power Down Mode 1 1 3 AVDD Standby Mode 20 AGND Default Normal Operation Based on speed grade By asserting the PDWN pin high the AD9237 is placed in power down mode In this state the ADC typically dissipates 1 mW During power down the output drivers are placed in a high impedance state Low power dissipation in power down mode is achieved by shutting down the reference reference buffer biasing networks clock and duty cycle stabilizer circuitry The decoupling capacitors on REFT and REFB
13. are discharged when entering power down mode and then must be recharged when returning to normal operation Asa result the wake up time is related to the time spent in power down mode and shorter standby cycles result in proportionally shorter wake up times With the recommended 0 1 uF and 10 uF decoupling capacitors and it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 3 ms to restore full operation Rev 0 Page 20 of 28 By asserting the PDWN pin to AVDD 3 the AD9237 is placed in standby mode In this state the ADC typically dissipates 20 mW The output drivers are placed in a high impedance state The reference circuitry is enabled allowing for a quick start upon bringing the ADC into normal operating mode DIGITAL OUTPUTS The AD9237 output drivers can be configured to interface with 2 5 V or 3 3 V logic families by matching DRVDD to the digital supply of the interfaced logic The output drivers are sized to provide sufficient output current to drive a wide variety of logic families However large drive currents tend to cause current glitches on the supplies that can affect converter performance Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9237 these transients can
14. most amplifiers is not adequate to achieve the true performance of the AD9237 This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled For these applications differential transformer coupling is the recommended input configuration as shown in Figure 37 05455 042 Figure 3 Differential Vy Configuration Thessignal characteristics considered when selecting a transformer Most RF transformers saturate at frequencies below a few MHz and excessive signal power can cause core saturation which leads to distortion Single Ended Input Configuration A single ended input can provide adequate performance in cost sensitive applications In this configuration there is degradation in SFDR and distortion performance due to the large input common mode swing However if the source impedances on each input are matched there should be little effect on SNR performance Figure 38 details a typical single ended input configuration 1 05455 099 Figure 38 Single Ended Input Configuration Rev 0 Page 17 of 28 AD9237 Table 7 Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF V Span Factor Resulting Differential Span V p p External Reference AVDD N A 2 4x External Reference Span Factor 1 Internal Fixed Reference VREF 0 5 2 1 0V 1 4 0V Programmable Reference 0 2 V to VREF 0 5 x 1 R2 R1 2 4x VRE
15. range 40 C to 85 Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM 10 STAGE 1 1 2 BIT CLOCK DUTY CYCLE STABILIZER 05455 001 AGND CLK PDWN MODE DGND Figure 1 PRODUCT HIGHLIGHTS 1 Evaluation boards available for all speed grades 2 Operating at 65 MSPS the AD9237 consumes low 190 mW at 65 MSPS 135 mW at 40 MSPS and 85 mW at 20 MSPS 3 Power scaling reduces the operating power further when running at lower speeds 4 The AD9237 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2 5 V and 3 3 V logic families 5 The patented SHA input maintains excellent performance for input frequencies beyond Nyquist and can be configured for single ended or differential operation 6 The AD9237 is optimized for selectable and flexible input ranges from 1 V p p to 4 V p p 7 Anoutput enable pin allows for multiplexing of the outputs 8 Two step power down supports a st
16. to the SENSE pin This puts the reference amplifier in a non inverting mode with the VREF output defined as 10uF VREF 0 5 x z AD9237 05455 044 Figure 40 Programmable Reference Configuration Rev 0 Page 18 of 28 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics Figure 41 shows the typical drift characteristics of the internal reference in both 1 V and 0 5 V modes When multiple ADCs track one another a single reference internal or external reduces gain matching errors When the SENSE pin is connected to AVDD the internal reference is disabled allowing the use of an external reference An internal reference buffer loads the external reference with an equivalent 7 load The internal buffer still generates the positive and negative full scale references REFT and REFB for the ADC core The input span is always four times the value of the reference voltage divided by the span factor therefore the external reference must be limited to a maximum of 1 V 0 7 0 6 0 5 1V REFERENCE 0 4 0 3 VREF ERROR 0 2 Y REFERENCE 05455 046 40 20 0 20 40 60 8085 TEMPERATURE Figure 41 Typical VREF Drift If the internal reference of the AD9237 is used to drive multiple converters to improve gain matching the loading of the refer e
17. 0 10 10 10 10 Input Capacitance 2 2 2 pF LOGIC OUTPUTS DRVDD 3 3 V High Level Output Voltage 50 pA 3 29 3 29 3 29 V High Level Output Voltage 0 5 mA 3 25 3 25 3 25 V Low Level Output Voltage IOL 1 6 mA 0 2 0 2 0 2 V Low Level Output Voltage IOL 50 uA 0 05 0 05 0 05 V DRVDD 2 5V High Level Output Voltage 50 uA 2 49 2 49 2 49 V High Level Output Voltage 0 5 mA 2 45 2 45 2 45 V Low Level Output Voltage IOL 1 6 mA 0 2 0 2 0 2 V Low Level Output Voltage IOL 50 pA 0 05 0 05 0 05 V 1 Output voltage levels measured with 5 pF load on each output ACSPECIFICATIONS AVDD 3 V DRVDD 2 5 V maximum sample rate 2 V differential input 0 5 dBFS 1 0 V internal reference Tum to Tmax unless otherwise noted Table 3 AD9237BCP 20 AD9237BCP 40 AD9237BCP 65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL TO NOISE RATIO SNR finput 2 4 MHz 66 8 66 5 66 5 dBc finput 9 7 MHz 65 6 66 6 dBc finput 19 6 MHz 65 3 66 6 dBc finput 34 2 MHz 64 0 66 1 dBc finpur 70 MHz 66 0 66 3 65 9 dBc SIGNAL TO NOISE RATIO AND DISTORTION SINAD finput 2 4 MHz 66 7 66 4 66 3 dBc finput 9 7 MHz 65 1 66 5 dBc 19 6 MHz 64 4 66 4 dBc finput 34 2 MHz 63 5 65 8 dBc finpur 70 MHz 65 6 65 8 65 2 dBc EFFECTIVE NUMBER OF BITS ENOB finput 9 7 MHz 10 8 Bits finput 19 6 MHz 10 7 Bits finput 34 2 MHz 10 6 Bits
18. 37 40 Two Tone SNR SFDR vs Analog Input with 69 70 MHz fii 69 MHz 70 MHz 90 85 SFDR 80 m 5 75 a a 5 70 SNR 1 65 E 50 k 8 55 8 0 25 50 75 100 125 0 25 50 75 100 125 INPUT FREQUENCY MHz INPUT FREQUENCY MHz Figure 27 AD9237 65 SNR SFDR vs Input Frequency Figure 30 AD9237 40 SNR SFDR vs Input Frequency EI z 2 S T 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 CODE CODE Figure 28 Typical INL Figure 31 Typical DNL Rev 0 Page 14 of 28 SINAD dBc AD9237 20 37 40 AD9237 65 10 20 30 40 50 CLOCK FREQUENCY MSPS Figure 32 AD9237 SINAD ENOB vs Clock Frequency with Nyquist 60 70 10 75 10 67 10 50 10 83 ENOB Bits 10 59 05455 062 Rev 0 Page 15 of 28 AD9237 90 85 80 m 5 75 o z 65 60 gt 40 20 0 20 40 60 8085 TEMPERATURE Figure 33 AD9237 65 SNR SFDR vs Temperature with fiw 32 5MHz AD9237 APPLYING THE AD9237 THEORY OF OPERATION The AD9237 uses a calibrated 11 stage pipeline architecture with a patented input SHA implemented Each stage of the pipeline excluding the last consists of a low resolution flash ADC connected to a switched capacitor digital to analog converter DAC and an interstage residue amplifier
19. ABLED m a ul tc 3 CS ENABLED g lt o N CS DISABLED 8 0 5 10 15 20 25 30 32 5 30 35 40 45 50 55 60 65 70 FREQUENCY MHz DUTY CYCLE Figure 14 AD9237 65 100 MHz FFT Figure 17 SNR SFDR vs Clock Duty Cycle SFDR dBFS 2V p p A SFDR dBFS 2V p E SFDR dBFS 1V p p 2 SNR dBFS 2V FDR dBc 2V p p Es SNR dBFS 4V 5 SNR dBFS 2V Bc 1V p p 5 Ld 5 SNR dBF a a a E FDR dBc 4V p s c e SFDR dBc 2V p p Im 9 SNR 2V E 2 SNR 3 SNR dBc 2V 5 30 25 20 15 10 5 0 30 25 20 15 10 5 0 INPUT AMPLITUDE dBFS INPUT AMPLITUDE dBFS Figure 15 AD9237 65 SNR SFDR vs Input Amplitude with fiw 35 MHz Figure 18 AD9237 65 SNR SFDR vs Input Amplitude with fin 35 MHz SFDR dBFS 2V p p SFDR dBFS 2V p p 5 5 SEE 80 srpR mra 2708 o o t a 5 B E SNR dB 5 5 SNR dBFS 1V o o 2 SNR dBc 2V p p 8 3 SNR dBc 1V 8 30 25 20 15 10 5 0 30 25 20 15 10 5 0 INPUT AMPLITUDE dBFS INPUT AMPLITUDE dBFS Figure 16 AD9237 40 SNR SFDR vs Input Amplitude with fn 20 MHz Figure 19 AD9237 20 SNR SFDR vs Input Amplitude with fin 10 MHz Rev 0 Page 12 of 28 AD9237 SNR 67 0dBFS SFDR 87 8dBFS AMPLITUDE dBc 01 05455 095 0 5 10 15 20 25 30 32 FREQUENCY MHz Figure 20 AD9237 65 Two Tone FFT 45 MHz
20. ANALOG DEVICES 12 Bit 20 MSPS 40 MSPS 65 MSPS 3 V Low Power A D Converter 109237 FEATURES Ultralow power 85 mW at 20 MSPS 135 mW at 40 MSPS 190 mW at 65 MSPS SNR 66 dBc to Nyquist at 65 MSPS SFDR 80 dBc to Nyquist at 65 MSPS DNL 0 7 LSB Differential input with 500 MHz bandwidth Flexible analog input 1 V p p to 4 V range Offset binary twos complement or gray code data formats Output enable pin 2 step power down Full power down and sleep mode Clock duty cycle stabilizer APPLICATIONS Ultrasound and medical imaging Battery powered instruments Hand held scope meters Low cost digital oscilloscopes Low power digital still LU nd copiers Low power communications GENERAL DESCRIPTION The AD9237 is a family of monolithic single 3 V supply 12 bit 20 MSPS 40 MSPS 65 MSPS analog to digital converters ADC This family features a high performance sample and hold amplifier SHA and voltage reference The AD9237 uses a multistage differential pipelined architecture with output error correction logic to provide 12 bit accuracy at 20 MSPS 40 MSPS 65 MSPS data rates and guarantees no missing codes over the full operating temperature range With significant power savings over previously available ADCs the AD9237 is suitable for applications in imaging and medical ultrasound Fabricated on an advanced CMOS process the AD9237 is available in a 32 lead LFCSP and is specified over the industrial temperature
21. F See Figure 40 Span _Factor 1 Internal Fixed Reference AGND to 0 2 1 0 2 20V 1 1 0V VOLTAGE REFERENCE stable and accurate 0 5 V voltage reference is built into the AD9237 The input range can be adjusted by varying the reference voltage applied to the AD9237 using either the internal reference or an externally applied reference voltage The input span of the ADC tracks reference voltage changes linearly 10uF In all reference configurations REFT and REFB drive the A D conversion core and in conjunction with the span factor establish its input span The input range of the ADC always equals four times the voltage af Y reference pin divided by the span factor for either an internal an external referende It is required to decouple REFT to REFB with 0 1 uF and 10 uF decoupling capacitors as shown in Figure 39 05455 043 Internal Reference Connection A comparator within the AD9237 detects the potential at the SENSE pin and configures the reference into one of four possible states which are summarized in Table 7 If SENSE is grounded the reference amplifier switch is connected to the internal resistor divider setting VREF to 1 V see Figure 39 Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin completing the loop and providing a 0 5 V reference output If a resistor divider is 10uF connected as shown in Figure 40 then the switch is again set
22. MDAC The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline One bit of redundancy is used in each stage to facilitate digital correction of flash errors The last stage consists of a flash ADC The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples While the converter captures a new input sample every clock cydle it takes eight clock cycles for the conversion to be fully processed and to appear at the output as shown in Figure 2 The input stage contains a differential SHA that can be ac or dc coupled in differential or single ended modes The output staging block aligns the data carries out the error correction and passes the data to the output buffers The output buffers are powered from a separate supply allowing adjustment of the output voltage swing During power down ane stand by operation the output buffers 20 pe i state The ADC samples the analog input on the rising edge of the clock System disturbances just prior to or immediately following the rising edge of the clock and or excessive clock jitter can cause the SHA to acquire the wrong input value and should be minimized ANALOG INPUT AND REFERENCE OVERVIEW The analog input to the AD9237 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differen
23. analysis is reduced by 3 dB Aperture Delay t4 The delay between the 50 point of the rising edge of the clock and the instant at which the analog input is sampled Aperture Jitter The sample to sample variation in aperture delay Integral Nonlinearity INL The deviation of each individual code from a line drawn from negative full scale through positive full scale The point used as negative full scale occurs LSB before the first code transition Positive full scale is defined as a level 1 LSBs beyond the last code transition The deviation is measured from the middle of each particular code to the true straight line Differential Nonlinearity DNL No Missing Codes An ideal ADC exhibits code transitions that are exactly 1 LSB apart DNL is the deviation from this ideal value Guaranteed no missing codes to 12 bit resolution indicates that all 4096 codes must be present over all operating ranges Offset Error i i The major carry transition should occur for an analog value LSB below VIN VIN Offset error is defined as the deviation of the actual transition from that point Gain Error The first code transition should occur at an analog value LSB above negative full scale The last transition should occur at an analog value 1 LSB below the positive full scale Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last cod
24. andby mode in addition to a power down mode 9 The OTR output bit indicates when the signal is beyond the selected input range 10 The clock duty cycle stabilizer DCS maintains converter performance over a wide range of clock pulse widths One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved AD9237 TABLE OF CONTENTS Features coo ud S ME 1 Tetmihology e E HER 9 Applications zt REESE S RUD REX 1 Equivalent Circuits senene a E E EER 10 Functional Block Diagram sse 1 Typical Performance Characteristics 11 General Description esee tentent entente 1 Applying the AD9237 16 Prod ct HiehligBts 1 Theory of Operation oo RR 16 Revision History eee teen e a etico 2 Analog Input and Reference Overview 16 Specifications 3 Voltage Reterence A 18 DGSpecificatlons s ite im ente REPERI etit etes 3 Clock Input Considerations seen 19 Digital Specifications a i tette 4 Power Dissipation Power Scaling and Standby Mode 19 Sp cifications uere endet eb tentes 4 Digital eee iur Re ir e 21 Switching Specificationis ietee
25. ate It is not intended for rapid access to the data bus Note that the OE pin is referenced to the digital supplies DRVDD and should not exceed that voltage Timing The AD9237 provides latched data outputs with a pipeline delay of eight clock cycles Data outputs are available one propagation delay trp after the rising edge of the clock signal Refer to Figure 2 for a detailed timing diagram Rev 0 Page 21 of 28 AD9237 LFCSP EVALUATION BOARD An alternative differential analog input path using an AD8351 op amp is included in the layout but is not populated in production Designers interested in evaluating the op amp with the ADC should remove C15 R12 and R3 and populate the op amp circuit The passive network between the AD8351 outputs and the AD9237 allows the user to optimize the frequency response of the op amp for the application The typical bench setup used to evaluate the ac performance of the AD9237 is shown in Figure 47 The AD9237 can be driven single ended or differentially through a transformer Separate power pins are provided to isolate the DUT from the support circuitry Each input configuration can be selected by proper connection of various jumpers refer to the schematics HP8644 2V p p REFIN SIGNAL SYNTHESIZER AD9237 EVALUATION BOARD 10MHz HP8644 2V p p REFOUT CLOCK SYNTHESIZER 05455 051 Figure 47 LFCSP Evaluation Board Connections TY ALI Rev 0 Page 22 of 28 AD9237
26. detract from the converter s dynamic performance As detailed in Table 10 the data format can be selected for either offset binary twos complement or gray code Operational Mode Selection The AD9237 can output data in either offset binary twos complement or gray is also provisi n for enabling or disabling stabilize The MODE pin is a multilevel input that controls the data format except for gray code and DCS state The MODE pin is internally pulled down to AGND by a 70 resistor The input threshold values and corresponding mode selections are outlined in Table 10 The gray code output format is obtained by connecting GC to AVDD When the part is in gray code mode the MODE pin controls the DCS function only The GC pin is internally pulled down to AGND by a 70 resistor Table 10 MODE Selection AD9237 completed By logically AND ing OTR with the MSB and its complement overrange high or underrange low conditions can be detected Table 11 is a truth table for the overrange under range circuit in Figure 46 which uses NAND gates Systems requiring programmable gain condition of the AD9237 can after eight clock cycles detect an out of range condition therefore eliminating gain selection iterations In addition OTR can be used for digital offset and gain calculation OTR DATA OUTPUTS 1111 1111 1111 FS 1 LSB 0 1111 1111 1110
27. e included in the PCB design but are omitted at assembly Rev 0 Page 27 of 28 AD9237 OUTLINE DIMENSIONS PIN 1 INDICATOR 0 50 G BSC 4 EXPOSED 3 25 PAD 3 10 SQ F BOTTOM VIEW 0 50 040 4 0 30 NONNA 3 50 REF COPLANARITY 0 20 REF 0 08 COMPLIANT TO JEDEC STANDARDS MO 220 VHHD 2 Figure 57 32 Lead Lead Frame Chip Scale Package LFCSP_VQ 5mm x 5 mm Body Very Thin Quad CP 32 2 Dimensions shown in millimeters PIN 1 INDICATOR 0 25 MIN ORDERING GUIDE Model Temperature Range Package Description 4 Package Option AD9237BCPZ 20 2 140549 3570 32 Lead Lead Frame Chip Scale Package LFCSP VO CP 32 2 AD9237BCPZRL7 20 40 C to 85 C 32 Lead Lead Frame Chip Scale Package EFCSP VQ CP 32 2 AD9237BCPZ 40 2 409 to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 32 2 AD9237BCPZRL7 40 2 409 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 32 2 AD9237BCPZ 65 2 409 to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 32 2 AD9237BCPZRL7 65 2 409 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 32 2 AD9237BCP 20EB AD9237BCP 40EB AD9237BCP 65EB Evaluation Board Evaluation Board Evaluation Board 17 Pb free part It is recommended that the exposed paddle be soldered to the ground plane There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with ex
28. e transitions Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial 25 value to the value at or Tmax Power Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit Total Harmonic Distortion The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal AD9237 Signal To Noise and Distortion SINAD The ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc Effective Number of Bits ENOB The effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD using the following formula 1 76 6 02 Signal to Noise Ratio SNR The ratio of the rms signal to the rms value of the sum of all other spectral components below the Nyquist frequency excluding the first six harmonics and dc Spurious Free Dynamic Range SFDR SFDR is the difference in dB between the rms amplitude of the input signal and the rms value of the peak spurious signal The peak spurious signal may not be an harmonic Two Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious compon
29. ent The peak spurious component IMD Clock Pulse Width and Duty GyGle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance Pulse width low is the minimum time the clock pulse should be left in the low state At a given clock rate these specifications define an acceptable clock duty cycle Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit Maximum Conversion Rate The clock rate at which parametric testing is performed Output Propagation Delay trp The delay between the clock logic threshold and the time when all bits are within valid logic levels Out of Range Recovery Time The time it takes the ADC to reacquire the analog input after a transition from 10 above positive full scale to 10 above negative full scale or from 10 below negative full scale to 10 below positive full scale 1 AC specifications may be reported in dBc degrades as signal levels are lowered or in dBFS always related back to converter full scale Rev 0 Page 9 of 28 AD9237 EQUIVALENT CIRCUITS AVDD VIN 05455 004 2 li Figure 4 Equivalent Analog Input Circuit 05455 005 Figure 5 Equivalent MODE MODE2 GC OE Input Circuit UM Rev 0 Page 10 of 28 DRVDD 4 rant 05455 006
30. evel allows the AD9237 to accommodate ground referenced inputs Although optimum performance is achieved with a differential input a single ended source can be driven into VIN or VIN In this configuration one input accepts the signal while the opposite input should be set to midscale by connecting it to an appropriate reference For example a 2 V signal can be applied to VIN while a 1 V reference is applied to VIN The AD9237 then accepts an input signal varying between 2 V and 0 V In the single ended configuration distortion performance may degrade significantly as compared to the differential case However the effect is less noticeable at lower input frequencies and in the lower speed grade models AD9237 40 and AD9237 20 Differential Input Configurations As previously detailed optimum performance is achieved while driving the AD9237 in a differential input configuration For baseband applications the AD8351 differential driver provides excellent performance and a flexible interface to the ADC The output common mode voltage of the AD8351 is easily set to AVDD 2 and the driver can be configured in a Sallen Key filter topology to provide band limiting of the input signal Figure 36 details a typical configuration using the AD8351 AD9237 AVDD VIN AD9237 05455 041 Figure 36 Differential Input Configuration Using the AD8351 At input frequencies in the second Nyquist zone and above the performance of
31. nce by the other converters must be considered Figure 42 shows how the internal reference voltage is affected by loading 2 mA load is the maximum recommended load 0 05 4 li 0 10 lt DM 0 15 N ERROR 05455 093 0 0 5 1 0 1 5 2 0 2 5 3 LOAD mA Figure 42 VREF Accuracy vs Load AD9237 CLOCK INPUT CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and as a result can be sensitive to clock duty cycle Commonly a 596 tolerance is required on the clock duty cycle to maintain dynamic performance characteristics The AD9237 contains a clock duty cycle stabilizer DCS that retimes the nonsampling or falling edge providing an internal clock signal with a nominal 50 duty cycle This allows a wide range of clock input duty cycles without affecting the performance of the AD9237 As shown in Figure 17 noise and distortion performance are nearly flat over a 30 range of duty cycle with the DCS enabled The duty cycle stabilizer uses a delay locked loop DLL to create the nonsampling edge As a result any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate High speed high resolution ADCs are sensitive to the quality of the clock input The degradation in SNR at a given full scale input frequency fixpur due only to rms apert
32. of 28 AD9237 This maximum current occurs when every output bit switches on every clock cycle that is a full scale square wave at the Nyquist frequency 2 In practice the DRVDD current is established by the average number of output bits switching which is determined by the encode rate and the characteristics of the analog input signal 190 170 150 z 130 AD9237 65 o a 110 AD9237 40 90 5 AD9237 20 8 70 8 10 20 30 40 50 60 65 SAMPLE RATE MSPS Figure 43 Total Power vs Sample Rate with fiw 10 MHz For the AD9237 20 speed grade the digital power consumption can represent as much as 1096 of the total dissipation Digital power consumption can be minimized by reducing the capacitive load presented to the output drivers The data in Figure 43 was taken with a 5 pF 1644 output driver The AD9237 is designed to provide excellent performance with minimum power The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption Each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency as shown in Figure 43 The power scaling feature provides an additional power savings when enabled as shown in Figure 44 The power scaling mode cannot be enabled if the clock is varied during operation This is because the internal circuitry cannot quickly track
33. posed paddle soldered to the customer board 2005 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D05455 0 10 05 0 ANALOG DEVICES Rev 0 Page 28 of 28 www analog com
34. s driving VIN and VIN should be matched so that common mode settling errors are symmetrical These errors are reduced by the common mode rejection of the ADC An internal differential reference buffer creates positive and negative reference voltages REFT and REFB that define the span of the ADC core Rev 0 Page 16 of 28 The output common mode of the reference buffer is set to mid supply and the REFT and REFB voltages and input span are defined as REFT VREF REFB VREF _ Ax REFT _ 4xVREF Span _ Factor Span Span _ The previous equations show that the and REFB voltages are symmetrical about the midsupply voltage and the input span is proportional to the value of the VREF voltage see Table 7 for more details The internal voltage reference can be pin strapped to fixed values of 0 5 V or 1 0 V or adjusted within this range as discussed in the Internal Reference Connection section Maximum SNR performance is achieved with the AD9237 set to an input span of 2 V p p or greater The relative SNR degradation is 3 dB when changing from 2 V p p mode to 1 V p p mode The SHA must be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage The minimum and maximum common mode input levels are defined as VREF 2 AVDD VREP 2 The minimum common mode input l
35. tial input signal The SHA input can support a wide common mode range and maintain excellent performance as shown in Figure 34 An input common mode voltage of midsupply minimizes signal dependant errors and provides optimum performance Figure 35 shows the clock signal alternately switching the SHA between sample mode and hold mode When the SHA is switched into sample mode the signal source must be capable of charging the sample capacitors and settling within one half of a clock cycle A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source 90 2 5MHz SFDR 80 34 2MHz SFDR 70 2 5MHz SNR a E 34 2MHz SNR 60 50 40 30 8 0 0 5 1 0 1 5 2 0 2 5 3 0 INPUT COMMON MODE LEVEL V Figure 34 AD9237 65 SNR SFDR vs Input Common Mode Level In addition a small shunt capacitor placed across the inputs provides dynamic charging currents This passive network creates a low pass filter at the ADC s input therefore the precise values are dependant on the application In IF under sampling applications the shunt capacitor s should be reduced or removed depending on the input frequency In combination with the driving source impedance the capacitors limit the input bandwidth a H J 05455 039 Figure 35 Switched Capacitor SHA Input For best dynamic performance the source impedance
36. ure jitter 5 can be calculated by 1 SNR Degradation 20 log 5 2f Inis quati ny dfe rms App represents the root sum squazre of all jitter sourges which include the clock input analog input signal and ADC aperture jitter specification Undersampling applications are particularly sensitive to jitter The clock input should be treated as an analog signal in cases where aperture jitter can affect the dynamic range of the AD9237 Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise Low jitter crystal controlled oscillators make the best clock sources If the clock is generated from another type of source such as gating dividing or other methods then it should be retimed by the original clock at the last step The lowest typical conversion rate of the AD9237 is 1 MSPS At clock rates below 1 MSPS dynamic performance may degrade POWER DISSIPATION POWER SCALING AND STANDBY MODE As shown in Figure 43 the power dissipated by the AD9237 is proportional to its sample rate The digital power dissipation does not vary substantially between the three speed grades because it is determined primarily by the strength of the digital drivers and the load on each output bit The maximum DRVDD current can be calculated as X Croan X X N where N is 12 the number of output bits Rev 0 Page 19
37. us OUT OF RANGE RECOVERY TIME 1 1 2 Cycles With duty cycle stabilizer enabled Output delay is measured from CLK 5096 transition to DATA 5096 transition with 5 pF load on each output 3 Wake up time is dependent on value of decoupling capacitors typical values shown with 0 1 uF and 10 pF capacitors and REFB Rev 0 Page 5 of 28 AD9237 TIMING DIAGRAM ANALOG INPUT Il OU C EO OUS 4 05455 002 Figure 2 Timing Diagram TY ALI Rev 0 Page 6 of 28 ABSOLUTE MAXIMUM RATINGS Table 5 With Pin Name Respect to Min Max Unit ELECTRICAL AVDD AGND 03 439 V DRVDD DGND 03 43 9 V AGND DGND 03 403 V AVDD DRVDD 3 9 439 V Digital DGND 0 3 DRVDD 0 3 V Outputs OE CLK MODE AGND 0 3 AVDD 0 3 V MODE2 VIN VIN AGND 0 3 AVDD 0 3 V VREF AGND 0 3 AVDD 0 3 V SENSE AGND 0 3 AVDD 0 3 V REFB REFT AGND 0 3 AVDD 0 3 V PDWN AGND 0 3 AVDD 0 3 V ENVIRONMENTAL Operating Temperature 40 85 Junction Temperature 150 Lead Temperature 10 sec 300 Storage Temperature 65 150 1 Typical thermal impedances 32 lpad L ECSP 32 5 232 71 C W These measurements weretakenon 4 layetipoard in with EIA JESD51 1 ESD CAUTION ESD electrostatic discharge sensitive de
38. vice Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality AD9237 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired Functional operability is not necessarily implied Exposure to absolute maximum rating conditions for an extended period may affect device reliability WARNING ESD SENSITIVE DEVICE Rev 0 Page 7 of 28 AD9237 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6 Pin Function Descriptions 32 AVDD 31 AGND 30 VIN 29 28 AGND 27 AVDD 26 REFT 25 REFB MODE2 VREF TE INDICATOR PDWN AD9237 OTR GC TOP VIEW D11 MSB DNC Not to Scale D10 00 LSB D9 D1 D8

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