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ANALOG DEVICES AD7760 handbook

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1. sss 33 Control Register 2 Address 0x0002 sss 33 Status Register Read Only sss 34 Offset Register Address 0x0003 sss 34 Gain Register Address 0x0004 sse 34 Overrange Register Address 0x0005 sss 34 Outline Dimensions REPRE n GER ees 35 Ordering GUd tun 35 Rev A Page 2 of 36 AD7760 REVISION HISTORY 8 06 Rev 0 to Rev A Updated Package Option ss Universal Change to Features etse es Ee vivan det slot ES Eg sE E ONA 1 Changes to Specifications 4 Changes to Absolute Maximum Ratings see 8 Changes to Terminology Section see 11 Added Figure 36 Through Figure 39 sesse se sss 17 Added Modulator Data Output Mode Section 19 Added Figure 41 Through Figure 47 sss 19 Added Modulator Data Output Mode Interface Section 20 Changes to Reading Data Section 22 Added Synchronization Section ee ee ee eke ee ee 22 Changes to Clocking the AD7760 Section sss 24 Added Buffering the MCLK Signal Section 24 Added MCLK Jitter Requirements Heading 24 Changes to Driving the AD7760 Section 26 Changes to EIgure 5 D tree e eene 26 Added T ue tes 26 Changes to Figure 551 beat rete e es N Dee kk ee ere
2. 2 5V A 0V A 2 5V A 2 5V B 0V B 2 5V 04975 056 Figure 51 Transfer Function for the AD7760 Filtered Output Where Va and Vs are Inputs to the On Board Differential Amplifier A1 3 685V Vint 2 048V 0 410V 3 685V Vin 2 048V 0 410V 04975 055 Figure 52 Differential Amplifier Signal Conditioning Rev A Page 26 of 36 AD1160 To obtain maximum performance from the AD7760 it is advisable to drive the ADC with differential signals Figure 53 shows how a bipolar single ended signal biased around ground can drive the AD7760 with the use of an external op amp such as the AD8021 2R AD8021 I V 04975 042 Figure 53 Single Ended to Differential Conversion The AD7760 employs a double sampling front end as shown in Figure 54 For simplicity only the equivalent input circuit for Vint is shown The equivalent input circuitry for Vm is the same 04975 043 Figure 54 Equivalent Input Circuit Sampling Switches SS1 and SS3 are driven by ICLK whereas Sampling Switches SS2 and SS4 are driven by ICLK When ICLK is high the analog input voltage is connected to CS1 On the falling edge of ICLK the SS1 and SS3 switches open and the analog input is sampled on CS1 Similarly when ICLK is low the analog input voltage is connected to CS2 On the rising edge of ICLK the SS2 and SS4 switches open and the analog input is sampled on CS2 Capacitors CPA CPB1 and CPB2 represent parasiti
3. 87 67dB TONE A 999 75kHz TONE B 1 00025MHz THIRD ORDER IMD 89 15dB AMPLITUDE dB AMPLITUDE dB 04975 024 04975 027 995 997 999 1001 1003 1005 995 997 999 1001 1003 1005 FREQUENCY kHz FREQUENCY kHz Figure 23 Normal Mode IMD 1 MHz Center Frequency 8x Decimation Figure 26 Normal Mode IMD 1 MHz Center Frequency 8x Decimation 100 5 105 100 0 107 99 5 A08 NORMAL MODE 99 0 s 3 S 98 5 111 zZ 9 98 0 11 LOWP MODE 97 5 115 97 0 Ed 8 96 5 117 0 10 20 30 40 0 10 20 30 40 MCLK FREGUENCY MHz MCLK FREQUENCY MHz Figure 24 SNR vs MCLK Frequency 8x Decimation 6 dB 1 kHz Input Tone Figure 27 THD vs MCLK Frequency 8x Decimation 6 dB 1 kHz Input Tone 116 112 a 7 108 LL LL m m H H a m 104 100 0 64 128 192 256 0 64 128 192 256 DECIMATION RATE DECIMATION RATE Figure 25 Normal Mode SNR vs Decimation Rate 1 kHz Input Tone Figure 28 Low Power SNR vs Decimation Rate 1 kHz Input Tone Rev A Page 15 of 36 AD7760 4500 3000 4000 2500 3500 3000 2500 2000 1500 1000 1000 500 3 0 0 OCCURRENCE OCCURRENCE 04975 030 04975 032 8385222 8385238 8385254 8385270 8383530 83835246 8383562 8383578 8383594 8383610 24 BIT CODE 24 BIT CODE Figure 29 Normal Mode 24 Bit Histogram 256x Decimation Figure 32 Low Power 24 Bit Histogram 256x Decimation
4. 600 500 ul ul o o zZz z LL LL ra 4 ra ra 2 2 o o o o e o 200 100 8385016 8385116 8385216 8385316 8385416 8385516 8383236 8383386 8383536 8383686 8383836 24 BIT CODE 24 BIT CODE Figure 30 Normal Mode 24 Bit Histogram 8x Decimation Figure 33 Low Power 24 Bit Histogram 8x Decimation 0 0010 0 0015 85 C 0 0010 0 0005 25 C 0 0008 3 3 d 0 a z z 0 40 C 0 0005 0 0005 i 0 0010 8 0 0010 8 0 4194304 8388608 12582912 16777216 0 4194304 8388608 12582912 16777216 24 BIT CODE 24 BIT CODE Figure 31 24 Bit INL Normal Mode Figure 34 24 Bit INL Low Power Mode Rev A Page 16 of 36 0 6 0 4 0 2 DNL LSB e 04975 035 0 4194304 8388608 12582912 16777216 24 BIT CODE Figure 35 24 Bit DNL T E N Q Q lt 0 2 4 6 8 10 12 14 16 48 20 ICLK FREQUENCY MHz Figure 36 Alpp2 vs ICLK Frequency AVpp2 5 V 60 50 40 T E a 30 D a 20 10 0 3 0 2 4 6 8 10 12 14 16 18 20 ICLK FREQUENCY MHz Figure 37 Decimate x 8 Dlpo vs ICLK Frequency DVop 2 5 V Dipp mA Rev A Page 17 of 36 Dipp mA N a AD7760 04975 059 0 2 4 6 8 10 12 14 16 18 20 ICLK FREQUENCY MHz Figure 38 Decimate x 32 Dlpp vs ICLK Frequency DVpp 2 5 V 04975 060 0 2 4 6 8 10 12 14 16 18 20 ICLK FREQUENCY
5. MHz Figure 39 Decimate x 256 Dlpp vs ICLK Frequency DVpp 2 5 V AD7760 THEORY OF OPERATION The AD7760 employs a Z A conversion technique to convert the analog input into an equivalent digital word The modulator samples the input waveform and outputs an equivalent digital word to the digital filter at a rate equal to ICLK By employing oversampling the quantization noise is spread across a wide bandwidth from 0 to ficix This means that the noise energy contained in the signal band of interest is reduced see Figure 40a To further reduce the quantization noise in the signal band of interest a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the signal band see Figure 40b The digital filtering that follows the modulator removes the large out of band quantization noise see Figure 40c while also reducing the data rate from ficix at the input of the filter to ficix 8 or less at the output of the filter depending on the decimation rate used Digital filtering has certain advantages over analog filtering It does not introduce significant noise or distortion and can be made perfectly linear in terms of phase The AD7760 employs three FIR filters in series By using different a W A of decimation ratio w and bypassing i omt range of data rat it obtained at the ICLK rate see Modulator Data Output Mode section The first filter receives the data from the modul
6. Suitable component values for the first order filter are listed in Table 8 Using the values in the table as an example yields a 10 dB attenuation at the first alias point of 19 MHz 5 040 Cre Fig lifier Con Table 8 Normal Mo e alu Rre Ru VREF Rin Cs Crs 4096V 1kQ 650 180 56pF 33 pF Figure 52 shows the signal conditioning that occurs using the circuit shown in Figure 50 with a 42 5 V input signal biased around ground and the component values and conditions listed in Table 8 The differential amplifier always biases the output 2 5V 2 5V 2 5V 2 5V INPUTS TO THE AD7760 DIFFERENTIAL AMPLIFIER OUTPUTS OF THE AD7760 DIFFERENTIAL AMPLIFIER signal to sit on the optimum common mode of Vrer 2 in this case 2 048 V The signal is also scaled to give the maximum allowable voltage swing with this reference value This is calculated as 80 of Vir that is 0 8 x 4 096 V 3 275 V p p on each input With a 4 096 V reference a 5 V supply must be provided to the reference buffer AV nn4 With a 2 5 V reference a 3 3 V supply must be provided to AVpp4 Figure 51 shows the transfer function in terms of the 24 bit digital output codes twos complement coding of the AD7760 vs the voltage signals V4 and Vs applied to the on board differential amplifier A1 as shown in Figure 52 24 BITS 011 111 011 110 000 010 AD7760 00 001 24 BIT OUTPUT 000 000 B
7. TONE A 999 75kHz TONE B 1 00025MHz 04975 018 L ao U N a AMPLITUDE dB U a e JV A TART 150 i u eie 200 0 250 500 1000 FREQUENCY kHz Figure 18 Normal Mode IMD 1 MHz Center Frequency 8x Decimation TONE A 999 75kHz 04975 019 1250 20 TONE B 1 00025MHz SECOND ORDER IMD 105 6dB LI o o AMPLITUDE dB de o N e 2000 4000 6000 8000 FREQUENCY kHz Figure 19 Normal Mode IMD 1 MHz Center Frequency 8x Decimation MAN l UR RUM gabi WA U 04975 020 10000 1 N e AMPLITUDE dB LI e 0 250 500 750 FREQUENCY kHz TONE A 999 75kHz 25 TONE B 1 00025MHz 75 04975 021 1000 1250 Figure 20 Low Power FFT 1 MHz 6 dB Input Tone 8x Decimation AMPLITUDE dB LI a e 150 175 200 0 250 500 750 FREQUENCY kHz TONE A 999 75kHz 04975 022 1000 1250 Figure 21 Low Power IMD 1 MHz Center Frequency 8x Decimation 20 TONE B 1 00025MHz SECOND ORDER IMD 115 7dB U e o AMPLITUDE dB I eo o N o R Rd rtg 2000 4000 6000 FREGUENCY kHz Rev A Page 14 of 36 04975 023 8000 10000 Figure 22 Low Power IMD 1 MHz Center Frequency 8x Decimation AD1160 TONE A 999 75kHz TONE B 1 00025MHz THIRD ORDER IMD
8. Vin Vin Veer 4 096 V 3 25 V p p Input Capacitance At internal buffer inputs 5 pF typ At modulator inputs 55 pF typ REFERENCE INPUT OUTPUT Veer Input Voltage Vpp3 3 3 V 596 12 5 V max Vpp3 5 V 5 4 096 V max Veer Input DC Leakage Current 6 UA max Veer Input Capacitance 5 pF max POWER DISSIPATION Total Power Dissipation Normal mode 958 mW max Low power mode 661 mW max Standby Mode Clock stopped 6 35 mW max POWER REQUIREMENTS AVoo1 Modulator Supply 5 42 5 V AVop2 General Supply 5 5 V AVoo3 Differential Amplifier Supply 3 15 45 25 V min max AVoo4 Reference Buffer Supply 3 15 5 25 V min max DVoo 5 2 5 V Vorive 1 65 2 7 V min max Normal Mode Alpp1 Modulator mA typ max Alpp2 General mA typ max Alpo4 Ref L AVop4 5 V mA typ max Low Pow m C Q Alpp1 Modulator mA typ max Alop2 General mA typ max Alpp4 Reference Buffer AVpp4 5 V mA typ max Aloo3 Differential Amplifier AVpp3 5 V both modes mA typ max Dlop Both modes mA typ max DIGITAL I O MCLK Input Amplitude 5 V typ Input Capacitance 7 3 pF typ Input Leakage Current 5 HA max Three State Leakage Current D15 DO 5 HA max Vin 0 7 X Vorive V min Vint 0 3 X VDRIVE V max Vou 1 5 Vmin Von 2 4 V typ Vou 0 1 V max 1 See the Terminology section 2 SNR specifications in decibels are referred to a full scale input FS Tested with an input signal at 0 5 dB below full scale unless otherwise specified 3 Current scales wi
9. 0 0 must be written to this bit 9 SYNC Synchronize Setting this bit initiates an internal synchronization routine Setting this bit simultaneously on multiple device YS 8to5 FL rkength Bi t be set when the DL t ilter igidownloaded 4 BY sifilter 3 er 3l programmable FIR is byg 3 BYP F1 Bypass Filter 1 If this bit is 0 Filter 1 is bypassed This should only occur when the user requires unfiltered modulator data to be output 2to0 DEC 2 0 Decimation Rate These bits set the decimation rate of Filter 2 All Os implies that the filter is bypassed A value of 1 corresponds to 2x decimation a value of 2 corresponds to 4x decimation and so on up to the maximum value of 5 corresponding to 32x decimation Bit 15 to Bit 9 are self clearing bits 2 Only one of the bits from Bit 14 to Bit 11 can be set in any write operation because it determines the contents of the next read operation CONTROL REGISTER 2 ADDRESS 0x0002 Default Value After RESET OxOO9B Recommended register setting for power up and normal operation using clock divide by 2 CDIV 0 mode 0x0002 MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO 0 0 0 0 0 0 0 0 0 0 CDIV 0 PD LPWR 1 DIPD Table 16 Bit Descriptions of Control Register 2 Bit Mnemonic Description 5 CDIV Clock Divider Bit This sets the divide ratio of the MCLK signal to produce the internal ICLK Setting CDIV 0 divides the MCL
10. 35 us 3 6 us 562 5 kHz 2 5 MHz 20 MHz 4x 2x 2x Fully filtered 1 625 us 22 8 us 500 kHz 1 25 MHz 20 MHz 4x 4x Bypassed Partially filtered 1 725 us 6 us 281 25 kHz 1 25 MHz 20 MHz 4x 4x 2x Fully filtered 1 775 us 44 4 us 250 kHz 625 kHz 20 MHz 4x 8x Bypassed Partially filtered 2 6 us 10 8 us 140 625 kHz 625 kHz 20 MHz 4x 8x 2x Fully filtered 2 25 us 87 6 us 125 kHz 312 5 kHz 20 MHz 4x 16x Bypassed Partially filtered 4 175 us 20 4 us 70 3125 kHz 312 5 kHz 20 MHz 4x 16x 2x Fully filtered 3 1 us 174 us 62 5 kHz 156 25 kHz 20 MHz 4x 32x Bypassed Partially filtered 7 325 us 39 6 us 35 156 kHz 156 25 kHz 20 MHz 4x 32x 2x Fully filtered 4 65 us 346 8 us 31 25 kHz 78 125 kHz 12 288 MHz 4x 8x 2x Fully filtered 3 66 US 142 6 us 76 8 kHz 192 kHz 12 288 MHz 4x 16x 2x Fully filtered 5 05 us 283 2 us 38 4 kHz 96 kHz 12 288 MHz 4x 32x Bypassed Partially filtered 11 92 us 64 45 us 21 6 kHz 96 kHz 12 288 MHz 4x 32x 2x Fully filtered 7 57 us 564 5 us 19 2 kHz 48 kHz Rev A Page 18 of 36 MODULATOR DATA OUTPUT MODE Operating the AD7760 in modulator output mode enables the output of data directly from the Z A modulator This mode of operation bypasses the AD7760 on board digital filtering capabilities outputting data in its unfiltered form As discussed in the Theory of Operation section the AD7760 operates using oversampling which spreads quantization noise over a wide bandwidth The decrease in the quantization no
11. Pin No Mnemonic Descki 6 33 5V ith ord 4 14 15 27 24 12 7 34 5 13 16 18 28 23 29 31 32 11 9 41 44 63 1 35 42 43 53 62 64 19 20 21 27 25 26 10 8 AVpp2 AVpp3 AVop4 AGND1 AGND2 AGND3 AGND4 REFGND DVDD VDRIVE DGND VinAt ViNA VourA VoutA Vint VIN VREF DECAPA in 34 respectively endations section IGT and Ecom 5 V Power Supply These pins should be decoupled to AGND2 Pin 5 and Pin 13 with 100 nF capacitors on each of Pin 4 Pin 14 and Pin 15 Pin 27 should be connected to Pin 14 via a 15 nH inductor See the Decoupling and Layout Recommendations section for details 3 3 V to 5 V Power Supply for Differential Amplifier This pin should be decoupled to AGND3 Pin 23 with a 100 nF capacitor See the Decoupling and Layout Recommendations section for details 3 3 V to 5 V Power Supply for Reference Buffer This pin should be decoupled to Pin 9 with a 10 nF capacitor in series with a 10 Q resistor Power Supply Ground for Analog Circuitry Powered by AVpp1 Power Supply Ground for Analog Circuitry Powered by AVpp2 Power Supply Ground for Analog Circuitry Powered by AVoo3 Power Supply Ground for Analog Circuitry Powered by AVpp4 Reference Ground Ground connection for the reference voltage 2 5 V Power Supply for Digital Circuitry and FIR Filter This pin should be decoupled to DGND with a 100 nF capacitor Logic P
12. a short user defined filter with 24 taps The frequency response is shown in Figure 58 AMPLITUDE dB 100 200 300 FREQUENCY kHz 500 600 04975 045 Figure 58 24 Tap FIR Frequency Response The coefficients for the filter are listed in Table 12 and are shown from the center of symmetry outwards The raw coefficients were tool an generated usin da Fd ria 67 108 86 Table 12 24 Tap FIR Coefficients Coefficient Raw Scaled 1 0 365481974 53188232 2 0 201339905 29300796 3 0 009636604 1402406 4 0 075708848 11017834 5 0 042856209 6236822 6 0 019944246 2902466 7 0 036437914 5302774 8 0 007592007 1104856 9 0 021556583 3137108 10 0 024888355 3621978 11 0 012379538 1801582 12 0 001905756 277343 FLEN 3 0 Number of Coefficients Filter Length 0000 Default Default 0001 6 12 0011 12 24 0101 18 36 0111 24 48 1001 30 60 1011 36 72 1101 42 84 1111 48 96 Rev A Page 31 of 36 AD7760 Table 13 shows the hexadecimal values in sign and magnitude format that are downloaded to the AD7760 to realize this filter The table is also split into the bytes that are summed to produce the checksum The checksum generated from these coefficients Table 14 lists the 16 bit words the user would write to the AD7760 to set up the ADC and download this filter assuming an output data rate of 1 25 MHz has been
13. all internal digital circuitry and powers down the part Holding this pin low keeps the AD7760 in a reset state 3 MCLK Master Clock Input A low jitter buffered digital clock must be applied to this pin The output data rate depends on the frequency of this clock See the Clocking the AD7760 section for more details 2 MCLKGND Master Clock Ground Sensing Pin 36 SYNC Synchronization Input A falling edge on this pin resets the internal filter This can be used to synchronize multiple devices in a system See the Synchronization section for more details 39 RD WR Read Write Input This pin in conjunction with the chip select pin is used to read and write data to and from the AD7760 If this pin is low when CS is low a read takes place If this pin is high when CS is low a write occurs See the Modulator Data Output Mode and AD7760 Interface sections for more details 38 DRDY Data Ready Output Each time new conversion data is available an active low pulse 2 ICLK period wide is produced on this pin See the Modulator Data Output Mode and AD7760 Interface sections for more details 40 cs Chip Select Input Used in conjunction with the RD WR pin to read and write data from and to the AD7760 See the Modulator Data Output Mode and AD7760 Interface sections for more details wan BDI C com AD Rev A Page 10 of 36 TERMINOLOGY Signal to Noise Ratio SNR SNR is the ratio of the rms value of the actual input signal to the rms sum of all
14. becomes Magnitude 15 0 To ensure that a filter is downloaded correctly a checksum must also be generated and then downloaded following the final coefficient The checksum is a 16 bit word generated by splitting each 32 bit word into four bytes and summing the bytes from all coefficients up to a maximum of 192 bytes 48 coefficients x four bytes The same checksum is generated internally in the AD7760 and compared with the downloaded checksum The DL OK bit in the status register is set if these two checksums agree To download a user filter 1 Write to Control Register 1 setting the DL FILT bit and the correct filter length bits corresponding to the length of the filter to be downloaded see Table 11 2 Write the first half of the current coefficient data 00000 sign bit Magnitude 25 16 e first coeffici to be writ one adja i symm 3 Write the second half of the current coefficient data Magnitude 15 0 4 Repeat Step 2 and Step 3 for each coefficient 5 Write the 16 bit checksum 6 Use the following methods to verify that the filter coefficients are downloaded correctly a Read the status register checking the DL OK bit b Read data and observe the status of the DL_OK bit Note that because the user coefficients are stored in RAM they are cleared after a RESET operation or a loss of power Table 11 Filter Length Values EXAMPLE FILTER DOWNLOAD AD7760 The following is an example of downloading
15. capacitor or a direct connection to the supply but instead is connected to Pin 14 via a 15 nH inductor ADDITIONAL DECOUPLING There are two other decoupling pins on the AD7760 Pin 8 DECAPA and Pin 30 DECAPB Pin 8 should be decoupled with a 100 nF capacitor and Pin 30 requires a 33 pF capacitor REFERENCE VOLTAGE FILTERING A low noise reference source such as the ADR431 2 5 V or ADR434 4 096 V is suitable for use with the AD7760 The reference voltage supplied to the AD7760 should be decoupled and filtered as shown in Figure 56 The recommended scheme for the ref end isa 100 O serie t a 100uFta Or followed by a seri is 10 Q andifina or placed as close as possible to the Vre pin decoupling this capacitor to the associated ground pin Pin 11 U3 TV KO PIN 10 C11 C46 100uF I 04975 047 Figure 56 Reference Connection DIFFERENTIAL AMPLIFIER COMPONENTS The correct components for use around the on chip differential amplifier are detailed in Table 8 Matching the components on both sides of the differential amplifier is important to minimize distortion of the signal applied to the amplifier A tolerance of 0 196 or better is required for these components Symmetrical routing of the tracks on both sides of the differential amplifier also assists in achieving the stated performance BIAS RESISTOR SELECTION The AD7760 requires a resistor to be connected between the Raus and AGND pins The value
16. impedance CLOCK DIVIDE BY 2 MODE CDIV 0 When operating in modulator output mode with CDIV 0 that is ICLK MCLK 2 the frequency of the DRDY signal created is half that of the MCLK frequency input to the device The timing scheme that is used when CDIV 0 depends on the number of MCLK cycles that occur between RESET and SYNC If the number of MCLK cycles n between the rising edge of RESET and the rising edge of SYNC see Figure 44 is an even value use the interface timing shown in Figure 43 If n is an odd value use the interface timing shown in Figure 45 CS RD WR D 0 15 6 INVALID DATA c MOD DATAM MOD DATAM 1 C X wove Figure 43 AD7760 Modulator Output Mode CDIV 1 and CDIV 0 nis even tis 04975 050 ee d n X tyCLK 04975 051 Figure 44 AD7760 Relative Timing Between RESET and SYNC in Modulator Output Mode CDIV 0 Rev A Page 20 of 36 AD1160 DRDY tro L D 0 15 L INVALID DATA L MOD DATA M e MOD DATA M 1 L X wove a ha gt MCLK 11 gt ta 04975 052 Figure 45 AD7760 Modulator Output Mode CDIV 0 n is odd In the case where n is an odd number of MCLK cycles the modulator data output on Pins D 15 0 is output on the rising edge of DRDY In this case the modulator data should be read on the falling edge of MCLK when DRDY is logic low Figure 45 shows timing details to be used when re
17. of their respective owners DO4975 0 8 06 A DEVICES www analo g com Rev A Page 36 of 36
18. of this resistor is dependent on the reference voltage being applied to the device The resistor value should be selected to produce a current of 25 uA through the resistor to ground For a 2 5 V reference voltage the correct resistor value is 100 kQ and for a 4 096 V reference the correct resistor value is 160 kO LAYOUT CONSIDERATIONS While using the correct components is essential to achieve optimum performance the correct layout is just as important The AD7760 product page on the Analog Devices website contains the Gerber files for the AD7760 evaluation board These files should be used as a reference when designing any system using the AD7760 The location and orientation of some of the components mentioned in previous sections of this data sheet are critical and particular attention must be paid to the components that are located close to the AD7760 Locating these components farther away from the device can have a direct impact on the achievable maximum performance ed use of ground planes should also be carefully considered pie at capacitors n with that supply A ground plane should not be relied on as the sole return path for decoupling capacitors because the return current path using ground planes is not easily predictable EXPOSED PADDLE The AD7760 64 lead TOFP employs a 6 mm x 6 mm exposed paddle see Figure 59 The paddle reduces the thermal resistance of the package by providing a path for heat energy to
19. other spectral components below the Nyguist frequency excluding harmonics and dc The value for SNR is expressed in decibels Total Harmonic Distortion THD THD is the ratio of the rms sum of harmonics to the fundamental For the AD7760 it is defined as V V V V2 V THD dB 20 log T 1 where Vi is the rms amplitude of the fundamental V2 Vs Va Vs and Vsare the rms amplitudes of the second to the sixth harmonics Nonharmonic Spurious Free Dynamic Range SFDR SFDR is the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component excluding harmonics Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the ih value for the d ressed Intermodul With inputs Ene te sine waves at two frequencies fa and fb any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb where m n 0 1 2 3 and so on Intermodulation distortion terms are those for which neither m nor n are equal to 0 For example the second order terms include fa fb and fa fb and the third order terms include 2fa fb 2fa fb fa 2fb and fa 2fb The AD7760 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used In this case the second order terms are usually distanced in frequency from the original sine waves a
20. rising edge of SYNC until the DVALID bit is asserted is dependent on the filter configuration used See the Theory of Operation section and the values listed in Table 6 for details on calculating the time until DVALID is asserted Rev A Page 22 of 36 WRITING TO THE AD7760 There are many features and parameters that the user can change by writing to the AD7760 device See the Using the AD7760 section which details the writing seguence needed to initialize the operation of the part The AD7760 has programmable registers that are 16 bits wide This means that two write operations are required to program a register The first write contains the register address and the second write contains the register data An exception is when a user defined filter is being downloaded to the AD7760 This is described in detail in the Downloading a User Defined Filter section The AD7760 Registers section contains the register addresses and details AD1160 Figure 3 shows a write operation to the AD7760 The RD WR line is held high while the CS line is brought low for a minimum of four ICLK periods The register address is latched during this period The CS line is brought high again for a minimum of four ICLK periods before the register data is put onto the data bus If a read operation occurs between the writing of the register address and the register data the register address is cleared and the next write must be the register address This als
21. 2F65 12 2672124 428C5FC 36 128919 401F797 13 1056628 4101F74 37 14 1741563 1A92FB 38 15 1502200 1 16 835960 1 17 1528400 25 18 93626 16DBA 42 45234 BOB2 19 1269502 135EFE 43 114720 1C020 20 411245 6466D 44 102357 18FD5 21 864038 40D2F26 45 52669 CDBD 22 664622 40A242E 46 15559 3CC7 23 434489 6A139 47 1963 7AB The default filter should be sufficient for most applications It is a standard brick wall filter with a symmetrical impulse response The default filter has a length of 96 is nonaliasing and provides 120 dB of attenuation at Nyquist This filter not only performs signal antialiasing but also suppresses out of band quantization noise produced by the analog to digital conversion process Any significant relaxation in the stop band attenuation or transition bandwidth relative to the default filter can result in a failure to meet the SNR specifications The default filter characteristics scale with both the MCLK frequency applied and the decimation rate chosen by the user To create a filter note the following e The filter must be an even symmetrical FIR e The coefficients are in sign and magnitude format with 26 magnitude bits and sign coded as positive 0 e The filter length must be between 12 taps and 96 taps in steps of 12 e Because the filter is symmetrical the number of coefficients that must be downloaded is half the filter length The default
22. 6V 0011 1111 1111 1111 6 r 4 c 3 275V MODULATOR FULL SCALE 80 OF 4 096V Vint 3 6855V 0011 0011 0011 0010 Vin 0 4105V d Vint 2 048V 0000 0000 0000 0000 Vin 2 048V we 1100 1100 1100 1100 l_ ____ _4 Vint 0 4105V 80 OF 4 096V MODULATOR FULL SCALE 3 275V Vin 3 6855V Ed F 1100 0000 0000 0000 L lt l e 04975 049 Figure 42 Modulator Output Data Scaling As the nature of the modulator output is coarse relative to the fully filtered output of the AD7760 due to the associated quantization noise of the modulator output Bits D 3 0 of the modulator data alculations listed modulator pins Vint and Vm show Bits D 3 0 of the modulator output as zero Example 1 Vint 3 5 V Vm 0 595 V Modulator Output Code Vin Vin 4 096 V x 16384 3 5 V 0 595 V 4 096 V x 16384 411620 Direct Scaling 0010 1101 0110 0100 Value Output on Data Output Pins D 15 0 D 15 0 0010 1101 0110 0000 Example 2 Vint 0 595 V Vm 3 5 V Modulator Output Code Vm Vin 4 096 V x 16384 0 595 V 3 5 V 4 096 V x 16384 11620 Direct Scaling 1101 0010 1001 1100 Value Output on Data Output Pins D 15 0 D 15 0 1101 0010 1001 0000 Rev A Page 19 of 36 AD7760 MODULATOR DATA OUTPUT MODE INTERFACE The AD7760 can be configured in modulator data o
23. ANALOG DEVICES 2 5 MSPS 24 Bit 100 dB Sigma Delta ADC with On Chip Buffer AD7760 FEATURES 120 dB dynamic range at 78 kHz output data rate 100 dB dynamic range at 2 5 MHz output data rate 112 dB SNR at 78 kHz output data rate 100 dB SNR at 2 5 MHz output data rate 2 5 MHz maximum fully filtered output word rate Programmable oversampling rate 8x to 256x Fully differential modulator input On chip differential amplifier for signal buffering Low pass finite impulse response FIR filter with default or user programmable coefficients Modulator output mode Overrange alert bit Digital offset and gain correction registers Filter bypass modes Low power and power down modes Synchronization of multiple devices via SYNC pin Vibration analysi Instrument GENERAL DESCRIPTION The AD7760 is a high performance 24 bit 2 A analog to digital converter ADC It combines wide input bandwidth and high speed with the benefits of Z A conversion to achieve a perfor mance of 100 dB SNR at 2 5 MSPS making it ideal for high speed data acquisition Wide dynamic range combined with significantly reduced antialiasing requirements simplify the design process An integrated buffer to drive the reference a differential amplifier for signal buffering and level shifting an overrange flag internal gain and offset registers and a low pass digital FIR filter make the AD7760 a compact highly integrated data acquisition device requiring minimal p
24. C W Lead Temperature Soldering Vapor Phase Infrared 15 se ESD Absolute maximum voltage for Vin Viw and Vina Vinat is 6 0 V or AVpp3 0 3 V whichever is lower Absolute maximum voltage on digital inputs is 3 0 V or DVop 0 3 V whichever is lower 3 Absolute maximum voltage on Vrer input is 6 0 V or AVoo4 0 3 V whichever is lower Transient currents of up to 200 mA do not cause SCR latch up Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION A Alan ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality C com AD Rev A Page 8 of 36 AD1160 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5 Pin Function Descriptions AD7760 TOP VIEW Not to Scale GND3 AGND3 2 az aT 8 T S S S Z
25. FS 120 dBc typ Total Harmonic Distortion THD Input amplitude 0 5 dBFS 105 dB typ Input S ed dBFS 106 dB typ Decimate by 8 C DDR Dynamic R A i 9 dB min K dB typ Signal to Noise Ratio SNR fin 1 kHz input amplitude 0 5 dBF 100 dB typ fin 100 kHz input amplitude 0 5 dBFS 99 dB typ fin 1 MHz input amplitude 0 5 dBFS 98 dB typ Spurious Free Dynamic Range SFDR Nonharmonic fw 100 kHz input amplitude 6 dBFS 120 dBctyp Nonharmonic fin 1 MHz input amplitude 6 dBFS 114 dBc typ Total Harmonic Distortion THD Input amplitude 0 5 dBFS fiy 100 kHz 103 dB typ Input amplitude 6 dBFS fw 100 kHz 102 dB typ IMD Second Order fin A 989 95 kHz fin B 999 95 kHz 115 dB typ IMD Third Order fin A 989 95 kHz fw B 999 95 kHz 89 dB typ DC ACCURACY Resolution 24 Bits Differential Nonlinearity Guaranteed monotonic to 24 bits Integral Nonlinearity 0 00076 Yo typ Zero Error 0 014 Yo typ 0 02 96 max Gain Error 0 016 96 typ Zero Error Drift 0 00001 96 FS C typ Gain Error Drift 0 0002 96 FS C typ DIGITAL FILTER RESPONSE Decimate by 8 Group Delay MCLK 40 MHz 12 us typ Decimate by 32 Group Delay MCLK 40 MHz 47 us typ Decimate by 256 Group Delay MCLK 40 MHz 358 us typ Rev A Page 4 of 36 AD1160 Parameter Test Conditions Comments Specification Unit ANALOG INPUT Differential Input Voltage Vin Vin Vrer 2 5 V 2 V p p
26. K When a user defined filter is in use a checksum is generated when the filter coefficients pass through the filter This generated checksum is compared to the one downloaded If they match this bit is set 5 UFILT If a user defined filter is in use this bit is set 4 BYP F3 Bypass Filter 3 If Filter 3 is bypassed by setting the relevant bit in Control Register 1 this bit is also set 3 BYP F1 Bypass Filter 1 If Filter 1 is bypassed by setting the relevant bit in Control Register 1 this bit is also set 2to0 DEC 2 0 Decimation Rate These bits correspond to the bits set in Control Register 1 OFFSET REGISTER ADDRESS 0x0003 Non bit mapped Default Value 0x0000 The offset regis e such that OX7FFRX 1 imum negative value espond t 0 78125 respectively Offset correction is applied era any gain correction Using the default gain value of 1 25 and assuming a reference voltage of 4 096 V the offset correction range is approximately 25 mV GAIN REGISTER ADDRESS 0x0004 Non bit mapped Default Value OxA000 The gain register is scaled such that 0x8000 corresponds to a gain of 1 0 The default value of this register is 1 25 0xA000 This results in a full scale digital output when the input is at 80 of Vren tying in with the maximum analog input range of 80 of VREF p p OVERRANGE REGISTER ADDRESS 0x0005 Non bit mapped Default Value OxCCCC The ove om ith t output of the first LET in fload iffdication wit
27. K by 2 If CDIV 1 the ICLK frequency is equal to the MCLK 3 PD Power Down Setting this bit powers down the AD7760 reducing the power consumption to 6 35 mW 2 LPWR Low Power If this bit is set the AD7760 is operating in a low power mode The power consumption is reduced for a 6 dB reduction in noise performance 1 1 Write 1 to this bit 0 D1PD Differential Amplifier Power Down Setting this bit powers down the on chip differential amplifier Rev A Page 33 of 36 AD7760 STATUS REGISTER READ ONLY MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO PART1 PARTO DIE2 DIE1 DIEO O LPWR OVR DL_OK FILTOK UFILT BYP F3 BYP F1 DEC2 DEC1 DECO Table 17 Bit Descriptions of Status Register Bit Mnemonic Comment 15 14 PART 1 0 Part Number These bits are constant for the AD7760 13to 11 DIE 2 0 Die Number These bits reflect the current AD7760 die number for identification purposes within a system 10 0 This bit is set to 0 9 LPWR Low Power If the AD7760 is operating in low power mode this bit is set to 1 8 OVR If the current analog input exceeds the current overrange threshold this bit is set 7 DL OK When downloading a user filter to the AD7760 a checksum is generated This checksum is compared to the one downloaded following the coefficients If these checksums agree this bit is set 6 FILTO
28. NCY Hz Figure 7 Normal Mode FFT 1 kHz 60 dB Input Tone 256x Decimation Figure 10 Low Power FFT 1 kHz 60 dB Input Tone 256x Decimation Rev A Page 12 of 36 AD1160 0 0 25 25 50 50 8 75 75 ul ul a a 2 100 2 100 a a a a 125 125 lt lt 175 8 175 S 200 S 200 0 250 500 750 1000 1250 0 250 500 750 1000 1250 FREQUENCY kHz FREQUENCY kHz Figure 11 Normal Mode FFT 100 kHz 0 5 dB Input Tone 8x Decimation Figure 14 Low Power FFT 100 kHz 0 5 dB Input Tone 8x Decimation a W Q 2 E mI a lt 1250 FREQUENCY kHz FREQUENCY kHz Figure 12 Normal Mode FFT 100 kHz 6 dB Input Tone 8x Decimation Figure 15 Low Power FFT 100 kHz 6 dB Input Tone 8x Decimation 0 25 50 g 75 LI LI 5 8 100 E ET mI m 125 lt X 150 B 175 i 200 0 250 500 750 1000 1250 0 250 500 750 1000 1250 FREQUENCY kHz FREQUENCY kHz Figure 13 Normal Mode FFT 1 MHz 0 5 dB Input Tone 8x Decimation Figure 16 Low Power FFT 1 MHz 0 5 dB Input Tone 8x Decimation Rev A Page 13 of 36 AD7760 AMPLITUDE dB U a e 125 150 175 fi 200 0 250 500 750 1000 FREQUENCY kHz Figure 17 Normal Mode FFT 1 MHz 6 dB Input Tone 8x Decimation
29. ading the modulator output data where CDIV 0 and there is an odd number of MCLK cycles between the rising edge of RESET and the rising edge of SYNC The edge of MCLK that should be used under these conditions is illustrated in Figure 45 by arrows on the MCLK falling edges in question USING T INMODULATORO 0 The following is the recommended sequence for powering up and using the AD7760 1 Apply power 2 Start the clock oscillator applying MCLK 3 Take RESET low for a minimum of one MCLK cycle 4 Wait a minimum of two MCLK cycles after the rising edge of RESET 5 Write to Control Register 2 to power up the ADC and the differential amplifier as required The correct clock divider CDIV ratio should be programmed at this time 6 Write to Control Register 1 to set the bypass filter bits BYP F1 and BYP F3 and the decimation rate bits DEC 2 0 to 0 7 Wait a minimum of six MCLK cycles after the rising edge of CS has been released 8 Take SYNC low for equi Usin er D between n rising edge S RESET and the rising edge of SYNC Therefore when using this sequence with CDIV 0 the interface CLK cycles if timing shown in Figure 43 should be implemented Note that whether the number of MCLK cycles between the rising edge of RESET and SYNC is odd or even is irrelevant when the AD7760 is operated with CDIV 1 When using the AD7760 in modulator output mode the offset gain and overrang
30. alling edge while DRDY is logic low t20 19 ns min Data valid after MCLK falling edge while DRDY is logic low 1 tiak ic When ICLK MCLK DRDY pulse width depends on the mark space ratio of applied MCLK 3 Valid when using the modulator output mode with CDIV 1 See the Modulator Data Output Mode section for timing diagrams 5 Valid when using the modulator output mode with CDIV 0 Rev A Page 6 of 36 AD1160 TIMING DIAGRAMS 04975 002 D 0 15 DATA MSW LSW STATUS Figure 2 Filtered Output Parallel Interface Timing Diagram RD WR tis D 0 15 REGISTER ADDRESS REGISTER DATA Figure 3 AD7760 Register Write wan BDI C com AD 04975 004 Rev A Page 7 of 36 AD7760 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 4 Parameters Rating AVoo1 to GND 0 3 V to 3 V AVpp2 AVpp4 to GND 0 3V to 6 V DVoo to GND 0 3 V to 3 V Vorive to GND 0 3 V to 3 V Vin Vin to GND 0 3V to 6 V VinA VNA to GND 0 3V to 46V Digital Input Voltage to GND 0 3 V to DVoo 0 3 V MCLK to MCLKGND 0 3V to 6 V Vrer to GND 0 3 V to AVpp4 0 3 V AGND to DGND 0 3V to 40 3 V Input Current to Any Pin Except 10 mA Supplies Operating Temperature Range Commercial 40 C to 85 C Storage Temperature Range 65 C to 150 C Junction Temperature 150 C TOFP Exposed Paddle Package Osa Thermal Impedance 92 7 C W Osc Thermal Impedance 5 1
31. ator at a maximum frequency of 20 MHz and decimates it by 4 to output the data at 5 MHz The partially filtered data can be output at this stage The second filter allows the decimation rate to be chosen from 2x to 32x or to be completely bypassed Table 6 Configuration with Default Filter The third filter has a fixed decimation rate of 2x is user programmable and has a default configuration It is described in detail in the Programmable FIR Filter section This filter can also be bypassed Table 6 shows some characteristics of the default filter The group delay of the filter is defined to be the delay to the center of the impulse response and is equal to the computation plus the filter delays The delay until valid data is available the DVALID status bit is set is equal to twice the filter delay plus the computation delay a QUANTIZATION NOISE f 2 ICLK BAND OF INTEREST b NOISE SHAPING ficu x2 BAND OF INTEREST DIGITAL FILTER CUTOFF FREQUENCY e a ficu x2 a e BAND OF INTEREST Figure 40 S AADC 04975 037 ICLK Computation Pass Band Output Data Frequency Filter 1 Filter 2 Filter 3 Data State Delay Filter Delay Bandwidth Rate ODR 20 MHz Bypassed Bypassed Bypassed Unfiltered 0 0 10 MHz 20 MHz 20 MHz 4x Bypassed Bypassed Partially filtered 0 325 us 1 2 US 1 35 MHZ 5 MHz 20 MHz 4x Bypassed 2x Fully filtered 1 075 us 10 8 us 1MHz 2 5 MHz 20 MHz 4x 2x Bypassed Partially filtered 1
32. ause the new result overwrites the contents of the output register If a DRDY pulse occurs during a read operation the data read is invalid READING STATUS AND OTHER REGISTERS The AD7760 features a number of programmable registers To read back the contents of these registers or the status register the user must first write to the control register of the device setting a bit that corresponds to the register to be read The next read operation outputs the contents of the selected register instead of a conversion result The AD7760 Registers section provides more information on the relevant bits in the control register SHARING THE PARALLEL BUS By its nature the high accuracy of the AD7760 makes it sensitive to external noise sources These include digital activity on the parallel bus For this reason it is recommended that the AD7760 data lines be isolated from the system data bus by means of a latch or buffer to ensure all digital activity on the DO to D15 pins is controlled by the AD7760 If multiple synchronized AD7760 parts that share a properly distributed common MCLK signal exist in a system these parts can share a common bus without being isolated from each other This bus can then be isolated from the system bus by a single latch or buffer SYNCHRONIZATION The SYNC input to the AD7760 provides a synchronization function that allows the user to begin gathering samples of the analog front end input from a known poi
33. c capacitances that include the junction capacitances associated with the MOS switches Table 9 Equivalent Component Values Mode CS1 pF CS2 pF CPA pF CPB1 2 pF Normal 51 51 12 20 Low Power 13 13 12 5 USING THE AD7760 The following is the recommended sequence for powering up and using the AD7760 1 Apply power 2 Startthe clock oscillator applying MCLK 3 Take RESET low for a minimum of one MCLK cycle 4 Waita minimum of two MCLK cycles after RESET has been released 5 Write to Control Register 2 to power up the ADC and the differential amplifier as required The correct clock divider CDIV ratio should be programmed at this time 6 Write to Control Register 1 to set the output data rate 7 Wait a minimum of five MCLK cycles after CS has been released 8 Take SYNC low for a minimum of four MCLK cycles if required to synchronize multiple parts Data can then be read from the part using the default filter es The conversion e gromp delay of the filter Athe DVALID bit read with indeed valid offset gain and overrangethreshe dat i vali has ze the The user can then download a different filter if reguired see the Downloading a User Defined Filter section Values for gain offset and overrange threshold registers can be written or read at this stage Rev A Page 27 of 36 AD7760 DECOUPLING AND LAYOUT RECOMMENDATIONS Due to the high performance na
34. ce KEER Ee uae ee 18 Modulator Data Modulator Inp ts SS Modulator Data Output Scaling sss 19 Modulator Data Output Mode Interface s 20 Clock Divide by 1 Mode CDIV 1 use 20 Clock Divide by 2 Mode CDIV 0 ee 20 Using the AD7760 in Modulator Output Mode 21 AD7760 Interfaces eae eii Pa HEP sessyasaessovsassossvesoyete 22 Reading Data sesse sesse see se ee ee ee ee Re Re ee ee tenentes 22 Reading Status and Other Registers sss 22 Sharing the Parallel Bus see 22 Synchronizationc eee en EEG 22 Writing to the AD7760 uses sesse se see see ee ee ee ee ee ee enne 23 Clocking the AD7760 ees ee se ese a ek ee Re R 24 Buffering the MCLK signal seen 24 MCLE Jitter Requirements esee 24 DAVID the AD DU ee RR 26 Using the AD7700 ete E RHET 27 Decoupling and Layout Recommendations 28 Supply Decou pling eoe eene eee Nee gee 29 Additional Decoupling eee 29 Reference Voltage Filtering een 29 Differential Amplifier Components sss 29 Bias Resistor Selection oci eerte ier 29 Layout Considerations eerte 29 Exposed Paddle e doen ede Example Filter Download s 31 AD7760 Register M 33 Control Register 1 Address 0x0001
35. de tectus 28 Changes to Figure 56 eee RR Ue pen 29 Added Exposed Paddle Section sss 29 Change to Control Register 2 Address 0x0002 Section 33 Changes to Status Register Read Only Section 34 7 05 Revision 0 Initial Version wan BDI C com AD Rev A Page 3 of 36 AD7760 SPECIFIGATIONS AV ppl DVpp VDRIVE 2 5 V AV pp2 AV pp3 AV pp4 5 V Vrer 4 096 V MCLK amplitude 5 V TA 25 C normal mode using the on chip amplifier with components as shown in Table 8 unless otherwise noted Table 2 Parameter Test Conditions Comments Specification Unit DYNAMIC PERFORMANCE Decimate by 256 MCLK 40 MHz ODR 78 kHz fin 1 kHz Dynamic Range Modulator inputs shorted 119 dB min 120 5 dB typ Signal to Noise Ratio SNR Input amplitude 0 5 dBFS 112 dB typ Input amplitude 2 60 dBFS 59 dB typ Spurious Free Dynamic Range SFDR Nonharmonic input amplitude 6 dBFS 126 dBc typ Input amplitude 60 dBFS 77 dBc typ Total Harmonic Distortion THD Input amplitude 0 5 dBFS 105 dB typ Input amplitude 6 dBFS 106 dB typ Input amplitude 2 60 dBFS 75 dB typ Decimate by 32 MCLK 40 MHz ODR 625 kHz fw 2100 kHz Dynamic Range Modulator inputs shorted 108 dB min 109 5 dB typ Signal to Noise Ratio SNR Input amplitude 0 5 dBFS 107 dB typ Spurious Free Dynamic Range SFDR Nonharmonic input amplitude 6 dB
36. e change in the actual gain error value due to a temperature change of 1 C It is expressed as a percentage of full scale at room temperature Rev A Page 11 of 36 AD7760 TYPIGAL PERFORMANCE CHARACTERISTICS AV pp1 DVpp Vpavg 2 5 V AV pp2 AV pp3 AV pp4 5 V Varr 4 096 V Ta 25 C normal mode unless otherwise noted All FFTs are generated from 65 536 samples using a 7 term Blackman Harris window AMPLITUDE dB AMPLITUDE dB 04975 006 04975 009 0 4000 8000 12000 16000 20000 24000 0 4000 8000 12000 16000 20000 24000 FREQUENCY Hz FREQUENCY Hz Figure 5 Normal Mode FFT 1 kHz 0 5 dB Input Tone 256x Decimation Figure 8 Low Power FFT 1 kHz 0 5 dB Input Tone 256x Decimation a u S 5 2 5 amp E a II veil Lt ti dade Lu dh ML ad added ahii E 3 3 S 0 4000 8000 12000 16000 20000 24000 0 4000 8000 12000 16000 20000 24000 FREQUENCY Hz FREQUENCY Hz Figure 6 Normal Mode FFT 1 kHz 6 dB Input Tone 256x Decimation Figure 9 Low Power FFT 1 kHz 6 dB Input Tone 256x Decimation 0 25 50 2o75 ka 8 3 P 100 E i i 2 125 150 175 8 E 2 2 200 0 4000 8000 12000 16000 20000 24000 0 4000 8000 12000 16000 20000 24000 FREQUENCY Hz FREQUE
37. e registers are not operational The only registers that can be used are Control Register 1 and Control Register 2 Rev A Page 21 of 36 AD7760 AD7760 INTERFACE READING DATA When the AD7760 is outputting data at a 5 MHz output data rate or less the interface operates in a conventional mode as shown in Figure 2 using a 16 bit bidirectional parallel interface This interface is controlled by the RD WR and CS pins The 24 bit conversion data is output in twos complement format When a new conversion result is available an active low pulse is output on the DRDY pin To read a conversion result from the AD7760 two 16 bit read operations are performed The DRDY pulse indicates that a new conversion result is available Both RD WR and CS go low to perform the first read operation Shortly after both lines go low the data bus becomes active and the 16 most significant bits MSBs of the conversion result are output The RD WR and CS lines must return high for a full ICLK period before the second read is performed This second read contains the eight least significant bits LSBs of the conversion result along with six status bits These status bits are shown in Table 7 Descriptions of the other status bits are found in Table 17 Table 7 Status Bits During Data Read MSB D7 D6 DVALID OVR to a high impedance state Both read operations must be completed before a new conversion result is available bec
38. eripheral component selection In addition the device offers programmable decimation rates and the digital FIR filter can be adjusted if the default characteristics are not appropriate for the application The AD7760 is ideal for applications demanding high SNR without a complex front end signal processing design APPLICATIONS Data acquisition systems The differential input is sampled at up to 40 MSPS by an analog modulator The modulator output is processed by a series of low pass filters with the final filter having default or user programmable Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM Vin Vint MULTIBIT Z A MODULATOR RECONSTRUCTION PROGRAMMABLE DECIMATION CONTROL LOGIC VO OFFSET AND GAIN REGISTERS FIR FILTER ENGINE 04975 001 CS RD WR DRDY DBO TO DB15 Figure 1 con coefficients The sample rate filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of t
39. filter coefficients exemplify this with only 48 coefficients listed for a 96 tap filter e Coefficients are written from the center of the impulse response adjacent to the point of symmetry outwards e The coefficients are scaled so that the in band gain of the filter is equal to 134 217 726 with the coefficients rounded to the nearest integer For a low pass filter this is the equivalent of having the coefficients summed arithmetically including sign to a 67 108 863 Ox3FF FFFF positive value over the half impulse response coefficient set a maximum of 48 coefficients Anyadeyiatieggfrom this 0 1dB FREQUENCY 1 004MHz 20 3dB FREQUENCY 1 06MHz STOP BAND 1 25MHz 60 80 AMPLITUDE dB U S e 120 140 160 0 500 1000 1500 2000 2500 FREQUENCY kHz Figure 57 Default Filter Frequency Response 2 5 MHz ODR 04975 044 The procedure for downloading a user defined filter is detailed in the Downloading a User Defined Filter section Rev A Page 30 of 36 DOWNLOADING A USER DEFINED FILTER As previously mentioned the filter coefficients are 27 bits in length one sign and 26 magnitude bits Because the AD7760 has a 16 bit parallel bus the coefficients are padded with 5 MSB Os to generate a 32 bit word split into two 16 bit words for downloading The first 16 bit word for each coefficient becomes 00000 sign bit Magnitude 25 16 whereas the second word
40. flow between the package and the PCB and in turn increases the heat transfer efficiency from the AD7760 package Connecting the exposed paddle to the AGND plane of the PCB is essential in creating the conditions that allow the AD7760 package to perform to the highest specifications possible The exposed paddle should not be connected directly to any of the ground pins on the AD7760 and should only be connected to the analog ground plane Best practice is to use multiple vias connecting the exposed paddle to the AGND plane of the PCB Rev A Page 29 of 36 AD7760 PROGRAMMABLE FIR FILTER As previously mentioned the third FIR filter on the AD7760 is user programmable The default coefficients that are loaded upon reset are given in Table 10 and the frequency responses are shown in Figure 57 The frequencies quoted in Figure 57 scale directly with the output data rate Table 10 Default Filter Coefficients Dec Hex Dec Hex No Value Value No Value Value 0 53656736 332BCA0 24 700847 AB1AF 1 25142688 17FA5A0 25 70922 401150A 2 4497814 444A196 26 583959 408E917 3 11935847 4B62067 27 175934 402AF3E 4 1313841 4140C31 28 388667 5EE3B 5 6976334 6A734E 29 294000 47C70 6 3268059 31DDDB 30 183250 402CBD2 7 3794610 439E6B2 31 302597 4049E05 8 3747402 4392E4A 32 16034 3EA2 9 1509849 1709D9 33 238315 3A2EB 10 3428088 344EF8 34 88266 158CA 11 80255 1397F 35 143205 402
41. h delay Thi orafty gain scaling or ind adjustment The default value is OxCCCC which corresponds to 8096 of Vrer the maximum permitted analog input voltage Assuming Vrer 4 096 V the bit is then set when the input voltage exceeds approximately 6 55 V p p differential Once the overrange bit is set the DVALID bit in the status bits of the AD7760 ouptut is set to zero providing another indication that an input overrange has occurred Note that the overrange bit is set immediately if the analog input voltage exceeds 10096 of Vrer for more than four consecutive samples at the modulator rate Rev A Page 34 of 36 AD1160 OUTLINE DIMENSIONS TOP VIEW EXPOSED PAD PINS DOWN BOTTOM VIEW PINS UP Ost 24 0 BS LEAD PITCH i VIEW A i ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS 026 ACD HD Figure 59 64 Lead Thin Quad Flat Package Exposed Pad TQFP_EP SV 64 2 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD7760BSVZ 40 C to 85 C 64 Lead Thin Quad Flat Package Exposed Pad TQFP_EP SV 64 2 AD7760BSVZ REEL 40 C to 485 Lead Thi ad Flat Package Exposed Pad TOFP EP SV 64 2 EVAL AD7760E valuatiom Boar 1Z Pb free p Rev A Page 35 of 36 AD7760 NOTES wan BOM C com AD 2006 Analog Devices Inc All rights reserved Trademarks and AN ALOG registered trademarks are the property
42. he AD7760 The reference voltage supplied to the AD7760 determines the analog input range With a 4 V reference the analog input range is 3 2 V differential biased around a common mode of 2 V This common mode biasing can be achieved using the on chip differential amplifier further reducing the external signal conditioning requirements The AD7760 is available in an exposed paddle 64 lead TQFP and is specified over the industrial temperature range from 40 C to 85 C Table 1 Related Devices Part No Description AD7762 24 bit 625 kSPS 109 dB Z A parallel interface AD7763 24 bit 625 kSPS 109 dB 2 A serial interface One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 Analog Devices Inc All rights reserved AD7760 TABLE OF CONTENTS Features ss ie EE ka AG et seven 1 Applications AE RE RUD Rx 1 Functional Block Diagram serene 1 General Description see ee ee ek ek ee ee ee ee ee ee ee ee ee 1 REVISION HistOEy sesse osse ske ses ese ete tte ettet ese rra 3 Specifications ES ER sehe IE RO EE EE DE 4 Timing Specifications ee RR 6 Timing Diagrams eet iiti eiie eite 7 Absolute Maximum Ratings sees 8 ESD Caution EE N EE EE HE os 8 Pin Configuration and Function Descriptions 9 UR onako to ore EE pne tenete oett ed 11 Typical Performance Characteristics sees 12 Theory of Operation iss ss en
43. is recommended that the MCLK signal applied to the AD7760 has a 50 50 mark space ratio Whenoperatingsinse divide by 1 mo 1usin ratios reduces th applied to the AD7760 yielding maximum performance For example using a mark space ratio of 60 40 with CDIV 1 reduces the maximum MCLK frequency that will yield the maximum INL and THD performance to 16 MHz BUFFERING THE MCLK SIGNAL The MCLK signal for the AD7760 must be buffered before being input to the MCLK pin on the AD7760 device This can be done simply by routing the MCLK signal to both inputs of an AND gate see Figure 47 The recommended buffer is the NC7SZ08M5 which is a two input AND gate from Fairchild Semiconductor Using the buffer with a supply voltage of 5 V is advised to achieve optimum performance from the AD7760 AD7760 NC7SZ08M5 AND GATE 04975 054 Figure 47 Buffering the MCLK Signal Using the NC7SZ08M5 AND Gate Hz input to it i me 2 O MCLK JITTER REOUIREMENTS The MCLK jitter reguirements depend on a number of factors and are given by OSR t Tina SNR dB 2XAX fi D where OSR oversampling ratio fictx ODR fw maximum input frequency SNR dB target SNR Example 1 This example can be taken from Table 6 where ODR 2 5 MHz fictx 20 MHz fix max 1 MHz SNR 108 dB V8 1 79 ps ems 3x nx106x10 P This is the maximum allowable clock jitter for a full scale Take a sec
44. ise energy in the resulting signal band is illustrated in Figure 40a By coupling the use of oversampling with the use of a high order multibit Z A modulator the AD7760 further reduces the quantization noise in the signal band Figure 41 is an FFT of unfiltered data output from the AD7760 when it is used in modulator output mode This clearly demonstrates the shaping of the quantization noise performed by the AD7760 s Z A modulator MODULATOR INPUTS The maximum voltage input to each differential modulator input pin is 0 8 x 4 096 V 3 275 V 80 of Vrer which must sit on a common mode of Vrrr 2 This maximum differential input voltage is shown as the conditioned output of the AD7760 s on board differential amplifier in Figure 52 in the Driving the AD7760 section external circuitry that accompanies it is described in the Driving the AD7760 section AMPLITUDE dB 04975 048 FREQUENCY MHz Figure 41 FFT of Data Output by the AD7760 in Modulator Output Mode MODULATOR DATA OUTPUT SCALING In modulator output mode data is output in a 16 bit twos complement format on Pins D 15 0 however this data is AD7760 scaled to 15 bits The transfer function in Figure 42 shows the scaling involved for the 16 data bits output from Modulator Pins D 15 0 vs the maximum differential voltage input allowed for the modulator inputs Vin and Vin D 15 0 A 4 09
45. nd the third order terms are usually at a frequency close to the input frequencies As a result the second and third order terms are specified separately The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels AD7760 Integral Nonlinearity INL INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function Differential Nonlinearity DNL DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC Zero Error Zero error is the difference between the ideal midscale input voltage when both inputs are shorted together and the actual voltage producing the midscale output code Zero Error Drift Zero error drift is the change in the actual zero error value due to a temperature change of 1 C It is expressed as a percentage of full scale at room temperature Gain Error The first transition from 100 000 to 100 001 should occur for an analog voltage LSB above the nominal negative full scale The last transition from 011 110 to 011 111 should occur for an analog voltage 1 LSB below the nominal full scale a gain error is the deviation of the difference betwe tual level of the lastitra E P roihi evel Gain Error Drift Gain error drift is th
46. nt in time The SYNC function allows multiple AD7760s operated from the same MCLK RESET and SYNC signals to be synchronized so that each ADC simultaneously updates its output register The distribution of the signals that are common to each of the devices that are to be synchronized is extremely important in ensuring that the timing of each of the AD7760 devices is correct that is that each AD7760 device sees the same digital edges synchronously The SYNC signal is sensed on the falling edge of MCLK On the first falling edge of MCLK after SYNC goes logic low the digital filter sequencer is reset to 0 The filter is held in a reset state until a falling e signal signal with respect to MCLK DEVICE SYNCHRONIZED FROM THIS POINT IN TIME LI MIN SYNC LOGIC LOW 4 lt SYNC A tk 4 4 A E 3 Figure 46 Recommended SYNC Timing The rising edge of SYNC should be coincident with the rising edge of MCLK Thus the next falling edge of MCLK senses SYNC logic high and takes the filter out of its reset state By applying this signal scheme to multiple ADCs using the same MCLK and SYNC signals all of the devices will gather input samples synchronously Following a SYNC signal the digital filter needs time to settle before valid data can be read from the AD7760 The DVALID status bit D7 in Table 7 output with each conversion indicates when valid data is being output by the converter The time from the
47. o provides a method to revert back to a known situation if the user forgets whether the next write is an address or data Generally the AD7760 is written to and configured on power up and very infrequently if at all after that Following any write operation the full group delay of the filter must elapse before valid data is output from the AD7760 wan BDI C com AD Rev A Page 23 of 36 AD7760 CLOCKING THE AD7760 The AD7760 requires an external low jitter clock source This signal is applied to the MCLK pin and the MCLKGND pin is used to sense the ground from the clock source An internal clock signal ICLK is derived from the MCLK input signal The ICLK controls all internal operations of the AD7760 The maximum ICLK frequency is 20 MHz but due to an internal clock divider a range of MCLK frequencies can be used There are two ways to generate the ICLK ICLK MCLK CDIV 1 ICLK MCLK 2 CDIV 0 These options are selected from the control register see the AD7760 Registers section for more details On power up the default is ICLK MCLK 2 to ensure that the part can handle the maximum MCLK frequency of 40 MHz For output data rates equal to those used in audio systems a 12 288 MHz ICLK frequency can be used As shown in Table 6 output data rates of 192 kHz 96 kHz and 48 kHz are achievable with this ICLK frequency As mentioned previously this ICLK frequency can be derived from different MCLK frequencies It
48. ond example front Table 6 where ODR 48 kHz fax 12 288 MHz fix max 19 2 kHz SNR 120 dB N 256 t jm 2x x 19 2 10 x 10 133 ps The input amplitude also has an effect on these jitter figures For example if the input level was 3 dB below full scale the allowable jitter would be increased by a factor of V2 increasing the first example to 2 53 ps rms This happens when the maximum slew rate is decreased by a reduction in amplitude Figure 48 and Figure 49 illustrate this point showing the maximum slew rate of a sine wave of the same frequency but with different amplitudes Rev A Page 24 of 36 AD1160 1 0 0 5 N f 0 0 5 0 5 1 0 2 1 0 2 Figure 48 Maximum Slew Rate of Sine Wave with Amplitude of 2 V p p Figure 49 Maximum Slew Rate of Sine Wave with the Same Frequency as in Figure 48 with Amplitude of 1 V p p wan BDI C com AD Rev A Page 25 of 36 AD7760 DRIVING THE AD7760 The AD7760 has an on chip differential amplifier that operates with a supply voltage AVpp3 within the 3 15 V to 5 25 V range For a 4 096 V reference the supply voltage must be 5 V To achieve the specified performance in normal mode the differential amplifier should be configured as a first order antialias filter as shown in Figure 50 Any additional filtering should be carried out in previous stages using low noise high performance op amps such as the AD8021
49. ower Supply Input 1 8 V to 2 5 V The voltage supplied at these pins determines the operating voltage of the logic interface Both of these pins must be connected together and tied to the same supply Each pin should also be decoupled to DGND with a 100 nF capacitor Ground Reference for Digital Circuitry Positive Input to Differential Amplifier Negative Input to Differential Amplifier Negative Output from Differential Amplifier Positive Output from Differential Amplifier Positive Input to the Modulator Negative Input to the Modulator Reference Input The input range of this pin is determined by the reference buffer supply voltage AVpp4 See the Reference Voltage Filtering section for more details Decoupling Pin A 100 nF capacitor must be inserted between this pin and AGND Rev A Page 9 of 36 AD7760 Pin No Mnemonic Description 30 DECAPB Decoupling Pin A 33 pF capacitor must be inserted between this pin and AGND3 17 Reias Bias Current Setting Pin A resistor must be inserted between this pin and AGND For more details see the Bias Resistor Selection section 45 to 52 DB15 DB8 16 Bit Bidirectional Data Bus These are three state pins that are controlled by the CS pin and the RD WR 54 to 61 DB7 DBO pin The operating voltage for these pins is determined by the Vonve voltage See the Modulator Data Output Mode and AD7760 Interface sections for more details 37 RESET Afalling edge on this pin resets
50. range threshold registers Writing to these registers involves writing the register address first then a 16 bit data word Register addresses details of individual bits and default values are given in this section CONTROL REGISTER 1 ADDRESS 0x0001 Default Value 0x001A MSB LSB D15 D14 D13 D12 D11 D10 DI D8 D7 D6 D5 D4 D3 D2 D1 DO DL_ RD RD RD RD 0 SYNC FLEN3 FLEN2 FLEN1 FLENO BYP F3 BYP F1 DEC2 DEC1 DECO FILT OVR GAIN OFF STAT Table 15 Bit Descriptions of Control Register 1 Bit Mnemonic Description 15 DL FILT Download Filter Before downloading a user defined filter this bit must be set The filter length bits must also be set at this time The write operations that follow are interpreted as the user coefficients for the FIR filter until all the coefficients and the checksum have been written 14 RD OVR Read Overrange If this bit has been set the next read operation outputs the contents of the overrange threshold register instead of a conversion result 13 RD GAIN Read Gain If this bit has been set the next read operation outputs the contents of the digital gain register 12 RD OFF Read Offset If this bit has been set the next read operation outputs the contents of the digital offset register 11 RD STAT Read Status If this bit has been set the next read operation outputs the contents of the status register 10
51. selected Table 14 Sequence of Write Instructions to Set Up Device is Ox0E6B and Download the Filter Example Table 13 Filter Hexadecimal Values Word Description Word 1 Word 2 0x0001 Address of Control Register 1 Coefficient Byte 1 Byte 2 Byte3 Byte4 0x8079 Control register data DL filter set filter length 24 1 03 2B 96 88 set output data rate 1 25 MHz 2 01 BF 18 3C 0x032B First coefficient Word 1 3 00 15 66 26 0x9688 First coefficient Word 2 4 04 A8 1E 6A 0x01BF Second coefficient Word 1 5 04 5F 2A 96 0x183C Second coefficient Word 2 6 00 2C 49 C2 ss Other coefficients 7 00 50 E9 F6 0x0404 Twelfth final coefficient Word 1 8 00 10 DB D8 Ox3B5F Final coefficient Word 2 9 04 2F DE 54 OXOEGB Checksum Wait 0 5 x tiak x number of unused 10 04 37 44 SA coefficients for AD7760 to write Os to the remaining 11 04 1B 7D 6E unused coefficients 12 04 04 3B SE 0x0001 Address of control register 0x0879 Control register data Set read status and maintain filter length and decimation settings Read contents of status register Check Bit 7 DL OK to determine if the filter was downloaded correctly wan BDI C comi AD Rev A Page 32 of 36 AD7760 AD7760 REGISTERS The AD7760 has a number of user programmable registers The control registers are used to set the decimation rate the filter configuration the clock divider and so on There are also digital gain offset and over
52. th ICLK frequency See the Typical Performance Characteristics section Although the AD7760 can function with an MCLK amplitude of less than 5 V this is the recommended amplitude to achieve the performance as stated 5 Tested using the minimum Vorwe voltage of 1 65 V with a 400 pA load current 6 Tested using Vorive 2 5 V with a 400 pA load current Rev A Page 5 of 36 AD7760 TIMING SPECIFICATIONS AV ppl DVpp Vorive 2 5 V AV pp2 AV pp3 AV pp4 5 V Ta 25 C normal mode unless otherwise noted Table 3 Parameter Limit at Tmin Tmax Unit Description fMcLK 1 MHz min Applied master clock freguency 40 MHZ max ficuk 500 kHz min Internal modulator clock derived from MCLK 20 MHZ max ti 0 5 x tiak typ DRDY pulse width t 10 ns min DRDY falling edge to CS falling edge ts 3 ns min RD WR setup time to CS falling edge ta 0 5 x tak 16 ns max Data access time ts tick min CS low read pulse width te iik min CS high pulse width between reads t7 3 ns min RD WR hold time to CS rising edge ts 11 ns max Bus relinquish time to 0 5 x tik typ DRDY high period tio 0 5 x tiak typ DRDY low period ti 0 5 x tak 16 ns max Data access time t2 4 23 ns min Data valid prior to DRDY rising edge t 19 ns min Data valid after DRDY rising edge t14 11 ns max Bus relinquish time tis 4 X tik i CS low write pulse width tie 4 i CShighperiod betwe ti7 Data se i CO tis Data hol tigt 5 23 Data valid prior to MCLK f
53. ture of the AD7760 correct decoupling and layout techniques are required to obtain the performance as stated within this data sheet Figure 55 shows a simplified connection diagram for the AD7760 AVpp2 AVpp4 PIN 12 VBUF L9 PIN 27 VinAt LI ao VinAt VINA gt 1 Vma Yourie DO Youna VourA VourA 8 scl DECAPA DECAPB 25 Vint LT as Vint Vin 10 Vrerx L_ gt 9 7 i 17 1 35 42 43 R19 160kO L4 l Figure 55 Simplified Connection Diagram 4 4 2 PIN 14 lt PIN4 hs PIN 15 12 PIN 12 6 PIN 6 Es pna 24 CT PIN 24 27 N QN QN Tc e aon a aa a ZZZ Z ZZ Z a a 5 AGND2 AD7760BSV 23 AGND3 C PIN 27 AVpp2 44 VoRIVE VoRIVE DVpp PIN 44 s 0o 41 lt PIN 63 PIN 41 AVpp1 i Rev A Page 28 of 36 VoRIVE DBO DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB 0 15 DB10 DB11 DB12 DVpp L8 PIN 41 DVpp C58 it 04975 046 AD7760 SUPPLY DECOUPLING Every supply pin must be connected to the appropriate supply via a ferrite bead and decoupled to the correct ground pin with a 100 nF 0603 case size X7R dielectric capacitor There are two exceptions to this e Pin 12 AVpp4 must have a 10 Q resistor inserted between the pin and a 10 nF decoupling capacitor which is connected to ground at Pin 9 e Pin 27 AVpp2 does not require a separate decoupling
54. utput mode bypassing the default decimation filtering by writing 0 to each of the bits contained in Control Register 1 BYP F1 BYP F3 and DEC 2 0 This will bypass all digital decimation filtering offered by the AD7760 See the AD7760 Registers section for further details When the AD7760 is operating in modulator data output mode a different parallel interfacing scheme than that used for config urations where the AD7760 s data output is filtered is necessary The data output rate depends on the clock divider ratio that is used When the CDIV bit in Control Register 2 is set to logic high data is output at the MCLK frequency If the CDIV bit is set to logic low data is output at a frequency of MCLK 2 See the Clocking the AD7760 section CLOCK DIVIDE BY 1 MODE CDIV 1 When obtaining data from the AD7760 in modulator output mode both the RD WR and CS lines must be held low This brings the data bus out of its high impedance state Figure 43 shows the timing diagram for reading data in the modulator data output mode when operating with CDIV 1 that is ICLK MCLK A DRDY pulse is generated for each word The data on each of the 16 data output pins D 15 0 is valid on the rising edge of the DRDY pulse The DRDY pulse can be used to latch the modulator data into a FIFO or as a DMA control signal Shortly after the RD WR and CS lines return high the AD7760 stops outputting data and the data bus returns to high

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