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ANALOG DEVICES AD7687 handbook

1. 1000 VDD 5V kl VDD 2 5V E lu 10 gt O 6 VIO Z H q li W 04 e 0 001 a 10 100 1000 10000 100000 1000000 SAMPLING RATE SPS Figure 33 Operating Currents vs Sampling Rate SUPPLYING THE ADC FROM THE REFERENCE For simplified applications the AD7687 with its low operating current can be supplied directly using the reference circuit shown in Figure 34 The reference line can be driven by either e The system power supply directly e A reference voltage with enough current output capability such as the ADR43x e A reference buffer such as the AD8031 which can also filter the system power supply as shown in Figure 34 AD7687 r VDD AD7687 02972 033 1OPTIONAL REFERENCE BUFFER AND FILTER Figure 34 Example of Application Circuit DIGITAL INTERFACE Though the AD7687 has a reduced number of pins it offers flexibilitv in its serial interface modes The AD7687 when in CS mode is compatible with SPI QSPI digital hosts and DSPs for example Blackfin ADSP BF53x or ADSP 219x This interface can use either 3 wire or 4 wire A 3 wire interface using the CNV SCK and SDO signals minimizes wiring connections useful for instance in isolated applications A 4 wire interface using
2. 2 5 V 200 kSPS throughput 2 7 mW VDD 5 V 100 kSPS throughput 4 5 5 mW VDD 5 V 250 kSPS throughput 12 5 mW TEMPERATURE RANGE Specified Performance Tmn to Tmax 40 85 C 1 With all digital inputs forced to VIO or GND as required During acquisition phase 3 Contact sales for extended temperature range Rev 0 Page 4 of 28 AD7687 TIMING SPECIFICATIONS 40 C to 85 C VDD 4 5 V to 5 5 V VIO 2 3 V to 5 5 V or VDD 0 3 V whichever is the lowest unless otherwise stated See Figure 3 and Figure 4 for load conditions Table 4 Parameter Symbol Min Typ Max Unit Conversion Time CNV Rising Edge to Data Available tconv 0 5 2 2 us Acquisition Time taca 1 8 us Time Between Conversions tcyc 4 us CNV Pulse Width CS Mode tenvH 10 ns SCK Period CS Mode tsck 15 ns SCK Period Chain Mode tsck VIO Above 4 5 V 17 ns VIO Above 3 V 18 ns VIO Above 2 7 V 19 ns VIO Above 2 3 V 20 ns SCK Low Time tsck 7 ns SCK High Time tsckH 7 ns SCK Falling Edge to Data Remains Valid tHspo 5 ns SCK Falling Edge to Data Valid Delay tospo VIO Above 4 5 V 14 ns VIO Above 3 V 15 ns VIO Above 2 7 V 16 ns VIO Above 2 3 V 17 ns CNV or SDI E VIO Abov 5 C O 15 ns VIO Above 2 7 18 ns VIO Above 2 3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance CS Mode tois 25 ns SDI Valid Setup Time from CNV Rising Edge CS Mode tsspicnv 15 ns SDI Valid Hold Time from CNV Rising Edge CS Mode tHSDICNV 0 ns SCK
3. lezioni 3 2 l ful 55 35 15 5 2 7 3 1 3 5 3 9 SUPPLY V 4 3 Figure 20 Operating Currents vs Supply 5 45 65 85 TEMPERATURE C Figure 21 Power Down Currents vs Temperature lt G i o a OI 02972 020 O1 0 2972 019 OPERATING CURRENT HA OFESET GAIN ERROR LSB Tpspo DELAY ns TEMPERATURE C Figure 22 Operating Currents vs Temperature 45 65 TEMPERATURE C 85 Figure 23 Offset and Gain Error vs Temperature 105 5V 85 C N a VDD 2 5V 25 C VDD 3 3V 25 C 20 40 SDO CAPACITIVE LOAD pF 60 80 100 Figure 24 tospo Delay vs Capacitance Load and Supply Rev 0 Page 12 of 28 12 02972 021 02972 022 02972 023 o IN 32 768C 16 384C 32 768C 16 3840 REF GND AD7687 SWITCHES CONTROL BUSY CONTROL Losie OUTPUT CODE SW 02972 024 Figure 25 ADC Simplified Schematic CIRCUIT INFORMATION The AD7687 is a fast low power single supply precise 16 bit ADC using a successive approximation architecture The AD7687 is capable of converting 250 000 samples per second 250 kSPS and powers down t e When operati r exam 1 35 uW whioh i 1 a po The AD7687 provides the user with an on chip track and hold and does not exhibit anv pipeline delav or lat
4. E E 120 E lt x 140 a 160 8 ii 5 180 3 3 20 40 60 80 100 120 0 20 40 60 80 100 120 FREQUENCY kHz FREQUENCY kHz Figure 9 FFT Plot Figure 12 FFT Plot Rev 0 Page 10 of 28 SNR S N D dB S N D dB SNR dB AD7687 T a a 2 a a o IL z o LU a T H 2 3 2 7 3 1 3 5 3 9 4 3 4 7 5 1 5 5 3 REFERENCE VOLTAGE V 23 27 31 35 39 43 47 51 55 REFERENCE VOLTAGE V Figure 13 SNR S N D and ENOB vs Reference Voltage Figure 16 THD SFDR vs Reference Voltage 100 VREF 5V 10dB 95 VREF 2 5V 10dB 90 VREF 5V 1dB FI VREF 2 5V 1dB 85 a a T 80 5V 10dB 75 VREF 5V 10dB 70 S S 0 50 100 150 200 100 0 FREQUENCY kHz FREQUENCY kHz Figure 14 S N D vs Frequency Figure 17 THD vs Frequency 100 90 VREF 5V T 90 B 10 a T H 85 120 ct N 80 o 130 8 55 35 15 5 25 45 65 85 105 125 55 35 15 5 25 45 65 85 105 125 TEMPERATURE C TEMPERATURE C Figure 15 SNR vs Temperature Figure 18 THD vs Temperature Rev 0 Page 11 of 28 AD7687 100 SNR dB 1000 750 INPUT LEVEL dB Figure 19 SNR vs Input Level 02972 018 fs 100kSPS VDD OPERATING CURRENT HA 2 1000 750 500 POWER DOWN CURRENT nA 0 500 250
5. Mode tHscKcNV 8 ns SDI Valid Setup Time from SCK Falling Edge Chain Mode tsspisck 5 ns SDI Valid Hold Time from SCK Falling Edge Chain Mode tHSDISCK 4 ns SDI High to SDO High Chain Mode with BUSY indicator tpspospi 36 ns Rev 0 Page 6 of 28 ABSOLUTE MAXIMUM RATINGS AD7687 Table 6 Parameter Rating Analog Inputs IN IN GND 0 3 V to VDD 0 3 V or 130 mA REF GND 0 3 V to VDD 0 3 V Supply Voltages VDD VIO to GND 0 3 V to 7 V VDD to VIO 7 V Digital Inputs to GND 0 3 V to VIO 0 3 V Digital Outputs to GND 0 3 V to VIO 0 3 V Storage Temperature Range 65 C to 150 C Junction Temperature 150 C Osa Thermal Impedance Osc Thermal Impedance Lead Temperature Range 200 C W MSOP 10 44 C W MSOP 10 JEDEC J STD 20 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 1 See the Analog Input section ESD CAUTION ESD electrostatic discharge sensitive device Electrost electrostati is degradation 6r lo f atic charges as high as 4000V readilv accumulate on h this prodult featlife WARNING tel nile fu cp cee qa ol efor H ESD SENSIT
6. The data bits are then clocked out MSB first by subsequent SCK falling edges The data is valid on both SCK edges Although the rising edge can be used to capture the data OsbDI AD7687 spo O na DATA IN IRQ CLK 02972 036 Figure 37 CS Mode 3 Wire with BUSY Indicator Connection Diagram SDI High e tenvH CNV tconv taca gt tsck tsekL SCK 1 2 3 15 16 tuspo tsckH tpspo Ad tois Figure 38 CS Mode 3 Wire with BUSY Indicator Serial Interface Timing SDI High 02972 037 Rev 0 Page 19 of 28 AD7687 CS MODE 4 WIRE NO BUSY INDICATOR This mode is usually used when multiple AD7687s are connected to an SPI compatible digital host A connection diagram example using two AD7687s is shown in Figure 39 and the corresponding timing is given in Figure 40 With SDI high a rising edge on CNV initiates a conversion selects the CS mode and forces SDO to high impedance In this mode CNV must be held high during the conversion phase and the subsequent data readback if SDI and CNV are low SDO is driven low Prior to the minimum conversion time SDI could be used to select other SPI devices such as analog multiplexers but SDI must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator When the conversion is complete the AD7687 enters the acquisition phase and powers down Each ADC re
7. 0 dB input 36 5 dB fin 20 kHz Vre 2 5 V 92 92 5 dB Intermodulation Distortion 115 dB 1 LSB means least significant bit With the 5 V input range one LSB is 152 6 uV 2 See the Terminology section These specifications do include full temperature range variation but do not include the error contribution from the external reference 3All specifications in dB are referred to a full scale input FSR Tested with an input signal at 0 5 dB below full scale unless otherwise specified 4 fin 21 4 kHz fina 18 9 kHz each tone at 7 dB below full scale Rev 0 Page 3 of 28 AD7687 VDD 2 3 V to 5 5 V VIO 2 3 V to VDD Vre VDD Ta 40 C to 85 C unless otherwise noted Table 3 Parameter Conditions Min Typ Max Unit REFERENCE Voltage Range 0 5 VDD 0 3 V Load Current 250 kSPS REF 5 V 50 HA SAMPLING DVNAMICS 3 dB Input Bandwidth 2 MHz Aperture Delav VDD 5V 2 5 ns DIGITAL INPUTS Logic Levels Vi 0 3 0 3 x VIO V Vin 0 7 x VIO VIO 0 3 V lu 1 H HA lin 1 H HA DIGITAL OUTPUTS Data Format Serial 16 bits twos complement Pipeline Delav Conversion results available immediatelv after completed conversion Vor Isink 500 pA 0 4 V Vou Isource 500 WA VIO 0 3 V POWER SUPPLIES VDD Specified performance 2 3 5 5 V VIO Specified performance 2 3 VDD 0 3 V VIO Range 1 8 V Standby cor Ae C O 1 nA Power Dissipat 1 uW VDD 2 5 V 100 kSPS throughput 1 35 mW VDD
8. 5 LSB max 40 C to 85 C Tube 50 10 Lead MSOP RM 10 C03 AD7687BRMRL7 1 5 LSB max 40 C to 85 C Reel 1 000 10 Lead MSOP RM 10 c03 EVAL AD7687CB EVAL CONTROL BRD2 EVAL CONTROL BRD3 Evaluation Board Controller Board Controller Board 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL CONTROL BRDx for evaluation demonstration purposes These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators ww BDI C Con AD Rev 0 Page 26 of 28 AD7687 NOTES ww BDI C Con AD AD7687 NOTES ww BOM C Com AD 2005 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www analo g com sem Lal DEVICES Rev 0 Page 28 of 28
9. ANALOG DEVICES 16 Bit 1 5 LSB INL 250 kSPS PulSAR Differential ADC in MSOP QFN AD7687 APPLICATION DIAGRAM 0 5V TO 5V 2 5 TO 5V FEATURES 16 bit resolution with no missing codes Throughput 250 kSPS INL 0 4 LSB typ 1 5 LSB max 23 ppm of FSR Dynamic range 96 5 dB S N D 95 5 dB 20 kHz THD 118 dB 20 kHz True differential analog input range VREF O V to Vrer with Vrer up to VDD on both inputs No pipeline delay Single supply 2 3 V to 5 5 V operation with 1 8 V 2 5 V 3 V 5 V logic interface Serial interface SPI QSPI MICROWIRE DSP compatible Daisy chain multiple ADCs and BUSY indicator Power dissipation 1 35 mW 2 5 V 100 kSPS 4 mW 5 V 100 kSPS and 1 4 pW 2 5 V 100 SPS Standby current 1nA 10 lead MSOP MSOP 8 size and 3mm x OT 2 Pin for pin I 7685 APPLICATIONS Battery powered equipment Data acquisitions Instrumentation Medical instruments Process controls POSITIVE INL 0 32LSB NEGATIVE INL 0 41LSB INL LSB Figure 1 Integral Nonlinearity vs Code Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tra
10. D7687 are outlined in the documentation of the evaluation board for the AD7687 EVAL AD7687 The evaluation board package includes a fully assembled and tested evaluation board documentation and software for controlling the board from a PC via the EVAL CONTROL BRD3 see CREF CUDD CVIO Figure 48 Example of Layout of the AD7687 Bottom Layer Rev 0 Page 24 of 28 02972 046 02972 047 OUTLINE DIMENSIONS 3 00 BSC 3 00 BSC 4 90 BSC 7 0 95 0 85 i 1 10 MAX 0 75 TID 0 80 015 f eae NSEATING 023 fE E gt e 0 60 0 00 0 17 PLANE 908 0 40 COPLANARITY 0 10 COMPLIANT TO JEDEC STANDARDS MO 187 BA Figure 49 10 Lead Mini Small Outline Package MSOP RM 10 Dimensions shown in millimeters PIN 1 INDICATOR EXPOSED PAD BOTTOM VIEW 2 23 0 40 os 0 30 MAX 0 30 PADDLE CONNECTED TO GND 0 55 TYP 1 49 THIS CONNECTION IS NOT 1 zs SpE WEW L 0 05 MAX REQUIRED TO MEET THE lii ELECTRICAL PERFORMANCES LODI j 00 0 02 NOM SEATING pina 0 30 i REF PLANE a 0 18 Figure 50 10 Lead Lead Frame Chip Scale Package QFN LFCSP_WD 3mm x 3 mm Body Very Very Thin Dual Lead CP 10 9 Dimensions shown in millimeters 1 QFN package in development Contact sales for samples and availability Rev 0 Page 25 of 28 AD7687 AD7687 ORDERING GUIDE Integral Transport Media Package Package Model Nonlinearity Temperature Range Quantity Description Option Branding AD7687BRM 1
11. IVE DEVICE 02972 003 Figure 3 Load Circuit for Digital Interface Timing 30 VIO tDELAV U 2V OR VIO 0 5V1 g 2V OR VIO 0 5V1 0 8V OR 0 5V2 N 0 8V OR 0 5V2 70 VIO 12V IF VIO ABOVE 2 5V VIO 0 5V IF VIO BELOW 2 5V 20 8V IF VIO ABOVE 2 5V 0 5V IF VIO BELOW 2 5V 02972 004 Figure 4 Voltage Levels for Timing Rev 0 Page 7 of 28 AD7687 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 5 10 Lead MSOP Pin Configuration AD7687 TOP VIEW Not to Scale 02972 005 02972 006 Figure 6 10 Lead QFN LFCSP Pin Configuration 1 QFN package in development Contact sales for samples and availability Table 7 Pin Function Descriptions Pin No Mnemonic Type Function 1 REF Al Reference Input Voltage The REF range is from 0 5 V to VDD It is referred to the GND pin This pin should be decoupled closely to the pin with a 10 UF capacitor 2 VDD P Power Supply 3 IN Al Differential Positive Analog Input 4 IN AI Differential Negative Analog Input 5 GND P Power Supplv Ground 6 CNV DI Convert Input This input has multiple functions On its leading edge it initiates the conversions and selects the interface mode chain or CS In CS mode it enables the SDO pin when low In chain mode the 7 SDO i e CO i sult is output on tk is ize t 8 SCK i i ctedAthe cd n result is s s clock 9 SDI DI Serial Data Input This input provides multiple featur
12. Valid Setup Time from CNV Rising Edge Chain Mode tssckenv 5 ns SCK Valid Hold Time from CNV Rising Edge Chain Mode tuscKcNv 5 ns SDI Valid Setup Time from SCK Falling Edge Chain Mode tsspiscK 3 ns SDI Valid Hold Time from SCK Falling Edge Chain Mode tuspisck 4 ns SDI High to SDO High Chain Mode with BUSY indicator tpspospi VIO Above 4 5 V 15 ns VIO Above 2 3 V 26 ns Rev 0 Page 5 of 28 AD7687 40 C to 85 C VDD 2 3 V to 4 5 V VIO 2 3 V to 4 5 V or VDD 0 3 V whichever is the lowest unless otherwise stated See Figure 3 and Figure 4 for load conditions Table 5 Parameter Symbol Min Typ Max Unit Conversion Time CNV Rising Edge to Data Available tconv 0 7 3 2 Us Acquisition Time taca 1 8 Us Time Between Conversions tcyc 5 Us CNV Pulse Width CS Mode tenvH 10 ns SCK Period CS Mode tsck 25 ns SCK Period Chain Mode tsck VIO Above 3 V 29 ns VIO Above 2 7 V 35 ns VIO Above 2 3 V 40 ns SCK Low Time tsck 12 ns SCK High Time tsckH 12 ns SCK Falling Edge to Data Remains Valid tHspo 5 ns SCK Falling Edge to Data Valid Delay tospo VIO Above 3 V 24 ns VIO Above 2 7 V 30 ns VIO Above 2 3 V 35 ns CNV or SDI Low to SDO D15 MSB Valid CS Mode ten VIO Above 2 7 V 18 ns VIO Above 2 3 V 22 ns CNV or SDI Hig e toi 5 ns SDI Valid Setup CNV 30 ns SDI Valid Hold Ti HSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge Chain Mode tssckcnv 5 ns SCK Valid Hold Time from CNV Rising Edge Chain
13. Very low noise and high frequency AD8022 Low noise and high frequency OP 184 Low power low noise and low frequency AD8605 AD8615 5 V single supplv low power AD8519 Small low power and low frequency AD8031 High frequency and low power SINGLE TO DIFFERENTIAL DRIVER For applications using a single ended analog signal either bipolar or unipolar a single ended to differential driver allows for a differential input into the part see Figure 31 for the schematic When provided a single ended input signal this configuration produces a differential Vrer with midscale at Vree 2 ANALOG INPUT c E10V 5V VREF 02972 030 Figure 31 Single Ended to Differential Driver Circuit VOLTAGE REFERENCE INPUT The AD7687 voltage reference input REF has a dynamic input impedance and should therefore be driven by a low impedance urce with efficient decoupling between and GND pins as explain eda thedsavo pe ce for example a reference buffer sing the AD8031 or the AD8605 a 10 uF X5R 0805 size ceramic chip capacitor is appropriate for optimum performance Ifan unbuffered reference voltage is used the decoupling value depends on the reference used For instance a 22 uF X5R 1206 size ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference If desired smaller reference decoupling capacitor values down to 2 2 uF can be used with a minimal impact on performa
14. an be used to daisy chain multiple AD7687s on a 3 wire serial interface This feature is useful for reducing component count and wiring connections for example in isolated multiconverter applications or for systems with a limited interfacing capacity Data readback is analogous to clocking a shift register A connection diagram example using two AD7687s is shown in Figure 43 and the corresponding timing is given in Figure 44 When SDI and CNV are low SDO is driven low With SCK low a rising edge on CNV initiates a conversion selects the chain mode and disables the BUSY indicator In this mode CNV is held high during the conversion phase and the subsequent data readback When the conversion is complete the MSB is output 7687 SDOO J A CNV c SDI AD7687 sDoO OspI AD Figure 43 Chain Mode No BUSV Indicator Connection Diagram onto SDO and the AD7687 enters the acquisition phase and powers down The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges For each ADC SDI feeds the input of the internal shift register and is clocked by the SCK falling edge Each ADC in the chain outputs its data MSB first and 16 x N clocks are required to readback the N ADCs The data is valid on both SCK edges Although the rising edge can be used to capture the data a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7687s in the chain prov
15. ce Timing 02972 045 Rev 0 Page 23 of 28 AD7687 APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7687 should be designed so that the analog and digital sections are separated and confined to certain areas of the board The pinout of the AD7687 with all its analog signals on the left side and all its digital signals on the right side eases this task Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7687 is used as a shield Fast switching signals such as CNV or clocks should never run near analog signal paths Crossover of digital and analog signals should be avoided At least one ground plane should be used It could be common or split between the digital and analog sections In the latter case the planes should be joined underneath the AD7687s The AD7687 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances This is done by placing the reference decoupling ceramic capacitor close to and ideally right up against the REF and GND pins and connecting it with wide low impedance traces placed close to the 687 andicom t o traces to provide low impedance paths and ig the effect of glitches on the power supply lines An example of layout following these rules is shown in Figure 47 and Figure 48 EVALUATING THE AD7687 S PERFORMANCE Other recommended layouts for the A
16. demarks and registered trademarks are the property of their respective owners 1 8V TO VDD 3 OR 4 WIRE INTERFACE SPI DAISY CHAIN CS 02972 002 Figure 2 Table 1 MSOP QFN LFCSP SOT 23 16 Bit PulSAR ADC Type 100kSPS 250kSPS 500kSPS True Differential AD7684 AD7687 AD7688 Pseudo AD7683 AD7685 AD7686 Differential Unipolar AD7694 Unipolar AD7680 GENERAL DESCRIPTION rge fed dis successive DC that operates from a single power supply bD ween 2 3 V to 5 5 V It contains a low power high speed 16 bit sampling ADC with no missing codes an internal conversion clock and a versatile serial interface port The part also contains a low noise wide bandwidth short aperture delay track and hold circuit On the CNV rising edge it samples the voltage difference between IN and IN pins The voltages on these pins usually swing in opposite phase between 0 V to REF The reference voltage REF is applied externally and can be set up to the supply voltage Its power scales linearly with throughput The SPI compatible serial interface also features the ability using the SDI input to daisy chain several ADCs on a single 3 wire bus and provides an optional BUSY indicator It is compatible with 1 8 V 2 5 V 3 V or 5 V logic using the separate supply VIO The AD7687 is housed in a 10 lead MSOP or a 10 lead QEN LFCSP with operation specified from 40 C to 85 C 1 QFN package in developme
17. encv making it ideal for multiple multiplexed channel applications The AD7687 is specified from 2 3 V to 5 5 V and can be interfaced to any of the 1 8 V to 5 V digital logic family It is housed in a 10 lead MSOP or a tiny 10 lead QFN LFCSP that combines space savings and allows flexible configurations It is pin for pin compatible with the AD7685 AD7686 and AD7688 QFN package in development Contact sales for samples and availability CONVERTER OPERATION The AD7687 is a successive approximation ADC based on a charge redistribution DAC Figure 25 shows the simplified schematic of the ADC The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors which are connected to the SL a e array tied to the comparators input are onnected to GND via SW and SW All independent switches are connected to the analog inputs Thus the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN and IN inputs When the acquisition phase is complete and the CNV input goes high a conversion phase is initiated When the conversion phase begins SW and SW are opened first The two capacitor arrays are then disconnected from the inputs and connected to the GND input Therefore the differential voltage between the inputs IN and IN captured at the end of the acquisition phase is applied to the comparator inputs causing the comparator to become unbalanced By switching each element
18. es It selects the4interface mode of the ADC as follows Chain mode is selected if SDI is low during the CNV rising edge In this mode SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line The digital data level on SDI is output on SDO with a delay of 16 SCK cycles CS mode is selected if SDI is high during the CNV rising edge In this mode either SDI or CNV can enable the serial output signals when low and if SDI or CNV is low when the conversion is complete the BUSY indicator feature is enabled 10 VIO P Input Output Interface Digital Power Nominally at the same supply as the host interface 1 8 V 2 5 V 3 V or 5 V TAI Analog Input DI Digital Input DO Digital Output and P Power Rev 0 Page 8 of 28 AD7687 TERMINOLOGY Integral Nonlinearity Error INL It refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale The point used as negative full scale occurs LSB before the first code transition Positive full scale is defined as a level 1 LSB beyond the last code transition The deviation is measured from the middle of each code to the true straight line Figure 26 Differential Nonlinearity Error DNL In an ideal ADC code transitions are 1 LSB apart DNL is the maximum deviation from this ideal value It is often specified in terms of resolution for which no missing codes are guaran
19. falling edge allows a faster reading rate and This mode can also be used to daisy chain multiple AD7687s on a 3 wire serial interface while providing a BUSY indicator This feature is useful for reducing component count and wiring A connection diagram example using three AD7687s is shown in Figure 45 and the corresponding timing is given in Figure 46 When SDI and CNV are low SDO is driven low With SCK consequently more AD7687s in the chain provided the digital high a rising edge on CNV initiates a conversion selects the host has an acceptable hold time For instance with a 3 ns chain mode and enables the BUSY indicator feature In this digital host setup time and 3 V interface up to eight AD7687s mode CNV is held high during the conversion phase and the running at a conversion rate of 220 kSPS can be daisy chained subsequent data readback When all ADCs in the chain have to a single 3 wire port completed their conversions the nearend ADC ADC Cin a CNV CNV QSDI BO TGS SDOO OSDI ADPU SDOO jet sr oy 1 SIIT COTTA L D wW T Figure 45 Chain Mode with BUSY Indicator Connection Diagram CONVERT DIGITAL HOST DATA IN 02972 044 teve CNV SDIA tconv taca ACQUISITION ACQUISITION tssckcnv a V V V sek X XX tHsckenv gt t Lui ten DSDOSDI SDOA SDig tpspospi 5000 AD CD CD AND CED CED CE DEA Figure 46 Chain Mode with BUSY Indicator Serial Interfa
20. he code for an underranged analog input Vins Vin below Veer Venn 5V O 1 8V TO VDD REF VDD VIO 0 TO VREFO 3 OR 4 WIRE INTERFACES VREF TO 00 1SEE REFERENCE SECTION FOR REFERENCE SELECTION 2Cper IS USUALLY A 10 F CERAMIC CAPACITOR X5R 3SEE DRIVER AMPLIFIER CHOICE SECTION 4OPTIONAL FILTER SEE ANALOG INPUT SECTION 5SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE 02972 026 Figure 27 Typical Application Diagram with Multiple Supplies Rev 0 Page 14 of 28 ANALOG INPUT Figure 28 shows an equivalent circuit of the input structure of the AD7687 The two diodes D1 and D2 provide ESD protection for the analog inputs IN and IN Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0 3 V because this causes these diodes to begin to forward bias and start conducting current These diodes can handle a forward biased current of 130 mA maximum For instance these conditions could eventually occur when the input buffer s U1 supplies are different from VDD In such a case an input buffer with a short circuit current limitation can be used to protect the part n SI 2 a N G SI Ss as shown in frequency 90 80 a 70 e cc cc O 60 50 40 8 1 10 100 1000 FREQUENCV kHz Figure 29 Analog Input CMRR vs Frequencv AD7687 Dur
21. ided the digital host has an acceptable hold time The maximum conversion rate may be reduced due to the total readback time For instance with a 3 ns digital host set up time and 3 V interface up to eight AD7687s running at a conversion rate of 220 kSPS can be daisy chained on a 3 wire port CONVERT DIGITAL HOST SDIA 0 teve CNV l4 tconv taca ACQUISITION ACQUISITION Ja tssckcnv tisekenv gt ten gt SDO7 SDlg a o e w o w gt iv o 02972 043 Figure 44 Chain Mode No BUSV Indicator Serial Interface Timing Rev 0 Page 22 of 28 AD7687 CHAIN MODE WITH BUSY INDICATOR Figure 45 SDO is driven high This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host The AD7687 then enters the acquisition phase and powers down The data bits stored in the internal l ee l shift register are then clocked out MSB first bv subsequent connections for example in isolated multiconverter SCK falling edges For each ADC SDI feeds the input of the applications or for systems with a limited interfacing capacity internal shift register and is clocked by the SCK falling edge Data readback is analogous to clocking a shift register Each ADC in the chain outputs its data MSB first and 16 x N 1 clocks are required to readback the N ADCs Although the rising edge can be used to capture the data a digital host using the SCK
22. if SDI and CNV are low SDO is driven low Prior to the minimum conversion time SDI could be used to select other SPI devices such as analog multiplexers but SDI must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator When the conversion is complete SDO goes from high impedance to low With a pull up on the SDO line this transition can be used as an interrupt signal to initiate the data readback controlled by AD7687 the digital host The AD7687 then enters the acquisition phase and powers down The data bits are then clocked out MSB first by subsequent SCK falling edges The data is valid on both SCK edges Although the rising edge can be used to capture the data a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time After the optional 17th SCK falling edge or SDI going high whichever is earlier the SDO returns to high impedance OSsDI AD7687 SsDOO 02972 040 Figure 41 CS Mode 4 Wire with BUSY Indicator Connection Diagram ww BDH G C CNV a tcony a taca agi tsspicnv SDI tuspicnv tsck tsckL SCK 15 16 tHspo tsekH tospo A tois ten xo m XTX 02972 041 Figure 42 CS Mode 4 Wire with BUSY Indicator Serial Interface Timing Rev 0 Page 21 of 28 AD7687 CHAIN MODE NO BUSY INDICATOR This mode c
23. ing i l rate provided it has an acceptable hold time After the optional This mode is usually used when a single AD7687 is connected 17th SCK falling edge or when CNV goes high whichever is to an SPI compatible digital host having an interrupt input earlier SDO returns to high impedance The connection diagram is shown in Figure 37 and the If multiple AD7687s are selected at the same time the SDO corresponding timing is given in Figure 38 output pin handles this contention without damage or induced latch up Meanwhile it is recommended to keep this contention With SDI tied to VIO a rising edge on CNV initiates a RE COTE ae as short as possible to limit extra power dissipation conversion selects the CS mode and forces SDO to high impedance SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV CONVERT Prior to the minimum conversion time CNV could be used to select other SPI devices such as analog multiplexers but CNV DIGITAL HOST VIO must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSX signal indicator When the conversion is complete SDO goes from high impedance to low With a pull up on the SDO line this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host The AD7687 then enters the acquisition phase and powers down
24. ing the acquisition phase the impedance of the analog inputs IN or IN can be modeled as a parallel combination of capacitor Crm and the network formed by the series connection of Ruy and Cm Crm is primarily the pin capacitance Rw is typically 3 kO and is a lumped component made up of some serial resistors and the on resistance of the switches Civ is typically 30 pF and is mainly the ADC sampling capacitor During the conversion phase where the switches are opened the input impedance is limited to Crm Rm and Cm make a 1 pole low pass filter that reduces undesirable aliasing effects and limits the noise When the source impedance of the driving circuit is low the AD7687 can be driven directly Large source impedances significantly affect the ac performance especially total harmonic distortion THD The dc performances are less sensitive to the input impedance The maximum source impedance depends on the amount of THD that can be tolerated The THD degrades as a function of the source impedance and the maximum input frequency as shown in Figure 30 THD dB 02972 029 FREQUENCY kHz Figure 30 THD vs Analog Input Frequency and Source Resistance Rev 0 Page 15 of 28 AD7687 DRIVER AMPLIFIER CHOICE Although the AD7687 is easy to drive the driver amplifier needs to meet the following requirements e The noise generated by the driver amplifier needs to be kept as low as possible in order
25. nce especially DNL Regardless there is no need for an additional lower value ceramic decoupling capacitor for example 100 nF between the REF and GND pins POWER SUPPLY The AD7687 is specified over a wide operating range of 2 3 V to 5 5 V Unlike other low voltage converters it has a low enough noise to design a 16 bit resolution system with low supply and respectable performance It uses two power supply pins a core supply VDD and a digital input output interface supply VIO VIO allows direct interface with any logic between 1 8 V and VDD To reduce the supplies needed the VIO and VDD can be tied together The AD7687 is independent of power supply sequencing between VIO and VDD Additionally it is very Rev 0 Page 16 of 28 insensitive to power supply variations over a wide frequency range as shown in Figure 32 which represents PSRR over frequency 100 95 90 85 80 75 PSRR dB VDD 2 5V 70 65 60 55 50 02972 031 gt 1 10 100 1000 100 FREQUENCY kHz Figure 32 PSRR vs Frequency The AD7687 powers down automatically at the end of each conversion phase and therefore the power scales linearly with the sampling rate as shown in Figure 33 This makes the part ideal for low sampling rate even a few Hz and low battery powered applications
26. nt Contact sales for samples and availability One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved AD7687 TABLE OF CONTENTS Specifications nn A EAS eci 3 Power SUPplyicosrrr ie ii 16 Timing Specifications ieri rene 5 Supplying the ADC from the Reference 17 Absolute Maximum Ratings eee 7 Digital Interface asal sulle 17 ESD alii 7 CS MODE 3 Wire No BUSY Indicator 18 Pin Configurations and Function Descriptions 8 CS Mode 3 Wire with BUSY Indicator u 19 TENO lOS y xxii ie 9 CS Mode 4 Wire No BUSY Indicator sse 20 Typical Performance Characteristics rien 10 CS Mode 4 Wire with BUSY Indicator 21 Circuit Information rieti 13 Chain Mode No BUSY Indicatori 22 Converter Operation rie 13 Chain Mode with BUSY Indicator n 23 Typical Connection Diagram essences gt Application Hints ere 24 Analog Input ii 15 Tayota s a a S E piva deva A AN 24 Driver Amplifier Choice ieri 16 Evaluating the AD7687 s Performance 24 Single to Differential Driver mmmmmnnnannnzannnzannzonenzonen 16 O tline Dimensions oserei E E EES EEE 25 Voltage Reference InpUt emmenanznzznznnznzanznzzznznenmnznznnzznzn Ordering Guide eeeessse
27. nzzzennnnenzenzzzonnezzzzzznnnntazzonnenannnnazazzan 26 4 05 Revision 0 Initial Version Rev 0 Page 2 of 28 SPECIFICATIONS VDD 2 3 V to 5 5 V VIO 2 3 V to VDD Vre VDD Ta 40 C to 85 C unless otherwise noted AD7687 Table 2 Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range IN IN V REF VREF V Absolute Input Voltage IN IN 0 1 Veer 0 1 V Common Mode Input Range IN IN 0 Vrer 2 Vrer 2 0 1 V Analog Input CMRR fin 250 kHz 65 dB Leakage Current at 25 C Acquisition phase 1 nA Input Impedance See the Analog Input section ACCURACY No Missing Codes 16 Bits Differential Linearity Error 1 0 4 1 LSB Integral Linearity Error 1 5 0 4 1 5 LSB Transition Noise REF VDD 5V 0 35 LSB Gain Error Tmn to Tmax 6 LSB Gain Error Temperature Drift 0 3 ppm C Offset Error Tmn to Tmax VDD 4 5Vto5 5V 0 1 6 mV VDD 2 3V to 4 5 V 0 7 3 5 mV Offset Temperature Drift ppm C Power Supply Sensitivity VDD 5V 5 LSB THROUGHPUT A Conversi to55V kSPS to 45 V kSPS Transient Response Full scale step Us AC ACCURACY Dynamic Range Vre 5 V 95 8 96 5 dB Signal to Noise fin 20 kHz Vrer 5 V 94 95 5 dB fin 20 kHz Vrer 2 5 V 92 92 5 dB Spurious Free Dynamic Range fin 20 kHz 118 dB Total Harmonic Distortion fin 20 kHz 118 dB Signal to Noise Distortion fin 20 kHz Vrer 5 V 94 95 5 dB fin 20 kHz Veer 5 V 6
28. of the capacitor array between GND and REF the comparator input varies by binary weighted voltage steps Vrer 2 Vrer 4 Vrer 65536 The control logic toggles these switches starting with the MSB in order to bring the comparator back into a balanced condition After the completion of this process the part returns to the acquisition phase and the control logic generates the ADC output code and a BUSY signal indicator Because the AD7687 has an on board conversion clock the serial clock SCK is not required for the conversion process Rev 0 Page 13 of 28 AD7687 Transfer Functions TYPICAL CONNECTION DIAGRAM The ideal transfer characteristic for the AD7687 is shown in Figure 27 shows an example of the recommended connection Figure 26 and Table 8 diagram for the AD7687 when multiple supplies are available 011 111 011 110 011 101 ADC CODE TWOS COMPLEMENT 100 010 100 001 100 000 w FSR FSR 1 LSB FSR 1 LSB FSR 0 5 LSB FSR 1 5 LSB ANALOG INPUT 02972 025 Figure 26 ADC Ideal Transfer Function Table 8 Output Codes and Ideal Input Voltages Analog Input Description Vreer 5V Digital Output Code Hexa FSR 1LSB 9 7FFF Midscale 1 LSB 5 001 C O Midscale 0 000 Midscale 1 LSB 152 6 uV FFFF FSR 1LSB 4 999847 V 8001 FSR 5V 8000 This is also the code for an overranged analog input Vins Vin above Veer Venp This is also t
29. selects the CS mode and forces SDO to high impedance Once a conversion is initiated it continues to completion irrespective of the state of CNV For instance it could be useful to bring CNV low to select other SPI devices such as analog multiplexers but CNV must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator When the conversion is complete the AD7687 enters the acquisition phase and powers down When CNV goes low the MSB is output onto SDO The remaining data bits are then clocked by subsequent SCK falling edges The data is valid on both SCK edges Although the rising edge can be used SDI 1 to capture the data a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time After the 16th SCK falling edge or when CNV goes high whichever is earlier SDO returns to high impedance CONVERT DIGITAL HOST VIO OsbDI AD7687 sDOO DATAIN 02972 034 Figure 35 CS Mode 3 Wire No BUSY Indicator Connection Diagram SDI High l tcvc CNV ACQUISITION CONVERSION SCK tsckH gt tene gt tospo gt tsck TEA CC 02972 035 Figure 36 CS Mode 3 Wire No BUSY Indicator Serial Interface Timing SDI High Rev 0 Page 18 of 28 AD7687 CS MODE 3 WIRE WITH BUSY INDICATOR a digital host using the SCK falling edge allows a faster read
30. sult can be read by bringing low its SDI input which consequently outputs the MSB onto SDO The remaining data bits are then clocked by subsequent SCK falling edges The data is valid on both SCK edges Although the rising edge can be used to capture the data a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time After the 16th SCK falling edge or when SDI goes high whichever is earlier SDO returns to high impedance and another AD7687 can be read CNV tevc ACQUISITION CONVERSION tsspicnv be SDK SI tispicnv gt SDKCS2 SCK SDO ACQUISITION 02972 039 Figure 40 CS Mode 4 Wire No BUSY Indicator Serial Interface Timing Rev 0 Page 20 of 28 CS MODE 4 WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7687 is connected to an SPI compatible digital host which has an interrupt input and it is desired to keep CNV which is used to sample the analog input independent of the signal used to select the data reading This requirement is particularly important in applications where low jitter on CNV is desired The connection diagram is shown in Figure 41 and the corresponding timing is given in Figure 42 With SDI high a rising edge on CNV initiates a conversion selects the CS mode and forces SDO to high impedance In this mode CNV must be held high during the conversion phase and the subsequent data readback
31. teed Zero Error It is the difference between the ideal midscale voltage that is 0 V from the actual voltage producing the midscale output code that is 0 LSB Gain Error The first transition from 100 00 to 100 01 should occur at a level LSB above nominal negative full scale 4 999924 V for the 5 V range The last transition from 011 10 to 011 11 should occur for an analog voltage 1 LSB below the nominal full scale 4 999771 V for the a error is the Spurious Free Dynamic Range SFDR SFDR is the difference in decibels dB between the rms amplitude of the input signal and the peak spurious signal Effective Number of Bits ENOB ENOB is a measurement of the resolution with a sine wave input It is related to S N D by the following formula ENOB S N Dlas 1 76 6 02 and is expressed in bits Total Harmonic Distortion THD THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full scale input signal and is expressed in dB Dynamic Range It is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together The value for dynamic range is expressed in dB Signal to Noise Ratio SNR SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency excluding harmonics and dc The value for SNR is expressed in dB S i to thle rm N
32. the SDI CNV SCK and SDO signals allows CNV which initiates the conversions to be independent of the readback timing SBI This is in low jitter sa mp fn a The 6 i a a daisy chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register The mode in which the part operates depends on the SDI level when the CNV rising edge occurs The CS mode is selected if SDI is high and the chain mode is selected if SDI is low The SDI hold time is such that when SDI and CNV are connected together the chain mode is always selected In either mode the AD7687 offers the flexibility to optionally force a start bit in front of the data bits This start bit can be used as a BUSY signal indicator to interrupt the digital host and trigger the data reading Otherwise without a BUSY indicator the user must time out the maximum conversion time prior to readback The BUSY indicator feature is enabled as e In the CS mode if CNV or SDI is low when the ADC conversion ends Figure 38 and Figure 42 e Inthe chain mode if SCK is high during the CNV rising edge Figure 46 Rev 0 Page 17 of 28 AD7687 CS MODE 3 WIRE NO BUSY INDICATOR This mode is usually used when a single AD7687 is connected to an SPI compatible digital host The connection diagram is shown in Figure 35 and the corresponding timing is given in Figure 36 With SDI tied to VIO a rising edge on CNV initiates a conversion
33. to preserve the SNR and transition noise performance of the AD7687 Note that the AD7687 has a noise much lower than most of the other 16 bit ADCs and therefore can be driven by a noisier op amp while preserving the same or better system perform ance The noise coming from the driver is filtered by the AD7687 analog input circuit 1 pole low pass filter made by Rw and Cw or by the external filter if one is used Because the typical noise of the AD7687 is 53 uV rms the SNR degradation due to the amplifier is 5 SNR oss 20log 2 7 53 3S san 2Nen where f ses is the input bandwidth in MHz of the AD7687 2 MHz or the cutoff frequency of the input filter if one is used Nis the noi j buffer configuration en is the equivalent input noise voltage of the op amp in nV VHz e For ac applications the driver should have a THD performance commensurate with the AD7687 Figure 17 shows the THD vs frequency that the driver should exceed e For multichannel multiplexed applications the driver amplifier and the AD7687 analog input circuit must settle a full scale step onto the capacitor array at a 16 bit level 0 0015 15 ppm In the amplifier s data sheet settling at 0 1 to 0 01 is more commonly specified This could differ significantly from the settling time at a 16 bit level and should be verified prior to driver selection Table 9 Recommended Driver Amplifiers Amplifier Typical Application AD8021
34. yqui value for Sy N D is expressed in dB Aperture Delay Aperture delay is the measure of the acquisition performance It is the time between the rising edge of the CNV input and when the input signal is held for a conversion Transient Response It is the time required for the ADC to accurately acquire its input after a full scale step function was applied Rev 0 Page 9 of 28 AD7687 TYPICAL PERFORMANCE CHARACTERISTICS 1 5 POSITIVE INL 0 32LSB POSITIVE DNL 0 27LSB NEGATIVE INL 0 41LSB NEGATIVE DNL 0 24LSB a D a _ ki E i mini k A 5 Pre TREN ERY 3 a 0 16384 32768 49152 65535 70 16384 32768 49152 65535 CODE CODE Figure 7 Integral Nonlinearitv vs Code 300000 VDD REF 2 5V 258680 250000 200403 200000 n E 150000 mD 5 3 AVI f D o 100000 i Stk 0 Bi S 41 42 43 44 45 46 47 44 45 46 47 48 49 4A 4B AC CODE IN HEX CODE IN HEX Figure 8 Histogram of a DC Input at the Code Center Figure 11 Histogram of a DC Input at the Code Center 0 8192 POINT FFT 32768 POINT FFT 20 VDD REF 5V VDD REF 2 5V Fg 250KSPS Fg 250KSPS 40 Fin 2 1kHz T Fin 2kHz T SNR 95 5dB T SNR 92 8dB B THD 118 3dB THD 115 9dB 60 2nd HARM 130dB 2nd HARM 124dB iL 3rd HARM 122 7dB LL 3rd HARM 119dB 6 80 m m 2 Di w 100 LU Q Q

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