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ANALOG DEVICES AD7793 handbook

1. n is position Table 12 Register Selection RS2 RS1 RSO Register Register Size 0 0 0 Communications Register During a Write Operation 8 bit 0 0 0 Status Register During a Read Operation 8 bit 0 0 1 Mode Register 16 bit 0 1 0 Configuration Register 16 bit 0 1 1 Data Register 16 24 bit 1 0 0 ID Register 8 bit 1 0 1 IO Register 8 bit 1 1 0 Offset Register 16 bit AD7792 24 bit AD7793 1 1 1 Full Scale Register 16 bit AD7792 24 bit AD7793 Rev B Page 14 of 32 AD7792 AD7793 STATUS REGISTER RS2 RS1 RSO 0 0 0 Power On Reset 0x80 AD7792 0x88 AD7793 The status register is an 8 bit read only register To access the ADC status register the user must write to the communications register select the next operation to be a read and load Bit RS2 Bit RS1 and Bit RSO with 0 Table 13 outlines the bit designations for the status register SRO through SR7 indicate the bit locations and SR denotes that the bits are in the status register SR7 denotes the first bit of the data stream The number in parentheses indicates the power on reset default status of that bit SR7 SR6 SR4 SR3 SR2 SR1 SRO RDY 1 ERR O 0 1 0 0 0 0 CH2 0 CH1 0 CHO 0 Table 13 Status Register Bit Designations Bit Location Bit Name Description SR7 RDY Ready Bit for ADC Cleared when data is written to the ADC data register The RDY bit is set automat
2. SPECIFICATIONS AVpp 2 7 V to 5 25 V DVpp 2 7 V to 5 25 V GND 0 V all specifications Tum to Tmax unless otherwise noted Table 1 Parameter AD7792B AD7793B Unit Test Conditions Comments ADC CHANNEL Output Update Rate 4 17 to 470 Hz nom No Missing Codes 24 Bits min fapc 242 Hz AD7793 16 Bits min AD7792 Resolution See Output Noise and Resolution Specifications Output Noise and Update Rates See Output Noise and Resolution Specifications Integral Nonlinearity 15 ppm of FSR max Offset Error 1 UV typ Offset Error Drift vs Temperature 10 nV C typ Full Scale Error 5 10 UV typ Gain Drift vs Temperature 1 ppm C typ Gain 1 to 16 external reference 3 ppm C typ Gain 32 to 128 external reference Power Supply Rejection 100 dB min AIN 1 V gain gain 2 4 external reference ANALOG INPUTS Differential Input Voltage Ranges Vrer Gain V nom Veer REFIN REFIN or internal reference gain 1 to 128 Absolute AIN Voltage Limits Unbuffered Mode GND 30 mV V min Gain 1 or 2 AVpo 30 mV V max Buffer min V naf O In Amp Acti 3 min AVoo 1 1 V max Common Mode Voltage Vem 0 5 V min Vem AIN AIN 2 gain 4 to 128 Analog Input Current Buffered Mode or In Amp Active Average Input Current 1 nA max Gain 1 or 2 update rate lt 100 Hz 250 pA max Gain 4 to 128 update rate lt 100 Hz Average Input Current Drift 2 pA C typ Unbuffered Mode Gain 10r2 Average Input Curre
3. GND AVpp material and of equal length and IOUTI and IOUT2 match the error voltage across RL2 equals the error voltage across RLI and no error voltage is developed between AIN1 and AINI Twice the voltage is developed across RL3 but because this is a common mode voltage it does not introduce errors The reference voltage for the AD7792 AD7793 is also generated using one of these matched current sources It is developed using a precision resistor and applied to the differential reference pins of the ADC This scheme ensures that the analog input voltage span remains ratiometric to the reference voltage Any errors in the analog input voltage due to the temperature drift of the excitation current are compensated by the variation of the reference voltage REFIN REFIN DOUT RDY SERIAL INTERFACE f Q DIN AND Rev B Page 29 of 32 AD7792 AD7793 OUTLINE DIMENSIONS 0 15 0 20 si AD oos 4 0 30 0 65 devis SEATING BSC PLANE COPLANARITY 0 10 uw E 0 75 F 8 gt ja 0 60 COMPLIANT TO JEDEC STANDARDS MO 153 AB Figure 22 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 Dimensions shown in millimeters ORDERING GUIDE Model Temp kage Description k ion AD7792BRU 0 C 16 Lead T AD7792BRU RE 0 C 16 Lead TSSOP AD7792BRUZ 40 C to 10 Lead TS RU 1 AD7792BRUZ REEL 40 C to 105 C 16 Lead TSSOP RU 16 AD7793BRU 40 C to 105 C 16 Lead TSSOP R
4. By writing 01011100 to the communications register the user needs only to apply the appropriate number of SCLK cycles to the ADC and the 16 24 bit word is automatically placed on the DOUT RDY line when a conversion is complete The ADC should be configured for continuous conversion mode When DOUT RDY goes low to indicate the end of a conver sion sufficient SCLK cycles must be applied to the ADC and the data conversion is placed on the DOUT RDY line When the conversion is read DOUT RDY returns high until the next conversion is available In this mode the data can be read only once In addition the user must ensure that the data word is read before the next conversion is complete If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD7792 AD7793 to read the word the serial output register is reset when the next conversion is completed and the new conversion is placed in the output serial register To exit the continuous read mode the instruction 01011000 must be written to the communications register while the DOUT RDY pin is low While in the continuous read mode the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode Additionally a reset occurs if 32 consecutive 1s are seen on DIN Therefore DIN should be held low in continuous read mode until an instruction is written to the
5. ensure that a data read is not attempted while the register is being updated CS is used to select a device It can be used to decode the AD7792 AD7793 in systems where several components are connected to the serial bus Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7792 AD7793 with CS being used to decode the part Figure 3 shows the timing for a read operation from the AD7792 AD7793 output shift register and Figure 4 shows the timing for a write operation to the input shift register It is possible to read the same word from the data register several times even though the DOUT RDY line returns high after the first read operation However care must be taken to ensure that the read operations have been completed before the next output update occurs In continuous read mode the data register can be read only once The serial interface can operate in 3 wire mode by tying CS low In this case the SCLK DIN and DOUT RDY lines are used to communicate with the AD7792 AD7793 The end of the conversion can be monitored using the RDY bit in the status register This scheme is suitable for interfacing to microcon trollers If CS is required as a decoding signal it can be generated from a port pin For microcontroller interfaces it is recommended that SCLK idle high between data transfers The AD7792 AD7793 can be operated with CS being used as a frame synchronization signal This scheme is useful for DSP interfaces In
6. 0 8 1 7 V min V max DVop 5V Vr Vi 0 1 0 17 V min V max DVpp 5V Vr 0 9 2 V min V max DVpp 3V Vi 0 4 1 35 V min V max DVop 3 V Vr Vi 0 06 0 13 V min V max DVoo 3 V Input Currents 10 HA max Vin DVoo or GND Input Capacitance 10 pF typ All digital inputs LOGIC OUTPUTS INCLUDING CLK Von Output High Voltage DVop 0 6 V min DVop 3 V Isource 100 pA Vo Output Low Voltage 0 4 V max DVoo 3 V Isik 100 LA Von Output High Voltage 4 V min DVop 5 V Isource 200 pA Vor Output Low Voltage 0 4 V max DVoo 5 V Isinx 1 6 mA DOUT RDY 800 HA CLK Floating State Leakage Current 10 HA max Floating State Output Capacitance 10 pF typ Data Output Coding Offset binary SYSTEM CALIBRATION Full Scale Calibration Limit 41 05 x FS V max Zero Scale Calibration Limit 1 05 x FS V min Input Span 0 8 x FS V min max POWER RE Power Su g AVop to GND 2 7 5 25 V min max DVop to GND 2 7 5 25 V min max Power Supply Currents loo Current 140 HA max 110 pA typ AVoo 3V 125 pA typ AVoo 5V unbuffered mode external reference 185 HA max 130 pA typ AVpp 3 V 165 pA typ AVoo 5V buffered mode gain 1 or 2 external reference 400 uA max 300 HA typ AVoo 3V 350 pA typ AVop 5 V gain 4 to 128 external reference 500 HA max 400 pA typ AVpp 3 V 450 pA typ AVpo 5 V gain 4 to 128 internal reference Ipp Power Down Mode 1 HA max Temperature range is 40 C to 105 C At the 19 6 Hz
7. 1 1 1 System Full Scale Calibration User should connect the system full scale input to the channel input pins as selected by the CH2 to CHO bits A calibration takes 2 conversion cycles to complete RDY goes high when the calibration is initiated and returns low when the calibration is complete The ADC is placed in idle mode following a calibration The measured full scale coefficient is placed in the full scale register of the selected channel A full scale calibration is required each time the gain of a channel is changed selected channel Table 16 Update Rates Available FS3 FS2 FS1 FSO faoc Hz tserrie ms Rejection 50 Hz 60 Hz Internal Clock 0 0 0 0 x x 0 0 0 1 470 4 0 0 1 0 242 8 0 0 1 1 123 16 0 1 0 0 62 32 0 1 0 1 50 40 0 1 1 0 39 48 0 1 1 1 33 2 60 1 0 0 0 19 6 101 90 dB 60 Hz only Rev B Page 16 of 32 AD7792 AD7793 FS3 FS2 FS1 FSO faoc Hz tserrie ms Rejection 50 Hz 60 Hz Internal Clock 1 0 0 1 16 7 120 80 dB 50 Hz only 1 0 1 0 16 7 120 65 dB 50 Hz and 60 Hz 1 0 1 1 12 5 160 66 dB 50 Hz and 60 Hz 1 1 0 0 10 200 69 dB 50 Hz and 60 Hz 1 1 0 1 8 33 240 70 dB 50 Hz and 60 Hz 1 1 1 0 6 25 320 72 dB 50 Hz and 60 Hz 1 1 1 1 4 17 480 74 dB 50 Hz and 60 Hz CONFIGURATION REGISTER RS2 RS1 RSO 0 1 0 Power On Reset 0x0710 The configuration register is a 16 bit register from which data can be read
8. AD7792 AD7793 circuitry is powered down including the current sources burnout currents bias voltage generator and CLKOUT circuitry 1 0 0 Internal Zero Scale Calibration An internal short is automatically connected to the enabled channel A calibration takes 2 conversion cycles to complete RDY goes high when the calibration is initiated and returns low when the calibration is complete The ADC is placed in idle mode following a calibration The measured offset coefficient is placed in the offset register of the selected channel es 2 cgfiversion cycl c le r higher gai Version cycles i urns low JC alibration i ADC is placed ull scale coefficient is placed in the full scale register of the 1 0 1 Internal Full Scale Calibration Internal full scale calibrations cannot be performed when the gain equals 128 With this gain setting a system full scale calibration can be performed A full scale calibration is required each time the gain of a channel is changed to minimize the full scale error 1 1 0 System Zero Scale Calibration User should connect the system zero scale input to the channel input pins as selected by the CH2 to CHO bits A system offset calibration takes 2 conversion cycles to complete RDY goes high when the calibration is initiated and returns low when the calibration is complete The ADC is placed in idle mode following a calibration The measured offset coefficient is placed in the offset register of the selected channel
9. AD7793 can be reset by writing 32 consecutive 1s to the device This resets the logic the digital filter and the analog modulator while all on chip registers are reset to their default values A reset is automatically performed on power up When a reset is initiated the user must allow a period of 500 us before accessing any of the on chip registers A reset is useful if the serial interface becomes asynchronous due to noise on the SCLK line Rev B Page 25 of 32 AD7792 AD7793 AVop MONITOR Along with converting external voltages the ADC can be used to monitor the voltage on the AVpp pin When Bit CH2 to Bit CHO equal 1 the voltage on the AVpp pin is internally attenuated by 6 and the resultant voltage is applied to the X A modulator using an internal 1 17 V reference for analog to digital conversion This is useful because variations in the power supply voltage can be monitored CALIBRATION The AD7792 AD7793 provide four calibration modes that can be programmed via the mode bits in the mode register These are internal zero scale calibration internal full scale calibration system zero scale calibration and system full scale calibration which effectively reduces the offset error and full scale error to the order of the noise After each conversion the ADC con version result is scaled using the ADC calibration registers before being written to the data register The offset calibration coefficient is subtracted from the
10. ID register This is a read only register IO REGISTER RS2 RS1 RSO 1 0 1 Power On Reset 0x00 The IO register is an 8 bit register from which data can be read or to which data can be written This register is used to enable and select the value of the excitation currents Table 18 outlines the bit designations for the IO register I00 through IO7 indicate the bit locations IO denotes that the bits are in the IO register IO7 denotes the first bit of the data stream The number in parentheses indicates the power on reset default status of that bit 107 106 105 104 103 102 101 100 0 0 0 0 0 0 0 0 IEXCDIR1 0 IEXCDIRO 0 IEXCEN1 0 IEXCENO 0 Rev B Page 18 of 32 AD7792 AD7793 Table 18 IO Register Bit Designations Bit Location Bit Name Description 107 to 104 0 These bits must be programmed with a Logic 0 for correct operation 103 to 102 IEXCDIR1 to Direction of current sources select bits IEXCDIRO IEXCDIR1 IEXCDIRO Current Source Direction 0 0 Current Source IEXC1 connected to Pin IOUT1 Current Source IEXC2 connected to Pin IOUT2 0 1 Current Source IEXC1 connected to Pin IOUT2 Current Source IEXC2 connected to Pin IOUT1 1 0 Both current sources connected to Pin IOUT1 Permitted when the current sources are set to 10 HA or 210 pA only 1 1 Both current sources connected to Pin IOUT2 Permitted when the current sources are set to 10 pA or
11. Normal Mode Rejection Same as for analog inputs Common Mode Rejection 100 dB typ EXCITATION CURRENT SOURCES IEXC1 and IEXC2 Output Current 10 210 1000 HA nom Initial Tolerance at 25 C 5 typ Drift 200 ppm C typ Current Matching Drift Matchin ine tesa AAA Load Regulatio AVop 0 65 0 Matching between IEXC1 C2 Vout OV ppm C ty z CONA ALT p Output Compliance V max 10 pA or 210 pA currents selected AVop 1 1 V max 1 mA currents selected GND 30 mV V min TEMPERATURE SENSOR Accuracy 2 C typ Applies if user calibrates the temperature Sensitivity 0 81 mV C typ sensor BIAS VOLTAGE GENERATOR Vaias AVpp 2 V nom Vgias Generator Start Up Time See Figure 10 ms nF typ Dependent on the capacitance on the AIN pin INTERNAL EXTERNAL CLOCK Internal Clock Frequency 64 396 kHz min max Duty Cycle 50 50 96 typ External Clock Frequency 64 kHz nom A 128 kHz external clock can be used if the divide by 2 function is used Bit CLK1 CLKO 1 Duty Cycle 45 55 to 55 45 96 typ Applies for external 64 kHz clock a 128 kHz clock can have a less stringent duty cycle LOGIC INPUTS CS Vini Input Low Voltage 0 8 V max DVpp 5V 0 4 V max DVpp 3V Vinx Input High Voltage 2 0 V min DVpp 2 3Vor5V Rev B Page 4 of 32 AD7792 AD7793 Parameter AD7792B AD7793B Unit Test Conditions Comments SCLK CLK and DIN Schmitt Triggered Input Vr 1 4 2 V min V max DVoo 5V Vi
12. and filter and sets the RDY bit MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MD2 0 MD1 0 MDO 0 0 0 0 0 0 0 0 0 0 0 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MRO CLK1 0 CLKO 0 0 0 0 0 FS3 1 FS2 0 FS1 1 FSO 0 Table 14 Mode Register Bit Designations Bit Location Bit Name Description MR15 to MD2 to Mode Select Bits These bits select the operational mode of the AD7792 AD7793 see Table 15 MR13 MDO MR12toMR8 0 These bits must be programmed with a Logic 0 for correct operation MR7 to MR6 CLK1 to These bits are used to select the clock source for the AD7792 AD7793 Either an on chip 64 kHz clock can be CLKO used or an external clock can be used The ability to override using an external clock allows several AD7792 AD7793 devices to be synchronized In addition 50 Hz 60 Hz is improved when an accurate external clock drives the AD7792 AD7793 CLK1 CLKO ADC Clock Source 0 0 Internal 64 kHz Clock Internal clock is not available at the CLK pin 0 1 Internal 64 kHz Clock This clock is made available at the CLK pin 1 0 External 64 kHz Clock Used An external clock gives better 50 Hz 60 Hz rejection See specifications for external clock 1 1 External Clock Used The external clock is divided by 2 within the AD7792 AD7793 MR5 to MR4 0 These bits must be programmed with a Logic 0 for correct operation MR3 to MRO FS3toFSO Filter Update Rate Select Bits see Table 16 Rev
13. device SCLK n 9 b 18 E Figure 19 Continuous Read Rev B Page 23 of 32 AD7792 AD7793 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL The AD7792 AD7793 have three differential analog input channels These are connected to the on chip buffer amplifier when the device is operated in buffered mode and directly to the modulator when the device is operated in unbuffered mode In buffered mode the BUF bit in the mode register is set to 1 the input channel feeds into a high impedance input stage of the buffer amplifier Therefore the input can tolerate significant source impedances and is tailored for direct connection to external resistive type sensors such as strain gauges or resistance temperature detectors RTDs When BUF 0 the part is operated in unbuffered mode This results in a higher analog input current Note that this unbuffered input path provides a dynamic load to the driving source Therefore resistor capacitor combinations on the input pins can cause gain errors depending on the output impedance of the source that is driving the ADC input Table 19 shows the allowable external resistance capacitance values for unbuffered mode such that no gain error at the 20 bit level is introduced Table 19 External R C Combination for No 20 Bit Gain Error C pF R Q 50 9k 100 6 1000 0 5000 200 The AD7792 AD7793 can be operated in unbuffered mode only when the gain equals 1 or 2 At h
14. is open circuit It could also mean that the front end sensor is overloaded and is justified in outputting full scale or the reference may be absent thus clamping the data to all 1s When reading all 1s from the output the user needs to check these three cases before making a judgment If the voltage measured is 0 V it may indicate that the transducer has short circuited For normal operation these burnout currents are turned off by writing a 0 to the BO bit in the configuration register The current sources work over the normal absolute input voltage range specifications with buffers on EXCITAT The AD779 configurable constant nt to equal 10 uA 210 uA or 1 mA Both source currents from the AV are directed to either the IOUT1 or IOUT2 pin of the device These current sources are controlled via bits in the IO register The configuration bits enable the current sources direct the current sources to IOUTI or IOUT2 and select the value of the current These current sources can be used to excite external resistive bridge or RTD sensors BIAS VOLTAGE GENERATOR A bias voltage generator is included on the AD7792 AD7793 This biases the negative terminal of the selected input channel to AVpp 2 It is useful in thermocouple applications because the voltage generated by the thermocouple must be biased about some dc voltage if the gain is greater than 2 This is necessary because the instrumentation amplifier requires headroom to ensure
15. result prior to multiplication by the full scale coefficient To start a calibration write the relevant value to the MD2 to MDO bits in the mode register After the calibration is complete the contents of the corresponding calibration registers are updated the RDY bit in the status register is set the DOUT RDY pin goes low if CS is low and the A revert to idle mode During an internalize a leto fulliscale e respective zero input and full scale input are automatically connected internally to the ADC input pins A system calibration however expects the system zero scale and system full scale voltages to be applied to the ADC pins before the calibration mode is initiated In this way external ADC errors are removed From an operational point of view a calibration should be treated like another ADC conversion A zero scale calibration if required should always be performed before a full scale calibration System software should monitor the RDY bit in the status register or the DOUT RDY pin to determine the end of calibration via a polling sequence or an interrupt driven routine Both an internal offset calibration and a system offset calibration take two conversion cycles An internal offset calibration is not needed as the ADC itself removes the offset continuously To perform an internal full scale calibration a full scale input voltage is automatically connected to the selected analog input for this calibration W
16. the power consumption of the device If set the ADC operates in buffered mode allowing the user to place source impedances on the front end without contributing gain errors to the system The buffer can be disabled when the gain equals 1 or 2 For higher gains the buffer is automatically enabled With the buffer disabled the voltage on the analog input pins can be from 30 mV below GND to 30 mV above AVoo When the buffer is enabled it requires some headroom so the voltage on any input pin must be limited to 100 mV within the power supply rails CON3 0 This bit must be programmed with a Logic 0 for correct operation CON2 to CH2 to Channel Select Bits Written by the user to select the active analog input channel to the ADC CONO CHO CH2 CH1 CHO Channel Calibration Pair 0 0 0 AIN1 AIN1 0 0 0 1 AIN2 AIN2 1 0 1 0 AIN3 AIN3 2 0 1 1 AIN1 AIN1 0 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Temp Sensor Automatically selects gain 1 and internal reference 1 1 1 Moni Automatically selegts gains 1 17V C DATA REGISTER RS2 RS1 RSO 0 1 1 Power On Reset 0x0000 00 The conversion result from the ADC is stored in this data register This is a read only register On completion of a read operation from this register the RDY bit pin is set ID REGISTER RS2 RS1 RSO 1 0 0 Power On Reset OxXA AD7792 0xXB AD7793 The identification number for the AD7792 AD7793 is stored in the
17. this case the first bit MSB is effectively clocked out by CS because CS would normally occur after the falling edge of SCLK in DSPs T igue to run between dat DIN input if a gin l is written to the AD7792 AD7793 line for at least 32 serial clock cycles the serial interface is reset This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system Reset returns the interface to the state in which it is expecting a write to the communications register This opera tion resets the contents of all registers to their power on values Following a reset the user should allow a period of 500 us before addressing the serial interface The AD7792 AD7793 can be configured to continuously convert or to perform a single conversion See Figure 17 through Figure 19 Rev B Page 21 of 32 AD7792 AD7793 Single Conversion Mode In single conversion mode the AD7792 AD7793 are placed in shutdown mode between conversions When a single conver sion is initiated by setting MD2 MD1 MDO to 0 0 1 in the mode register the AD7792 AD7793 power up perform a single conversion and then return to shutdown mode The on chip oscillator requires 1 ms to power up A conversion requires a time period of 2 x tanc DOUT RDY goes low to indicate the completion of a conversion When the data word has been read from the data register DOUT RDY goes high If CS is low DOUT RD
18. 0 3V to DVop 0 3 V Charged devices and circuit boards can discharge AIN Digital Input Current 10 mA A without detection Although this product features r e patented or proprietary protection circuitry damage Operating Temperature Range 40 C to 105 C may occur on devices subjected to high energy ESD Storage Temperature Range 65 C to 150 C Avead Therefore proper ESD precautions should be taken to a avoid performance degradation or loss of functionality Maximum Junction Temperature 150 C TSSOP Osa Thermal Impedance 128 C W Osc Thermal Impedance 14 C W Lead Temperature Soldering Vapor Phase 60 sec 215 C Infrared 15 sec 220 C ww BDI C com AD Rev B Page 8 of 32 AD7792 AD7793 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 DIN 15 DOUT RDY AD7792 14 PVoo AD7793 13 AVpp TOP VIEW Not to Scale 12 GND 11 IOUT2 10 REFIN AIN3 9 REFIN AIN3 04855 005 Figure 5 Pin Configuration Table 4 Pin Function Descriptions Pin No Mnemonic Description 1 SCLK Serial Clock Input This serial clock input is for data transfers to and from the ADC The SCLK has a Schmitt triggered input making the interface suitable for opto isolated applications The serial clock can be continuous with all data transmitted in a continuous train of pulses Alternatively it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batch
19. 1 Changes to Table 8 Table 9 and Table 10 12 Changes to Table 16 ananas 16 Changes to Overview Section eee 20 Renamed Applications Section to Applications Information 29 Changes to Ordering Guide eee 30 Offset Register aiuta ERA 19 F ll Scale Registet ose Ren ERR 19 ADC Circuit Information 20 OVeEVIEWS use e IR RR p eie 20 Digital Interface cvizioeriontconi studeo de ili 21 Circuit Description cana 24 Analog Input Channel eee 24 Instrumentation Amplifier eee 24 Bipolar Unipolar Configuration ses 24 Data Output Coding ea 24 Burnout Currents nte EDI IEEE EEER NES neS 25 Excitation CUrrents rei 25 Bias Voltage Generator Reference i25 ROS CU eres il TII uM 25 AN Dp Monitor arca 26 Calibration iae lo areata 26 rounding and Layout empe e Temperature Measurement using an RTD ss 29 Ouutling Dimensions eei estie terere itin 30 Ordering Guide o REL RR BERE 30 4 05 Rev 0 to Rev A Changes to Absolute Maximum Ratings ee 8 G an sito Figure Ii aiar 22 Changes to Data Output Coding Section ss 24 Changes to Calibration Section see 26 Changes to Ordering Guide eee 30 10 04 Revision 0 Initial Version Rev B Page 2 of 32 AD7792 AD7793
20. 13 5 242 17 5 15 17 14 5 17 5 15 17 14 5 17 14 5 17 5 15 16 5 14 15 5 13 470 17 5 15 17 14 5 17 14 5 17 14 5 17 14 5 17 14 5 16 13 5 15 12 5 Table 10 Typical Resolution Bits vs Gain and Output Update Rate for the AD7792 Using the Internal Reference Update Rate Hz Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4 17 16 16 16 16 16 16 16 16 16 16 16 16 16 16 rr 8 33 16 16 16 16 16 16 16 16 16 16 16 16 16 16 6 15 5 16 7 16 16 16 16 16 16 16 16 16 16 16 16 16 16 6 15 332 16 16 16 16 16 16 16 16 16 16 16 16 16 15 5 6 14 5 62 16 16 16 16 16 16 16 16 16 16 16 16 16 15 5 ui 123 16 16 16 15 5 16 16 16 15 5 16 15 16 15 5 16 14 5 15 5 13 5 242 16 15 16 14 5 16 15 16 14 5 16 14 5 16 15 16 14 15 13 470 16 15 16 14 5 16 14 5 16 14 5 16 14 5 16 14 5 15 5 13 5 14 5 12 5 Rev B Page 12 of 32 AD7792 AD7793 TYPICAL PERFORMANCE CHARACTERISTICS 8388800 8388750 20 8388700 o E a W 8388650 9 w 8 8388600 2 40 o o o s 04855 006 04855 009 0 1 75 1 05 0 70 0 35 0 0 35 0 70 1 05 1 40 1 75 MATCHING 0 200 400 600 800 1000 READING NUMBER Figure 6 Typical Noise Plot Internal Reference Gain 64 Figure 9 Excitation Current Matching 1 mA at Ambient Tem
21. 2 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2004 2007 Analog Devices Inc All rights reserved AD7792 AD7793 TABLE OF CONTENTS Features RoR eS Oe RR OE aS LU LE Mer 1 Applications ien itte Ue REP RR 1 Functional Block Diagram eerte 1 General Description sissies 1 Revision History rei 2 SPecificationsa nori talia 3 Timing Characteristics ciet rented ettet ibn 6 TIMING Dia Stans zie tree tete eh aet eae eee eene aae ads 7 Absolute Maximum Ratings eerte 8 ESD Caution ieri REESE ER ERES 8 Pin Configuration and Function Descriptions 9 Output Noise and Resolution Specifications 11 External Reference sss wl Internal Reference 2 12 Typical Performance Characteristics rien 13 On Chip Registers sc pentola cieli 14 Communications Register rien 14 Status Register Mode Register HE AM Configuration Data Registeri nuca 18 ID Register iaia ia ici 18 TORE SISter x scuri 18 REVISION HISTORY 3 07 Rev A to Rev B Updated Format eri ettet Universal Change to Functional Block Diagram sss 1 Changes to Specifications Section sse 3 Changes to Specifications Endnote 1 sss 5 Changes to Table 5 Table 6 and Table 7 1
22. 210 pA only 101 to lOO IEXCENT to These bits are used to enable and disable the current sources along with selecting the value of the IEXCENO excitation currents IEXCEN1 IEXCENO Current Source Value 0 0 Excitation Current Disabled 0 1 10 uA 1 0 210 pA 1 1 1mA OFFSET REGISTER FULL SCALE REGISTER RS2 RS1 RSO 1 1 0 Power On Reset 0x8000 RS2 RS1 RSO 1 1 1 Power On Reset 0x5XXX AD7792 0x AD7792 0x5XXX00 Each analo Thefull s holds the ofi 0 cha is 24 register is 16 bits wide on the AD7792 and 24 bits wide on the full scale calibration coefficient for the ADC The AD7793 and its power on reset value is 0x8000 00 The offset AD7792 AD7793 have 3 full scale registers each channel register is used in conjunction with its associated full scale having a dedicated full scale register The full scale registers are register to form a register pair The power on reset value is read write registers however when writing to the full scale automatically overwritten if an internal or system zero scale registers the ADC must be placed in power down mode or idle calibration is initiated by the user The offset register is a mode These registers are configured on power on with factory read write register However the AD7792 AD7793 must be calibrated full scale calibration coefficients the calibration in idle mode or power down mode when writing to the being performed at gain 1 Therefore every device has offset regi
23. 5 16 18 5 16 17 5 15 16 5 14 470 18 5 16 8 15 5 18 5 16 18 5 16 18 15 5 18 15 5 17 14 5 16 13 5 Table 7 Typical Resolution Bits vs Gain and Output Update Rate for the AD7792 Using an External 2 5 V Reference Update Rate Hz Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4 17 16 16 16 16 16 16 16 16 16 16 UE 16 16 16 16 8 33 16 16 16 16 16 16 16 16 16 16 6 16 16 16 16 16 16 7 16 16 16 16 16 16 16 16 16 16 6 16 16 16 16 16 332 16 16 16 16 16 16 16 16 16 16 6 16 16 16 16 16 62 16 16 16 16 16 16 16 16 16 16 6 16 16 16 16 15 5 123 16 16 16 16 16 16 16 16 16 16 6 16 165 15 5 16 14 5 242 16 16 16 15 5 16 15 5 16 15 5 16 16 6 16 16 15 16 14 470 16 16 16 15 5 16 16 16 16 16 15 5 6 15 5 16 14 5 15 5 13 5 Rev B Page 11 of 32 AD7792 AD7793 INTERNAL REFERENCE Table 8 shows the output rms noise of the AD7792 AD7793 for some of the update rates and gain settings The numbers given are for the bipolar input range with the internal 1 17 V reference These numbers are typical and are generated with a differential input voltage of 0 V Table 9 and Table 10 show the effective resolution with the output peak to peak p p resolution given in parentheses for the AD7793 and AD7792 respectively It is important to note that the effective re
24. ANALOG 3 Channel Low Noise Low Power 16 24 Bit DEVICES A ADC with On Chip In Amp and Reference AD7792 AD7793 FEATURES Up to 23 bits effective resolution RMS noise 40 nV 4 17 Hz 85 nV 16 7 Hz Current 400 pA typical Power down 1 pA maximum Low noise programmable gain instrumentation amp Band gap reference with 4 ppm C drift typical Update rate 4 17 Hz to 470 Hz 3 differential inputs Internal clock oscillator Simultaneous 50 Hz 60 Hz rejection Programmable current sources On chip bias voltage generator Burnout currents Power supply 2 7 V to 5 25 V 40 C to 105 C temperature range Independent interface power supply 16 lead TSSOP package Interface 3 wire seti SPI QSPE mand D Schmitt trigger on SCLK APPLICATIONS Thermocouple measurements RTD measurements Thermistor measurements Gas analysis Industrial process control Instrumentation Portable instrumentation Blood analysis Smart transmitters Liquid gas chromatography 6 digit DVM Rev B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the pr
25. B Page 15 of 32 AD7792 AD7793 Table 15 Operating Modes MD2 MD1 MDO Mode 0 0 0 Continuous Conversion Mode Default In continuous conversion mode the ADC continuously performs conversions and places the result in the data register RDY goes low when a conversion is complete The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied Alternatively the user can instruct the ADC to output the conversion by writing to the communications register After power on a channel change or a write to the mode configuration or IO registers the first conversion is available after a period of 2 fapc Subsequent conversions are available at a frequency of fapc 0 0 1 Single Conversion Mode When single conversion mode is selected the ADC powers up and performs a single conversion The oscillator requires 1 ms to power up and settle The ADC then performs the conversion which takes a time of 2 faoc The conversion result is placed in the data register RDY goes low and the ADC returns to power down mode The conversion remains in the data register and RDY remains active low until the data is read or another conversion is performed 0 1 0 Idle Mode In idle mode the ADC filter and modulator are held in a reset state although the modulator clocks are still provided 0 1 1 Power Down Mode In power down mode all the
26. U 16 AD7793BRU REEL 40 C to 105 C 16 Lead TSSOP RU 16 AD7793BRUZ 40 C to 105 C 16 Lead TSSOP RU 16 AD7793BRUZ REEL 40 C to 105 C 16 Lead TSSOP RU 16 EVAL AD7792EBZ Evaluation Board EVAL AD7793EBZ Evaluation Board 1 Z RoHS Compliant Part Rev B Page 30 of 32 AD7792 AD7793 NOTES ww BDI C com AD AD7792 AD7793 NOTES ww BOM C com AL 2004 2007 Analog Devices Inc All rights reserved Trademarks and AN ALOG registered trademarks are the property of their respective owners D04855 0 3 07 B DEVICES www analog com Rev B Page 32 of 32
27. Y remains high until another conversion is initiated and completed The data register can be read several times if required even when DOUT RDY has gone high Continuous Conversion Mode This is the default power up mode The AD7792 AD7793 continuously converts the RDY pin in the status register going low each time a conversion is completed If CS is low the DOUT RDY line also goes low when a conversion is complete To read a conversion the user writes to the communications register indicating that the next operation is a read of the data register The digital conversion is placed on the DOUT RDY pin as soon as SCLK pulses are applied to the ADC DOUT RDY returns high when the conversion is read The user can read this register additional times if required However the user must ensure that the data register is not being accessed at the completion of the next conversion otherwise the new conversion word is lost ir eT DIN x 0x08 X we M i 0x58 WW BDIT Cc DOUT RDY 04855 015 Figure 17 Single Conversion a DIN Cm SCLK i 016 04855 Figure 18 Continuous Conversion Rev B Page 22 of 32 AD7792 AD7793 Continuous Read Rather than write to the communications register each time a conversion is complete to access the data the AD7792 AD7793 can be configured so that the conversions are placed on the DOUT RDY line automatically
28. age REFIN REFIN is 2 5 V but the part functions with a reference from 0 1 V to AVop Alternatively this pin can function as AIN3 where AIN3 is the positive terminal of the differential analog input pair AIN3 AIN3 10 REFIN AIN3 Negative Reference Input Analog Input REFIN is the negative reference input for REFIN This reference input can lie anywhere between GND and AVop 0 1 V This pin also functions as AIN3 which is the negative terminal of the differential analog input pair AIN3 AIN3 11 IOUT2 Output of Internal Excitation Current Source The internal excitation current source can be made available at this pin The excitation current source is programmable so that the current can be 10 pA 210 pA or 1 mA Either IEXC1 or IEXC2 can be switched to this output 12 GND Ground Reference Point 13 AVop Supply Voltage 2 7 V to 5 25 V 14 DVpp Digital Interface Supply Voltage The logic levels for the serial interface pins are related to this supply which is between 2 7 V and 5 25 V The DVop voltage is independent of the voltage on AVoo therefore AVo can equal 5 V with DVop at 3 V or vice versa Rev B Page 9 of 32 AD7792 AD7793 Pin No Mnemonic Description 15 DOUT RDY Serial Data Output Data Ready Output DOUT RDY serves a dual purpose It functions as a serial data output pin to access the output shift register of the ADC The output shift register can contain data f
29. alog input voltage can be represented as Code 2 x AIN x GAIN Vxrer When the ADC is configured for bipolar operation the output code is offset binary with a negative full scale voltage resulting in a code of 000 000 a zero differential input voltage resulting in a code of 100 000 and a positive full scale input voltage resulting in a code of 111 111 The output code for any analog input voltage can be represented as Code 2N x AIN x GAIN Vrer 1 where AIN is the analog input voltage GAIN is the in amp setting 1 to 128 and N 16 for the AD7792 and N 24 for the AD7793 Rev B Page 24 of 32 AD7792 AD7793 BURNOUT CURRENTS The AD7792 AD7793 contain two 100 nA constant current generators one sourcing current from AVpp to AIN and one sinking current from AIN to GND The currents are switched to the selected analog input pair Both currents are either on or off depending on the burnout current enable BO bit in the configuration register These currents can be used to verify that an external transducer is still operational before attempting to take measurements on that channel Once the burnout currents are turned on they flow in the external transducer circuit and a measurement of the input voltage on the analog input channel can be taken If the resultant voltage measured is full scale the user needs to verify why this is the case A full scale reading could mean that the front end sensor
30. and 39 2 Hz update rates the INL power supply rejection PSR common mode rejection CMR and normal mode rejection NMR do not meet the data sheet specification if the voltage on the AIN or AIN pins exceed AVpp 16 V typically When this voltage is exceeded the INL for example is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically Therefore for guaranteed performance at these update rates the absolute voltage on the analog input pins needs to be below AVpp 1 6 V Specification is not production tested but is supported by characterization data at initial product release 3 Following a calibration this error is in the order of the noise for the programmed gain and update rate selected Recalibration at any temperature removes these errors gt Full scale error applies to both positive and negative full scale and applies at the factory calibration conditions AVoo 4 V gain 1 TA 25 C 6 FS 3 0 are the four bits used in the mode register to select the output word rate 7 Digital inputs equal to DVop or GND with excitation currents and bias voltage generator disabled Rev B Page 5 of 32 AD7792 AD7793 TIMING CHARACTERISTICS AVpp 2 7 V to 5 25 V DVpp 2 7 V to 5 25 V GND 0 V Input Logic 0 0 V Input Logic 1 DVpp unless otherwise noted Table 2 Parameter Limit at Tmn Tmax B Version Unit Conditions Comments ts 100 ns min SCLK high pulse width ta 100 n
31. ased up to AVpp 2 The cold junction compensation is performed using a thermis tor in the diagram The on chip excitation current supplies the thermistor In addition the reference voltage for the cold junction measurement is derived from a precision resistor in series with the thermistor This allows a ratiometric measure ment so that variation of the excitation current has no effect on the measurement it is the ratio of the precision reference resistance to the thermistor resistance that is measured REFIN REFIN INTERNAL CLOCK AD7792 AD7793 04855 012 CLK Figure 20 Thermocouple Measurement Using the AD7792 AD7793 Rev B Page 28 of 32 AD7792 AD7793 TEMPERATURE MEASUREMENT USING AN RTD To optimize a 3 wire RTD configuration two identically matched current sources are required The AD7792 AD7793 which contain two well matched current sources are ideally suited to these applications One possible 3 wire configuration is shown in Figure 21 In this 3 wire configuration the lead resistances result in errors if only one current is used as the excitation current flows through RL1 developing a voltage error between AIN1 and AINI In the scheme outlined the second RTD current source is used to compensate for the error introduced by the excitation current flowing through RLI The second RTD current flows through RL2 Assuming RLI and RL2 are equal the leads would normally be of the same
32. continuous read mode the digital word can be read only once 1 Sample tested during initial release to ensure comp Ji own the time requifed for t Isink 1 6mA WITH DVpp 5V 100pA WITH DVpp 3V IsouRce 200HA WITH DVpp 5V 100pA WITH DVpp 3V Figure 2 Load Circuit for Timing Characterization 04855 002 Rev B Page 6 of 32 AD7792 AD7793 TIMING DIAGRAMS DOUT RDY 0 use t 1 gt t3 lt SCLK I t 04855 003 NOTES 1 1 2 INPUT O OUTPUT Figure 3 Read Cycle Timing Diagram SCLK I DIN 1 Rev B Page 7 of 32 AD7792 AD7793 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Stresses above those listed under Absolute Maximum Ratings Table 3 may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any Parameter Ratings h dit b oli ai AVoo to GND _0 3V to 7V ot er coni mons a ove t Oe ashe in the operational sections of this specification is not implied Exposure to absolute DVoo to GND 0 3Vto 7V A fi A maximum rating conditions for extended periods mav affect Analog Input Voltage to GND 0 3 V to AVoo 0 3 V device reliability Reference Input Voltage to GND 0 3 V to AVpo 0 3 V E ESD CAUTION Digital Input Voltage to GND 0 3 V to DVop 0 3 V ES Gal dci i n electrostatic discharge sensitive device Digital Output Voltage to GND
33. es of data 2 CLK Clock In Clock Out The internal clock can be made available at this pin Alternatively the internal clock can be disabled and the ADC can be driven by an external clock This allows several ADCs to be driven from a common clock allowing simultaneous conversions to be performed 3 CS Chip Select Input This is an active low logic input used to select the ADC CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating bp ice ta ardwi allowing the ADC to operate in 3 ith SCLK DIN and ed ith the device 4 ned ion Current Source The inte i re made available at 3 xcitation current sour ogram uffer O uA 210 pA or 1 mA Either IEXC1 or IEXC2 can be switched to this output 5 AIN1 Analog Input AIN1 is the positive terminal of the differential analog input pair AIN1 AIN1 6 AIN1 Analog Input AIN1 is the negative terminal of the differential analog input pair AIN1 AIN1 7 AIN2 Analog Input AIN2 is the positive terminal of the differential analog input pair AIN2 AIN2 8 AIN2 Analog Input AIN2 is the negative terminal of the differential analog input pair AIN2 AIN2 9 REFIN AIN3 Positive Reference Input Analog Input An external reference can be applied between REFIN and REFIN REFIN can lie anywhere between AVop and GND 0 1 V The nominal reference volt
34. ferent filter types depending on the output update rate so that the rejection of quantization noise and device noise is optimized When the update rate is from 4 17 Hz to 12 5 Hz a Sinc3 filter along with an averaging filter is used When the update rate is from 16 7 Hz to 39 Hz a modified Sinc3 filter is used This filter provides simultaneous 50 Hz 60 Hz rejection when the update rate equals 16 7 Hz A Sinc4 filter is used when the update rate is from 50 Hz to 242 Hz Finally an integrate only filter is used when the update rate equals 470 Hz AD7792 AD7793 Figure 13 to Figure 16 show the frequency response of the different filter types for several update rates DOUT RDY 04855012 dB 40 dB dB Rev B Page 20 of 32 MN TL 04855 018 0 20 40 60 80 100 120 FREQUENCY Hz Figure 13 Filter Profile with Update Rate 4 17 Hz 04855 019 Mini 0 20 40 60 80 100 120 160 180 200 FREQUENCY Hz Figure 14 Filter Profile with Update Rate 16 7 Hz 04855 020 0 500 1000 1500 FREQUENCY Hz Figure 15 Filter Profile with Update Rate 242 Hz 2000 2500 300 AD7792 AD7793 Ii Hl L IN 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 FREQUENCY Hz Figure 16 Filter Response at 470 Hz Update Rate DIGITAL INTERFACE The programmable functions of the AD7792 AD7793 a
35. gu ration register Therefore with an external 2 5 V reference the unipolar ranges are from 0 mV to 20 mV to 0 V to 2 5 V while the bipolar ranges are from 20 mV to 2 5 V When the in amp is active gain gt 4 the common mode voltage AIN AIN 2 must be greater than or equal to 0 5 V If the AD7792 AD7793 are operated with an external reference that has a value equal to AVpp the analog input signal must be limited to 9096 of Vrer gain when the in amp is active for correct operation BIPOLAR UNIPOLAR CONFIGURATION The analog input to the AD7792 AD7793 can accept either unipolar or bipolar input voltage ranges A bipolar input range does not imply that the part can tolerate negative voltages with respect to system GND Unipolar and bipolar signals on the AIN input are referenced to the voltage on the AIN input For example if AIN is 2 5 V and the ADC is configured for unipolar mode and a gain of 1 the input voltage range on the ATN pipis 2 If the alle is q e the affalog input e on Phesbipolar unipolar option is chosen by programming the U B bit in the configura tion register DATA OUTPUT CODING When the ADC is configured for unipolar operation the output code is natural straight binary with a zero differential input voltage resulting in a code of 00 00 a midscale voltage resulting in a code of 100 000 and a full scale input voltage resulting in a code of 111 111 The output code for any an
36. hen the gain equals 1 a calibration takes 2 conversion cycles to complete For higher gains 4 conversion cycles are required to perform the full scale calibration DOUT RDY goes high when the calibration is initiated and returns low when the calibration is complete The ADC is placed in idle mode following a calibration The measured full scale coefficient is placed in the full scale register of the selected channel Internal full scale calibrations cannot be performed when the gain equals 128 With this gain setting a system full scale calibration can be performed A full scale calibration is required each time the gain of a channel is changed to minimize the full scale error An internal full scale calibration can be performed at specified update rates only For gains of 1 2 and 4 an internal full scale calibration can be performed at any update rate However for higher gains internal full scale calibrations can be performed when the update rate is less than or equal to 16 7 Hz 33 2 Hz and 50 Hz only However the full scale error does not vary with update rate so a calibration at one update rate is valid for all update rates assuming the gain or reference source is not changed A system full scale calibration takes 2 conversion cycles to complete irrespective of the gain setting A system full scale calibration can be performed at all gains and all update rates If system offset calibrations are being performed along with sys
37. ically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data It is also set when the part is placed in power down mode The end of a conversion is indicated by the DOUT RDY pin also This pin can be used as an alternative to the status register for monitoring the ADC for conversion data SR6 ERR ADC Error Bit This bit is written to at the same time as the RDY bit Set to indicate that the result written to the ADC data register has been clamped to all Os or all 1s Error sources include overrange and underrange Cleared by a write operation to start a conversion SR5 to SRA 0 These bits are automatically cleared SR3 0 1 This bit is automatically cleared on the AD7792 and is automatically set on the AD7793 SR2 to SRO CH2 to CHO These bits indicate which channel is being converted by the ADC MODER RS2 RS1 The mode register is a 16 bit register from which data can be read or which can Ly i register is used to select the operating mode update rate and clock source Table 14 outlines the bit designations for the mode register MRO through MR15 indicate the bit locations MR denoting the bits are in the mode register MR15 denotes the first bit of the data stream The number in parentheses indicates the power on reset default status of that bit Any write to the setup register resets the modulator
38. igher gains the buffer is auto matically enabled The absolute input voltage range in buffered mode is restricted to a range between GND 100 mV and AVpp 100 mV When the gain is set to 4 or higher the in amp is enabled The absolute input voltage range when the in amp is active is restricted to a range between GND 300 mV and AVpp 1 1 V Take care in setting up the common mode voltage so that these limits are not exceeded to avoid degradation in linearity and noise performance The absolute input voltage in unbuffered mode includes the range between GND 30 mV and AVpp 30 mV as a result of being unbuffered The negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to GND INSTRUMENTATION AMPLIFIER Amplifying the analog input signal by a gain of 1 or 2 is performed digitally within the AD7792 AD7793 However when the gain equals 4 or higher the output from the buffer is applied to the input of the on chip instrumentation amplifier This low noise in amp means that signals of small amplitude can be gained within the AD7792 AD7793 while still maintaining excellent noise performance For example when the gain is set to 64 the rms noise is 40 nV typically which is equivalent to 21 bits effective resolution or 18 5 bits peak to peak resolution The AD7792 AD7793 can be programmed to have a gain of 1 2 4 8 16 32 64 and 128 using Bit G2 to Bit GO in the confi
39. ions of the layout differential commoiimod Rev B Page 26 of 32 AD7792 AD7793 The ground planes of the AD7792 AD7793 should be allowed to run under the AD7792 AD7793 to prevent noise coupling The power supply lines to the AD7792 AD7793 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs Avoid crossover of digital and analog signals Traces on opposite sides of the board should run at right angles to each other This reduces the effects of feedthrough through the board A microstrip technique is by far the best but it is not always possible with a double sided board In this technique the component side of the board is dedicated to ground planes and signals are placed on the solder side Good decoupling is important when using high resolution ADCs AVpp should be decoupled with 10 uF tantalum in parallel with 0 1 uF capacitors to GND DVpp should be decoupled with 10 uF tantalum in parallel with 0 1 uF capacitors to the systems DGND plane with the system s AGND to DGND connection being close to the AD7792 AD7793 To achieve the best from these decoupling components they should be placed as close as possible to the device ideally right up against
40. ions register determines whether the next operation is a read or write operation and to which register this operation takes place For read or write operations once the complete the interface returns to where it expects a write operation to the communications register This is the default state of the interface and on power up or after a reset the ADC is in this default state waiting for a write operation to the communications register In situations where the interface sequence is lost a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part Table 11 outlines the bit designations for the communications register CRO through CR7 indicate the bit location CR denoting the bits are in the communications register CR7 denotes the first bit of the data stream The number in parentheses indicates the power on reset default status of that bit subsequent read or write operation to the selected register is CR7 CR6 CR5 CR4 CR3 CR2 CR1 CRO WEN O R W O RS2 0 RS1 0 RSO 0 CREAD 0 0 0 0 0 Table 11 Communications Register Bit Designations Bit Location Bit Name Description CR7 CR6 CR5 to CR3 CR2 CR1 to CRO WEN RS2 to RSO CREAD Write Enable Bit A 0 must be written to this bit so that the write to the communications register actually occurs If a 1 is the first bit written the par
41. lar coding that is zero differential input results in 0x000000 output and a full scale differential input results in OXFFFFFF output Cleared by the user to enable bipolar coding Negative full scale differential input results in an output code of 0x000000 zero differential input results in an output code of 0x800000 and a positive full scale differential input results in an output code of OxFFFFFF CON11 BOOST This bit is used in conjunction with the VBIAS1 and VBIASO bits When set the current consumed by the bias voltage generator is increased This reduces its power up time CON10 to G2 to GO Gain Select Bits CON8 Written by the user to select the ADC input range as follows G2 G1 GO Gain ADC Input Range 2 5 V Reference 0 0 0 1 In amp not used 2 5V 0 0 1 2 In amp not used 1 25V 0 1 0 4 625 mV 0 1 1 8 312 5 mV 1 0 0 16 156 2 mV 1 0 1 32 78 125 mV 1 1 0 64 39 06 mV 1 1 1 128 19 53 mV Rev B Page 17 of 32 AD7792 AD7793 Bit Location Bit Name Description CON7 REFSEL Reference Select Bit The reference source for the ADC is selected using this bit REFSEL Reference Source 0 External Reference Applied between REFIN and REFIN 1 Internal Reference Selected CONG to 0 These bits must be programmed with a Logic 0 for correct operation CON5 CON4 BUF Configures the ADC for buffered or unbuffered mode of operation If cleared the ADC operates in unbuffered mode lowering
42. nt 400 nAN typ Input current varies with input voltage Average Input Current Drift 50 pA V C typ Normal Mode Rejection Internal Clock 50 Hz 60 Hz 65 dB min 80 dB typ 50 1 Hz 60 1 Hz FS 3 0 10105 50 Hz 80 dB min 90 dB typ 50 1 Hz FS 3 0 10015 60 Hz 90 dB min 100 dB typ 60 1 Hz FS 3 0 10005 External Clock 50 Hz 60 Hz 80 dB min 90 dB typ 50 1 Hz 60 1 Hz FS 3 0 10106 50 Hz 94 dB min 100 dB typ 50 1 Hz FS 3 0 10016 60 Hz 90 dB min 100 dB typ 60 1 Hz FS 3 0 10005 Common Mode Rejection DC 100 dB min AIN 1 V gain gain gt 4 50 Hz 60 HZ 100 dB min 50 1 Hz 60 1 Hz FS 3 0 10106 50 Hz 60 HZ 100 dB min 50 1 Hz FS 3 0 1001 5 60 1 Hz FS 3 0 1000 5 Rev B Page 3 of 32 AD7792 AD7793 Parameter AD7792B AD7793B Unit Test Conditions Comments REFERENCE Internal Reference Internal Reference Initial Accuracy 1 17 0 0196 V min max AVpp 4 V TA 25 C Internal Reference Drift 4 ppm C typ 15 ppm C max Power Supply Rejection 85 dB typ External Reference External REFIN Voltage 2 5 V nom REFIN REFIN REFIN Reference Voltage Range 0 1 V min AVop V max When Vere AVpo the differential input must be limited to 0 9 x Vrer gain if the in amp is active Absolute REFIN Voltage Limits GND 30 mV V min AVoo 30 mV V max Average Reference Input Current 400 nA V typ Average Reference Input Current 0 03 nA V C typ Drift
43. olution is calculated using the rms noise while the p p resolution is based on the p p noise The p p resolution represents the resolution for which there is no code flicker These numbers are typical and are rounded to the nearest LSB Table 5 Output RMS Noise uV vs Gain and Output Update Rate for the AD7792 and AD7793 Using an External 2 5 V Reference Update Rate Hz Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4 17 0 64 0 6 0 29 0 22 0 1 0 065 0 039 0 041 8 33 1 04 0 96 0 38 0 26 0 13 0 078 0 057 0 055 16 7 1 55 1 45 0 54 0 36 0 18 0 11 0 087 0 086 33 2 2 3 2 13 0 74 0 5 0 23 0 17 0 124 0 118 62 2 95 2 85 0 92 0 58 0 29 0 2 0 153 0 144 123 4 89 4 74 1 49 1 0 48 0 32 0 265 0 283 242 11 76 9 5 4 02 1 96 0 88 0 45 0 379 0 397 470 11 33 9 44 3 07 1 79 0 99 0 63 0 568 0 593 Table 6 Typical Resolution Bits vs Gain and Output Update Rate for the AD7793 Using an External 2 5 V Reference Update Rate Hz Gain of 1 8 Gain of 16 Gain Gain of 128 4 17 1 5 19 2 20 17 5 8 33 18 1 1 21 19 5 17 16 7 5 1 20 20 5 1 205 1 19 16 5 332 1 18 5 20 7 5 20 5 18 0 17 5 20 5 18 20 17 5 9 16 5 18 5 16 62 A 5 18 19 5 17 20 5 18 0 17 5 20 17 5 19 5 17 9 16 5 18 15 5 123 20 17 5 HU 19 5 17 9 16 5 19 5 17 19 16 5 18 15 5 17 14 5 242 18 5 16 8 15 5 18 15 5 da 5 18
44. operty of their respective owners FUNCTIONAL BLOCK DIAGRAM REFIN AIN3 REFIN AIN3 O GND b AVpp BAND GAP REFERENCE pe DOUT RDY amo OH SERIAL J AIN2 EL INTERFACE Bi DIN anz Q 34 sci INTERNAL AD7792 16 BIT CLOC AD7793 24 BIT 04855 001 CLK Figure 1 GENERAL DESCRIPTION The AD7792 AD7793 are low power low noise complete analog front ends for high precision measurement applications The AD7792 AD7793 contain a low noise 16 24 bit Y A ADC with three differential analog inputs The on chip low noise instrumentation amplifier means that signals of small ampli tude can be interfaced dir amp ctly t settifig o s is 40 equals 4 1 si The devices contain a precision low noise low drift internal band gap reference and can accept an external differential reference Other on chip features include programmable excitation current sources burnout currents and a bias voltage generator The bias voltage generator sets the common mode voltage of a channel to AVpp 2 gt update rate The devices can be operated with either the internal clock or an external clock The output data rate from the parts is software programmable and can be varied from 4 17 Hz to 470 Hz The parts operate with a power supply from 2 7 V to 5 25 V They consume a current of 400 uA typical and are housed in a 16 lead TSSOP package One Technology Way P O Box 9106 Norwood MA 0206
45. or to which data can be written This register is used to con figure the ADC for unipolar or bipolar mode enable or disable the buffer enable or disable the burnout currents select the gain and select the analog input channel Table 17 outlines the bit designations for the filter register CONO through CONI indicate the bit locations CON denotes that the bits are in the configuration register CON15 denotes the first bit of the data stream The number in parentheses indicates the power on reset default status of that bit CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8 VBIAS1 0 VBIASO O BO O U B 0 BOOST 0 G2 1 G1 1 G0 1 CON7 CON6 CON5 CONA CON3 CON2 CON1 CONO REFSEL 0 0 0 0 0 BUF 1 0 0 CH2 0 CH1 0 CHO 0 Table 17 Configuration Register Bit Designations Bit Location Bit Name Description CON15 to t Bias Volt Enable Theffegative termi f s car p to AVpp 2 These CON14 its are ith the boost bit AS1 VBIA C olt 0 0 Bias voltage generator disabled 0 1 Bias voltage connected to AIN1 1 0 Bias voltage connected to AIN2 1 1 Reserved CON13 BO Burnout Current Enable Bit When this bit is set to 1 by the user the 100 nA current sources in the signal path are enabled When BO 0 the burnout currents are disabled The burnout currents can be enabled only when the buffer or in amp is active CON12 U B Unipolar Bipolar Bit Set by user to enable unipo
46. perature Update Rate 16 7 Hz for AD7793 16 14 12 w 10 i o ul X g E 5 s o m o 6 6 o y a 2 5 7 8388482 8388520 8388560 8388600 8388640 8388680 8388720 8388750 1000 CODE LOAD CAPACITANCE nF Figure 7 Noise Distribution Histogram for AD7793 Figure 10 Bias Voltage Generator Power Up Time vs Load Capacitance Internal Reference Gain 64 Update Rate 16 7 Hz 3 0 Vpp 5V UPDATE RATE 16 6Hz Ta 25 C 20 27 2 ul o ul z 015 A z 10 n 8 z fe 1 0 0 5 0 3 0 i 2 0 12 0 8 04 0 04 08 12 16 20 0 05 10 15 20 25 30 35 40 45 50 MATCHING REFERENCE VOLTAGE V Figure 8 Excitation Current Matching 210 uA at Ambient Figure 11 RMS Noise vs Reference Voltage Gain 1 Temperature Rev B Page 13 of 32 AD7792 AD7793 ON CHIP REGISTERS The ADC is controlled and configured via a number of on chip registers which are described on the following pages In the following descriptions set implies a Logic 1 state and cleared implies a Logic 0 state unless otherwise stated COMMUNICATIONS REGISTER RS2 RS1 RSO 0 0 0 The communications register is an 8 bit write only register All communications to the part must start with a write operation to the communications register The data written to the communicat
47. re controlled using a set of on chip registers Data is written to these registers via the serial interface of the device read access to the on chip registers is also provided by this interface All communications with the device must start with a write to the communications register After power on or reset the device expects a write to its communications register The data written to this register determines whether the next operation is a read dB 04855 021 operation to the communications register followed by a write to the selected register A read operation from any other register except when continuous read mode is selected starts with a write to the communications register followed by a read operation from the selected register The serial interfaces of the AD7792 AD7793 consist of four signals C DIN SCLK and DOUT RDY The DIN line is used to transfer data into the on chip registers and DOUT RDY is used for accessing from the on chip registers SCLK is the serial clock input for the device and all data transfers either on DIN or DOUT RDY occur with respect to the SCLK signal The DOUT RDY pin operates as a data ready signal also the line going low when a new data word is available in the output register It is reset high when a read operation from the data register is complete It also goes high prior to the updating of the data register to indicate when not to read from the device to
48. rom any of the on chip data or control registers In addition DOUT RDY operates as a data ready pin going low to indicate the completion of a conversion If the data is not read after the conversion the pin goes high before the next update occurs The DOUT RDY falling edge can be used as an interrupt to a processor indicating that valid data is available With an external serial clock the data can be read using the DOUT RDY pin With CS low the data control word information is placed on the DOUT RDY pin on the SCLK falling edge and is valid on the SCLK rising edge 16 DIN Serial Data Input This serial data input is to the input shift register on the ADC Data in this shift register is transferred to the control registers within the ADC the register selection bits of the communications register identify the appropriate register ww BDI C com AD Rev B Page 10 of 32 AD7792 AD7793 OUTPUT NOISE AND RESOLUTION SPECIFICATIONS EXTERNAL REFERENCE Table 5 shows the output rms noise of the AD7792 AD7793 for some of the update rates and gain settings The numbers given are for the bipolar input range with an external 2 5 V reference These numbers are typical and are generated with a differential input voltage of 0 V Table 6 and Table 7 show the effective resolution with the output peak to peak p p resolution shown in parentheses for the AD7793 and AD7792 respectively It is important to note that the effective res
49. s min SCLK low pulse width Read Operation t 0 ns min CS falling edge to DOUT RDY active time 60 ns max DVpp 4 75 V to 5 25 V 80 ns max DVop 2 7 V to 3 6V t2 0 ns min SCLK active edge to data valid delay 60 ns max DVpp 4 75V to 5 25 V 80 ns max DVpp 2 7 V to 3 6V ts 6 10 ns min Bus relinquish time after CS inactive edge 80 ns max ts 0 ns min SCLK inactive edge to CS inactive edge t 10 ns min SCLK inactive edge to DOUT RDY high Write Operation ts 0 ns min CS falling edge to SCLK active edge setup time to 30 ns min Data valid to SCLK edge setup time tio 25 ns min Data valid to SCLK edge hold time tu 0 ns min CS rising edge to SCLK edge hold time tr tr 5 ns 1096 to 90 of DVod 2 See Figure 3 and 3 These numbers ar SCLK active edge is 5These numbers are derived from the measured time taken by the data output to change 0 5 V when loaded wi The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances 6 RDY returns high after a read of the ADC In single conversion mode and continuous conversion mode the same data can be read again if required while RDY is high although care should be taken to ensure that subsequent reads do not occur close to the next output update In
50. solution is calculated using the rms noise while the p p resolution is typical and are rounded to the nearest LSB calculated based on p p noise The p p resolution represents the resolution for which there is no code flicker These numbers are Table 8 Output RMS Noise uV vs Gain and Output Update Rate for the AD7792 and AD7793 Using the Internal Reference Update Rate Hz Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4 17 0 81 0 67 0 32 0 2 0 13 0 065 0 04 0 039 8 33 1 18 1 11 0 41 0 25 0 16 0 078 0 058 0 059 16 7 1 96 1 72 0 55 0 36 0 25 0 11 0 088 0 088 33 2 2 99 2 48 0 83 0 48 0 33 0 17 0 13 0 12 62 3 6 3 25 1 03 0 65 0 46 0 2 0 15 0 15 123 5 83 5 01 1 69 0 96 0 67 0 32 0 25 0 26 242 11 22 8 64 2 69 1 9 1 04 0 45 0 35 0 34 470 12 46 10 58 4 58 2 1 27 0 63 0 50 0 49 Table 9 Typical Resolution Bits vs Gain and Output Update Rate for the AD7793 Using the Internal Reference Update Rate Hz Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4 17 21 5 19 20 5 18 21 18 5 20 5 18 20 17 5 20 17 5 20 17 5 19 16 5 8 33 21 18 5 20 17 8 20 17 20 17 5 20 17 5 18 15 5 16 7 5 17 19 5417 19 16 17 5 15 33 2 l 9 16 19 16 5 ika 1 17 14 5 62 5 8 5 19 16 18 5 55 1 17 14 5 123 18 5 16 18 15 5 18 5 16 18 15 5 17 5 15 18 15 5 17 4 5 16
51. ster different default coefficients The coefficients are different depending on whether the internal reference or an external reference is selected The default value is automatically overwritten if an internal or system full scale calibration is initiated by the user or the full scale register is written to Rev B Page 19 of 32 AD7792 AD7793 ADC CIRCUIT INFORMATION OVERVIEW The AD7792 AD7793 are low power ADCs that incorporate a X A modulator a buffer reference in amp and an on chip digital filter intended for the measurement of wide dynamic range low frequency signals such as those in pressure transducers weigh scales and temperature measurement applications The part has three differential inputs that can be buffered or unbuffered The device can be operated with the internal 1 17 V reference or an external reference can be used Figure 12 shows the basic connections required to operate the part GND AVpp REFIN REFIN BAND GAP 3 l REFERENCE gt THERMOCOUPLE JUNCTION R lt Rc DIN INTERNAL Aoo CLOCK CLK Figure 12 Basic Connection Diagram The output rate of the AD7792 AD7793 fa mable The allowabl settling times ar the major functioff of 60 Hz rejection is optimized when the update rate equals 16 7 Hz or less as notches are placed at both 50 Hz and 60 Hz with these update rates See Figure 14 The AD7792 AD7793 use slightly dif
52. t does not clock on to subsequent bits in the register It stays at this i Cte s bit 0 is written to the WEN bit re loaded to gates that the Next operationis a i indicates that the next operation is a read e designated register Register Address Bits These address bits are used to select which of the ADC s registers are being selected during this serial interface communication See Table 12 Continuous Read of the Data Register When this bit is set to 1 and the data register is selected the serial interface is configured so that the data register can be continuously read For example the contents of the data register are placed on the DOUT pin automatically when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete The communications register does not have to be written to for data reads To enable continuous read mode the instruction 01011100 must be written to the communications register To exit the continuous read mode the instruction 01011000 must be written to the communications register while the RDY pin is low While in continuous read mode the ADC monitors activity on the DIN line so that it can receive the instruction to exit continuous read mode Additionally a reset occurs if 32 consecutive 1s are seen on DIN Therefore DIN should be held low in continuous read mode until an instruction is to be written to the device These bits must be programmed to Logic 0 for correct operation
53. t is unbuffered therefore excessive R C source impedances introduce gain errors The reference voltage REFIN REFIN REFIN is 2 5 V nominal but the AD7792 AD7793 are functional with reference voltages from 0 1 V to AVpp In applications where the exci tation voltage or current for the transducer on the analog input also drives the reference voltage for the part the effect of the low frequency noise in the excitation source is removed because the application i is ratiometric If the AD7792 AD7793 3 noise reference sotirees for the AD7792 AD7793 incide the ADR381 iud ADR391 which are low noise low power references Also note that the reference inputs provide a high impedance dynamic load Because the input impedance of each reference input is dynamic resistor capacitor combinations on these inputs can cause dc gain errors depending on the output impedance of the source that is driving the reference inputs Reference voltage sources like those recommended above such as ADR391 typically have low output impedances and are therefore tolerant to having decoupling capacitors on REFIN without introducing gain errors in the system Deriving the reference input voltage across an external resistor means that the reference input sees a significant external source impedance External decoupling on the REFIN pins is not recommended in this type of circuit configuration RESET The circuitry and serial interface of the AD7792
54. tem full scale calibrations the offset calibration should be performed before the system full scale calibration is initiated GROUNDING AND LAYOUT ofithe ADC are alog m on of the part removes conimon mode noise on these inputs The digital filter provides rejection of broadband noise on the power supply except at integer multiples of the modulator sampling frequency The digital filter also removes noise from the analog and reference inputs provided that these noise sources do not saturate the analog modulator As a result the AD7792 AD7793 are more immune to noise interference than a conventional high resolution converter However because the resolution of the AD7792 AD7793 is so high and the noise levels from the AD7792 AD7793 are so low care must be taken with regard to grounding and layout The printed circuit board that houses the AD7792 AD7793 should be designed such that the analog and digital sections are separated and confined to certain areas of the board A mini mum etch technique is generally best for ground planes because it provides the best shielding It is recommended that the GND pins of the AD7792 AD7793 be tied to the AGND plane of the system In any layout it is important to keep in mind the flow of currents in the system ensuring that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations Avoid forcing digital currents to flow through the AGND sect
55. that signals close to GND or AV are converted accurately The bias voltage generator is controlled using the VBIASI and VBIASO bits in conjunction with the boost bit in the configura tion register The power up time of the bias voltage generator is dependent on the load capacitance To accommodate higher load capacitances the AD7792 AD7793 have a boost bit When this bit is set to 1 the current consumed by the bias voltage generator increases so that the power up time is considerably reduced Figure 10 shows the power up time when boost equals O and 1 for different load capacitances The current consumption of the AD7792 AD7793 increases by 40 uA when the bias voltage generator is enabled and boost equals 0 With the boost function enabled the current consumption increases by 250 HA REFERENCE The AD7792 AD7793 have an embedded 1 17 V reference that can be used to supply the ADC or an external reference can be applied The embedded reference is a low noise low drift reference the drift being 4 ppm C typically For external references the ADC has a fully differential input capability for the channel The reference source for the AD7792 AD7793 is selected using the REFSEL bit in the configuration register When the internal reference is selected it is internally con nected to the modulator It is not available on the REFIN pins The common mode range for these differential inputs is from GND to AVpp The reference inpu
56. the device All logic chips should be decoupled with 0 1 uF ceramic capacitors to DGND ww BDI C com AD Rev B Page 27 of 32 AD7792 AD7793 APPLICATIONS INFORMATION The AD7792 AD7793 provide a low cost high resolution analog to digital function Because the analog to digital function is provided by a X A architecture the parts are more immune to noisy environments making them ideal for use in sensor measurement and industrial and process control applications TEMPERATURE MEASUREMENT USING A THERMOCOUPLE Figure 20 outlines a connection from a thermocouple to the AD7792 AD7793 In a thermocouple application the voltage generated by the thermocouple is measured with respect to an absolute reference so the internal reference is used for this conversion The cold junction measurement uses a ratiometric configuration so the reference is provided externally Because the signal from the thermocouple is small the AD7792 AD7793 are operated with the in amp enabled to THERMOCOUPLE JUNCTION R REFIN GND AVpp BOE amplify the signal from the thermocouple As the input channel is buffered large decoupling capacitors can be placed on the front end to eliminate any noise pickup that may be present in the thermocouple leads The AD7792 AD7793 have a reduced common mode range with the in amp enabled so the bias voltage generator provides a common mode voltage so that the voltage generated by the thermocouple is bi

ANALOG DEVICES AD7793 handbook

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