ANALOG DEVICES AD7400A Manual
Contents
1. UL CSA VDE Recognized Under 1577 Approved under CSA Component Certified according to DIN VVDE V 0884 10 Component Recognition Program Acceptance Notice 5A VDE V 0884 10 2006 12 3750 V rms isolation voltage Reinforced insulation per CSA 60950 1 03 and Reinforced insulation per DIN V VDE V 0884 10 IEC 60950 1 630 V rms maximum working voltage VDE V 0884 10 2006 12 891 V peak File E214100 File 205078 File 2471900 4880 0001 In accordance with UL 1577 each AD7400A is proof tested by applying an insulation test voltage 24500 V rms for 1 sec current leakage detection limit 7 5 pA In accordance with DIN V VDE V 0884 10 each AD7400A is proof tested by applying an insulation test voltage 21671 V peak for 1 sec partial discharge detection limit 5 pC Rev A Page 5 of 20 AD7400A DIN V VDE V 0884 10 VDE V 0884 10 INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data Maintenance of the safety data is ensured by means of protective circuits Table 5 Parameter Symbol Characteristic Unit INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage lt 300 V rms Ito IV For Rated Mains Voltage x 450 V rms Ito Il For Rated Mains Voltage lt 600 V rms Ito Il CLIMATIC CLASSIFICATION 40 105 21 POLLUTION DEGREE DIN VDE 0110 Table 1 2 MAXIMUM WORKING INSULATION VOLTAGE Viorm 891 V peak INPUT TO OUTPUT TE2. ORDERING GUIDE Model Temperature Range Package Description Option AD7400AYNSZ 40 C to 125 C 8 Lead DIP Style Surface Mount Package With Gull Wing Leads PDIP_SMD NS 8 AD7400AYRWZ 40 C to 125 C 16 Lead Standard Small Outline Package SOIC_W RW 16 AD7400AYRWZ RL 40 C to 125 C 16 Lead Standard Small Outline Package SOIC W RW 16 EVAL AD7400AEDZ Standalone Evaluation Board EVAL CED1Z Development Board ZZ RoHS Compliant Part Rev A Page 18 of 20 AD7400A NOTES Rev A Page 19 of 20 AD7400A NOTES 2008 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D07077 0 9 08 A DEVICES www analo g com Rev A Page 20 of 20
3. Rev A Page 8 of 20 AD7400A TYPICAL PERFORMANCE CHARACTERISTICS Ta 25 C using 20 kHz brickwall filter unless otherwise noted 110 100 90 80 70 T T S 60 kJ x a Z 50 S a o 40 30 20 Vpp1 Vppz 5V 10 NO DECOUPLING CAPACITOR VnippLE 200mV SINE WAVE ON Vpp 0 100 1k 10k 100k 1M 10M E 50 100 150 200 250 300 350 SUPPLY RIPPLE FREQUENCY Hz B INPUT AMPLITUDE mV B Figure 7 PSRR vs Supply Ripple Frequency Without Supply Decoupling Figure 10 SINAD vs Vin 1 MHz Filter Used Vint 200mV TO 200mV a o a E a x S 5 o z a 0 500 1000 1500 2000 2500 3000 3500 4000 8 0 10 000 20 000 30 000 40 000 50 000 60 000 INPUT FREQUENCY Hz E CODE B Figure 8 SINAD vs Analog Input Frequency for Various Supply Voltages Figure 11 Typical DNL 200 mV Range Using Sinc Filter 256 Decimation Rate 0 0 8 8192 POINT FFT Vint 200mV TO 200mV 20 fin 35Hz Vin 0V SINAD 79 6991dB 0 6 40 THD 92 6722dB DECIMATION BY 256 OA 60 _ a 80 o g E 100 E o ul 120 3 0 2 140 04 160 180 5 0 6 e 0 2 4 6 8 10 12 14 16 18 20 amp 0 10 000 20 000 30 000 40 000 50 000 60 000 FREQUENCY kHz CODE E Figure 9 Typical F
4. diagram of the analog input is shown in Figure 23 A signal source driving the analog input must be able to provide the charge onto the sampling capacitors every half MCLKOUT cycle and settle to the required accuracy within the next half cycle 2pF 2pF 7077 027 MCLKOUT 2a 98 eA os Figure 23 Analog Input Equivalent Circuit Because the AD7400A samples the differential voltage across its analog inputs low noise performance is attained with an input circuit that provides low common mode noise at each input The amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the AD7400A When a capacitive load is switched onto the output of an op amp the amplitude drops momentarily The op amp tries to correct the situation and in the process hits its slew rate limit This nonlinear response which can cause excessive ringing can lead to distortion To remedy the situation a low pass RC filter can be connected between the amplifier and the input to the AD7400A The external capacitor at each input aids in supplying the current spikes created during the sampling process and the resistor isolates the op amp from the transient nature of the load The recommended circuit configuration for driving the differential inputs to achieve best performance is shown in Figure 24 A capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by o
5. FREE 13 Differential Inputs sees 14 Current Sensing Applications sse 14 Voltage Sensing Applications sse 14 Digital Filters ansia 15 Applications Information eene 17 Grounding and Layout essent 17 Evaluating the AD7400A Performance e 17 Insulation T3fetinie zeiten ertet thao 17 Outline Dimensions Ordering Guide ion cda Rev A Page 2 of 20 SPECIFICATIONS AD7400A Vppi 4 5 V to 5 5 V Vom 3 V to 5 5 V Vint 200 mV to 200 mV except where specified and Vm 0 V single ended Ta 40 C to 125 C except where specified fucix 10 MHz tested with Sinc filter 256 decimation rate as defined by Verilog code unless otherwise noted Table 1 Y Version Parameter Min Typ Max Unit Test Conditions Comments STATIC PERFORMANCE Resolution 16 Bits Filter output truncated to 16 bits Integral Nonlinearity 2 12 LSB Vin 200 mV Ta 40 C to 125 C 4 16 LSB Vin 250 mV Ta 40 C to 85 C 4 22 LSB Vin 250 mV Ta 40 C to 125 C Differential Nonlinearity 0 9 LSB Guaranteed no missing codes to 16 bits Offset Error 50 500 uV Offset Drift vs Temperature 1 5 4 uV C 40 C to 125 C Offset Drift vs Voo1 120 uV V Gain Error 15 mV 40 C to 85 C 2 mV 40 C to 125 C Gain Error Drift vs temperature 23 uV C 40 C to 125 C G
6. an appropriate digital filter The serial I O can use a 5 V or a3 V supply Vor The serial interface is digitally isolated High speed CMOS combined with monolithic air core transformer technology means the on chip isolation provides outstanding performance characteristics superior to alternatives such as optocoupler devices The part contains an on chip reference and has an operating temperature range of 40 C to 125 C The AD7400A is offered in an 8 lead surface mount PDIP with gull wing leads and a 16 lead SOIC package Protected by U S Patents 5 952 849 6 873 065 and 7 075 329 Other patents are pending FUNCTIONAL BLOCK DIAGRAM Vppi CONTROL LOGIC 1 1 Rev A Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners UPDATE ENCODE Figure 1 Vpp2 AD7400A C MCLKOUT WATCHDOG wa D 07077 001 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2008 Analog Devices Inc All rights reserved AD7400A TABLE OF CONTEN
7. frequency t 40 ns max Data access time after MCLK rising edge t 10 ns min Data hold time after MCLK rising edge ta 0 4 X tmcLkouT ns min Master clock low time ta 0 4 X tmcLkouT ns min Master clock high time 1 Sample tested during initial release to ensure compliance Mark space ratio for clock output is 40 60 to 60 40 Measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross 0 8 V or 2 0 V TO OUTPUT PIN ho 07077 002 Figure 2 Load Circuit for Digital Output Timing Specifications at a m MCLKOUT i j i T 1 I ti gt t2 a pat Figure 3 Data Timing 07077 003 Rev A Page 4 of 20 INSULATION AND SAFETY RELATED SPECIFICATIONS AD7400A Table 3 Parameter Symbol Value Unit Conditions Input to Output Momentary Withstand Voltage Viso 3750 min Vrms 1 minute duration Minimum External Air Gap Clearance L 101 7 46 min mm Measured from input terminals to output terminals shortest distance through air Minimum External Tracking Creepage L 102 8 1 min mm Measured from input terminals to output terminals shortest distance path along body Minimum Internal Gap Internal Clearance 0 017 min mm Insulation distance through insulation Tracking Resistance Comparative Tracking Index CTI gt 175 V DIN IEC 112 VDE 0303 Part 1 Isolation Group Illa Material group DIN VDE 0110 1 89 Table 1 REGULATORY INFORMATION Table 4
8. mV ideally results in a stream of all 1s This is the absolute full scale range of the AD7400A while 250 mV is the specified full scale range as shown in Table 9 Table 9 Analog Input Range Analog Input Voltage Input Full Scale Range 640 mV Positive Full Scale 320 mV Positive Typical Input Range 250 mV Positive Specified Input Range 200 mV Zero 0 mV Negative Specified Input Range 200 mV Negative Typical Input Range 250 mV Negative Full Scale 320 mV To reconstruct the original information this output needs to be digitally filtered and decimated A Sinc filter is recommended because this is one order higher than that of the AD7400A modulator If a 256 decimation rate is used the resulting 16 bit word rate is 39 KHz assuming a 10 MHz internal clock frequency Figure 21 shows the transfer function ofthe AD7400A relative to the 16 bit output 65535 53248 SPECIFIED RANGE ADC CODE 320mV 200mv 200mV 320mV 07077 020 ANALOG INPUT Figure 21 Filtered and Decimated 16 Bit Transfer Characteristic NONISOLATED 5V 3V 07077 018 THIS FILTER IS IMPLEMENTED WITH AN FPGA OR DSP Figure 22 Typical Application Circuit Rev A Page 13 of 20 AD7400A DIFFERENTIAL INPUTS The analog input to the modulator is a switched capacitor design The analog signal is converted into charge by highly linear sampling capacitors A simplified equivalent circuit
9. 0 250 6 35 0 372 9 45 0 246 6 25 4 tU o vm 0 300 7 62 REF 0 134 3 40 0 065 1 651 0 135 3 43 0 130 3 30 REF ji REF 0 126 3 20 0 012 0 305 0 010 0 245 L Lad 0 008 0 203 0 037 0 94 E 0 012 0 303 Ji 0 035 0 89 5 0 100 2 54 0 004 0 303 Le 0 033 0 84 0 a 1 118 0 053 1 35 0 040 1 016 0 051 1 30 0 036 0 915 0 049 1 25 NOTE THAT THIS IS A PDIP CONVERTED TO SMD CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCHES EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 32 8 Lead DIP Style Surface Mount Package With Gull Wing Leads PDIP_SMD NS 8 Dimensions shown in inches and millimeters 090507 A 10 50 0 4134 10 10 0 3976 7 60 0 2992 7 40 0 2913 10 65 0 4193 10 00 0 3937 1 27 0 0500 0 75 0 0295 yp BSC 2 65 0 1043 7 D 0 25 0 0098 0 30 0 0118 2 35 0 0925 5 0 10 0 0039 AP v3 COPLANARITY y ol le 0 10 0 sit 0 51 0 0201 10201 BEC dd Dan 1 27 0 0500 0 31 0 0122 0 20 0 0079 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 013 AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 032707 B Figure 33 16 Lead Standard Small Outline Package SOIC_W Wide Body RW 16 Dimensions shown in millimeters and inches
10. A reg 23 0 diff2 reg 23 0 diff3 reg 23 0 diffl d reg 23 0 diff2 d reg 15 0 DATA reg 7 0 word count reg word clk reg init Perform the Sinc ACTION always 8 mdatal if mdatal 0 ip datal lt 0 to a 1 for 2 s comp else change from a 0 ip datal lt 1 ACCUMULATOR INTEGRATOR Perform the accumulation IIR at the speed of the modulator MCLKOUT IP DATA1 07077 021 Figure 26 Accumulator Z one sample delay MCLKOUT modulators conversion bit rate always 86 negedge mclk1 or posedge reset if reset begin initialize acc registers on reset accl lt 0 acc2 lt 0 acc3 lt 0 end else begin perform accumulation process accl lt accl ip_datal acc2 lt acc2 accl acc3 lt acc3 acc2 end DECIMATION STAGE MCLKOUT WORD_CLK El always posedge mclk1 or posedge reset if reset word_count lt 0 else word_count lt word_count 1 always word count word clk lt word_count 7 Rev A Page 15 of 20 AD7400A DIFFERENTIATOR including decimation stage Perform the differentiation stage FIR at a lower speed 4 DIFF1 4 DIFF2 DIFF3 ACC3 07077 022 WORD CLK Figure 27 Differentiator Z one sample delay WORD CLK output word rate xf always posedge word_clk or posedge reset if reset begin acc3_d2 lt 0 diffl_d lt 0 diff2_d lt diffl lt 0 dif
11. ANALOG DEVICES FEATURES 10 MHz clock rate Second order modulator 16 bits no missing codes 2 LSB INL typical at 16 bits 1 5 uV C typical offset drift On board digital isolator On board reference 250 mV analog input range Low power operation 15 5 mA typical at 5 5 V 40 C to 125 C operating range 8 lead surface mount PDIP package with gull wing leads and 16 lead SOIC package AD7401A external clock version in 16 lead SOIC Safety and regulatory approvals UL recognition 3750 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884 10 VDE V 0884 10 2006 12 Viorm 891 V peak APPLICATIONS AC motor controls Shunt current monitoring Data acquisition systems Analog to digital and opto isolator replacements Isolated Sigma Delta Modulator AD7400A GENERAL DESCRIPTION The AD7400A is a second order X A modulator that converts an analog input signal into a high speed 1 bit data stream with on chip digital isolation based on Analog Devices Inc iCoupler technology The AD7400A operates from a 5 V power supply and accepts a differential input signal of 250 mV 320 mV full scale The analog input is sampled continuously by the analog modulator eliminating the need for external sample and hold circuitry The input information is contained in the output stream as a density of ones with a data rate of 10 MHz The original information can be reconstructed with
12. FT X200 mV Range Figure 12 Typical INL 200 mV Range Using Sinc Filter 256 Decimation Rate Using Sinc Filter 256 Decimation Rate Rev A Page 9 of 20 AD7400A OFFSET uV GAIN 0 20 TEMPERATURE C Figure 13 Offset Drift vs Temperature 0 20 45 35 25 15 5 5 15 25 35 45 55 65 75 85 95 105 TEMPERATURE C Ipp2 mA 07077 012 07077 032 CMRR dB Figure 14 Gain Error Drift vs Temperature for Various Supply Voltages Ipp1 mA 11 0 125 C f 85 C 10 5 10 0 iD a 25 C 40 C 9 0 8 5 0 33 0 21 0 09 0 03 0 15 Vpp2 Vpp1 0 27 Vin DC INPUT VOLTAGE V Figure 15 lov vs Vin at Various Temperatures 5V 0 39 NOISE mV 07077 013 Rev A Page 10 of 20 125 C Vpp2 Vpp1 5V 04 03 02 0 1 0 0 1 0 2 0 3 0 4 Vin DC INPUT VOLTAGE V Figure 16 Ipp2 vs Vin at Various Temperatures 100 1k 10k 100k 1M 10M COMMON MODE RIPPLE FREQUENCY Hz Figure 17 CMRR vs Common Mode Ripple Frequency BANDWI Vin DC INPUT V Figure 18 RMS Noise Voltage vs Vin DC Input 07077 014 07077 015 07077 017 MC
13. LKOUT MHz o eo e o e h te N o o o o o o oo 10 O 10 10 10 Q 10 QY 10 an I v NOT HOH OF 0 o TEMPERATURE C Figure 19 MCLKOUT vs Temperature for Various Supplies 07077 024 Rev A Page 11 of 20 AD7400A AD7400A TERMINOLOGY Differential Nonlinearity Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC Integral Nonlinearity Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function The endpoints of the transfer function are specified negative full scale 250 mV Vin Vis Code 7169 and specified positive full scale 250 mV Vin Vin Code 58 366 for the 16 bit level Offset Error Offset is the deviation of the midscale code Code 32 768 for the 16 bit level from the ideal Vin Vm that is 0 V Gain Error Gain error includes both positive full scale gain error and negative full scale gain error Positive full scale gain error is the deviation of the specified positive full scale code 58 366 for the 16 bit level from the ideal Vi Vm 250 mV after the offset error is adjusted out Negative full scale gain error is the deviation of the specified negative full scale code 7169 for the 16 bit level from the ideal Vin V
14. ST VOLTAGE METHOD B1 Viorm X 1 875 Ver 100 Production Test tm 1 sec Partial Discharge lt 5 pC Ven 1671 V peak INPUT TO OUTPUT TEST VOLTAGE METHOD A Ver After Environmental Test Subgroup 1 1426 V peak Viorm X 1 6 Ver tm 60 sec Partial Discharge lt 5 pC After Input and or Safety Test Subgroup 2 Safety Test Subgroup 3 1069 V peak Viorm X 1 2 Ver tm 60 sec Partial Discharge lt 5 pC HIGHEST ALLOWABLE OVERVOLTAGE TRANSIENT OVERVOLTAGE tra 10 sec Vir 6000 V peak SAFETY LIMITING VALUES MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE ALSO SEE Figure 4 Case Temperature Ts 150 C Side 1 Current ls 265 mA Side 2 Current Is2 335 mA INSULATION RESISTANCE AT Ts Vio 500 V Rs gt 10 Q SAFETY LIMITING CURRENT mA 07077 026 CASE TEMPERATURE C Figure 4 Thermal Derating Curve Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884 10 Rev A Page 6 of 20 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted All voltages are relative to their respective ground Table 6 Parameter Rating Von to GND 0 3 V to 6 5V Vpoz to GND2 0 3 V to 6 5 V Analog Input Voltage to GND 0 3 V to Voo1 0 3 V Output Voltage to GND2 0 3 V to Vop2 0 3 V Input Current to Any Pin Except Supplies 10mA Operating Temperature Range 40 C to 125 C Storage Temperature Range 65 C to 150 C Junction Temperature 150 C PDIP Package O
15. TS Features oce nO Ren a OOS 1 Applications eiii tenida 1 General DeSCTIp viscosidad 1 Functional Block Diagram seen 1 Revision History serey nnt a ERR E ER S 2 Specifications ete epit tet a tere 3 Timing Specifications c scaissessssisecssosieonssossesesserinocdsonionnscondesessonses 4 Insulation and Safety Related Specifications 5 Regulatory Information eene 5 DIN V VDE V 0884 10 VDE V 0884 10 Insulation Characteristics cioe iterato tereti 6 Absolute Maximum Ratings eee 7 ESD Cautiori coiere i ei ee i tyi 7 Pin Configuration and Function Descriptions 8 Typical Performance Characteristics sse 9 REVISION HISTORY 9 08 Rev 0 to Rev A Added 16 Lead SOIC sse Universal Changes to General Description Section sss 1 Changes to Table 1 Test Conditions Comments Column 3 Changes to Timing Specifications Table Summary 4 Changes to Table 4 Note 2 sse 5 Added Figure 6 Renumbered Sequentially 8 Changes to Terminology Section sees 12 Updated Outline Dimensions m Changes to Ordering Guide sse 5 08 Revision 0 Initial Version Terminology eene ds 12 Theory Of Operation iiie e e etel ib iode 13 Circuit Information 4 eher tante ette tenente ebbe edad 13 Analog Input terr ee IRR RODA
16. ain Error Drift vs Vooi 110 uV V ANALOG INPUT Input Voltage Range 250 4250 mV For specified performance full range 320 mV Dynamic Input Current 7 8 uA Vint 400 mV Vn 20V 9 10 pA Vin 500 mV Vin 0 V 0 5 uA Vint Vin 0V Input Capacitance 10 pF DYNAMIC SPECIFICATIONS Vint 35 Hz Signal to Noise and Distortion SINAD Ratio 70 78 dB Vin 200 mV 68 78 dB Vint 250 mV Signal to Noise Ratio SNR 73 80 dB Vin 200 mV 72 80 dB Vint 250 mV Total Harmonic Distortion THD 84 dB Vin 200 mV 82 dB Vint 250 mV Peak Harmonic or Spurious Noise SFDR 86 dB Vin 200 mV 84 dB Vint 250 mV Effective Number of Bits ENOB 11 5 12 5 Bits Vin 200 mV 11 12 5 Bits Vint 250 mV Isolation Transient Immunity 25 30 kV us LOGIC OUTPUTS Output High Voltage Vou Vop2 0 1 V lo 200 pA Output Low Voltage Vo 0 4 V lo 200 uA POWER REQUIREMENTS Vppi 4 5 5 5 V Vpp2 3 5 5 V lppi 11 13 mA Voo 5 5 V loo2 4 5 6 mA Voo2 5 5 V 3 3 5 mA Vpo2 3 3 V 1 All voltages are relative to their respective ground See the Terminology section 3 See Figure 15 1 See Figure 16 Rev A Page 3 of 20 AD7400A TIMING SPECIFICATIONS Von 4 5 V to 5 5 V Vom 3 V to 5 5 V Ta 40 C to 125 C except where specified Table 2 Parameter Limit at tmn tax Unit Description fucikour 10 MHz typ Master clock output frequency 9 11 MHz min MHz max Master clock output
17. cuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev A Page 7 of 20 AD7400A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5 8 Lead PDIP Pin Configuration Table 8 Pin Function Descriptions 07077 004 07077 104 NC NO CONNECT Figure 6 16 Lead SOIC Pin Configuration Pin No PDIP SOIC Mnemonic Description 1 1 7 Voo1 Supply Voltage 4 5 V to 5 5 V This is the supply voltage for the isolated side of the AD7400A and is relative to GND 2 2 Vin Positive Analog Input Specified range of 250 mV 3 3 Vin Negative Analog Input Normally connected to GND N A 4to6 10 12 15 NC No Connect 4 8 GND Ground 1 This is the ground reference point for all circuitry on the isolated side 5 9 16 GND Ground 2 This is the ground reference point for all circuitry on the nonisolated side 6 11 MDAT Serial Data Output The single bit modulator output is supplied to this pin as a serial data stream The bits are clocked out on the rising edge of the MCLKOUT output and are valid on the following MCLKOUT rising edge 7 13 MCLKOUT Master Clock Logic Output 10 MHz Typical The bit stream from the modulator is valid on the rising edge of MCLKOUT 8 14 Vpp2 Supply Voltage 3V to 5 5 V This is the supply voltage for the nonisolated side and is relative to GND
18. e system accuracy as illustrated in Figure 25 However there is a tradeoff between accuracy and throughput rate and therefore higher decimation rates result in lower throughput solutions A Sinc filter is recommended for use with the AD7400A This filter can be implemented on an FPGA or a DSP Suzy e 1 z where DR is the decimation rate 90 SINC 80 19 SINC2 60 m 50 E E 40 o 1 an SINC 20 10 0 1 10 100 1k 07077 025 DECIMATION RATE Figure 25 SNR vs Decimation Rate for Different Filter Types The following Verilog code provides an example of a Sinc filter implementation on a Xilinx Spartan II 2 5 V FPGA This code can possibly be compiled for another FPGA such as an Altera device Note that the data is read on the negative clock edge in this case although it can be read on the positive edge if preferred Figure 25 shows the effect of using different decimation rates with various filter types Data is read on negative clk edge module DEC256SINC24B mdatal mclki1 reset DATA used to clk filter used to reset filter ip data to be input mclkl input reset input mdatal filtered output 15 0 DATA filtered op integer location integer info file reg 23 0 ip datal reg 23 0 acci reg 23 0 acc2 reg 23 0 acc3 reg 23 0 acoes di reg 23 0 acc3 d2 reg 23 0 diff1 AD7400
19. f2 lt 0 diff3 lt 0 end else begin diffl lt acc3 acc3_d2 diff2 lt diffl diffl d diff3 diff2 diff2 d acc3 d2 lt acc3 diffl d lt diffl diff2 d lt diff2 end Clock the Sinc output into an output register WORD CLK 07077 023 Figure 28 Clocking Sinc Output into an Output Register WORD CLK output word rate af always posedge word_clk begin DATA 15 lt diff3 23 DATA 14 lt diff3 22 DATA 13 lt diff3 21 DATA 12 lt diff3 20 DATA 11 lt diff3 19 DATA 10 lt diff3 18 DATA 9 lt diff3 17 DATA 8 lt diff3 16 DATA 7 lt diff3 15 DATA 6 lt diff3 14 DATA 5 lt diff3 13 DATA 4 lt diff3 12 DATA 3 lt diff3 11 DATA 2 lt diff3 10 DATA 1 lt diff3 9 DATA 0 lt diff3 8 end endmodule Rev A Page 16 of 20 APPLICATIONS INFORMATION GROUNDING AND LAYOUT Supply decoupling with a value of 100 nF is strongly recommended on both Vpn and Vom Decoupling on one or both Vp pins does not significantly affect performance In applications involving high common mode transients ensure that board coupling across the isolation barrier is minimized Furthermore the board layout should be designed so that any coupling that occurs equally affects all pins on a given component side Failure to ensure this may cause voltage differentials between pins to exceed the absolute maximum ratings of the de
20. in 250 mV after the offset error is adjusted out Gain error includes reference error Signal to Noise and Distortion SINAD Ratio This ratio is the measured ratio of signal to noise and distortion at the output of the ADC The signal is the rms amplitude of the fundamental Noise is the sum of all nonfundamental signals up to half the sampling frequency fs 2 excluding dc The ratio is dependent on the number of quantization levels in the digitization process the more levels the smaller the quantization noise The theoretical signal to noise and distortion ratio for an ideal N bit converter with a sine wave input is given by Signal to Noise and Distortion 6 02N 1 76 dB Therefore for a 12 bit converter SINAD is 74 dB Effective Number of Bits ENOB The ENOB is defined by ENOB SINAD 1 76 6 02 Total Harmonic Distortion THD THD is the ratio of the rms sum of harmonics to the fundamental For the AD7400A it is defined as JV3 V V Vy v THD dB 20 log 7 1 where Vi is the rms amplitude of the fundamental Va V3 Va Vs and Ve are the rms amplitudes of the second through the sixth harmonics Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum up to fs 2 excluding dc to the rms value of the fundamental Normally the value of this specification is determined by the largest harm
21. ne input to be effectively supplied by the other input The series resistor again isolates any op amp from the current spikes created during the sampling process Recommended values for the resistors and capacitor are 22 Q and 47 pF respectively AD7400A 07077 028 Figure 24 Differential Input RC Network CURRENT SENSING APPLICATIONS The AD7400A is ideally suited for current sensing applications where the voltage across a shunt resistor is monitored The load current flowing through an external shunt resistor produces a voltage at the input terminals of the AD7400A The AD7400A provides isolation between the analog input from the current sensing resistor and the digital outputs By selecting the appropriate shunt resistor value a variety of current ranges can be monitored Choosing Rsense The shunt resistor values used in conjunction with the AD7400A are determined by the specific application requirements in terms of voltage current and power Small resistors minimize power dissipation while low inductance resistors prevent any induced voltage spikes and good tolerance devices reduce current variations The final values chosen are a compromise between low power dissipation and good accuracy Low value resistors have less power dissipated in them but higher value resistors may be required to use the full input range of the ADC thus achieving maximum SNR performance When the peak sense current is known the voltage range of
22. nsing resistor and the digital output which is then processed by a digital filter to provide an N bit word ANALOG INPUT The differential analog input of the AD7400A is implemented with a switched capacitor circuit This circuit implements a second order modulator stage that digitizes the input signal into a 1 bit output stream The sample clock MCLKOUT provides the clock signal for the conversion process as well as the output data framing clock This clock source is internal on the AD7400A The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference A digital stream that accurately represents the analog input over time appears at the output of the converter see Figure 20 MODULATOR OUTPUT FS ANALOG INPUT ii FS ANALOG INPUT 07077 019 ANALOG INPUT Figure 20 Analog Input vs Modulator Output A differential signal of 0 V ideally results in a stream of 1s and Os at the MDAT output pin This output is high 50 of the time and low 5096 of the time A differential input of 200 mV produces a stream of Is and Os that are high 81 25 of the time for a 250 mV input the output stream is high 89 06 of the time A differential input of 200 mV produces a stream of 1s and Os that are high 18 7596 of the time for a 250 mV input the output stream is high 10 9496 of the time ISOLATED 5V INPUT CURRENT RSHUNT AD7400A A differential input of 320
23. onic in the spectrum but for ADCs where the harmonics are buried in the noise floor it is a noise peak Common Mode Rejection Ratio CMRR CMRR is defined as the ratio of the power in the ADC output at 250 mV frequency f to the power of a 250 mV p p sine wave applied to the common mode voltage of Vint and Vm of frequency fs as CMRR dB 10 log Pf Pf where Pf is the power at frequency f in the ADC output Pfsis the power at frequency fs in the ADC output Power Supply Rejection Ratio PSRR Variations in power supply affect the full scale transition but not the converter linearity PSRR is the maximum change in the specified full scale 250 mV transition point due to a change in power supply voltage from the nominal value see Figure 7 Isolation Transient Immunity The isolation transient immunity specifies the rate of rise fall of a transient pulse applied across the isolation boundary beyond which clock or data is corrupted The AD7400A was tested using a transient pulse frequency of 100 kHz Rev A Page 12 of 20 THEORY OF OPERATION CIRCUIT INFORMATION The AD7400A isolated Z A modulator converts an analog input signal into a high speed 10 MHz typical single bit data stream the time average of the single bit data from the modulator is directly proportional to the input signal Figure 22 shows a typical application circuit where the AD7400A is used to provide isolation between the analog input a current se
24. sa Thermal Impedance 116 8 C W Osc Thermal Impedance 38 9 C W SOIC Package Osa Thermal Impedance 89 2 C W Osc Thermal Impedance 55 6 C W Resistance Input to Output Rio 1020 Capacitance Input to Output Cro 1 7 pF typ RoHS Compliant Temperature Soldering Reflow 260 0 C ESD 2 5 kV AD7400A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Table 7 Maximum Continuous Working Voltage Parameter Max Unit Constraint AC Voltage 565 V peak 50 year minimum Bipolar Waveform lifetime AC Voltage 891 V peak Maximum CSA VDE Unipolar Waveform approved working voltage DC Voltage 891 V Maximum CSA VDE approved working voltage 1 Refers to continuous voltage magnitude imposed across the isolation barrier See the Insulation Lifetime section for more details Transient currents of up to 100 mA do not cause SCR to latch up JEDEC 2S2P standard board 3f 1 MHz ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge A without detection Although this product features patented or proprietary protection cir
25. the AD7400A 200 mV is divided by the maximum sense current to yield a suitable shunt value If the power dissipation in the shunt resistor is too large the shunt resistor can be reduced in which case less of the ADC input range is used Using less of the ADC input range results in performance that is more susceptible to noise and offset errors because offset errors are fixed and are thus more significant when smaller input ranges are used Rsense must be able to dissipate the I2R power losses If the power dissipation rating of the resistor is exceeded its value may drift or the resistor may be damaged resulting in an open circuit This can result in a differential voltage across the terminals of the AD400A in excess of the absolute maximum ratings see Table 6 If Isense has a large high frequency component take care to choose a resistor with low inductance VOLTAGE SENSING APPLICATIONS The AD7400A can also be used for isolated voltage monitoring For example in motor control applications it can be used to sense bus voltage In applications where the voltage being monitored exceeds the specified analog input range of the AD7400A a voltage divider network can be used to reduce the voltage being monitored to the required range Rev A Page 14 of 20 DIGITAL FILTER The overall system resolution and throughput rate is determined by the filter selected and the decimation rate used The higher the decimation rate the greater th
26. vice thereby leading to latch up or permanent damage Any decoupling used should be placed as close to the supply pins as possible Series resistance in the analog inputs should be minimized to avoid any distortion effects especially at high temperatures If possible equalize the source impedance on each analog input to minimize offset Beware of mismatch and thermocouple effects on the analog input PCB tracks to reduce offset drift EVALUATING THE AD7400A PERFORMANCE An AD7400A evaluation board is available with split ground planes and a board split beneath the AD7400A package to ensure isolation This board allows access to each pin on the device for evaluation purposes The evaluation board package includes a fully assembled and tested evaluation board documentation and software for controlling the board from the PC via the EVAL CED1Z The software also includes a SINC filter implemented on an FPGA The evaluation board is used in conjunction with the EVAL CED1Z board and can be used as a standalone board The software allows the user to perform ac fast Fourier transform and dc histogram of codes tests on the AD7400A The software and documentation are on a CD that ships with the evaluation board AD7400A INSULATION LIFETIME All insulation structures subjected to sufficient time and or voltage are vulnerable to breakdown In addition to the testing performed by the regulatory agencies Analog Devices has carried out an e
27. xtensive set of evaluations to determine the lifetime of the insulation structure within the AD7400A These tests subjected populations of devices to continuous cross isolation voltages To accelerate the occurrence of failures the selected test voltages were values exceeding those of normal use The time to failure values of these units were recorded and used to calculate acceleration factors These factors were then used to calculate the time to failure under normal operating conditions The values shown in Table 7 are the lesser of the following two values e The value that ensures at least a 50 year lifetime of continuous use e The maximum CSA VDE approved working voltage Note that the lifetime of the AD7400A varies according to the waveform type imposed across the isolation barrier The iCoupler insulation structure is stressed differently depending on whether the waveform is bipolar ac unipolar ac or dc Figure 29 Figure 30 and Figure 31 illustrate the different isolation voltage waveforms RATED PEAK VOLTAGE NL Figure 29 Bipolar AC Waveform 07077 029 RATED PEAK VOLTAGE N Figure 30 Unipolar AC Waveform 07077 030 RATED PEAK VOLTAGE 07077 031 ov Figure 31 DC Waveform Rev A Page 17 of 20 AD7400A OUTLINE DIMENSIONS 0 379 9 63 0 375 9 53 0 371 9 43 A 5 FE f Ts 5 0 388 9 86 0 254 6 45 0 380 9 65
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ANALOG DEVICES AD7400A Manual ad7203 digital to analog converter