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ANALOG DEVICES AD9258 handbook

1. 0 50 dBc CHANNEL B 0 25 a bs a Z tc 8 a S 2 2 g a o 0 25 8 0 50 25 35 45 55 65 75 8 95 105 115 125 i 0 SAMPLE RATE MSPS 5 Figure 50 AD9258 125 Single Tone SNR SFDR vs Sample Rate fs with fn 70 1 MHz 700 000 0 0 72LSB rms 90 600 000 500 000 dad iP 70 T 400 000 5 E m 300 000 5 5 g 2 a 50 200 000 40 100 000 0 30 N 3 N 2 N 1 N N 1 N 2 N43 OUTPUT CODE 5 Figure 51 AD9258 125 Grounded Input Histogram DITHER ENABLED DITHER DISABLED INL ERROR LSB 2048 4096 er 6144 8192 10 240 12 288 14 336 16 384 OUTPUT CODE 08124 032 Figure 52 AD9258 125 INL with fi 9 7 MHz Rev A Page 24 of 44 2048 4096 6144 8192 10 240 12 288 14 336 16 384 OUTPUT CODE Figure 53 AD9258 125 DNL with 9 7 MHz SFDR dBc 08124 033 SNR dBFS 0 75 0 80 0 85 0 90 0 95 1 00 1 05 1 10 1 15 INPUT COMMON MODE VOLTAGE V Figure 54 SNR SFDR vs Input Common Mode VCM with fin 30 MHz 1 20 081 24 053 AD9258 EQUIVALENT CIRCUITS vn a Lar SENSE 08124 007 08124 012 Figure 55 Equivalent Analog Input Circuit Figure 60 Equivalent SENSE Circuit AVDD DRVDD L L 26k 10kQ 10kO CLK CLK CSB 3500 Figure 56 Equivalent Clock Input Circuit Figure 61 Equivalent CSB Input Circui
2. Em H 62 VIN B 61 VIN B 60 AVDD 58 RBIAS 57 VCM 56 SENSE 54 AVDD 53 AVDD El 52 VIN A 51 VIN A 50 AVDD 49 AVDD CLK CLK SYNC NC NC DOB LSB D1B D2B D3B DRVDD 10 D4B 11 D5B 12 D6B 13 D7B 14 D8B 15 D9B 16 oo On EM INDICATOR 48 PDWN 47 OEB 45 SCLK DFS 44 SDIO DCS AD9258 41 D12A 40 D11A PARALLEL CMOS TOP VIEW Not to Scale 38 D9A 37 DRVDD 35 D7A 34 D6A 33 D5A NOTES 1 NC NO CONNECT 2 THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION f 10 b 00 0 G D13B MSB 21 H ORB 2 DCOB 2 DCOA 2 NC 2 NC 2 DOA LSB 27 DRVDD 2 D1A 2 D2A 3 D3A 3 D4A 3 08124 005 Figure 6 LFCSP Parallel CMOS Pin Configuration Top View Table 8 Pin Function Descriptions Parallel CMOS Mode Pin No Mnemonic Type Description ADC Power Supplies 10 19 28 37 DRVDD Supply Digital Output Driver Supply 1 8 V Nominal 49 50 53 54 59 AVDD Supply Analog Power Supply 1 8 V Nominal 60 63 64 4 5 25 26 NC Do Not Connect 0 AGND Ground The exposed thermal pad on the bottom of the package provides the analog Exposed Pad ground for the part This exposed pad must be connected to ground for proper operation ADC Analog 51 VINA Input Differential Analog Input Pin 4 for Channel A
3. Differential Input Configurations Optimum performance is achieved while driving the AD9258 in a differential input configuration For baseband applications the AD8138 ADA4937 2 and ADA4938 2 differential drivers provide excellent performance and a flexible interface to the ADC The output common mode voltage of the ADA4938 2 is easily set with the VCM pin of the AD9258 see Figure 66 and the driver can be configured in a Sallen Key filter topology to provide band limiting of the input signal 76 80 VIN AD9258 VCM 08124 035 Figure 66 Differential Input Configuration Using the ADA4938 2 For baseband applications in which SNR is a key parameter differential transformer coupling is the recommended input configuration An example is shown in Figure 67 To bias the analog input the VCM voltage can be connected to the center tap of the secondary winding of the transformer q 2 V AD9258 VCM 0 1pF eT Figure 67 Differential Transformer Coupled Configuration 08124 036 Rev A Page 27 of 44 AD9258 The signal characteristics must be considered when selecting a transformer Most RF transformers saturate at frequencies below a few megahertz MHz Excessive signal power can also cause core saturation which leads to distortion At input frequencies in the second Nyquist zone and above the noise performance of most amplifiers is not adequate to achieve the true SNR p
4. PARALLEL LVDS TOP VIEW Not to Scale 48 PDWN 47 OEB 46 CSB 45 SCLK DFS 44 SDIO DCS 43 OR 42 OR 41 013 MSB 40 D13 MSB 39 D12 38 D12 37 DRVDD 36 011 35 D11 34 D10 33 D10 NOTES 1 NC NO CONNECT 2 THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION 08124 006 Figure 7 LFCSP Interleaved Parallel LVDS Pin Configuration Top View Table 9 Pin Function Descriptions Interleaved Parallel LVDS Mode AD9258 Pin No Mnemonic Type Description ADC Power Supplies 10 19 28 37 DRVDD Supply Digital Output Driver Supply 1 8 V Nominal 49 50 53 54 59 AVDD Supply Analog Power Supply 1 8 V Nominal 60 63 64 4 5 6 7 NC Do Not Connect 0 AGND Ground The exposed thermal pad on the bottom of the package provides the analog Exposed Pad ground for the part This exposed pad must be connected to ground for proper operation ADC Analog 51 VIN A Input Differential Analog Input Pin for Channel A 52 VIN A Input Differential Analog Input Pin for Channel A 62 VIN B Input Differential Analog Input Pin for Channel B 61 VIN B Input Differential Analog Input Pin for Channel B 55 VREF Input Output Voltage Reference Input Output 56 SENSE Input Voltage Reference Mode Select See Table 11 for details 58 RBIAS Input Output
5. applies to local registers only OxFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave ADC Functions 0x08 Power modes 1 Open External Open Open Open Internal power down 0x80 Determines local power mode local various generic down pin 00 normal operation modes of chip function 01 full power down operation local 10 standby 0 pdwn 11 normal operation 1 stndby 0x09 Global clock Open Open Open Open Open Open Open Duty cycle 0x01 global stabilizer default 0x0B Clock divide Open Open Open Open Open Clock divide ratio 0x00 Clock divide global 000 divide by 1 values other 001 divide by 2 than 000 010 divide by 3 automatically 011 divide by 4 cause the duty E cycle stabilizer 100 divide by 5 to become 101 divide by 6 active 110 divide by 7 111 divide by 8 0x0D Test mode Open Open Reset PN Reset PN Open Output test mode 0x00 When this local long gen short gen 000 off default register is set 001 midscale short the test data 010 positive FS is placed on the output 011 negative FS pins in place of 100 alternating checkerboard normal data 101 PN long sequence 110 PN short sequence 111 one zero word toggle Rev A Page 38 of 44 AD9258 Default Default Address Reg
6. e tssync Rag SYNC Figure 5 SYNC Input Timing Requirements 08124 004 Rev A Page 11 of 44 AD9258 AD9258 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS The exposed paddle must be soldered to the ground plane for the LFCSP package Soldering the exposed paddle to the PCB increases the reliability of the solder joints and maximizes the thermal capability of the package Typical 05 is specified for a 4 layer PCB with a solid ground plane As shown in Table 7 airflow improves heat dissipation which reduces In addition metal in direct contact with the package leads from metal traces through holes ground and power planes reduces Table 7 Thermal Resistance Airflow Velocity Package Type m sec Ow Unit 64 Lead LFCSP 0 18 5 1 0 C W CP 64 6 1 0 16 1 9 2 C W 2 5 14 5 C W Table 6 Parameter Rating ELECTRICAL AVDD to AGND 0 3V to 2 0V DRVDD to AGND 0 3 V to 2 0V VIN A VIN B VINCA VIN B to AGND 0 3V to AVDD 02V CLK CLK to AGND 0 3 V to AVDD 0 2 V SYNC to AGND 0 3 V to AVDD 02V VREF to AGND 0 3V to AVDD 0 2 V SENSE to AGND 0 3V to AVDD 0 2 V VCM to AGND 0 3V to AVDD 0 2V RBIAS to AGND 0 3V to AVDD 0 2V CSB to AGND 0 3 V to DRVDD 0 2 V SCLK DFS to AGND 0 3 V to DRVDD 0 2 V SDIO DCS to AGND 0 3V to DRVDD 0 2 V OEB 0 3V to DRVDD 02V PDWN 0 3V to DRVDD 0 2
7. 52 VIN A Input Differential Analog Input Pin for Channel A 62 VIN B Input Differential Analog Input Pin for Channel B 61 VIN B Input Differential Analog Input Pin for Channel B 55 VREF Input Output Voltage Reference Input Output 56 SENSE Input Voltage Reference Mode Select See Table 11 for details 58 RBIAS Input Output External Reference Bias Resistor 57 VCM Output Common Mode Level Bias Output for Analog Inputs 1 CLK Input ADC Clock Input True 2 CLK Input ADC Clock Input Complement Digital Input 3 SYNC Input Digital Synchronization Pin Slave mode only Digital Outputs 27 DOA LSB Output Channel A CMOS Output Data 29 D1A Output Channel A CMOS Output Data 30 D2A Output Channel A CMOS Output Data 31 D3A Output Channel A CMOS Output Data Rev A Page 13 of 44 AD9258 Pin No Mnemonic Type Description 32 D4A Output Channel A CMOS Output Data 33 D5A Output Channel A CMOS Output Data 34 D6A Output Channel A CMOS Output Data 35 D7A Output Channel A CMOS Output Data 36 D8A Output Channel A CMOS Output Data 38 D9A Output Channel A CMOS Output Data 39 D10A Output Channel A CMOS Output Data 40 D11A Output Channel A CMOS Output Data 41 12 Output Channel A CMOS Output Data 42 D13A MSB Output Channel A CMOS Output Data 43 ORA Output Channel A Overrange Output 6 DOB LSB Output Channel B CMOS Output Data 7 D1B Output Channel B CMOS Output Data
8. External Reference Bias Resistor 57 VCM Output Common Mode Level Bias Output for Analog Inputs 1 CLK Input ADC Clock Input True 2 CLK Input ADC Clock Input Complement Digital Input 3 SYNC Input Digital Synchronization Pin Slave mode only Digital Outputs 9 LSB Output Channel A Channel B LVDS Output Data 0 True 8 LSB Output Channel A Channel B LVDS Output Data 0 Complement 12 D1 Output Channel A Channel B LVDS Output Data 1 True 11 D1 Output Channel A Channel B LVDS Output Data 1 Complement 14 D2 Output Channel A Channel B LVDS Output Data 2 True 13 D2 Output Channel A Channel B LVDS Output Data 2 Complement Rev A Page 15 of 44 AD9258 Pin No Mnemonic Type Description 16 D3 Output Channel A Channel B LVDS Output Data 3 True 15 D3 Output Channel A Channel LVDS Output Data 3 Complement 18 D4 Output Channel A Channel B LVDS Output Data 4 True 17 D4 Output Channel A Channel B LVDS Output Data 4 Complement 21 D54 Output Channel A Channel B LVDS Output Data 5 True 20 D5 Output Channel A Channel B LVDS Output Data 5 Complement 23 D6 Output Channel A Channel B LVDS Output Data 6 True 22 D6 Output Channel A Channel LVDS Output Data 6 Complement 27 D7 Output Channel A Channel B LVDS Output Data 7 True 26 D7 Output Channel A Channel LVDS Output Data 7 Complement 30 D8 Output Channel A Channel B LVDS Output Dat
9. Rev A Page 16 of 44 AD9258 TYPICAL PERFORMANCE CHARACTERISTICS AVDD 1 8 V DRVDD 1 8 V rated sample rate DCS enabled 1 0 V internal reference 2 V p p differential input VIN 1 0 dBFS and 32k sample T4 25 C unless otherwise noted 0 80MSPS 80MSPS 2 4MHz 1dBFS 200 3MHz 9 1dBFS 20 SNR 78 2dB 79 2dBFS SNR 74 3dB 75 3dBFS SFDR 99dBc SFDR 83dBc 40 p A m m SECOND HARMONIC 5 60 z SECOND HARMONIC THIRD HARMONIC E 5 80 a a 08124 062 08124 065 FREQUENCY MHz FREQUENCY MHz Figure 8 AD9258 80 Single Tone FFT with fin 2 4 MHz Figure 11 AD9258 80 Single Tone FFT with fiw 200 1 MHz 80MSPS 70 1MHz 6dBFS SNR 71 6dB 77 6dBFS SFDR 97dBc 80MSPS 70 1MHz 1dBFS SNR 77 0dB 78 0dBFS SFDR 89 0dBc THIRD HARMONIC SECOND HARMONIC X lal illu Aui lia abl il ai 0 10 20 30 FREQUENCY MHz FREQUENCY MHz Figure 9 AD9258 80 Single Tone FFT with fiw 70 1 MHz Figure 12 AD9258 80 Single Tone FFT with fi 70 1 MHz with Dither Enabled THIRD HARMONIC SECOND HARMONIC AMPLITUDE dBFS AMPLITUDE dBFS gt 08124 063 08124 066 80MSPS 140 1MHz 1dBFS SNR 75 5dB 76 5dBFS SFDR 82 0dBc AMPLITUDE dBFS SNR SFDR dBc AND dBFS SNR dBFS SFDR dBc SNR dBc
10. 1dBFS 20 SNR 74 0dB 75 0dBFS SFDR 80dBc 40 0 THIRD HARMONIC SECOND HARMONIC 80 100 t T t jl 120 140 0 10 20 30 40 50 FREQUENCY MHz Figure 23 AD9258 105 Single Tone FFT with fw 200 3 MHz 105MSPS 70 1MHz 6dBFS SNR 72 0dB 78 0dBFS SFDR 97dBc SECOND THIRD HARMONIC HARMONIC BALL Lilo iai add m 0 10 20 30 40 50 FREQUENCY MHz 08124 077 08124 078 Figure 24 AD9258 105 Single Tone FFT with 70 1 MHz with Dither Enabled SNR SFDR dBc AND dBFS 120 e SNR dBFS SFDR dBc SNR dBc SFDR dBFS 0 100 90 80 70 60 50 40 30 20 10 0 INPUT AMPLITUDE dBFS 08124 079 Figure 25 AD9258 105 Single Tone SNR SFDR vs Input Amplitude Ain Rev A Page 19 of 44 with fiy 98 12 MHz AD9258 SNRFS DITHER ON SNRFS DITHER OFF 90 F SFDRFS DITHER ON SFDRFS DITHER OFF SNR SFDR dBFS 100 90 80 70 60 50 40 30 20 10 0 INPUT AMPLITUDE dBFS 08124 080 NUMBER OF HITS Figure 26 AD9258 105 Single Tone SNR SFDR vs Input Amplitude Ain with fiy 30 MHz with and without Dither Enabled SNR 40 C SFDR 40 C SNR 25 C SFDR 25 C SNR 85 C SFDR 85 C SNR SFDR dBFS AND dBc 0 50 100 150 200 250 300 INPUT FREQ
11. 50 75 100 125 08124 056 ENCODE FREQUENCY MHz Figure 81 AD9258 125 Power and Current vs Encode Frequency LVDS Output Mode 1 0 0 5 0 4 TOTAL POWER A Les E z hr E 0 3 z 4 amp 3 E lt 022 o amp 5 o E Ss 0 WS 0 25 35 45 55 65 75 85 95 105 ENCODE FREQUENCY MSPS Figure 82 AD9258 105 Power and Current vs Encode Frequency LVDS Output Mode 08124 086 1 0 0 25 yl T EY amp E z m 0 6 TOTAL POWER 0 15 5 amp 8 d lt 0 4 0 10 2 E 5 D ccce ESAME T 0 0 5 25 35 45 55 65 75 i ENCODE FREQUENCY MSPS Figure 83 AD9258 80 Power and Current vs Encode Frequency LVDS Output Mode By asserting PDWN either through the SPI port or by asserting the PDWN pin high the AD9258 is placed in power down mode In this state the ADC typically dissipates 2 5 mW During power down the output drivers are placed in a high impedance state Asserting the PDWN pin low returns the AD9258 to its normal operating mode Low power dissipation in power down mode is achieved by shutting down the reference reference buffer biasing networks and clock Internal capacitors are discharged when entering power down mode and then must be recharged when returning to normal operation When using the SPI port interface the user can place the ADC in power down mode or standby mode Standby mode allows the user to k
12. AD9258 provides two data clock output DCO signals intended for capturing the data in an external register In CMOS output mode the data outputs are valid on the rising edge of DCO unless the DCO clock polarity has been changed via the SPI In LVDS output mode the DCO and data output switching edges are closely aligned Additional delay can be added to the DCO output using SPI Register 0x17 to increase the data setup time In this case the Channel A output data is valid on the rising edge of DCO and the Channel B output data is valid on the falling edge of DCO See Figure 2 Figure 3 and Figure 4 for a graphical timing description of the output modes Input V Condition V Offset Binary Output Mode Twos Complement Mode OR VIN VIN lt VREF 0 5 LSB 00 0000 0000 0000 10 0000 0000 0000 1 VIN VIN VREF 00 0000 0000 0000 10 0000 0000 0000 0 VIN VIN 0 10 0000 0000 0000 00 0000 0000 0000 0 VIN VIN VREF 1 0 LSB 1111111111 1111 011111 1111 1111 0 VIN VIN gt VREF 0 5 LSB 1111111111 1111 011111 1111 1111 1 Rev A Page 33 of 44 AD9258 BUILT IN SELF TEST BIST AND OUTPUT TEST The AD9258 includes built in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging A BIST built in self test feature is included that verifies the integrity of the digital datapath of the AD9258 Various output test op
13. Figure 76 Balun Coupled Differential Clock Up to 625 MHz 08124 046 If a low jitter clock source is not available another option is to ac couple a differential PECL signal to the sample clock input pins as shown in Figure 77 The AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 AD9516 AD9517 AD9518 clock drivers offer excellent jitter performance 0 1pF 0 1pF CLOCK INPUT AD951x 1000 AD9258 o iyr PECL DRIVER nang 5 CLOCK 6 of CLK INPUT 50kQ 2400 2400 08124 047 Figure 77 Differential PECL Sample Clock Up to 625 MHz A third option is to ac couple a differential LVDS signal to the sample clock input pins as shown in Figure 78 The AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 AD9516 AD9517 AD9518 clock drivers offer excellent jitter performance 0 1 CLOCK INPUT AD951x 0 1yF LVDS DRIVER CLOCK INPUT 50kQ 50kQ 08124 048 Figure 78 Differential LVDS Sample Clock Up to 625 MHz Rev A Page 30 of 44 In some applications it may be acceptable to drive the sample clock inputs with a single ended CMOS signal In such applica tions the CLK pin should be driven directly from a CMOS gate and the CLK pin should be bypassed to ground with a 0 1 uF capacitor see Figure 79 OPTIONAL 0 1 f CLOCK 1000 D E INPUT 5001 1500 RESISTOR IS OPTIONAL a E Figure 79 Single Ended 1 8 V CMOS Input Clock Up to 200 MHz Input Clock Divider The AD9258 contains an input clock di
14. SFDR dBc SFDR 85 C e a 40 z a 2 E 8 8 60 G g 80 g a 100 SFDR dBFS IMD3 dBFS 120 NN 0 50 100 150 200 250 300 90 08124 025 08124 028 INPUT FREQUENCY MHz INPUT AMPLITUDE dBFS Figure 47 AD9258 125 Two Tone SFDR IMD3 vs Input Amplitude Ain Figure 44 AD9258 125 T vs Input Frequency fin with fi 169 1 MHz 172 1 MHz fs 125 MSPS wi p p Full Scale 95 125MSPS 29 1MHz 7dBFS 90 32 1MHz 7dBFS SFDR 88 8dBc 95 8dBFS g 85 SFDR dBc _ a o o a 80 3 5 a m 75 SNR dBFS d 3 65 60 9 0 50 100 150 200 250 300 i INPUT FREQUENCY MHz 5 FREQUENCY MHz S Figure 45 AD9258 125 Single Tone SNR SFDR vs Input Frequency fin Figure 48 AD9258 125 Two Tone FFT with fw 29 1 MHz and fw 32 1 MHz with 1 V p p Full Scale 0 125MSPS 169 1MHz 7dBFS 172 1MHz 7dBFS SFDR 81 7dBc 88 7dBFS p SFDR dBc g Z 0 kJ 2 F 8 60 E IMD3 dBc a E E 80 a o 100 SFDR dBFS T IMD3 dBFS 2 90 78 66 54 42 30 18 6 2 FREQUENCY MHz 8 INPUT AMPLITUDE dBFS 8 Figure 49 AD9258 125 Two Tone FFT with fw 169 1 MHz and Figure 46 AD9258 125 Two Tone SFDR IMD3 vs Input Amplitude Aw fing 172 1 MHz with fiw 29 1 MHz hus 32 1 MHz fs 125 MSPS Rev A Page 23 of 44 AD9258
15. V DOA DOB through D13A D13B to 0 3 V to DRVDD 0 2V AGND DCOA DCOB to AGND 0 3V to DRVDD 02V ENVIRONMENTAL Operating Temperature Range 40 C to 85 C Ambient Maximum Junction Temperature 150 C Under Bias Storage Temperature Range 65 C to 150 C Ambient The inputs and outputs are rated to the supply voltage AVDD or DRVDD 0 2 V but should not exceed 2 1 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Per JEDEC 51 7 plus JEDEC 25 5 2S2P test board 2 Per JEDEC JESD51 2 still air or JEDEC JESD51 6 moving air 3 Per MIL Std 883 Method 1012 1 4 Per JEDEC JESD51 8 still air ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev A Page 12 of 44 AD9258 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS na gs lt lt
16. V p p default 0x24 BIST signature BIST signature 7 0 0x00 Read only LSB local 0x25 BIST signature BIST signature 15 8 0x00 Read only MSB local 0x30 Dither enable Open Open Open Dither Open Open Open Open 0x00 local Enable Digital Feature Control 0x100 Sync control Open Open Open Open Open Clock Clock Master 0x00 global divider divider sync next sync sync enable only enable Rev A Page 39 of 44 AD9258 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register OxFF see the AN 877 Application Note Interfacing to High Speed ADCs via SPI Sync Control Register 0x100 Bits 7 3 Reserved Bit 2 Clock Divider Next Sync Only If the master sync enable bit Address 0x100 Bit0 and the clock divider sync enable bit Address 0x100 Bit 1 are high Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest The clock divider sync enable bit Address 0x100 Bit 1 resets after it syncs Bit 1 Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider The sync signal is enabled when Bit 1 is high and Bit 0 is high This is continuous sync mode Bit 0 Master Sync Enable Bit 0 must be high to enable any of the sync functions If the sync capability is not used this bit should remain low to conserve power Rev A Page 40 of 44 AD9258 APPLICATIONS INFORMA
17. at 100 MHz with 1 0 dBFS on one channel and no input on the alternate channel DIGITAL SPECIFICATIONS AVDD 1 8 V DRVDD 1 8 V maximum sample rate VIN 1 0 dBFS differential input 1 0 V internal reference and DCS enabled unless otherwise noted Table 3 Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS CLK CLK Logic Compliance CMOS LVDS LVPECL Internal Common Mode Bias Full 0 9 V Differential Input Voltage Full 0 3 3 6 V p p Input Voltage Range Full AGND AVDD V Input Common Mode Range Full 0 9 1 4 V High Level Input Current Full 100 4100 Low Level Input Current Full 100 100 Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kQ SYNC INPUT Logic Compliance CMOS Internal Bias Full 0 9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1 2 AVDD V Low Level Input Voltage Full AGND 0 6 V High Level Input Current Full 100 4100 Low Level Input Current Full 100 100 Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kQ Rev A Page 7 of 44 AD9258 Parameter Temperature Min Typ Max Unit LOGIC INPUT CSB High Level Input Voltage Full 1 22 2 1 V Low Level Input Voltage Full 0 0 6 V High Level Input Current Full 10 10 yA Low Level Input Current Full 40 132 uA Input Resistance Full 26 kQ Input Capacitance Full 2 pF LOGIC INPUT SCLK DFS High Level Input Voltage Full 1 22 2 1 V Low L
18. clock input which is used to synchronize serial interface reads and writes SDIO Serial Data Input Output A dual purpose pin that typically serves as an input or an output depending on the instruction being sent and the relative position in the timing frame CSB Chip Select Bar An active low control that gates the read and write cycles AD9258 The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing An example of the serial timing and its definitions can be found in Figure 84 and Table 5 Other modes involving the CSB are available When the CSB is held low indefinitely which permanently enables the device this is called streaming The CSB can stall high between bytes to allow for additional external timing When CSB is tied high SPI functions are placed in high impedance mode This mode turns on any SPI pin secondary functions During an instruction phase a 16 bit instruction is transmitted Data follows the instruction phase and its length is determined by the 0 and W1 bits In addition to word length the instruction phase determines whether the serial frame is a read or write operation allowing the serial port to be used both to program the chip and to read the contents of the on chip memory The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued If the instruction is a r
19. is not easily reduced by the internal stabilization circuit The duty cycle control loop does not function for clock rates of less than 20 MHz nominally The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically A wait time of 1 5 us to 5 us is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal During the time period that the loop is not locked the DCS loop is bypassed and internal device timing is dependent on the duty cycle of the input clock signal In such applications it may be appropriate to disable the duty cycle stabilizer In all other applications enabling the DCS circuit is recommended to maximize ac performance AD9258 Jitter Considerations High speed high resolution ADCs are sensitive to the quality of the clock input For inputs near full scale the degradation in SNR from the low frequency SNR SNRu at a given input frequency due to jitter tms can be calculated by SNRur 10 log 2n x finpur X tjus 10 C00 In the equation the rms aperture jitter represents the clock input jitter specification IF undersampling applications are particularly sensitive to jitter as illustrated in Figure 80 The measured curve in Figure 80 was taken using an ADC clock source with approxi mately 65 fs of jitter which combines with the 70 fs of jitter inherent in the AD9258 to pr
20. not be written Default Values After the AD9258 is reset critical registers are loaded with default values The default values for the registers are given in the memory map register table Table 17 Logic Levels An explanation of logic level terminology follows e Bitis set is synonymous with bit is set to Logic 1 or writing Logic 1 for the bit e Clear a bit is synonymous with bit is set to Logic 0 or writing Logic 0 for the bit Transfer Register Map Address 0x08 through Address 0x18 and Address 0x30 are shadowed Writes to these addresses do not affect part operation until a transfer command is issued by writing Ox01 to Address OxFE setting the transfer bit This allows these registers to be updated internally and simultaneously when the transfer bit is set The internal update takes place when the transfer bit is set and the bit autoclears Channel Specific Registers Some channel setup functions such as the signal monitor thresholds can be programmed differently for each channel In these cases channel address locations are internally duplicated for each channel These registers and bits are designated in Table 17 as local These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05 If both bits are set the subsequent write affects the registers of both channels In a read cycle only Channel A or Channel B should be set to read one
21. 8 D2B Output Channel B CMOS Output Data 9 D3B Output Channel B CMOS Output Data 11 D4B Output Channel B CMOS Output Data 12 D5B Output Channel B CMOS Output Data 13 D6B Output Channel B CMOS Output Data 14 D7B Output Channel B CMOS Output Data 15 D8B Output Channel B CMOS Output Data 16 D9B Output Channel B CMOS Output Data 17 D10B Output Channel B CMOS Output Data 18 D11B Output Channel B CMOS Output Data 20 D12B Output Channel B CMOS Output Data 21 D13B MSB Output Channel B CMOS Output Data 22 ORB Output Channel B Overrange Output 24 DCOA Output Channel A Data Clock Output 23 DCOB Output Channel B Data Clock Output SPI Control 45 SCLK DFS Input SPI Serial Clock Data Format Select Pin in External Pin Mode 44 SDIO DCS Input Output SPI Serial Data l O Duty Cycle Stabilizer Pin in External Pin Mode 46 CSB Input SPI Chip Select Active Low ADC Configuration 47 OEB Input Output Enable Input Active Low in External Pin Mode 48 PDWN Input Power Down Input in External Pin Mode In SPI mode this input can be configured as power down or standby Rev A Page 14 of 44 63 AVDD 62 VIN B 61 VIN B 60 AVDD 59 AVDD 58 RBIAS 57 VCM a gt 56 SENSE 53 AVDD 52 VIN A B 51 VIN A 50 AVDD 49 AVDD CLK CLK SYNC NC NC NC NC DO LSB D0 LSB DRVDD 10 D1 11 D1 12 D2 13 D2 14 D3 15 D3 16 Ow PIN 1 INDICATOR AD9258
22. ADC clock duty cycle allowing the converters to maintain excellent performance AD9258 The ADC output data can be routed directly to the two external 14 bit output ports These outputs can be set to either 1 8 V CMOS or LVDS Flexible power down options allow significant power savings when desired Programming for setup and control is accomplished using a 3 wire SPI compatible serial interface The AD9258 is available in a 64 lead LFCSP and is specified over the industrial temperature range of 40 C to 85 C Rev A Page 3 of 44 AD9258 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD 1 8 V DRVDD 1 8 V maximum sample rate VIN 1 0 dBFS differential input 1 0 V internal reference DCS enabled unless otherwise noted Table 1 AD9258BCPZ 80 AD9258BCPZ 105 AD9258BCPZ 125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full 0 1 0 5 0 1 0 5 0 4 0 65 FSR Gain Error Full 0 4 2 5 0 4 2 5 0 4 2 5 FSR Differential Full 0 5 0 5 0 5 LSB Nonlinearity DNL 25 C 0 25 0 25 0 25 LSB Integral Nonlinearity Full 1 1 1 3 1 4 LSB INL 25 C 0 55 0 7 0 8 LSB MATCHING CHARACTERISTIC Offset Error Full 0 1 0 4 0 1 0 4 0 2 0 45 FSR Gain Error Full 0 3 1 3 0 3 1 3 0 3 1 3 FSR TEMPERATURE DRIFT Offset Error Fu
23. ANALOG 14 Bit 80 MSPS 105 MSPS 125 MSPS 1 8 V Dual DEVICES Analog to Digital Converter ADC AD9258 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR 77 6 dBFS 70 MHz and 125 MSPS AVDD Mee brs DRVDD SFDR 88 dBc 70 MHz and 125 MSPS Low power 750 mW 125 MSPS 1 8 V analog supply operation 1 8 V CMOS or LVDS output supply ORA Integer 1 to 8 input clock divider VIN A il D13A MSB Ti IF sampling frequencies to 300 MHz VIN A L A LSB 152 8 dBm Hz small signal input noise with 200 O input impedance 70 MHz and 125 MSPS VREF Optional on chip dither Programmable internal ADC voltage reference Integrated ADC sample and hold inputs Flexible analog input range 1 V p p to 2 V p p RBIAS ORB Differential analog inputs with 650 MHz bandwidth VIN B D D13B MSB ADC clock duty cycle stabilizer Bar TO VIN B Q LSB 95 dB channel isolation crosstalk Serial port control User configurable built in self test BIST capability AGND SYNC PDWN OEB Energy saving power down modes NOTES 1 PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY i APPLICATIONS SEE FIGURE 7 FORLVDS PIN NAMES 8 Communications 1 Diversity radio systems PRODUCT HIGHLIGHTS Multimode digital receivers 3G 1 GSM EDGE W CDMA LTE CDMA2000 WiMAX TD SCDMA I Q demodulation systems Smart antenna systems General purpose software radios Broadband data applications Ultrasound equipment On chip dither
24. CPZ 80 AD9258BCPZ 105 AD9258BCPZ 125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz Conversion Rate DCS Enabled Full 20 80 20 105 20 125 MSPS DCS Disabled Full 10 80 10 105 10 125 MSPS CLK Period Divide by 1 Mode tax Full 12 5 9 5 8 ns CLK Pulse Width High tc Divide by 1 Mode DCS Enabled Full 3 75 6 25 8 5 285 4 75 6 65 2 4 4 5 6 ns Divide by 1 Mode DCS Disabled Full 5 95 6 25 6 55 4 5 4 75 5 0 3 8 4 4 2 ns Divide by 2 Mode Through Full 0 8 0 8 0 8 ns Divide by 8 Mode Aperture Delay ta Full 1 0 1 0 1 0 ns Aperture Uncertainty Jitter tj Full 0 07 0 07 0 07 ps rms DATA OUTPUT PARAMETERS CMOS Mode Data Propagation Delay tpo Full 2 8 3 5 4 2 2 8 3 5 4 2 2 8 3 5 4 2 ns DCO Propagation Delay toco Full 3 1 3 1 3 1 ns DCO to Data Skew tsxew Full 06 04 0 06 04 0 06 04 0 ns LVDS Mode Data Propagation Delay tpo Full 2 9 3 7 4 5 2 9 3 7 45 29 3 7 45 ns DCO Propagation Delay toco Full 3 9 3 9 3 9 ns DCO to Data Skew tsxew Full 01 02 05 0 31 02 0 5 031 02 0 5 ns CMOS Mode Pipeline Delay Full 12 12 12 Cycles Latency LVDS Mode Pipeline Delay Full 12 12 5 12 12 5 12 12 5 Cycles Latency Channel A Channel B Wake Up Time Full 500 500 500 US Out of Range Recovery Time Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the divider Additional DCO delay can be added by writing to Bit 0 throug
25. DD Twos complement enabled AGND default Offset binary enabled OEB AVDD Outputs in high impedance AGND default Outputs enabled PDWN AVDD Chip in power down or standby AGND default Normal operation SPI ACCESSIBLE FEATURES Table 16 provides a brief description of the general features that are accessible via the SPI These features are described in detail in the AN 877 Application Note Interfacing to High Speed ADCs via SPI The AD9258 part specific features are described in detail following Table 17 the external memory map register table Table 16 Features Accessible Using the SPI Feature Name Description Mode Clock Offset Test I O Output Mode Output Phase Output Delay VREF Allows the user to set either power down mode or standby mode Allows the user to access the DCS set the clock divider set the clock divider phase and enable the sync Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set the output mode including LVDS Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the reference voltage Rev A Page 36 of 44 AD9258 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations The memory map is roughly divided into four sections the chip configur
26. DYNAMIC RANGE SFDR Without Dither AIN 23 dBFS fin 2 4 MHz 25 C 93 100 88 dBFS fin 70 MHz 25 C 95 96 89 dBFS fin 140 MHz 25 C 98 96 90 dBFS fin 200 MHz 25 C 102 100 89 dBFS With On Chip Dither AIN 23 dBFS fin 2 4 MHz 25 C 107 106 107 dBFS fin 70 MHz 25 C 106 107 106 dBFS fin 140 MHz 25 C 106 105 103 dBFS fin 200 MHz 25 C 105 106 105 dBFS Rev A Page 6 of 44 AD9258 AD9258BCPZ 80 AD9258BCPZ 105 AD9258BCPZ 125 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit WORST OTHER HARMONIC OR SPUR Without Dither fin 2 4 MHz 25 C 100 100 99 dBc fin 70 MHz 25 C 100 96 99 94 98 94 dBc Full 96 94 94 dBc fin 140 MHz 25 C 97 97 97 dBc fin 200 MHz 25 C 95 95 95 dBc With On Chip Dither fin 2 4 MHz 25 C 109 107 107 dBc fin 70 MHz 25 C 105 96 106 95 105 95 dBc Full 96 95 95 dBc fin 140 MHz 25 C 106 104 103 dBc fin 200 MHz 25 C 102 104 97 dBc TWO TONE SFDR WITHOUT DITHER fin 29 MHz 7 dBFS 32 MHz 7 dBFS 25 C 93 92 90 dBc fin 169 MHz 7 dBFS 172 MHz 7 dBFS 25 C 81 80 82 dBc CROSSTALK Full 95 95 95 ANALOG INPUT BANDWIDTH 25 C 650 650 650 MHz 1 See the AN 835 Application Note Understanding High Speed ADC Testing and Evaluation for a complete set of definitions Crosstalk is measured
27. R LSB 500 000 400 000 300 000 0 N 3 N 2 N 1 N N 1 N 2 N 3 OUTPUT CODE Figure 17 AD9258 80 Grounded Input Histogram DITHER ENABLED DITHER DISABLED 2000 4000 6000 8000 10 000 12 000 14 000 16 000 OUTPUT CODE Figure 18 AD9258 80 INL with fiw 9 7 MHz 08124 072 Rev A Page 18 of 44 2000 4000 6000 8000 10 000 12 000 14 000 16 000 OUTPUT CODE Figure 19 AD9258 80 DNL with fin 9 7 MHz 08124 071 08124 073 AMPLITUDE dBFS AMPLITUDE dBFS AMPLITUDE dBFS 105MSPS 2 4MHz 1dBFS SNR 77 5dB 78 5dBFS SFDR 90dBc SECOND HARMONIC THIRD HARMONIC 0 10 20 30 40 50 FREQUENCY MHz Figure 20 AD9258 105 Single Tone FFT with f 2 4 MHz 105MSPS 70 1MHz 1dBFS SNR 76 8dB 77 8dBFS SFDR 93 5dBc THIRD HARMONIC HARMONIC Li lh Al lul m Ll Lus 0 10 20 30 40 50 FREQUENCY MHz Figure 21 AD9258 105 Single Tone FFT with fi 70 1 MHz 105MSPS 140 1MHz 1dBFS SNR 75 5dB 76 5dBFS SFDR 85 0dBc SECOND HARMONIC THIRD HARMONIC Sa T PNE E Um i T RET TOE T nial lia i bi dl Ad La 0 10 20 30 40 50 FREQUENCY MHz Figure 22 AD9258 105 Single Tone FFT with fi 140 1 MHz 08124 074 08124 075 08124 076 AMPLITUDE dBFS AMPLITUDE dBFS AD9258 0 105MSPS 200 3MHz 9
28. SFDR dBFS 0 100 90 80 70 60 50 40 30 20 10 INPUT AMPLITUDE dBFS 08124 064 08124 067 FREQUENCY MHz Figure 10 AD9258 80 Single Tone FFT with fw 140 1 MHz Figure 13 AD9258 80 Single Tone SNR SFDR vs Input Amplitude Aw with fiw 98 12 MHz Rev A Page 17 of 44 AD9258 SNRFS DITHER ON SNRFS DITHER OFF SNR SFDR dBFS 100 90 80 70 60 50 40 30 20 10 INPUT AMPLITUDE dBFS 08124 068 800 000 700 000 600 000 NUMBER OF HITS 200 000 100 000 Figure 14 AD9258 80 Single Tone SNR SFDR vs Input Amplitude Ain with 30 MHz with and without Dither Enabled SFDR SFDR SFDR SNR 40 C 40 C SNR Q 25 C 9 25 C SNR 85 C 85 C SNR SFDR dBFS AND dBc 0 50 100 150 200 250 INPUT FREQUENCY MHz Figure 15 AD9258 80 Single Tone SNR SFDR vs Input Frequency fw 300 with 2 V p p Full Scale 105 SNR CHANNEL B 100 SFDR CHANNEL B SNR CHANNEL A SFDR CHANNEL A 5 a 95 z 4 2 m 90 z m 85 4 z a 80 75 25 30 35 40 45 50 55 60 65 70 75 SAMPLE RATE MSPS e 08124 070 08124 069 Figure 16 AD9258 80 Single Tone SNR SFDR vs Sample Rate fs with fin 70 1 MHz INL ERROR LSB DNL ERRO
29. TION DESIGN GUIDELINES Before starting design and layout of the AD9258 as a system it is recommended that the designer become familiar with these guidelines which discuss the special circuit connections and layout requirements that are needed for certain pins Power and Ground Recommendations When connecting power to the AD9258 it is recommended that two separate 1 8 V supplies be used Use one supply for analog AVDD use a separate supply for the digital outputs DRVDD For both AVDD and DRVDD several different decoupling capa citors should be used to cover both high and low frequencies Place these capacitors close to the point of entry at the PCB level and close to the pins of the part with minimal trace length A single PCB ground plane should be sufficient when using the AD9258 With proper decoupling and smart partitioning of the PCB analog digital and clock sections optimum performance is easily achieved LVDS Operation The AD9258 defaults to CMOS output mode on power up If LVDS operation is desired this mode must be programmed using the SPI configuration registers after power up When the AD9258 powers up in CMOS mode with LVDS termination resistors 100 on the outputs the DRVDD current can be higher than the typical value until the part is placed in LVDS mode This additional DRVDD current does not cause damage to the AD9258 but it should be taken into account when consid ering the maximum DRVDD current
30. UENCY MHz Figure 27 AD9258 105 Single Tone SNR SFDR vs Input Frequency fin with 2 V p p Full Scale 08124 081 105 SNR CHANNEL B SFDR CHANNEL B 100 SNR CHANNEL A SFDR CHANNEL A SNR SFDR dBFS AND dBc 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100105 SAMPLE RATE MSPS Figure 28 AD9258 105 Single Tone SNR SFDR vs Sample Rate fs with fn 70 1 MHz 08124 082 INL ERROR LSB DNL ERROR LSB Rev A Page 20 of 44 700 000 600 000 500 000 400 000 300 000 200 000 100 000 0 N 3 N 2 N 1 N N 1 N 2 N 3 OUTPUT CODE Figure 29 AD9258 105 Grounded Input Histogram DITHER ENABLED DITHER DISABLED 0 50 0 25 2000 4000 6000 8000 10 000 12 000 14 000 16 000 OUTPUT CODE Figure 30 AD9258 105 INL with hy 9 7 MHz 08124 084 2000 4000 6000 8000 10 000 12 000 14 000 16 000 OUTPUT CODE Figure 31 AD9258 105 DNL with fiw 9 7 MHz 08124 083 08124 085 AMPLITUDE dBFS AMPLITUDE dBFS AMPLITUDE dBFS 125MSPS 2 4MHz 1dBFS SFDR 89dBc SNR 76 6dB 77 6dBFS SECOND HARMONIC va THIRD HARMONIC FREQUENCY MHz Figure 32 AD9258 125 Single Tone FFT with fy 2 4 MHz 125MSPS 30 3MHz 1dBFS SNR 76 4dB 77 4dBFS SFDR 91 2dBc THIRD HARMONIC SECOND HARMONIC 30 40 FREQUENCY MHz Fi
31. a 8 True 29 D8 Output Channel A Channel B LVDS Output Data 8 Complement 32 D9 Output Channel A Channel B LVDS Output Data 9 True 31 D9 Output Channel A Channel B LVDS Output Data 9 Complement 34 D10 Output Channel A Channel B LVDS Output Data 10 True 33 D10 Output Channel A Channel B LVDS Output Data 10 Complement 36 011 Output Channel A Channel B LVDS Output Data 11 True 35 D11 Output Channel A Channel B LVDS Output Data 11 Complement 39 D12 Output Channel A Channel B LVDS Output Data 12 True 38 D12 Output Channel A Channel B LVDS Output Data 12 Complement 41 D13 MSB Output Channel A Channel B LVDS Output Data 13 True 40 D13 MSB Output Channel A Channel B LVDS Output Data 13 Complement 43 OR Output Channel A Channel B LVDS Overrange Output True 42 OR Output Channel A Channel B LVDS Overrange Output Complement 25 DCO Output Channel A Channel B LVDS Data Clock Output True 24 DCO Output Channel A Channel B LVDS Data Clock Output Complement SPI Control 45 SCLK DFS Input SPI Serial Clock Data Format Select Pin in External Pin Mode 44 SDIO DCS Input Output SPI Serial Data l O Duty Cycle Stabilizer Pin in External Pin Mode 46 CSB Input SPI Chip Select Active Low ADC Configuration 47 OEB Input Output Enable Input Active Low in External Pin Mode 48 PDWN Input Power Down Input in External Pin Mode In SPI mode this input can be configured as power down or standby
32. ation registers Address 0x00 to Address 0x02 the channel index and transfer registers Address 0x05 and Address OxFF the ADC functions registers including setup control and test Address 0x08 to Address 0x30 and the digital feature control register Address 0x100 The memory map register table see Table 17 lists the default hexadecimal value for each hexadecimal address shown The column with the heading Bit 7 MSB is the start of the default hexadecimal value given For example Address 0x18 the VREF select register has a hexadecimal default value of 0 This means that Bit 7 1 Bit 6 1 and the remaining bits are 0s This setting is the default reference selection setting The default value uses a 2 0 V p p reference For more information on this function and others see the AN 877 Application Note Interfacing to High Speed ADCs via SPI This application note details the functions con trolled by Register 0x00 to Register The remaining register Register 0x100 is documented in the Memory Map Register Table section Open Locations All address and bit locations that are not included in Table 17 are not currently supported for this device Unused bits of a valid address location should be written with 0s Writing to these locations is required only when part of an address location is open for example Address 0x18 If the entire address location is open for example Address 0x13 this address location should
33. between multiple parts the SYNC input signal should be externally synchronized to the input clock signal meeting the setup and hold times shown in Table 5 The SYNC input should be driven using a single ended CMOS type signal Rev A Page 31 of 44 AD9258 POWER DISSIPATION AND STANDBY MODE As shown in Figure 81 the power dissipated by the AD9258 varies with its sample rate In CMOS output mode the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit The maximum DRVDD current IDRVDD can be calculated as IDRVDD VDRVDD x Croan X fax x N where N is the number of output bits 28 plus two DCO outputs in the case of the AD9258 This maximum current occurs when every output bit switches on every clock cycle that is a full scale square wave at the Nyquist frequency of fax 2 In practice the DRVDD current is established by the average number of output bits switching which is determined by the sample rate and the characteristics of the analog input signal Reducing the capacitive load presented to the output drivers reduces digital power consumption The data in Figure 81 was taken in LVDS output mode using the same operating conditions as those used for the Typical Performance Characteristics section 1 25 0 5 1 00 0 4 E E t 0 75 03 amp tc z TOTAL POWER d o 2 d gt 0 50 0 2 S E 2 0 25 0 1 IDRVDD 0 0 25
34. chronous to the ADC clock noise from these signals can degrade converter performance If the on board SPI bus is used for other devices it may be necessary to provide buffers between this bus and the AD9258 to prevent these signals from transi tioning at the converter inputs during critical sampling periods Some pins serve a dual function when the SPI is not being used When the pins are strapped to AVDD or ground during device power on they are associated with a specific function The Digital Outputs section describes the strappable functions supported on the AD9258 CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers the SDIO DCS pin the SCLK DFS pin the OEB pin and the PDWN pin serve as standalone CMOS compatible control pins When the device is powered up it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer output data format output enable and power down feature control In this mode the CSB chip select bar should be con nected to AVDD which disables the serial port interface When the device is in SPI mode the PDWN and OEB pins remain active For SPI control of output enable and power down the OEB and PDWN pins should be set to their default states Table 15 Mode Selection External Pin Voltage Configuration SDIO DCS AVDD default Duty cycle stabilizer enabled AGND Duty cycle stabilizer disabled SCLK DFS AV
35. code when using the SPI control Table 12 SCLK DFS Mode Selection External Pin Mode Voltage at Pin SCLK DFS SDIO DCS AGND Offset binary DCS disabled default AVDD Twos complement DCS enabled default Digital Output Enable Function OEB The AD9258 has a flexible three state ability for the digital output pins The three state mode is enabled using the OEB pin or through the SPI If the OEB pin is low the output data drivers and DCOs are enabled If the OEB pin is high the output data drivers and DCOs are placed in a high impedance state This OEB function is not intended for rapid access to the data bus Note that OEB is referenced to the digital output driver supply DRVDD and should not exceed that supply voltage When using the SPI the data outputs and DCO of each channel can be independently three stated by using the output enable bar bit Bit 4 in Register 0x14 Table 13 Output Data Format TIMING The AD9258 provides latched data with a pipeline delay of 12 clock cycles Data outputs are available one propagation delay ten after the rising edge of the clock signal The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9258 These transients can degrade converter dynamic performance The lowest typical conversion rate of the AD9258 is 10 MSPS At clock rates below 10 MSPS dynamic performance can degrade Data Clock Output DCO The
36. d with a 0 1 uF capacitor as shown in Figure 67 RBIAS The AD9258 requires that a 10 kQ resistor be placed between the RBIAS pin and ground This resistor sets the master current reference of the ADC core and should have at least a 1 tolerance Reference Decoupling The VREF pin should be externally decoupled to ground with a low ESR 1 0 uF capacitor in parallel with a low ESR 0 1 uF ceramic capacitor SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required Because the SCLK CSB and SDIO signals are typically asynchronous to the ADC clock noise from these signals can degrade converter performance If the on board SPI bus is used for other devices it may be necessary to provide buffers between this bus and the AD9258 to keep these signals from transitioning at the converter inputs during critical sampling periods Rev A Page 41 of 44 AD9258 OUTLINE DIMENSIONS 48 PIN 1 INDICATOR 0 50 TOP VIEW ae 5 a BSC EXPOSED PAD 7 50 SQ SC S BOTTOM VIEW 735 0 50 i 0 40 Y 0 30 n t 0 25 MIN qoo 12 MAX 0 80 MAX REF 0 85 Bo l 0 65 TYP FOR PROPER CONNECTION OF 0 80 a 0 05 MAX THE EXPOSED PAD REFER TO Oe EE L 0 02 NOM HOSTA SEATING 0 30 SECTION OF THIS DATA SHEET PLANE 0 20 REF 0 18 COMPLIANT STANDARDS MO 220 VMMD 4 Figure 85 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 9 mm x 9 mm Body Very Thin Quad CP 64 6 Dimensions shown
37. dBFS 8 Figure 38 AD9258 125 Single Tone FFT with fw 70 1 MHz 6 dBFS Figure 41 AD9258 125 Single Tone SNR SFDR vs Input Amplitude Au with Dither Enabled with fin 2 4 MHz 120 125MSPS SFDR dBFS 70 1MHz 23dBFS SNR 56 1dB 79 1dBFS 100 SFDR 67 7dBc 3 SNR dBFS a 2 80 I a 5 THIRD HARMONIC A a 8 60 P SECOND HARMONIC S SFDR dBc 40 5 SNR dBc o 20 0 100 90 80 70 60 50 40 30 20 10 0 INPUT AMPLITUDE dBFS 08123 088 08124 024 FREQUENCY MHz Figure 39 AD9258 125 Single Tone FFT with fiw 70 1 MHz 23 dBFS Figure 42 AD9258 125 Single Tone SNR SFDR vs Input Amplitude Au with Dither Disabled 1M Sample with fiw 98 12 MHz 120 125MSPS 70 1MHz 23dBFS SNR 55 4dB 78 4dBFS SFDR 86 2dBc 110 a P a a 100 8 s SECOND HARMONIC THIRD HARMONIC i a m 90 80 C 70 z Z 100 90 80 70 60 50 40 30 20 10 0 i FREQUENCY MHz B INPUT AMPLITUDE dBFS S Figure 40 AD9258 125 Single Tone FFT with fin 70 1 MHz 23 dBFS Figure 43 AD9258 125 Single Tone SNR SFDR vs Input Amplitude Au with Dither Enabled 1M Sample with fiw 30 MHz with and without Dither Enabled Rev A Page 22 of 44 AD9258 0 SNR 40 C SFDR 40 C SNR 25 C 20 SFDR 25 S SNR Q 85 C 9
38. e consists of a dual front end sample and hold circuit followed by a pipelined switched capacitor ADC The quantized outputs from each stage are combined into a final 14 bit result in the digital correction logic The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples Sampling occurs on the rising edge of the clock Each stage of the pipeline excluding the last consists of a low resolution flash ADC connected to a switched capacitor digital to analog converter DAC and an interstage residue amplifier MDAC The MDAC magnifies the difference between the recon structed DAC output and the flash input for the next stage in the pipeline One bit of redundancy is used in each stage to facilitate digital correction of flash errors The last stage simply consists of a flash ADC The input stage of each channel contains a differential sampling circuit that can be ac or dc coupled in differential or single ended modes The output staging block aligns the data corrects errors and passes the data to the output buffers The output buffers are powered from a separate supply allowing digital output noise to be separated from the analog core During power down the output buffers go into a high impedance state ANALOG INPUT CONSIDERATIONS The analog input to the AD9258 is a differential switched capacitor circuit that has been designed for optimum performa
39. eadback operation performing a readback causes the serial data input output SDIO pin to change direction from an input to an output at the appropriate point in the serial frame All data is composed of 8 bit words Data can be sent in MSB first mode or in LSB first mode MSB first is the default on power up and can be changed via the SPI port configuration register For more information about this and other features see the AN 877 Application Note Interfacing to High Speed ADCs via SPI g o g o z d gt 2 J B H 2 d gt 2 08124 052 Figure 84 Serial Port Interface Timing Diagram Rev A Page 35 of 44 AD9258 HARDWARE INTERFACE The pins described in Table 14 comprise the physical interface between the user programming device and the serial port of the AD9258 The SCLK pin and the CSB pin function as inputs when using the SPI The SDIO pin is bidirectional functioning as an input during write phases and as an output during readback The SPI is flexible enough to be controlled by either FPGAs or microcontrollers One method for SPI configuration is described in detail in the AN 812 Application Note Micro controller Based Serial Port Interface SPI Boot Circuit The SPI port should not be active during periods when the full dynamic performance of the converter is required Because the SCLK signal the CSB signal and the SDIO signal are typically asyn
40. eep the internal reference circuitry powered when faster wake up times are required DIGITAL OUTPUTS The AD9258 output drivers can be configured to interface with 1 8 V CMOS logic families The AD9258 can also be configured for LVDS outputs standard ANSI or reduced output swing mode using a DRVDD supply voltage of 1 8 V In CMOS output mode the output drivers are sized to provide sufficient output current to drive a wide variety of logic families However large drive currents tend to cause current glitches on the supplies that may affect converter performance Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches The default output mode is CMOS with each channel output on separate busses as shown in Figure 2 The output can also be configured for interleaved CMOS via the SPI port In interleaved CMOS mode the data for both channels is output through the Channel A output bits and the Channel B output is placed into high impedance mode The timing diagram for interleaved CMOS output mode is shown in Figure 3 The output data format can be selected for either offset binary or twos complement by setting the SCLK DFS pin when operating in the external pin mode see Table 12 Rev A Page 32 of 44 AD9258 As detailed in the AN 877 Application Note Interfacing to High Speed ADCs via SPI the data format can be selected for offset binary twos complement or gray
41. end sampling distortion which dithering cannot improve However even for such large signal inputs dithering may be useful for certain applications because it makes the noise floor whiter As is common in pipeline ADCs the AD9258 contains small DNL errors caused by random component mis matches that produce spurs or tones that make the noise floor somewhat randomly colored part to part Although these tones are typically at very low levels and do not limit SFDR when the AD9258 ADC is quantizing large signal inputs dithering converts these tones to noise and produces a whiter noise floor Small Signal FFT For small signal inputs the front end sampling circuit typically contributes very little distortion and therefore the SFDR is likely to be limited by tones caused by DNL errors due to random component mismatches Therefore for small signal inputs typi cally those below 6 dBFS dithering can significantly improve SFDR by converting these DNL tones to white noise Static Linearity Dithering also removes sharp local discontinuities in the INL transfer function of the ADC and reduces the overall peak to peak INL In receiver applications utilizing dither helps to reduce DNL errors that cause small signal gain errors Often this issue is overcome by setting the input noise 5 dB to 10 dB above the converter noise By utilizing dither within the converter to correct the DNL errors the input noise requirement can be reduced
42. erformance of the AD9258 For applications in which SNR is a key parameter differential double balun coupling is the recommended input configuration see Figure 68 In this configuration the input is ac coupled and the CML is provided to each input through a 33 Q resistor These resistors compensate for losses in the input baluns to provide a 50 O impedance to the driver In the double balun and transformer configurations the value of the input capacitors and resistors is dependent on the input fre quency and source impedance and may need to be reduced or removed Table 10 displays recommended values to set the RC 0 1uF 0 1uF 0 1uF 2v n e e 3 P network At higher input frequencies good performance can be achieved by using a ferrite bead in series with a resistor and removing the capacitors However these values are dependent on the input signal and should be used only as a starting guide Table 10 Example RC Network Frequency Range R1 Series C1 Differential R2Series C2 Shunt MHz Q Each pF QEach pF Each Oto 100 33 5 15 15 100 to 200 10 5 10 10 100 to 300 10 Remove 66 Remove 1 In this configuration R1 is a ferrite bead with a value of 10 100 MHz An alternative to using a transformer coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver An example is shown in Figure 69 See the AD8352 data sheet for more in
43. et to AVDD or AGND Rev A Page 5 of 44 AD9258 ADC AC SPECIFICATIONS AVDD 1 8 V DRVDD 1 8 V maximum sample rate VIN 1 0 dBFS differential input 1 0 V internal reference DCS enabled unless otherwise noted Table 2 AD9258BCPZ 80 AD9258BCPZ 105 AD9258BCPZ 125 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL TO NOISE RATIO SNR fin 2 4 MHz 25 C 79 0 78 4 77 7 dBFS fin 70 MHz 25 C 77 7 78 3 773 782 76 8 77 6 dBFS Full 77 4 76 9 76 0 dBFS fin 140 MHz 25 C 77 0 76 6 76 6 dBFS fin 200 MHz 25 C 75 3 74 9 75 1 dBFS SIGNAL TO NOISE AND DISTORTION SINAD fin 2 4 MHz 25 C 78 7 778 773 dBFS fin 70 MHz 25 C 77 5 78 0 771 780 76 5 77 0 dBFS Full 77 2 76 7 75 7 dBFS fin 140 MHz 25 C 75 1 75 6 75 3 dBFS fin 200 MHz 25 C 74 2 72 1 73 6 dBFS EFFECTIVE NUMBER OF BITS ENOB fin 2 4 MHz 25 C 12 8 12 6 12 5 Bits fin 70 MHz 25 C 12 7 12 6 12 5 Bits fin 140 MHz 25 C 12 2 12 3 12 2 Bits fin 200 MHz 25 C 12 0 11 7 11 9 Bits WORST SECOND OR THIRD HARMONIC fin 2 4 MHz 25 C 92 87 90 dBc fin 70 MHz 25 C 91 87 92 87 88 83 dBc Full 87 87 83 dBc fin 140 MHz 25 C 80 84 83 dBc fin 200 MHz 25 C 82 76 79 dBc SPURIOUS FREE DYNAMIC RANGE SFDR fin 2 4 MHz 25 C 92 87 90 dBc fin 70 MHz 25 C 87 91 87 92 83 88 dBc Full 87 87 83 dBc fin 140 MHz 25 C 80 84 83 dBc fin 200 MHz 25 C 82 76 79 dBc SPURIOUS FREE
44. evel Input Voltage Full 0 0 6 V High Level Input Current VIN 1 8 V Full 92 135 Low Level Input Current Full 10 10 yA Input Resistance Full 26 kQ Input Capacitance Full 2 pF LOGIC INPUT OUTPUT SDIO DCS High Level Input Voltage Full 1 22 2 1 V Low Level Input Voltage Full 0 0 6 V High Level Input Current Full 10 110 Low Level Input Current Full 38 128 yA Input Resistance Full 26 kQ Input Capacitance Full 5 pF LOGIC INPUTS OEB PDWN High Level Input Voltage Full 1 22 2 1 V Low Level Input Voltage Full 0 0 6 V High Level Input Current VIN 1 8 V Full 90 134 pA Low Level Input Current Full 10 10 Input Resistance Full 26 kQ Input Capacitance Full 5 pF DIGITAL OUTPUTS CMOS Mode DRVDD 1 8 V High Level Output Voltage lon 50 pA Full 1 79 V lou 0 5 mA Full 1 75 V Low Level Output Voltage lo 1 6 mA Full 0 2 V lo 50 pA Full 0 05 V LVDS Mode DRVDD 1 8V Differential Output Voltage Von ANSI Mode Full 290 345 400 mV Output Offset Voltage Vos ANSI Mode Full 1 15 1 25 1 35 V Differential Output Voltage Vop Reduced Swing Mode Full 160 200 230 mV Output Offset Voltage Vos Reduced Swing Mode Full 1 15 1 25 1 35 V Pull up Pull down Rev A Page 8 of 44 SWITCHING SPECIFICATIONS AD9258 AVDD 1 8 V DRVDD 1 8 V maximum sample rate VIN 1 0 dBFS differential input 1 0 V internal reference and DCS enabled unless otherwise noted Table 4 AD9258B
45. for the part To avoid this additional DRVDD current the AD9258 outputs can be disabled at power up by taking the OEB pin high After the part is placed into LVDS mode via the SPI port the OEB pin can be taken low to enable the outputs Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground AGND to achieve the best electrical and thermal performance A continuous exposed no solder mask copper plane on the PCB should mate to the AD9258 exposed paddle Pin 0 The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB These vias should be filled or plugged to prevent solder wicking through the vias which can compromise the connection To maximize the coverage and adhesion between the ADC and the PCB a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections This provides several tie points between the ADC and the PCB during the reflow process Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB For detailed information about packaging and PCB layout of chip scale packages see the AN 772 Application Note A Design and Manufacturing Guide for the Lead Frame Chip Scale Package LFCSP at www analog com VCM The VCM pin should be decoupled to groun
46. formation at VIN AD9258 VCM C 08124 038 Figure 68 Differential Double Balun Input Configuration Vcc 0 1 ANALOG INPUT 0 ANALOG INPUT 00 09258 08124 039 Figure 69 Differential Input Configuration Using the AD8352 Rev A Page 28 of 44 VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9258 The input range can be adjusted by varying the reference voltage applied to the AD9258 using either the internal reference or an externally applied reference voltage The input span of the ADC tracks reference voltage changes linearly The various reference modes are summarized in the sections that follow The Reference Decoupling section describes the best practices for PCB layout of the reference Internal Reference Connection A comparator within the AD9258 detects the potential at the SENSE pin and configures the reference into four possible modes which are summarized in Table 11 If SENSE is grounded the reference amplifier switch is connected to the internal resistor divider see Figure 70 setting VREF to 1 0 V for a 2 0 V p p full scale input In this mode with SENSE grounded the full scale can also be adjusted through the SPI port by adjusting Bit 6 and Bit 7 of Register 0x18 These bits can be used to change the full scale to 1 25 V p p 1 5 V p p 1 75 V p p or to the default of 2 0 V p p as shown in Table 17 Connecting
47. gure 33 AD9258 125 Single Tone FFT with 30 3 MHz 125MSPS 70 1MHz 1dBFS SNR 76 5dB 77 5dBFS SFDR 88 0dBc THIRD HARMONIC SECOND HARMONIC 30 40 FREQUENCY MHz Figure 34 AD9258 125 Single Tone FFT with fin 70 1 MHz 08124 016 08124 017 08124 018 Rev A Page 21 of 44 AMPLITUDE dBFS AMPLITUDE dBFS AMPLITUDE dBFS AD9258 125MSPS 140 1MHz 1dBFS SNR 75 5dB 76 5dBFS SFDR 85 0dBc THIRD HARMONIC SECOND HARMONIC FREQUENCY MHz Figure 35 AD9258 125 Single Tone FFT with f 140 1 MHz 125MSPS 200 3MHz 1dBFS SNR 74 3dB 75 3dBFS SFDR 81dBc THIRD HARMONI SECOND HARMONIC FREQUENCY MHz Figure 36 AD9258 125 Single Tone FFT with fw 200 3 MHz 125MSPS 220 1MHz 1dBFS SNR 74 0dB 75 0dBFS SFDR 79 3dBc THIRD HARMONIC SECOND HARMONIC 0 10 20 30 40 50 60 FREQUENCY MHz Figure 37 AD9258 125 Single Tone FFT with fw 220 1 MHz 08124 019 08124 020 08124 021 AD9258 120 125MSPS SFDR dBFS 70 1MHz 6dBFS SNR 71 6dB 77 6dBFS 100 SFDR 97dBc SNR dBFS F m 80 2 2 z lt a amp 60 P 5 SFDR dBc a z SECOND HARMONIC HIRD HARMONIC E dd SNR dBc 20 0 100 90 80 70 60 50 40 30 20 10 FREQUENCY MHz 8 INPUT AMPLITUDE
48. h Bit 4 in SPI Register 0x17 see Table 17 3 Wake up time is defined as the time required to return to normal operation from power down mode Rev A Page 9 of 44 AD9258 TIMING SPECIFICATIONS Table 5 Parameter Conditions Limit SYNC TIMING REQUIREMENTS tssync SYNC to rising edge of CLK setup time 0 30 ns typ tHsync SYNC to rising edge of CLK hold time 0 40 ns typ SPI TIMING REQUIREMENTS tos Setup time between the data and the rising edge of SCLK 2 ns min toH Hold time between the data and the rising edge of SCLK 2 ns min tak Period of the SCLK 40 ns min ts Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min THIGH SCLK pulse width high 10 ns min trow SCLK pulse width low 10 ns min TEN 500 Time required for the SDIO pin to switch from an input to an output relative to the SCLK 10 ns min falling edge tpis spo Time required for the SDIO pin to switch from an output to an input relative to the SCLK 10 ns min rising edge Timing Diagrams VIN CLK CLK DCOA DCOB CH A CH B DATA VIN CLK CLK DCOA DCOB CH A CH B DATA N 9 9 N 8 N 1 t N 4 5 N N 3 N 1 N 2 tcu terk ee s mA seed t t u e tskew tpp CX A AI ADNR Cal NS Figure 3 CMOS Interleaved Output Mode Data Output Timing Rev A Page 10 of 44 08124 002 081 24 057 08124 003 Figure 4 LVDS Mode Data Output Timing CLK
49. in millimeters ORDERING GUIDE Model Temperature Range Package Description AD9258BCPZ 80 AD9258BCPZRL7 80 AD9258BCPZ 105 AD9258BCPZRL7 105 AD9258BCPZ 125 AD9258BCPZRL7 125 AD9258 80EBZ AD9258 105EBZ AD9258 125EBZ Bm 9 00 BSC SQ lt 0 60 das MAX PIN 1 NN T UUUUU INDICATOR 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 C 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 64 Lead Lead Frame Chip Scale Package LFCSP_VQ Evaluation Board Evaluation Board Evaluation Board 041509 A Package Option CP 64 6 CP 64 6 CP 64 6 CP 64 6 CP 64 6 CP 64 6 17 RoHS Compliant Part Rev A Page 42 of 44 AD9258 NOTES Rev A Page 43 of 44 AD9258 NOTES 2009 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D08124 0 9 09 A DEVICES www analo g com Rev A Page 44 of 44
50. ing AVDD 08124 044 Figure 74 Equivalent Clock Input Circuit Clock Input Options The AD9258 has a very flexible clock input structure Clock input can be a CMOS LVDS LVPECL or sine wave signal Regardless of the type of signal being used clock source jitter is of the most concern as described in the Jitter Considerations section Figure 75 and Figure 76 show two preferred methods for clocking the AD9258 at clock rates up to 625 MHz A low jitter clock source is converted from a single ended signal to a differential signal using either an RF balun or an RF transformer The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz and the RF transformer is recom mended for clock frequencies from 10 MHz to 200 MHz The back to back Schottky diodes across the transformer balun secondary limit clock excursions into the AD9258 to approximately 0 8 V p p differential This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9258 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance Mini Circuits ADC ADT1 1WT 1 1Z AD9258 0 1pF xrug D E CLOCK ic INPUT soo 1000 1 SCHOTTKY 9 0 1uF DIODES i i HSMS2822 5 Figure 75 Transformer Coupled Differential Clock Up to 200 MHz ADC 1nF 0 1uF AD9258 CLOCK INPUT 500 0 1 1nF SCHOTTKY DIODES HSMS2822
51. ister Bit 7 Bit 0 Value Notes Hex Name MSB Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 LSB Hex Comments OxOE BIST enable Open Open Open Open Open Reset BIST Open BIST 0x04 global sequence enable OxOF ADC input Open Open Open Open Open Open Open Common 0x00 global mode servo enable 0x10 Offset adjust Offset adjust in LSBs from 127 to 128 0x00 local twos complement format 0x14 Output mode Drive Output CMOS Output Open Output Output format 0x00 Configures the strength type output enable must be invert 00 offset binary outputs and 0 51 0 CMOS Interleave bar written local 01 twos complement the format of LVDS 1 LVDS enable local low 01 gray code the data 1 global global global 11 offset binary reduced local swing LVDS global 0x16 Clock phase nvert Open Open Open Open Input clock divider phase adjust 0x00 Allows control DCO clock 000 no delay selection of global 001 1 input clock cycle clock delays 010 2 input clock cycles TE 011 23 input clock cycles SOC Oro e 100 4 input clock cycles 101 5 input clock cycles 110 6 input clock cycles 111 27 input clock cycles 0x17 DCO output Open Open Open DCO clock delay 0x00 delay global delay 2500 ps x register value 31 00000 0 ps 00001 81 ps 00010 161 ps 11110 2 2419 ps 11111 2500 ps 0x18 VREF select Reference voltage Open Open Open Open Open Open 0xCO global selection 00 1 25 V p p 01 1 5 V p p 10 1 75 V p p 11 2 0
52. ll 2 2 2 ppm C Gain Error Full 15 15 15 ppm C INTERNAL VOLTAGE REFERENCE Output Voltage Error Full 5 12 5 12 5 12 mV 1 V Mode Load Regulation Full 5 5 5 mV 1 0 mA INPUT REFERRED NOISE VREF 1 0 V 25 C 0 62 0 63 0 7 LSB rms ANALOG INPUT Input Span VREF Full 2 2 2 V p p 1 0 V Input Capacitance Full 8 8 8 pF Input Common Full 0 9 0 9 0 9 V Mode Voltage REFERENCE INPUT Full 6 6 6 kQ RESISTANCE POWER SUPPLIES Supply Voltage AVDD Full 1 7 1 8 1 9 1 7 1 8 1 9 1 7 1 8 1 9 V DRVDD Full 1 7 1 8 1 9 1 7 1 8 1 9 1 7 1 8 1 9 V Supply Current IAVDD Full 234 240 293 300 390 400 mA IDRVDD 1 8 V Full 33 43 53 mA CMOS IDRVDD 1 8 V Full 81 81 90 mA LVDS Rev A Page 4 of 44 AD9258 AD9258BCPZ 80 AD9258BCPZ 105 AD9258BCPZ 125 Max Unit Parameter Temperature Min Typ Max Min Typ Max Min Typ POWER CONSUMPTION DC Input Full 462 487 565 590 750 777 mW Sine Wave Input Full 481 605 797 mW DRVDD 1 8V CMOS Output Mode Sine Wave Input Full 568 671 865 mW DRVDD 1 8 V LVDS Output Mode Standby Power Full 45 45 45 mW Power Down Power Full 0 5 2 5 0 5 2 5 0 5 2 5 mW 1 Measured with a low input frequency full scale sine wave with approximately 5 pF loading on each output bit Input capacitance refers to the effective capacitance between one differential input pin and AGND 3 Standby power is measured with a dc input and with the CLK pins inactive s
53. nal Fixed Reference VREF 0 5 1 0 Programmable Reference 0 2V to VREF R2 2 x VREF 0 5 x 1 see Figure 71 R1 Internal Fixed Reference AGND to 0 2 V 1 0 2 0 Rev A Page 29 of 44 AD9258 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac teristics Figure 73 shows the typical drift characteristics of the internal reference in 1 0 V mode When the SENSE pin is tied to AVDD the internal reference is disabled allowing the use of an external reference An internal reference buffer loads the external reference with an equivalent 6 load see Figure 62 The internal buffer generates the positive and negative full scale references for the ADC core Therefore the external reference must be limited to a maximum of 1 0 V 2 0 1 5 VREF 1 0V 1 0 0 5 0 0 5 REFERENCE VOLTAGE ERROR mV 40 20 0 20 40 60 80 TEMPERATURE C Figure 73 Typical VREF Drift CLOCK INPUT CONSIDERATIONS 08124 055 For optimum performance the AD9258 sample clock inputs CLK and CLK should be clocked with a differential signal The signal is typically ac coupled into the CLK and CLK pins via a transformer or capacitors These pins are biased internally see Figure 74 and require no external bias If the inputs are floated the CLK pin is pulled low to prevent spurious clock
54. nce while processing a differential input signal The clock signal alternatively switches the input between sample mode and hold mode see Figure 64 When the input is switched into sample mode the signal source must be capable of charging the sample capacitors and settling within of a clock cycle A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source A shunt capacitor can be placed across the inputs to provide dynamic charging currents This passive network creates a low pass filter at the ADC input therefore the precise values are dependent on the application In intermediate frequency IF undersampling applications any shunt capacitors should be reduced In combination with the driving source impedance the shunt capacitors limit the input bandwidth Refer to the AN 742 Application Note Frequency Domain Response of Switched Capacitor ADCs the AN 827 Application Note A Resonant Approach to Interfacing Amplifiers to Switched Capacitor ADCs and the Analog Dialogue article Transformer Coupled Front End for Wideband A D Converters for more information on this subject refer to www analog com 08124 034 Figure 64 Switched Capacitor Input For best dynamic performance the source impedances driving VIN and VIN should be matched and the inputs should be differentially balanced An internal differential reference buffer creates positi
55. oduce the result shown 80 0 05ps 75 MEASURED 70 s 0 20ps a 8 x 65 2 7 60 0 50ps 55 1 00ps 1 50 5 50 E 1 10 100 1k 08124 050 INPUT FREQUENCY MHz Figure 80 SNR vs Input Frequency and Jitter The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9258 Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise Low jitter crystal controlled oscillators make the best clock sources If the clock is generated from another type of source by gating dividing or another method it should be retimed by the original clock at the last step Refer to the AN 501 Application Note and the AN 756 Application Note visit www analog com for more information about jitter performance as it relates to ADCs CHANNEL CHIP SYNCHRONIZATION The AD9258 has a SYNC input that offers the user flexible synchronization options for synchronizing the clock divider The clock divider sync feature is useful for guaranteeing synchro nized sample clocks across multiple ADCs The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence The SYNC input is internally synchronized to the sample clock however to ensure that there is no timing uncertainty
56. of the two registers If both bits are set during an SPI read cyde the part returns the value for Channel A Registers and bits designated as global in Table 17 affect the entire part or the channel features for which independent settings are not allowed between channels The settings in Register 0x05 do not affect the global registers and bits Rev A Page 37 of 44 AD9258 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device Table 17 Memory Map Registers Default Default Address Register Bit 7 Bit 0 Value Notes Hex Name MSB Bit6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 LSB Hex Comments Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles configuration are mirrored global so LSB first mode or MSB first mode registers correctly regardless of shift mode 0x01 Chip ID 8 bit chip ID 7 0 0x33 Read only global AD9258 0x33 default 0x02 Chip grade Open Open Speed grade ID Open Open Open Open Speed grade global 01 125 MSPS ID used to 10 105 MSPS differentiate 11 80 MSPS devices read only Channel Index and Transfer Registers 0x05 Channel Open Open Open Open Open Open Data Data 0x03 Bits are set index Channel Channel A to determine B default which device default on the chip receives the next write command
57. option for improved SFDR performance with low power analog input 2 Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz 3 Operation from a single 1 8 V supply and a separate digital output driver supply accommodating 1 8 V CMOS or LVDS outputs 4 Standard serial port interface SPI that supports various product features and functions such as data formatting offset binary twos complement or gray coding enabling the clock DCS power down test modes and voltage reference mode 5 Pin compatibility with the AD9268 allowing a simple migration from 14 bits to 16 bits The AD9258 is also pin compatible with the AD9251 AD9231 and AD9204 family of products for lower sample rate low power applications Rev A Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2009 Analog Devices Inc All rights reserved AD9258 TABLE OF CONTENTS Feature
58. pee i pi etin 33 Built In Self Test BIST and Output 34 Built In Self Test BIST esee 34 Output Test 34 Serial Port Interface SPI ariii ay 35 Configuration Using the SPI sse 35 Hardware Interface eee et els 36 Configuration Without the SPI sss 36 SPI Accessible Features eee ettet eere e Rate 36 eter s 37 Reading the Memory Map Register 37 Memory Map Register Table sse 38 Memory Map Register Descriptions sss 40 Applications Information eene 41 Design Guidelines ade eere Rr Ren 41 Outline E Te 42 Ordering G den eee etta 42 Rev A Page 2 of 44 GENERAL DESCRIPTION The AD9258 is a dual 14 bit 80 MSPS 105 MSPS 125 MSPS analog to digital converter ADC The AD9258 is designed to support communications applications where high performance combined with low cost small size and versatility is desired The dual ADC core features a multistage differential pipelined architecture with integrated output error correction logic Each ADC features wide bandwidth differential sample and hold analog input amplifiers that support a variety of user selectable input ranges An integrated voltage reference eases design consid erations A duty cycle stabilizer is provided to compensate for variations in the
59. put voltage at an optimal level If both channels are operational Channel A is monitored However if Channel A is in power down or standby mode then the Channel B input is monitored Dither The AD9258 has an optional dither mode that can be selected for one or both channels Dithering is the act of injecting a known but random amount of white noise commonly referred to as dither into the input of the ADC Dithering has the effect of improving the local linearity at various points along the ADC transfer function Dithering can significantly improve the SFDR when quantizing small signal inputs typically when the input level is below 6 dBFS As shown in Figure 65 the dither that is added to the input of the ADC through the dither DAC is precisely subtracted out digitally to minimize SNR degradation When dithering is enabled the dither DAC is driven by a pseudorandom number generator PN gen In the AD9258 the dither DAC is precisely calibrated to result in only a very small degradation in SNR and the SINAD The typical SNR and SINAD degradation values with dithering enabled are only 1 dB and 0 8 dB respectively NOME EI AD9258 1 1 2 DITHER ENABLE 08124 058 Figure 65 Dither Block Diagram Large Signal FFT In most cases dithering does not improve SFDR for large signal inputs close to full scale for example with a 1 dBFS input For large signal inputs the SFDR is typically limited by front
60. s oce LL uer 1 Applications oeste tan 1 Functional Block Diagram sse 1 Product Highlights cre tet ope e a e Oden 1 REVISION S eese 2 General Descriptio tette mt ee 3 Specifications eite rte iiie aero ended 4 ADC DC Specifications dte itera pierna 4 ADG AG Specifications ecd reet eta iva 6 Digital Specifications seen 7 Switching Specifications seen 9 Timing Specifications e tei nitet 10 Absolute Maximum Ratings Thermal Characteristics ESD Caution cie ern ES Pin Configurations and Function Descriptions 13 Typical Performance Characteristics ses 17 Equivalent Circuits i td e quee 25 Theory of Operation tereti teniente nto 26 ERU RRRER RETE 26 Analog Input Considerations sse 26 Voltage Reference iere erento iais 29 REVISION HISTORY 9 09 Rev 0 to Rev A Changes to Features Lists sists certet iter re tiae eher Changes to Specifications Section Changes t Table oet eidte tete RR Mee Changes to Typical Performance Characteristics Section 17 5 09 Revision 0 Initial Version Clock Input Considerations see 30 Channel Chip Synchronization se 31 Power Dissipation and Standby Mode 32 Digital Outp ts dett a ERRORES 32 TIAE eet teet
61. s can be performed with or without an analog signal if present the analog signal is ignored but they do require an encode clock For more information see the AN 877 Application Note Interfacing to High Speed ADCs via SPI Rev A Page 34 of 44 SERIAL PORT INTERFACE SPI The AD9258 serial port interface SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC The SPI gives the user added flexibility and customization depending on the application Addresses are accessed via the serial port and can be written to or read from via the port Memory is organized into bytes that can be further divided into fields which are documented in the Memory Map section For detailed operational information see the AN 877 Application Note Interfacing to High Speed ADCs via SPI CONFIGURATION USING THE SPI Three pins define the SPI of this ADC the SCLK DFS pin the SDIO DCS pin and the CSB pin see Table 14 The SCLK DFS a serial clock is used to synchronize the read and write data presented from and to the ADC The SDIO DCS serial data input output is a dual purpose pin that allows data to be sent to and read from the internal ADC memory map registers The CSB chip select bar is an active low control that enables or disables the read and write cycles Table 14 Serial Port Interface Pins Pin Function SCLK Serial Clock The serial shift
62. t DRVDD AVDD L l L I PAD VREF I 6kQ 1 I Figure 57 Digital Output Figure 62 Equivalent VREF Circuit DRVDD 3500 3500 PDWN SDIO DCS 26kQ 1 I 08124 015 08124 010 Figure 58 Equivalent SDIO DCS Circuit Figure 63 Equivalent PDWN Input Circuit DRVDD SCLK DFS 3500 OR OEB 26 08124 011 Figure 59 Equivalent SCLK DFS OEB Input Circuit Rev A Page 25 of 44 AD9258 THEORY OF OPERATION The AD9258 dual core analog to digital converter ADC design can be used for diversity reception of signals in which the ADCs are operating identically on the same carrier but from two separate antennae The ADCs can also be operated with inde pendent analog inputs The user can sample any fs 2 frequency segment from dc to 200 MHz using appropriate low pass or band pass filtering at the ADC inputs with little loss in ADC performance Operation to 300 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion In nondiversity applications the AD9258 can be used as a base band or direct downconversion receiver in which one ADC is used for I input data and the other is used for Q input data Synchronization capability is provided to allow synchronized timing between multiple devices Programming and control of the AD9258 are accomplished using a 3 wire SPI compatible serial interface ADC ARCHITECTURE The AD9258 architectur
63. the SENSE pin to the VREF pin switches the reference amplifier output to the SENSE pin completing the loop and pro viding a 0 5 V reference output for a 1 V p p full scale input VIN A VIN B VIN A VIN B AD9258 08124 040 Figure 70 Internal Reference Configuration Table 11 Reference Configuration Summary AD9258 If a resistor divider is connected externally to the chip as shown in Figure 71 the switch again sets to the SENSE pin This puts the reference amplifier in a noninverting mode with the VREF output defined as follows VREF 0 5x 1 x RI The input range of the ADC always equals twice the voltage at the reference VREF pin for either an internal or an external reference VIN A VIN B VIN A VIN B AD9258 08124 041 Figure 71 Programmable Reference Configuration If the internal reference of the AD9258 is used to drive multiple converters to improve gain matching the loading of the reference by the other converters must be considered Figure 72 shows how the internal reference voltage is affected by loading o s B NI b 1 0 2 0 REFERENCE VOLTAGE ERROR 1 a 02 04 06 08 10 12 14 16 1 8 LOAD CURRENT mA Figure 72 Reference Voltage Accuracy vs Load Current I o 08124 054 Selected Mode SENSE Voltage Resulting VREF V Resulting Differential Span V p p External Reference AVDD N A 2 x external reference Inter
64. tions are also provided to place predictable values on the outputs of the AD9258 BUILT IN SELF TEST BIST The BIST is a thorough test of the digital portion of the selected AD9258 signal path When enabled the test runs from an internal pseudorandom noise PN source through the digital datapath starting at the ADC block output The BIST sequence runs for 512 cycles and stops The BIST signature value for Channel A or Channel B is placed in Register 0x24 and Register 0x25 If one channel is chosen its BIST signature is written to the two registers If both channels are chosen the results from Channel A are placed in the BIST signature registers The outputs are not disconnected during this test so the PN sequence can be observed as it runs The PN sequence can be continued from its last value or reset from the beginning based on the value programmed in Register OxOE Bit 2 The BIST signature result varies based on the channel configuration OUTPUT TEST MODES The output test options are shown in Table 17 When an output test mode is enabled the analog section of the ADC is discon nected from the digital back end blocks and the test pattern is run through the output formatting block Some of the test patterns are subject to output formatting and some are not The seed value for the PN sequence tests can be forced if the PN reset bits are used to hold the generator in reset mode by setting Bit 4 or Bit 5 of Register OxOD These test
65. ve and negative reference voltages that define the input span of the ADC core The span of the ADC core is set by this buffer to 2 x VREF Input Common Mode The analog inputs of the AD9258 are not internally dc biased In ac coupled applications the user must provide this bias externally Setting the device so that VCM 0 5 x AVDD or 0 9 V is recommended for optimum performance but the device functions over a wider range with reasonable perfor mance see Figure 54 An on board common mode voltage reference is included in the design and is available from the VCM pin Optimum performance is achieved when the common mode voltage of the analog input is set by the VCM pin voltage typically 0 5 x AVDD The VCM pin must be decoupled to ground by a 0 1 capacitor as described in the Applications Information section Rev A Page 26 of 44 Common Mode Voltage Servo In applications where there may be a voltage loss between the VCM output of the AD9258 and the analog inputs the common mode voltage servo can be enabled When the inputs are ac coupled and a resistance of gt 100 Q is placed between the VCM output and the analog inputs a significant voltage drop can occur and the common mode voltage servo should be enabled Setting Bit 0 in Register OxOF to a logic high enables the VCM servo mode In this mode the AD9258 monitors the common mode input level at the analog inputs and adjusts the VCM output level to keep the common mode in
66. vider with the ability to divide the input clock by integer values between 1 and 8 For divide ratios of 1 2 or 4 the duty cycle stabilizer DCS is optional For other divide ratios divide by 3 5 6 7 and 8 the duty cycle stabilizer must be enabled for proper part operation The AD9258 clock divider can be synchronized using the external SYNC input Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written A valid SYNC causes the clock divider to reset to its initial state This synchro nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and as a result may be sensitive to clock duty cycle The AD9258 requires a tight tolerance on the clock duty cycle to maintain dynamic performance characteristics The AD9258 contains a duty cycle stabilizer DCS that retimes the nonsampling falling edge providing an internal clock signal with a nominal 5096 duty cycle This allows the user to provide a wide range of clock input duty cycles without affecting the perfor mance of the AD9258 Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS enabled Jitter in the rising edge of the input is still of paramount concern and

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