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ANALOG DEVICES OP275 handbook

1. CURRENT NOISE DENSITY pA V Hz 10 100 1k 100k FREQUENCY Hz TPC 17 Current Noise Density vs Frequency 0 275 16 14 I VOMI 12 2 R 210 2 8 o VOM 6 lt 4 7 5 Ty 25 C 2 Vg 154 0 100 1k 10k LOAD RESISTANCE Q TPC 12 Maximum Output Voltage vs Load Resistance 120 110 100 ABSOLUTE OUTPUT CURRENT mA 59 5 0 25 50 75 100 TEMPERATURE TPC 15 Short Circuit Current vs Temperature 500 400 300 UNITS 200 100 0123 4 5 67 8 9 10 TCVos pV C TPC 18 TCVos Distribution 10 8 6 0 1 0 01 4 gt i o0 n d 5 0 1 0 01 a 6 8 10 500 400 300 200 100 0 100 200 300 400 500 0 100 200 300 400 500 600 700 800 900 100 200 300 400 500 INPUT OFFSET VOLTAGE pV SETTLING TIME ns CAPACITIVE LOAD pF TPC 19 Input Offset Vos TPC 20 Step Size vs Settling TPC 21 Slew Rate vs Capacitive Distribution Time Load 40 35 30 i POE TATAR CCE 3 2 15 10 o 5 50 25 0 25 50 75 100 DIFFERENTIAL INPUT VOLTAGE V
2. amp C TPC 22 Slew Rate vs Differential TPC 23 Slew Rate vs Temperature TPC 24 Negative Slew Rate Input Voltage 2kO Vs 15 Ay 1 CH 80 0 FS 10 0 MKR 6 23 nV Hz Is pepe 2 1 000 2 awe TPC 25 Positive Slew Rate TPC 26 Small Signal Response TPC 27 Voltage Noise Density 2 15 Ay 1 2 5 Ay 1 vs Frequency Vs 15 V 6 REV 0 275 APPLICATIONS Circuit Protection OP275 has been designed with inherent short circuit protection to ground An internal 30 Q resistor in series with the output limits the output current at room temperature to Isc 40 mA and Igc 90 mA typically with 15 V supplies However shorts to either supply may destroy the device when excessive voltages or currents are applied If it is possible for a user to short an output to a supply for safe operation the output current of the OP275 should be design limited to 30 mA as shown in Figure 1 Total Harmonic Distortion Total Harmonic Distortion Noise THD N of the OP275 is well below 0 001 with any load down to 600 However this is dependent upon the peak output swing In Figure 2 the THD Noise with 3 V rms output is below 0 001 In Figure 3 THD Noise is below 0 001 for the 10 and 2 loads but increases to above 0 1 for the 600 load condition This is a result of t
3. a E PSRR 0 180 5 240 2 40 2 2 6 20 225 8 20 20 40 270 0 0 60 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 1k 10k 100k 1M 10M 100M FREQUENCY Hz FREQUENCY Hz FREQUENCY Hz 7 Common Mode TPC 8 Power Supply Rejection vs TPC 9 Open Loop Gain Rejection vs Frequency Frequency Phase vs Frequency 4 REV 65 N X z o 10 On 60 3 B tr a 1 E 55 2 5 x A GBW 5 E ma 50 lt z a 4 7 40 50 25 0 25 50 75 100 TEMPERATURE C TPC 10 Gain Bandwidth Product Phase Margin vs Temperature gt 1 5 2 o E 2 2 2 z gt lt gt 0 1k 10k 100k 1 OM FREQUENCY Hz I TPC 13 Maximum Output Swing vs Frequency 300 250 1 E 200 tc 5 o 150 o lt a 100 2 a 2 7 50 0 50 25 0 25 50 75 100 TEMPERATURE C TPC 16 Input Bias Current vs Temperature REV C Avc 1 NEGATIVE EDGE Ayc 1 OVERSHOOT Vin 100mV 0 0 100 200 300 400 500 LOAD CAPACITANCE pF TPC 11 Small Signal Overshoot vs Load Capacitance SUPPLY CURRENT mA 5 10 15 20 25 SUPPLY VOLTAGE V TPC 14 Supply Current vs Supply Voltage a gt
4. ORDERING GUIDE Model Temperature Range Package Description Package Option OP275GP 40 C to 855 C 8 Lead PDIP N OP275GS 4409 85 C 8 450 R OP275GS RBEL 140 C tol t850 8 LeadSOIC LR OP275GS REEL7 40 C to 85 C 8 Lead SOIC R 8 OP275GSZ 40 C to 85 C 8 Lead SOIC R 8 OP275GSZ REEL 409 to 85 C 8 Lead SOIC R 8 OP275GSZ REEL7 40 C to 85 C 8 Lead SOIC R 8 Z Pb free part CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection Although the OP275 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality REV C ESD WARNING SENSITIVE DEVICE 0P275 Typical Performance Characteristics 25 1500 20 1250 gt 15 z g 10 gt 1000 8 o n 5 2 m o ul lt 8 O p O 750
5. lt 2 lt 5 9 l gt 2 500 5 10 5 15 9 250 o 20 25 0 0 5 10 x15 x20 x25 50 25 0 25 50 75 100 10k 100k 1M 10M SUPPLY VOLTAGE V TEMPERATURE FREQUENCY Hz TPC 1 Output Voltage Swing TPC 2 Open Loop Gain vs TPC 3 Closed Loop Gain and vs Supply Voltage Temperature Phase Ay 41 50 60 MARKER 15 309 059Hz 60 A H 60 115dB F uy 40 E z oe d V 45 100 A 25 50 s ii 50 25 VeL 25 C 40 1 1 40 2 20 e n 30 135 2 10 n Ayc 10 9 20 90 9 a 10 9 30 2 MARKER 15 309 058Hz 5 8 5 Aver 100 2 10 90 606Deg 45 0 l u Aver 1 20 0 9 9 10 10 45 I o 10 a 20 20 90 30 a 0 10k 100k 1M 10M i Tk 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M FREQUENCY Hz i FREQUENCY Hz FREQUENCY Hz TPC 4 Open Loop Gain TPC 5 Closed Loop Gain vs TPC 6 Closed Loop Output Phase vs Frequency Frequency Impedance vs Frequency 120 120 100 m m 80 0 5100 100 2kQ a d PSRR GAIN Ta 25 m 60 45 b 5 50 gt 40 0 58 90 3 MS z 58 d 3 Vs 15 PHASE 2 ui 25 8 ui 60 60 a 20 135 gt al
6. SCHOTTKY DIODES D1 D4 ARE HEWLETT PACKARD HP5082 2835 IS 1 2 OP260AJ 15 IC2 IS PMI OP41EJ Figure 11 OP275 s Settling Time Test Fixture Figure 14 Conmpencating the Feedback Pole Attention to Source Impedances Minimizes Distortion s Since the 275 is a very low distortion amplifier careful atten Figure 12 Unity Gain Follower tion should be given to source impedances seen by both inputs As with many FET type amplifiers the p channel JFETs in the 15V OP275 s input stage exhibit a gate to source capacitance that var ies with the applied input voltage In an inverting configuration the inverting input is held at a virtual ground and as such does not vary with input voltage Thus since the gate to source voltage is constant there is no distortion due to input capacitance modu lation In noninverting applications however the gate to source voltage is not constant The resulting capacitance modulation can cause distortion above 1 kHz if the input impedance is greater than 2 and unbalanced Rg Re O Vour Rg Rg Re IF Rg Re gt 2kO FOR MINIMUM DISTORTION Figure 13 Unity Gain Inverter In inverting and noninverting applications the feedback resis tance forms a pole with the source resistance and capacitance Figure 15 Balanced Input Impedance to Minimize Rs and Cs and the OP275 s input capacitance Cr as shown Distortion in Noninverting Amplifier Circuits in Figure 14 With Rs a
7. VIN 4V p p 100Hz RL 2 43kQ A1 1 2 OP275 Figure 10 Overload Recovery Time Test Circuit Measuring Settling Time The design of OP275 combines a high slew rate and a wide gain bandwidth product to produce a fast settling ts lt 1 us amplifier for 8 and 12 bit applications The test circuit designed to mea sure the settling time of the OP275 is shown in Figure 11 This test method has advantages over false sum node techniques in that the actual output of the amplifier is measured instead of an error voltage at the sum node Common mode settling effects are exercised in this circuit in addition to the slew rate and band width effects measured by the false sum node method Of course a reasonably flat top pulse is required as the stimulus output waveform of the OP275 under test is clamped by Schottky diodes and buffered by the JFET source follower signal is amplified by a factor of 10 by the OP260 and then Schottky clamped at the output to prevent overloading the oscilloscope s input amplifier The OP41 is configured as a fast integrator which provides overall dc offset nulling High Speed Operation As with most high speed amplifiers care should be taken with supply decoupling lead dress and component placement Recommended circuit configurations for inverting and nonin verting applications are shown in Figures 12 and 13 REV C 0 275 16V 20V O OUTPUT TO SCOPE 16V 20V 5V
8. 12 G4 98 24 23 28 1 C2 5 6 364E 12 TL 97 4 100 3 COMMON MODE GAIN NETWORK WITH ZERO AT IOS 1 2 1E 9 1 kHz EOS 9 3 POLY 1 26 28 0 5E 3 1 Ql 5 2 7 QX R12 25 26 1E6 Q2 6 9 8 QX C7 25 26 1 5915E 12 R5 7 4 1 672 R13 26 98 1 R6 8 4 1 672 E2 25 98 POLY 2 1 98 2 98 0 2 50 Di 2 36 DZ 2 50 D2 L 36 DZ EN 3 1 10 0 1 POLE AT 100 MHz GN1 0 2 13 0 1E 3 GN2 0 I 16 0 1 3 R14 27 98 1 C8 27 98 4 1 899E 9 EREF 98 0 28 1 65 9831 2 24 1 97 0 99 B a 51 0 50 0 1 OUTPUT STAGE VOLTAGE NOISE SOURCE R15 28 99 100E3 R16 28 50 100E3 DN1 35 110 DEN C9 28 50 1 6 DN2 10 11 DEN ISY 99 50 1 85E 3 VN1 35 9 DC 2 R17 29 99 100 VN2 0 11 DC 2 R18 29 50 100 L2 29 34 1 9 CURRENT NOISE SOURCE G6 32 50 27 29 10 3 G7 33 250 29 27 10 3 DN3 122 3 DIN G8 29 99 99 27 10E 3 DN4 13 14 DIN G9 50x 29 27 50 10 3 VN3 12 0 DC 2 V4 30 29 1223 VN4 0 14 DC 2 V5 29 31 3 8 F1 29 0 V4 1 CURRENT NOISE SOURCE F2 0 29 V5 1 D5 27 30 DX DN5 15 16 DIN D6 31 224 DX DN6 16 17 DIN D7 99 732 DX VN5 15 0 DC 2 D8 99 33 DX VN6 0 17 DC 2 D9 50 32 DY D10 50 33 DY GAIN STAGE amp DOMINANT POLE AT 32 Hz MODELS USED R7 18 98 1 09E6 C3 18 98 4 9 MODEL PNP BF 5E5 G1 98 18 5 6 4 57E 1 MODEL DX D IS 1E 12 V2 97 19 1 35 MODEL DY D IS 1E 15 BV 50 V3 20022584 1235 MODEL DZ D IS 1E 15 BV 7 0 D3 18 19 DX MODEL DEN D IS 1E 12 RS 4 35K KF 1 95E 15 D4 20 18 DX AF 1 MODEL DIN D IS 1E 12 RS
9. 135 3 43 0 015 0 120 3 05 0 180 038 4 57 MIN MAX 0 015 0 38 0 150 3 81 SE ed 0 010 0 25 Location Page 2104 Sheet changed from REV B to REV C Changes to ABSOLUTE MAXIMUM RATINGS 2 1 2 3 Changes to ORDERING GUIDE entrate eto De e ae EO Wa Ace CREER US M e 3 Updated OUTLINE DIMENSIONS 1 2 RE eR Oe IC mu doe P eee Reve a NI Doe ER HORE 12 1 03 Data Sheet changed from REV A to REV B Deleted WAFER TEST LIMTTS eu RIVE Gat npa dE RI EIER HR EAE ERIS Ran e ue rer RE e 3 Edits to ABSOLUTE MAXIMUM 5 1 3 Editsto ORDERING GUIDE eorpore RR ce RC RM UC ER HIC UR Wake er aOR rae tede aad 3 Deleted DICE CHARACTERISTICS Sane ace PG Nec We CE REGI PE PAY E e Y ee Y S 3 Updated OUTLINE DIMENSIONS RN So OR eR ee he aes 12 12 REV 00298 0 2 04
10. 268 1 08 15 AF 1 ENDS REV C 11 0 275 OUTLINE DIMENSIONS 8 Lead Standard Small Outline Package SOIC S Suffix R 8 Dimensions shown in millimeters and inches 5 00 0 1968 0 1 M 8 5 4 00 0 1574 6 20 0 2440 3 80 0 1497 T1 4 5 80 0 2284 1 27 0 0500 0 50 0 0196 5 BSC 1 75 0 0688 0 25 0 0099 0 25 0 0099 0 25 0 0098 1 35 0 0532 0 10 0 0040 IN 051 0 0201 RT VT COPLANARITY SEATING 0 31 00 0122 0 25 0 0098 1 27 0 0500 ATING 0 17 0 0067 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8 Lead Plastic Dual in Line Package PDIP P Suffix N 8 Dimensions shown in inches and millimeters 0 375 9 53 0 365 9 27 0 355 9 02 ia 0 295 7 49 0 285 7 24 0 275 6 98 0 325 8 26 0 310 7 87 1 1 0 130 3 30 PLANE 0 008 0 20 0 110 2 79 2 79 0 060 1 52 0 022 0 56 0 050 1 27 0 018 0 46 0 045 1 14 0 014 0 36 COMPLIANT TO JEDEC STANDARDS MO 095AA CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History 0 300 7 62 0 150 3 81 p 0
11. Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or oth erwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 8 Lead PDIP P Suffix Improved performance is also provided with bias and offset currents greatly reduced over purely bipolar designs Input offset voltage is guaranteed at 1 mV and is typically less than 200 uV This allows the 275 to be used in many dc coupled or sum min applications without the je for special selections or the added noise of additional g fset adjustment circuitry The output is capable of driving 600 Q loads to 10 V rms while maintaining low distortion THD Noise at 3 V rms is a low 0 000696 OP275 is specified over the extended industrial 40 C to 85 C temperature range OP275s are available in both plas tic DIP and SOIC 8 packages SOIC 8 packages are available in 2500 piece reels Many audio amplifiers are not offered in SOIC 8 surface mount packages for a variety of reasons however the OP275 was designed so that it would offer full performance in surface mount packaging One Technology Way PO Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www
12. 0 800 1000 Cioap PF Figure 16 Bandwigth vs High Speed Low Noise Differential Line Driver The circuit in Figure 17 is a unique line driver widely used in industrial applications With 18 V supplies the line driver can deliver a differential signal of 30 V p p into a 2 5 kO load The high slew rate and wide bandwidth of the OP275 combine to yield a full power bandwidth of 130 kHz while the low noise front end produces a referred to input noise voltage spectral density of 10 nV Hz A1 1 2 OP275 A2 A3 1 2 OP275 GAIN 82 SET R2 R4 R5 R1 AND R6 R7 R8 R3 Figure 17 High Speed Low Noise Differential Line Driver 10 The design is transformerless balanced transmission system where output common mode rejection of noise is of paramount importance Like the transformer based design either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1 Other circuit gains can be set according to the equation in the diagram This allows the design to be easily set to noninverting inverting or differential operation A 3 Pole 40 KHz Low Pass Filter closely matched and uniform ac characteristics of the 275 make it ideal for use in GIC Generalized Impedance Converter and FDNR Frequency Dependent Negative Resistor filter applications The circuit in Figure 18 illustrates a linear phase 3 pole 40 kHz low pass filter using an OP275 as an indu
13. ANALOG DEVICES Dual Bipolar JFET Audio Operational Amplifier 0P275 PIN CONNECTIONS 8 Lead Narrow Body SOIC S Suffix FEATURES Excellent Sonic Characteristics Low Noise 6 nV Hz Low Distortion 0 0006 High Slew Rate 22 V s Wide Bandwidth 9 MHz Low Supply Current 5 mA Low Offset Voltage 1 mV Low Offset Current 2 nA Unity Gain Stable SOIC 8 Package PDIP 8 Package APPLICATIONS High Performance Audio Active Filters Fast Amplifiers Integrators GENERAL DESCRIPTION The OP275 is the first amplifier to feature the Butler Amplifier front end This new front end design combines both bipolar and JFET transistors to attain amplifiers with thesaccuracy and low noise performance of bipolar transistors and the speed and sound quality of JFETs Distortionplus Noise equals that of previous audio amplifiers but at much lower supply currents A very low l f corner of below 6 Hz maintains a flat noise density response Whether noise is measured at either 30 Hz or 1 kHz it is only 6 nV Hz The JFET portion of the input stage gives the OP275 its high slew rates to keep distortion low even when large output swings are required and the 22 V us slew rate of the OP275 is the fastest of any standard audio amplifier Best of all this low noise and high speed are accomplished using less than 5 mA of supply current lower than any standard audio amplifier Protected by U S Patent No 5 101 126 REV C
14. Voltage Range Vs t4 5 22 V DYNAMIC PERFORMANCE Slew Rate SR Ry 2 15 22 V us Full Power Bandwidth BWp kHz Gain Bandwidth Product GBP 9 MHz Phase Margin On 62 Degrees Overshoot Factor Vin 100 mV Ay 1 600 0 100 pF 10 Specifications subject to change without notice 2 REV 0 275 ABSOLUTE MAXIMUM RATINGS Supply Voltage cessus e Rech ene e alae aia 22V Input Voltage opto cent GUY I EAS 22V Differential Input Voltage 7 5V Output Short Circuit Duration to GND Indefinite Storage Temperature Range P S Packages 659 to 150 Operating Temperature Range 2 chord 32s Wt ale m e esa 40 C to 85 C Junction Temperature Range Pp S Packages wv I wee Re 65 C to 150 C Lead Temperature Range Soldering 60sec 300 C Package Type 0 Orc Unit 8 Lead Plastic DIP P 103 43 C W 8 Lead SOIC S 158 43 C W NOTES Absolute maximum ratings apply to packaged parts unless otherwise noted For supply voltages greater than 22V the absolute maximum input voltage is equal to the supply voltage 3Shorts to either supply may destroy the device See data sheet for full details UA is specified for the worst case conditions i e 074 is specified for device in socket for PDIP packages is specified for device soldered in circuit board for SOIC packages
15. analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved 0P275 SPECIFICATIONS ELECTRI CAL CHARACTERISTI CS V 215 0 V T 25 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit AUDIO PERFORMANCE THD Noise Vin 3 V rms 2 kQ f 1 kHz 0 006 Voltage Noise Density f 30 Hz 7 nV Hz f 1kHz 6 nV Hz Current Noise Density in f 1 kHz 1 5 pA Hz Headroom THD Noise 0 01 Ry 2 kQ Vs 18 V gt 12 9 dBu INPUT CHARACTERISTICS Offset Voltage Vos 1 mV 409 x T4 85 1 25 mV Input Bias Current Ig Vem 0V 100 350 nA Vem OV 40 C x T4 85 100 400 nA Input Offset Current Ios Vem 0V 2 50 nA Vem 0V 40 C x T4 85 2 100 nA Input Voltage Range Vem 10 5 10 5 V Common Mode Rejection Ratio CMRR Vom 10 5V 409 x T4 85 80 106 dB Large Signal Voltage Gain Ayo Ry 2 250 V mV Ry 2 40 C lt T4 85 C 175 V mV 600 0 200 V mV Offset Voltage Drift AVos AT 2 OUTPUT CHARACTERISTICS Output Voltage Swing Vo Ry 2 13 5 13 9 13 5 V AK 340 ET lt 8556 6 13 V 1 1 PRE 60404 55 318 deas V POWER SUPPLY Power Supply Rejection Ratio PSRR Vs 4 5V to 18 V 85 111 dB Vs t4 5V to 18V 409 x T 85 C 80 dB Supply Current Isy Vs 4 5 V to 18 V Vo OV Ry 40 x Ty x 85 C 4 5 mA Vs t22V Vo 0 V Ri 0 409 x T4 85 C 5 5 mA Supply
16. ctance simulator gyrator The circuit uses one OP275 A2 and A3 for the FDNR and one 275 1 and A4 as an input buffer and bias current source for A3 Amplifier A4 is configured in a gain of 2 to set the pass band magnitude response to 0 dB The ben efits of this filter topology over classical approaches are that the op amp used in the FDNR is not in the signal path and that the filter s performance is relatively insensitive to component varia tions Also the configuration is such that large signal levels can be handled without overloading any of the filter s internal nodes As shown in Figure 19 the OP275 s symmetric slew rate and low distortion produce a clean well behaved transient response R1 95 3 2 R6 1870 4 12k0 A1 A4 1 2 275 A2 1 2 275 Vout 10V p p 10kHz SCALE VERTICAL 2V DIV HORIZONTAL 10ps DIV Figure 19 Low Pass Filter Transient Response REV C 0 275 OP275 SPICE Model POLE ZERO PAIR AT 1 5 MHz 2 7 MHz Node assignments R8 21 98 1 3 noninverting input R9 21 22 1 25E 3 inverting input 4 22 98 47 2 12 positive supply G2 98 21 18 28 1E 3 negative supply output POLE AT 100 MHz kk SUBCKT OP275 1 2 99 50 34 R10 23 98 1 C5 23 98 1 59E 9 INPUT STAGE amp POLE AT 100 MHz G3 98 23 21 28 1 R3 5 5I 2 188 POLE 100 MHz R4 6 51 2 188 CIN 1 2 3 7 12 R11 24 98 1 1 1 98 7 12 C6 24 98 1 59E 9 CM2 2 98 7 5E
17. ge of the OP275 may exhibit phase reversal if either of its inputs exceeds its negative common mode input voltage This might occur in very severe industrial applications where a sensor or system fault might apply very large voltages on the inputs of the OP275 Even though the input voltage range of the OP275 is 10 5 V an input voltage of approximately 13 5 V will cause output voltage phase reversal In inverting amplifier con figurations the OP275 s internal 7 5 V input clamping diodes will prevent phase reversal however they will not prevent this effect from occurring in noninverting applications For these applications the fix is a simple one and is illustrated in Figure 9 A 3 92 kO resistor in series with the noninverting input of the OP275 cures the problem Rep Vout Rs 3 92k0 2 Reg IS OPTIONAL L Figure 9 Output Voltage Phase Reversal Fix Overload or Overdrive Recovery Overload or overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to a rated output voltage from a saturated condition This recovery time is important in applications where the amplifier must recover quickly after a large abnormal transient event The circuit shown in Figure 10 was used to evaluate the OP275 s overload recovery time The OP275 takes approximately 1 2 ms to recover to Vour 10 V and approximately 1 5 us to recover to 10 V R1 1kQ R2 10kQ Vout
18. he output swing capability of the OP275 Notice the results in Figure 4 showing THD versus Vy V rms This figure shows that the THD Noise remains very low until the output reaches 9 5 V rms This performance is similar to competitive products Rfg B mE mu 71 reEpBAck Rx 332 0 Vout O 1 A Figure 1 Recommended Output Short Circuit Protection 0 010 Ap 6000 2k 10kQ Vg 15V Vin 3V rms o Ay 1 2 T 0 001 0 0005 20 100 10k 20k 1k FREQUENCY Hz Figure 2 THD Noise vs Frequency vs 1 Ap x 6000 01 Ay 1 Vg 187 Vin 10 rms 3 2 T 0 010 80kHz FILTERS 2 2 0 001 10 0 0 0001 20 10 10k 20k 1k FREQUENCY Hz Figure 3 THD Noise vs Vin 210 V rms REV C 0 010 Vg 181 R 6000 0 001 5 00001 i OUTPUT SWING V rms Figure 4 Headroom THD Noise vs Output Amplitude V rms Rioan 600 Q Vsyp 18 output of the OP275 is designed
19. nd Rz in the kilohm range this pole can create excess phase shift and even oscillation A small capacitor in parallel and eliminates this problem By setting Rs Cs the effect of the feedback pole is completely removed Figure 15 shows some guidelines for maximizing the distortion performance of the OP275 in noninverting applications The best way to prevent unwanted distortion is to ensure that the parallel combination of the feedback and gain setting resistors Rg and Rg is less than 2 Keeping the values of these resistors small has the added benefits of reducing the thermal noise of the circuit REV C 9 0 275 dc offset errors If the parallel combination of Rg and Rg is larger than 2 then an additional resistor Rs should be used in series with the noninverting input The value of Rg is deter mined by the parallel combination of Rp and Rg to maintain the low distortion performance of the OP275 Driving Capacitive Loads The OP275 was designed to drive both resistive loads to 600 0 and capacitive loads of over 1000 pF and maintain stability While there is a degradation in bandwidth when driving capacitive loads the designer need not worry about device stability The graph in Figure 16 shows the 0 dB bandwidth of the OP275 with capaci tive loads from 10 pF to 1000 pF 10 9 8 BANDWIDTH MHz a 4 3 2 1 0 0 200 400 60
20. rately For the OP275 the noise is gained by approximately 1020 using the circuit shown in Figure 7 Any readings on the Audio Precision must then be divided by the gain In imple menting this test fixture good supply bypassing is essential Figure 7 Noise Test Fixture Input Overcurrent Protection The maximum input differential voltage that can be applied to the OP275 is determined by a pair of internal Zener diodes connected across its inputs They limit the maximum differential input voltage to 17 5 V This is to prevent emitter base junetion breakdown from occurring in theAnput stage of the OP275 when very large differential voltages are applied Howeversto preserve the 275 low input noise voltage internal resistances in series with the inputs were not used to limit the current in the clamp diodes In small signal applications this is not an issue however in applications where large differential voltages can be inadvert ently applied to the device large transient currents can flow through these diodes Although these diodes have been designed to carry a current of 5 mA external resistors as shown in Figure 8 should be used in the event that the OP275 s differential voltage were to exceed 7 5 V 14 0 2 Figure 8 Input Overcurrent Protection Output Voltage Phase Reversal Since the OP275 s input stage combines bipolar transistors for low noise and p channel JFETs for high speed performance the output volta
21. to maintain low harmonic distortion while driving 600 Q loads However driving 600 loads with very high output swings results in higher distortion if clipping occurs common example of this is in attempting to drive 10 V rms into any load with 15 V supplies Clipping will occur and distortion will be very high To attain low harmonic distortion with large output swings supply voltages may be increased Figure 5 shows the performance of the OP275 driving 600 Q loads with supply voltages varying from 18 V to 20 V Notice that with 18 V supplies the distortion is fairly high while with 20 V supplies it is a very low 0 000796 0 0001 0 001 6000 5 Vout 10V rms 1kHz 0 01 0 1 0 17 18 19 20 21 22 SUPPLY VOLTAGE V Figure 5 THD Noise vs Supply Voltage Noise The voltage noise density of the OP275 is below 7 nV Hz from 30 Hz This enables low noise designs to have good performance throughout the full audio range Figure 6 shows a typical 275 with a 1 f corner at 2 24 Hz CH 80 0 FS MKR 45 6nV Hz 10 0nV DIV BW 0 145 2 Figure 6 1 f Noise Corner Vs 15 V Ay 1000 0 275 Noise Testing For audio applications the noise density is usually the most important noise parameter For characterization the OP275 is tested using an Audio Precision System One The input signal to the Audio Precision must be amplified enough to measure it accu

ANALOG DEVICES OP275 handbook

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