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ANALOG DEVICES AD8054 handbook

1. 6 3 5V 7 2 4 E 0 1 1 10 100 500 100k 1M 10M 100M 500M 2 FREQUENCY MHz z FREQUENCY Hz z Figure 8 AD8051 AD8052 Gain vs Frequency vs Supply Figure 11 AD8054 Gain vs Frequency vs Supply Vs 5V RL 2kQ TO 2 5V C 5pF G Vour 0 2V p p T T kJ 2 z z Ei q 5 5 Vg 5V G 1 RL 2kQ Vout 0 2V p p TEMPERATURE AS SHOWN 0 1 1 10 100 500 1 10 100 500 5 FREQUENCY MHz FREQUENCY MHz Figure 9 AD8051 AD8052 Gain vs Frequency vs Temperature Figure 12 AD8054 Gain vs Frequency vs Temperature Rev H Page 10 of 24 AD8051 AD8052 AD8054 6 3 6 3 6 2 6 2 6 1 GS F 60 60 8 59 9 59 ul ul ss 58 2 2 z 57 57 z z Vs 5V 5 6 S 9 9 56 Rp z 2000 5 5 5 5 L Ri z 1500 s 5 4 Vour 0 2V p 5 4 Vout 0 2V p p 1 0 5 3 2 5 3 S
2. OUTLINE DIMENSIONS 8 75 0 3445 8 55 0 3366 n n 7 4 00 0 1575 6 20 0 2441 3 80 0 1496 5 80 0 2283 pu 0 50 0 0197 1 75 0 0689 0 25 0 0098 0 25 0 0098 1 35 0 0531 8 0 10 0 0039 y P r COPLANARITY alle SEATING L Fla 0 10 0 51 0 0201 PLANE 0 25 0 0098 1 27 0 0500 0 31 0 0122 0 17 0 0067 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 012 AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 53 14 Lead Standard Small Outline Package SOIC_N Narrow Body R 14 Dimensions shown in millimeters and inches 060606 A 2 90 BSC 10 gt he 0 50 SEATING e 0 60 0 30 PLANE 0 0 45 0 30 COMPLIANT TO JEDEC STANDARDS MO 178 AA Figure 54 5 Lead Small Outline Transistor Package SOT 23 RJ 5 Dimensions shown in millimeters Rev H Page 21 of 24 AD8051 AD8052 AD8054 0 85 1 10 MAX het a 0 80 045 7 ose o2 4 8 gt e 0 60 0 00 022 0 08 0 0 40 COPLANARITY SEATING 0 10 PLANE COMPLIANT TO JEDEC STANDARDS MO 187 AA Figure 55 8 Lead Mini Small Outline Package MSOP RM 8 Dimensions shown in millimeters 5 00 0 1968 4 00 0 1574 3 80 0 1497 6 20 0 2441 5 80 0 2284 0 50 0 0196 o 51 0 0201 B M
3. 40 C to 125 C 14 Lead TSSOP 13 Tape and Reel RU 14 AD8054ARUZ REEL7 40 C to 125 C 14 Lead TSSOP 7 Tape and Reel RU 14 1 Z RoHS Compliant Part denotes lead free product may be top or bottom marked Rev H Page 23 of 24 AD8051 AD8052 AD8054 NOTES ww BOM C com AL 2007 Analog Devices Inc All rights reserved Trademarks and AN ALOG registered trademarks are the property of their respective owners D01062 0 12 07 H DEVICES www analog com Rev H Page 24 of 24
4. 0 1 1 0 100 1 10 100 FREQUENCY MHz FREQUENCY MHz E Figure 13 AD8051 AD8052 0 1 dB Gain Flatness vs Frequency G lt 2 Figure 16 AD8054 0 1 dB Gain Flatness vs Frequency G lt 2 9 9 8 8 Vs 5V Vour 2V p p 7 7 6 6 mo a5 Z Z z 4 z 4 Vs 5V S 3 3 Vout 4V p p 2 ah 1 1 RF 0 o Vout AS SHO sl zi 0 1 1 10 100 500 0 1 1 10 100 500 z FREGUENCY MHz s FREQUENCY MHz s Figure 14 AD8051 AD8052 Large Signal Frequency Response G 2 Figure 17 AD8054 Large Signal Frequency Response G 2 80 80 70 Vs 75V 70 Vs 5V R 2kQ Ru 2kQ 60 60 C 5pF a 50 3 m 50 e E s z o z o 40 40 a lt GAIN a i GAIN 3 z a 0 o a 180 E 30 9 S 30 2 20 50 PHASE 45 S 20 1355 a PHASE MARGIN ui di PHASE 45 PHASE ul a 10 90 2 a 40 MARGIN 490 2 o I o J T n n 0 135 0 45 10 180 10 0 20 20 2 0 01 0 1 1 10 100 500 ki 30k 100k 1M 10M 100M 500M FREGUENCY MHz 7 FREQUENCY Hz S Figure 15 AD8051 AD8052 Open Loop Gain and Phase vs Frequency Figure 18 AD8054 Open Loop Gain and Phase Margin vs Frequency Rev H Page 11 of 24 AD8051 AD8052 AD8054 1000 Vour 2V p p Vs 3V Gz 1 Vs 5V E Rf 2kO RL 1000 5 Vs 5V G 92 z Rp 20 RL 1 4 o z E T x K 1 100 G u a a o 2
5. 0 5 V During this overdrive condition the output stays at the rail The rail to rail output range of the AD8051 AD8052 AD8054 is provided by a complementary common emitter output stage High output drive capability is provided by injecting all output stage predriver currents directly into the bases of the output devices Q8 and Q36 Biasing of Q8 and Q36 is accomplished by I8 and I5 along with a common mode feedback loop not shown This circuit topology allows the AD8051 AD8052 to drive 45 mA of output current and allows the AD8054 to drive 30 mA of output current with the outputs within 0 5 V ofthe supply rails 01062 045 Figure 40 AD8051 AD8052 Simplified Schematic Rev H Page 16 of 24 AD8051 AD8052 AD8054 APPLICATION INFORMATION OVERDRIVE RECOVERY Overdrive of an amplifier occurs when the output and or input range is exceeded The amplifier must recover from this over drive condition As shown in Figure 41 the AD8051 AD8052 AD8054 recover within 60 ns from negative overdrive and within 45 ns from positive overdrive aM Penine TT OUTPUT 2V DIV 1 01062 042 Figure 43 AD8051 AD8052 200 mV Step Response C 50 pF 10000 Ese EZ s 30 EI OVERSHOOT ER aes En JE sb a 2 Figure 41 Overdrive Recovery 9 Rs 00 o DRIVING CAPACITIVE LOADS u 400 E S
6. C W patented or proprietary protection circuitry damage 14 Lead SOIC 90 C W dy A may occur on devices subjected to high energy ESD 14 Lead TSSOP 120 C W Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev H Page 9 of 24 AD8051 AD8052 AD8054 TYPICAL PERFORMANCE CHARACTERISTICS 5 Vs 5V Get 4L Vs s 2 G 2 GAIN AS SHOWN pcd Re 0 i Rp lt 2kQ 3 Re AS SHOWN F 2L R50 ta a aj 5 0 5 Vour 0 2V p p z G 5 z 1 a 1 Rp 2kQ lt E G 10 lt pu Sa a Q 2 Re 0 1 S Rf 2kQ v N d zc G 10 z Rp 2kQ x 3 F 6 4L Vs 5V s z GAIN AS SHOWN Z 4 5 L Rp AS SHOWN RL 2kQ 5 6 Vout 0 2V p p e 6 Rf 2kO 7 5 7 2 0 1 1 10 100 500 100k 1M 10M 100M 500M FREQUENCY MHz Z FREQUENCY Hz Figure 7 AD8051 AD8052 Normalized Gain vs Frequency Vs 5 V Figure 10 AD8054 Normalized Gain vs Frequency Vs 5 V 3 6 2 Vs AS SHOWN G H G 1 PITI 5 R 22kO 3V LL 2ka TSI Ci 5pF z 4 Vout 0 2V p p Vour 0 2V p p sv o H 3 5V a Vs 5V m 3 kJ z 2 z 1 lt lt 3 o 4 A 15V 5 2 3V
7. R 21500 445to 46to 40to 4 5to V 443 44 6 13 8 4 5 Output Current Vout 4 5 V to 4 5 V 45 30 mA Tmn Tmax 45 30 mA Short Circuit Current Sourcing 100 60 mA Sinking 160 100 mA Capacitive Load Drive G 41 AD8051 AD8052 50 pF G 2 AD8054 40 pF Rev H Page 7 of 24 AD8051 AD8052 AD8054 AD8051A AD8052A AD8054A Parameter Conditions Min Typ Max Min Typ Max Unit POWER SUPPLY Operating Range 3 12 3 12 V Ouiescent Current Amplifier 4 8 5 5 2 875 3 4 mA Power Supply Rejection Ratio AVs 1 68 80 68 80 dB OPERATING TEMPERATURE RANGE RJ 5 40 485 C RM 8 R 8 RU 14 R 14 40 4125 40 4125 C ww BDI C com ALI Rev H Page 8 of 24 AD8051 AD8052 AD8054 ABSOLUTE MAXIMUM RATINGS Table 4 MAXIMUM POWER DISSIPATION Parameter Ratings The maximum power that can be safely dissipated by the Supply Voltage 12 6V AD8051 AD8052 AD8054 is limited by the associated rise in Internal Power Dissipation SOIC Packages SOT 23 Package Observe power derating curves Observe power derating curves junction temperature The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic approximately 150 C Temporarily exceeding this limit can cause a shift in parametric performance due to a change in the stresses exerted on the die IS package fone d by the package Exceeding a
8. Z 3 100 S lt o 55 p 40 o LI g 1 000 2 30 gt 0 310 2 5 E 20 O 0 100 5 o 0 031 10 0 010 N 0 s 0 1 1 10 100 500 0 5 1 0 1 5 20 FREQUENCY MHz S INPUT STEP V p p Z Figure 27 Closed Loop Output Resistance vs Freguency Figure 30 Settling Time vs Input Step Rev H Page 13 of 24 AD8051 AD8052 AD8054 OUTPUT SATURATION VOLTAGE V 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Vs 5V Von 85 C Von 25 C Vou 40 C VoL 85 C VoL 25 C h VoL 40 C 01062 031 LOAD CURRENT mA Figure 31 AD8051 AD8052 Output Saturation Voltage vs Load Current OPEN LOOP GAIN dB 100 90 80 70 0 05 10 15 20 25 30 35 40 45 50 OUTPUT VOLTAGE V 01062 032 Figure 32 Open Loop Gain vs Output Voltage C Rev H Page 14 of 24 1 000 Vs lt 5V amp 0 875 5V Von 125 C lt 0 750 d 5V Vou 25 C gt 0 625 z o 5V Von 40 C S 0 500 B 0 375 E k a 0 250 5 Vor 125 C O I 0 125 VoL 25 C Vor 40 C 0 3 6 9 12 15 18 21 24 27 30 LOAD CURRENT mA Figure 33 AD8054 Output Saturation Voltage vs Load Current com AL 01062 033 AD8051 AD8052 AD8054 Ans LL IL er ey 01062 034 01062 037
9. conversion it is not desirable to have the sync pulses on the video signal These pulses reduce the dynamic range of the video signal and do not provide any useful information for such a function A sync stripper removes the synchronizing pulses from a video signal while passing all the useful video information Figure 51 shows a practical single supply circuit that uses only a single AD8051 It is capable of directly driving a reverse terminated video line VIDEO WITH SYNC VIDEO WITHOUT SYNC VBLANK 0 4N GROUND GROUND 3V OR 5V OR 2 Vgi Auk 2 Figure 51 Sync Stripper The video signal plus sync is applied to the noninverting input with the proper termination The amplifier gain is set to 2 via the two 1 kO resistors in the feedback circuit A bias voltage must be applied to R1 so that the input signal has the sync pulses stripped at the proper level The blanking level of the input video pulse is the desired place to remove the sync information This level is multiplied by 2 by the amplifier This level must be at ground at the output for the sync stripping action to take place Since the gain of the amplifier from the input of R1 to the output is 1 a voltage equal to 2 x Vatanx must be applied to make the blanking level come out at ground SINGLE SUPPLY COMPOSITE VIDEO LINE DRIVER Many composite video signals have their blanking level at ground and have video information that is both positive and negat
10. dE NE URS SEATING A 0 40 0 0157 PLANE 0 17 0 0067 COMPLIANT TO JEDEC STANDARDS MS 012 AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 56 8 Lead Standard Small Outline Package SOIC N Narrow Body R 8 Dimensions shown in millimeters and inches 012407 A 0 20 0 09 En 075 T 8 ke 0 60 0 0 45 COPLANARITY 0 10 COMPLIANT TO JEDEC STANDARDS MO 153 AB 1 Figure 57 14 Lead Thin Shrink Small Outline Package TSSOP RU 14 Dimensions shown in millimeters Rev H Page 22 of 24 AD8051 AD8052 AD8054 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8051AR 40 C to 125 C 8 Lead SOIC_N R 8 AD8051AR REEL 40 C to 125 C 8 Lead SOIC_N 13 Tape and Reel R 8 AD8051AR REEL7 40 C to 125 C 8 Lead SOIC_N 7 Tape and Reel R 8 AD8051ARZ 40 C to 85 C 8 Lead SOIC_N R 8 AD8051ARZ REEL 40 C to 85 C 8 Lead SOIC_N 13 Tape and Reel R 8 AD8051 ARZ REEL7 40 C to 85 C 8 Lead SOIC_N 7 Tape and Reel R 8 AD8051ART R2 40 C to 85 C 5 Lead SOT 23 7 Tape and Reel RJ 5 H2A AD8051ART REEL 40 C to 85 C 5 Lead SOT 23 13 Tape and Reel RJ 5 H2A AD8051ART REEL7 40 C to 85 C 5 Lead SOT 23 7 Tape and Reel RJ 5 H2A AD8051ARTZ R2 40 C to 85 C 5 Lead SOT 23 7 Tape and Reel
11. extended temperature range of 40 C to 125 C One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2007 Analog Devices Inc All rights reserved AD8051 AD8052 AD8054 TABLE OF CONTENTS FOALS 1 Applications a a E PER je BRI 1 Pin Connections Top Views eerte 1 General Description asian 1 Revision History eese 2 Specifications cocotte te 3 Absolute Maximum Ratings eerte 9 Thermal Resistance isis sasssa 9 Maximum Power Dissipation eese 9 ESD Cauti isese n E R 9 Typical Performance Characteristics se 10 Xheory of Operation nere ette ciet 16 REVISION HISTORY 12 07 Rev G to Rev H Changes to Applications oc enem 1 Updated Outline Dimensions 21 Changes to Ordering Guide sees 23 5 06 Rev F to Rev G Changes to Figure IR arsodi like rne 12 Changes to the Ordering Gude sees 22 9 04 Rev E to Rev F Changes to Ordering Guide 7 Changes to T 5e ERES 15 3 04 Rev D to Rev E Changes to General Description sss 2 Changes to Specifications Changes to Ordering Guide Circuit Description ertet ARRE 16 Application Informations essere 17 Overdrive Recovery cce peat t Ebo eed 17 Driving Capacitive Loads sse 17 Layout Considerations ertet 18 Active FILES tates e
12. swing at the output for an op amp to pass a composite video signal of arbitrarily varying duty cycle without distortion Some circuits use a sync tip clamp to hold the sync tips at a relatively constant level to lower the amount of dynamic signal swing required However these circuits can have artifacts such as sync tip compression unless they are driven by a source with a very low output impedance The AD8031 AD8092 A D8054 e adequate signal swing wh n rungi ingle 5 V 1 V p p r signal that has the nine level at ground The input network level shifts the video signal by means of ac coupling The noninverting input of the op amp is biased to half of the supply voltage The feedback circuit provides unity gain for the dc biasing of the input and provides a gain of 2 for any signals that are in the video bandwidth The output is ac coupled and terminated to drive the line The capacitor values were selected for providing minimum tilt or field time distortion of the video signal These values would be required for video that is considered to be studio or broadcast quality However if a lower consumer grade of video sometimes referred to as consumer video is all that is desired the values and the cost of the capacitors can be reduced by as much as a factor of five with minimum visible degradation in the picture 01062 052 Figure 52 Single Supply Composite Video Line Driver Rev H Page 20 of 24 AD8051 AD8052 AD8054
13. 100 LILO Et T CT 7TH 75 08 110 8TH 88 12 120 9TH 77 87 1 2 3 4 5 6 7 8 9 10 FREQUENCY MHz Figure 48 FFT Plot for AD8051 Driving the AD9201 at 1 MHz 01062 049 10 FUND PART o 0 FFTSIZE 8192 p FCLK 20 0MHz FUND 9 5MHz 20 VIN 0 44dB 30 THD 57 08 m SNR 54 65 S 40 SINAD 52 69 g 50 ENOB 8 46 2ND E go b SFDR 60 18 a 2ND 60 18 T z pra iB pm 3RD 60 23 ti z 4TH 82 01 MTT 5TH 78 83 90 STH 8128 100 TID POT tt T HI UH d 7TH T1 28 110 8TH 84 54 9TH 92 78 120 1 2 3 4 5 6 7 8 9 10 FREQUENCY MHz Figure 49 FFT Plot for AD8051 Driving the AD9201 at 9 5 MHz 01062 050 Vpp DATA OUT 01062 048 Figure 50 The AD8051 Driving an AD9201 a 10 Bit 20 MSPS Analog to Digital Converter Rev H Page 19 of 24 AD8051 AD8052 AD8054 SYNC STRIPPER Synchronizing pulses are sometimes carried on video signals so as not to require a separate channel to carry the synchronizing information However for some functions such as analog to digital
14. 8 a AST 2ND 3RD 4TH 5TH 6TH 7TH gTH gTH 10TH 41TH P MODULATING RAMP LEVEL IRE MODULATING RAMP LEVEL IRE Z Figure 21 AD8051 AD8052 Differential Gain and Phase Errors Figure 24 AD8054 Differential Gain and Phase Errors Rev H Page 12 of 24 AD8051 AD8052 AD8054 10 Vs 5V 20 Rp z 1kQ RL lt AS SHOWN 30 vour 2V p p 40 a m 2 2 RL 1000 50 x x E 60 2 3 9 9 70 K RL 1kO o L o 80 90 lili p 100 2 110 g 0 2 0 1 1 10 100 500 FREQUENCY MHz FREQUENCY MHz Z Figure 25 AD8052 Crosstalk Output to Output vs Freguency Figure 28 AD8054 Crosstalk Output to Output vs Freguency 0 20 Vs 5V Vs 5V 10 10 S 20 0 30 10 PSRR g 40 m 20 2 m 50 c 30 4 a z 0 O 60 a 40 PSRR 70 5 80 6 90 70 100 g 80 amp 0 00 0 1 1 10 100 500 5 0 01 0 1 1 10 100 500 lt FREQUENCY MHz FREQUENCY MHz Figure 26 CMRR vs Frequency Figure 29 PSRR vs Frequency 100 000 70 Vs lt 5V 31 000 G 7 11 60 10 000 B w z 50
15. ANALOG DEVICES Low Cost High Speed Rail to Rail Amplifiers AD8051 AD8052 AD8054 FEATURES High speed and fast settling on 5 V 110 MHz 3 dB bandwidth G 1 AD8051 AD8052 150 MHz 3 dB bandwidth G 1 AD8054 145 V ps slew rate 50 ns settling time to 0 1 Single supply operation Output swings to within 25 mV of either rail Input voltage range 0 2 V to 4 V Vs lt 5V Video specifications G 2 0 1 dB gain flatness 20 MHz Ri 1500 Differential gain phase 0 03 0 03 Low distortion 80 dBc total harmonic 1 MHz Ri 100 Q Outstanding load drive capability Drives 45 mA 0 5 V from supply rails AD8051 AD8052 Drives 50 pF capacitive load G 1 AD8051 AD8052 Low power 2 75 mA amplifier AD8054 Low power 4 4 mA amplifier AD8051 AD8052 APPLICATIONS Active filte Analog to digit v Clock buffer Consumer video Professional cameras CCD imaging systems CD DVD ROMs GENERAL DESCRIPTION The AD8051 single AD8052 dual and AD8054 quad are low cost high speed voltage feedback amplifiers The amplifiers operate on 3 V 5 V or 5 V supplies at low supply current They have true single supply capability with an input voltage range extending 200 mV below the negative rail and within 1 V of the positive rail Despite their low cost the AD8051 AD8052 AD8054 provide excellent overall performance and versatility The output voltage swings to within 25 mV of each rail providing maximum ou
16. Figure 34 100 mV Step Response G 1 01062 038 VOLTS 8 id a o 8 5 01062 039 Figure 36 Large Signal Step Response Vs 5 V G 2 Figure 39 Large Signal Step Response Vs 5 V G 1 Rev H Page 15 of 24 AD8051 AD8052 AD8054 THEORY OF OPERATION CIRCUIT DESCRIPTION The AD8051 AD8052 AD8054 are fabricated on the Analog Devices Inc proprietary eXtra Fast Complementary Bipolar XFCB process which enables the construction of PNP and NPN transistors with similar fTs in the 2 GHz to 4 GHz region The process is dielectrically isolated to eliminate the parasitic and latch up problems caused by junction isolation These features allow the construction of high frequency low distortion amplifiers with low supply currents This design uses a differential output input stage to maximize bandwidth and headroom see Figure 40 The smaller signal swings required on the first stage outputs nodes SIP SIN reduce the effect of nonlinear currents due to junction capacitances and improve the distortion per formance This design achieves harmonic distortion of 80 dBc 1 MHz into 100 O with Vour 2 V p p gain 1 ona single 5 V supply The inputs of the device can handle voltages from 0 2 V below the negative rail to within 1 V ofthe positive rail Exceeding these values do not cause phase reversal however the input ESD devices begin to conduct if the input voltages exceed the rails by greater than
17. RJ 5 H06 AD8051ARTZ REEL 40 C to 85 C 5 Lead SOT 23 13 Tape and Reel RJ 5 H06 AD8051ARTZ REEL7 40 C to 85 C 5 Lead SOT 23 7 Tape and Reel RJ 5 H06 AD8052AR 40 C to 125 C 8 Lead SOIC N R 8 AD8052AR REEL 40 C to 125 C 8 Lead SOIC N 13 Tape and Reel R 8 AD8052AR REEL7 40 C to 125 C 8 Lead SOIC N 7 Tape and Reel R 8 AD8052ARZ 40 C to 125 C 8 Lead SOIC N R 8 AD8052ARZ REEL 40 C to 125 C 8 Lead SOIC_N 13 Tape and Reel R 8 AD8052ARZ REEL7 40 C to 125 C 8 Lead SOIC_N 7 Tape and Reel R 8 AD8052ARM 40 C to 125 C 8 Lead MSOP RM 8 H4A AD8052ARM REEL 40 C to 125 C 8 Lead MSOP 13 Tape and Reel RM 8 H4A AD8052ARM REEL7 40 C to 125 C 8 Lead MSOP 7 Tape and Reel RM 8 H4A AD8052ARMZ 40 C to 125 C 8 Lead MSOP RM 8 H4A AD8052ARMZ REEL7 40 C to gsL ead Tape and Reel RM HAAR AD8054AR 4 to 1 Lead SOIC_N R 1 AD8054AR C to 1 LeadiSOIC N ne a R AD8054AR REEL7 40 C to 4 Lead _N 7 Tape and Reel 14 AD8054ARZ 40 C to 125 C 14 Lead SOIC N R 14 AD8054ARZ REEL 40 C to 125 C 14 Lead SOIC_N 13 Tape and Reel R 14 AD8054ARZ REEL7 40 C to 125 C 14 Lead SOIC N 7 Tape and Reel R 14 AD8054ARU 40 C to 125 C 14 Lead TSSOP RU 14 AD8054ARU REEL 40 C to 125 C 14 Lead TSSOP 13 Tape and Reel RU 14 AD8054ARU REEL7 40 C to 125 C 14 Lead TSSOP 7 Tape and Reel RU 14 AD8054ARUZ 40 C to 125 C 14 Lead TSSOP RU 14 AD8054ARUZ REEL
18. Re Re m n jo S NZ Vour P e Y adding a low value resistor in series with the load Figure 44 1 2 3 4 5 6 and Figure 45 show the effect of a series resistor on the capaci Act VN E tive drive for varying voltage gains As the closed loop gain is Figure 44 AD8051 AD8052 Capacitive Load Drive vs Closed Loop Gain increased the larger phase margin allows for larger capacitive loads with less peaking Adding a series resistor with lower A000 closed loop gains accomplishes the same effect For large Vs 5V L B s 30 capacitive loads the frequency response of the amplifier is OVERGHODT dominated by the roll off of the series resistor and the load s T Rg 100 capacitance amp 8 3 Rs 00 ad 6 wi 100 4 5 lt Rg Re 2 R Vin m 0 100mV ST lt STEP 500 z 2 z v m 10 z Vs 5V 1 2 3 4 5 6 S emo Ac VIV R 2kQ ne ZEN 8 c 50pF Figure 45 AD8054 Capacitive Load Drive vs Closed Loop Gain 40 Vour 200mV p p e 01062 041 10 FREQUENCY MHz Figure 42 AD8051 AD8052 Closed Loop Frequency Response Ci 50 pF Rev H Page 17 of 24 AD8051 AD8052 AD8054 LAYOUT CONSIDERATIONS The specified high speed performance of the AD8051 AD8052 AD8054 requires careful attention to board layout and component selection Proper RF design techniques and low parasitic component selection are necessary The PCB should have a ground plane covering
19. UA Input Offset Current 0 15 0 8 0 2 12 HA Open Loop Gain Ri 2 kO 80 96 80 96 dB Tmn Tmax 94 94 dB R 21500 74 82 72 80 dB Tmn Tmax 76 76 dB INPUT CHARACTERISTICS Input Resistance 290 300 ko Input Capacitance 14 1 5 pF Input Common Mode Voltage Range 0 2 to 0 2 to V 2 2 Common Mode Rejection Ratio Vcn 2 0Vto 1 5V 72 88 70 86 dB Rev H Page 5 of 24 AD8051 AD8052 AD8054 AD8051A AD8052A AD8054A Parameter Conditions Min Typ Max Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Swing RL 10 kQ to 1 5 V 0 01 to 0 025 to V 2 99 2 98 RL 2 kOto 1 5V 0 0 75to 0 02 to 0 1to 0 35to V 2 9 2 98 2 9 2 965 Ru 1500 to 1 5 V 0 2 to 0 125 to 0 35to 0 15 to V 2 75 2 875 2 55 2 75 Output Current Vour 0 5 V to 2 5 V 45 25 mA Tmn Tmax 45 25 mA Short Circuit Current Sourcing 60 30 mA Sinking 90 50 mA Capacitive Load Drive G 1 AD8051 AD8052 45 pF G 2 AD8054 35 pF POWER SUPPLY Operating Range 3 12 3 12 V Ouiescent Current Amplifier 4 2 4 8 2 625 3 125 mA Power Supply Rejection Ratio AVs lt 0 5 V 68 80 68 80 dB OPERATING TEMPERATURE RANGE RJ 5 40 85 C RM 8 R 8 RU 14 R 14 40 125 40 4125 C 1 Refer to Figure 19 ww BDII C co Rev H Page 6 of 24 AD8051 AD8052 AD8054 Ta 25 C Vs 5 V Rr 2 kQ to ground unless otherwise noted Table 3 AD8051A AD8052A AD8054A Parameter Conditions Min Typ Max Min T
20. all unused portions of the component side of the board to provide a low impedance path The ground plane should be removed from the area near the input pins to reduce parasitic capacitance Chip capacitors should be used for supply bypassing One end should be connected to the ground plane and the other within 3 mm of each power pin An additional large 4 7 uF to 10 uF tantalum electrolytic capacitor should be connected in parallel but not necessarily so close to supply current for fast large signal changes at the output The feedback resistor should be located close to the inverting input pin to keep the parasitic capacitance at this node to a minimum Parasitic capacitance of less than 1 pF at the inverting input can significantly affect high speed performance Stripline design techniques should be used for long signal traces greater than about 25 mm These should be designed with a characteristic impedance of 50 Q or 75 O and be properly terminated at each end ACTIVE FILT Active filters at h amps to work effectively Excessive phase shift produced b lower frequency op amps can significantly affect active filter performance Figure 46 shows an example of a 2 MHz biquad bandwidth filter that uses three op amps of an AD8054 Such circuits are sometimes used in medical ultrasound systems to lower the noise bandwidth of the analog signal before analog to digital conversion Note that the unused amplifier s inputs should
21. be tied to ground BAND PASS FILTER OUTPUT Figure 46 2 MHz Biquad Band Pass Filter Using AD8054 The frequency response of the circuit is shown in Figure 47 0 GAIN dB 30 A 10k 100k 1M 10M 100M FREQUENCY Hz 01062 047 Figure 47 Frequency Response of 2 MHz Band Pass Biquad Filter Rev H Page 18 of 24 01062 046 AD8051 AD8052 AD8054 ANALOG TO DIGITAL AND DIGITAL TO ANALOG APPLICATIONS Figure 50 is a schematic showing the AD8051 used as a driver for an AD9201 a 10 bit 20 MSPS dual analog to digital converter This converter is designed to convert I and Q signals in communications systems In this application only the I channel is being driven The I channel is enabled by applying a logic high to SELECT Pin 13 The AD8051 is running from a dual supply and is configured for a gain of 2 The input signal is terminated in 50 Q and the output is 2 V p p which is the maximum input range of the AD9201 The 22 Q series resistor limits the maximum current that flows and helps to lower the distortion of the ADC The AD9201 has differential inputs for each channel These are designated the A and B inputs The B inputs of each channel are connected to VREF Pin 22 which supplies a positive reference of 2 5 V Each of the B inputs has a small low pass filter that also helps to reduce distortion The output of the op amp
22. c Distortion fc 5 MHz Vovr 2V p p 67 68 dB G 42 Input Voltage Noise f 10 kHz 16 16 nV 4Hz Input Current Noise f 10 kHz 850 850 fA VHz Differential Gain Error NTSC G 42 R 21500to2 5V 0 09 96 0 03 96 Differential Phase Error NTSC 0 19 Degrees Degrees Crosstalk 60 dB DC PERFORMANCE Input Offset Voltage 17 10 17 12 mV Tmn Tmax 25 30 mV Offset Drift 10 15 uV C Input Bias Current 14 2 5 2 4 5 UA Tmn Tmax 3 25 4 5 UA Input Offset Current 0 1 0 75 0 2 1 2 HA Open Loop Gain Ri 2 kO to 2 5 V 86 98 82 98 dB Tmn Tmax 96 96 dB RL 150 0 to 2 5 V 76 82 74 82 dB Tmn Tmax 78 78 dB INPUT CHARACTERISTICS Input Resistance 290 300 ko Input Capacitance 14 1 5 pF Input Common Mode Voltage Range 0 2 to 0 2 to V 4 4 Common Mode Rejection Ratio Vem OV to 3 5 V 72 88 70 86 dB Rev H Page 3 of 24 AD8051 AD8052 AD8054 AD8051A AD8052A AD8054A Parameter Conditions Min Typ Max Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Swing Ri 10 kO to 2 5 V 0 015 to 0 03 to V 4 985 4 975 Ri 2 kO to 2 5 V 0 1to 0 025to 0 125to 0 05 to V 4 9 4 975 4 875 4 95 Ri lt 1500 to 2 5 V 0 3to 0 2to 0 55 to 0 25 to V 4625 48 44 4 65 Output Current Vovr 0 5 V to 4 5 V 45 30 mA Tmn Tmax 45 30 mA Short Circuit Current Sourcing 80 45 mA Sinking 130 85 mA Capacitive Load Drive G 41 AD8051 AD8052 50 pF G 2 AD8054 40 pF POWER SUPPLY Operating Range 3 12 3 12 V Ouiescent Cu
23. is ac coupled into INA I Pin 16 via two parallel capacitors to provide good high frequency and low frequency coupling The 1 kO resistor references the signal to VREF that is applied to INB I Thus INA I swings both positive and negative with respect to the bias voltage applied to INB I With the sampli digital output frequencies were of the Nyquist frequency These signals were well filtered to minimize any harmonics Figure 48 shows the FFT response of the ADC for the case of a 1 MHz analog input The SFDR is 71 66 dB and the analog to digital is producing 8 8 ENOB effective number of bits When the analog frequency was raised to 9 5 MHz the SFDR was reduced to 60 18 dB and the ADC operated with 8 46 ENOBs as shown in Figure 49 The inclusion of the AD8051 in the circuit did not worsen the distortion performance of the AD9201 10 EUND PART 0 0 T FFTSIZE 8192 40 FCLK 20 0MHz FUND 998 5kHz 20 VIN 0 51dB 30 THD 68 13 T e SNR 54 97 ui SINAD 54 76 Q 50 ENOB 8 80 E 60 SFDR 71 66 E 7 ma RE 2ND 7453 ND 3RD ATH ty 1 eTH 9TH i 3RD 76 06 80 em Y 4TH 76 35 l j na 5TH 79 05 20 MM 6TH 80 36
24. ive Such signals require dual supply amplifiers to pass them However by ac level shifting a single supply amplifier can be used to pass these signals The following complications can arise from such techniques Signals of bounded peak to peak amplitude that vary in duty cycle require larger dynamic swing capacity than their bounded peak to peak amplitude after they are ac coupled As a worst case the dynamic signal swing will approach twice the peak to peak value The two conditions that define the maximum dynamic swing requirements are a signal that is mostly low but goes high with a duty cycle that is a small fraction ofa percent and the other extreme defined by the opposite condition The worst case of composite video is not quite this demanding One bounding condition is a signal that is mostly black for an entire frame but has a white full amplitude minimum width spike at least once in a frame The other extreme is for a full white video signal The blanking intervals and sync tips of such a signal have negative going excursions in compliance with the composite video specifications The combination of horizontal and vertical blanking intervals limit such a signal to being at the highest white level for a maximum of about 7596 of the time As a result of the duty cycles between the two extremes previously presented a 1 V p p composite video signal that is multiplied by a gain of 2 requires about 3 2 V p p of dynamic voltage
25. junction temperature of 175 C for TSSOP Package Observe power an extended period can result in device failure derating curves While the AD8051 AD8052 AD8054 are internally short Input Voltage Common Mode Vs circuit protected this cannot be sufficient to guarantee that the Differential Input Voltage 2 5V maximum junction temperature 150 C is not exceeded under Output Short Circuit Duration Observe power derating curves 65 C to 150 C all conditions To ensure proper operation it is necessary to observe the maximum power derating curves Storage Temperature Range R 2 5 Operating Temperature Range A Grade 40 C to 125 C Lead Temperature Soldering 10 sec 300 C s 20 1 See Table 5 S Stresses above those listed under Absolute Maximum Ratings 1 5 may cause permanent damage to the device This is a stress a LI 10 Cy device reliability THERMAL RESISTANCE 255 35 15 5 15 35 55 75 95 115 AMBIENT TEMPERATURE C 01062 006 Specification is for device in free air 8 Lo Figure 6 Maximum Power Dissipation vs Table 5 Thermal Resistance Temperature for AD8051 AD8052 AD8054 Package Type Osa Unit ESD CAUTION 8 Lead SOIC 125 C W ESD electrostatic discharge sensitive device 5 Lead SOT 23 180 C W Charged devices and circuit boards can discharge A without detection Although this product features 8 Lead MSOP 150
26. rrent Amplifier 4 4 5 2 75 3 275 mA Power Supply Rejection Ratio AVs 1V 70 80 68 80 dB OPERATING TEMPERATURE RANGE RJ 5 40 485 C RM 8 R 8 RU 14 R 14 40 4125 40 125 C 1 Refer to Figure 19 ww BDII C co Rev H Page 4 of 24 AD8051 AD8052 AD8054 Ta 25 C Vs 3 V Ri 2 kO to 1 5 V unless otherwise noted Table 2 AD8051A AD8052A AD8054A Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G 41 Vout 0 2 V p p 70 110 80 135 MHz G 1 2 Vout 50 65 MHz 0 2 V p p Bandwidth for 0 1 dB Flatness G 2 Vout 0 2 V p p R lt 1500 to2 5V Rr 402 0 AD8051A 17 MHz AD8052A Rr 200 Q AD8054A 10 MHz Slew Rate G lt 1 Vour lt 2 V step 90 135 110 150 V us Full Power Response G 1 Vout 1 V p p 65 85 MHz Settling Time to 0 1 G 1 Vout 2 V step 55 55 ns NOISE DISTORTION PERFORMANCE Total Harmonic Distortion fc 5 MHz Vour 2 V p p 47 48 dB Gz 1R z1000to1 5V Input Voltage Noise f 10 kHz 16 16 nV 4Hz Input Current Noise f 10 kHz 600 600 fA VHz Differential Gain Error NTSC G lt 2 Vcu lt 1 V RL 1500to 1 5 V 0 11 0 13 Ru lt 1kOto 1 5V 0 09 0 09 Differential Phase Error NTSC Degrees WW GO zz Crosstalk dB DC PERFORMANCE Input Offset Voltage 1 6 10 1 6 12 mV Tmn Tmax 25 30 mV Offset Drift 10 15 uV C Input Bias Current 1 3 2 6 2 4 5 HA Tmn Tmax 3 25 4 5
27. tput dynamic range with excellent overdrive recovery Rev H Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners PIN CONNECTIONS TOP VIEWS Vs Vour 01062 002 01062 001 NC NO CONNECT Figure 1 SOIC 8 R 01062 003 01062 004 Figure 3 SOIC R 8 and MSOP RM 8 Figure 4 SOIC R 14 and TSSOP RU 14 m o A a lt h 1 2k e o N x THD s 0 5 V w o po a M o A a o o a PEAK TO PEAK OUTPUT VO o 1 10 50 FREQUENCY MHz 01062 005 Figure 5 Low Distortion Rail to Rail Output Swing The AD8051 AD8052 AD8054 are well suited for video electronics cameras video switchers or any high speed portable equipment Low distortion and fast settling make them ideal for active filter applications The AD8051 AD8052 in the 8 lead SOIC the AD8052 in the MSOP the AD8054 in the 14 lead SOIC and the 14 lead TSSOP packages are available in the
28. tte teme 18 Analog to Digital and Digital to Analog Applications 19 Syne Stripper ze issi S dS esee ERE a like 20 Single Supply Composite Video Line Driver 20 Outline Dimensions dus 21 Ordering Guides oett ER 23 2 03 Rev C to Rev D Changes to General Description essen 1 Changes to Specifications Changes to Absolute Maximum Ratings esee 6 3 Rev B to Rev C Changesffo Ge gesto P Changes to Specifications Changes to Absolute Maximum Ratings ee 9 Changes to Figure 2 no eiie Pe RP eti keep veti 9 Changes to Ordering Guide eee 9 Updated Outline Dimensions eere 20 Rev H Page 2 of 24 AD8051 AD8052 AD8054 SPECIFICATIONS Ta 25 C Vs 5 V Ri 2 kO to 2 5 V unless otherwise noted Table 1 AD8051A AD8052A AD8054A Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G 1 Vout 0 2 V p p 70 110 80 150 MHz G 1 2 Vout 0 2 V p p 50 60 MHz Bandwidth for 0 1 dB Flatness G 2 Vour 0 2 V p p RL 1500 to 2 5 V Rr 806 0 AD8051A 20 MHz AD8052A Rr 200 Q AD8054A 12 MHz Slew Rate G lt 1 Vovr 2 V step 100 145 140 170 V us Full Power Response G 1 Vout 2 V p p 35 45 MHz Settling Time to 0 1 G 1 Vout 2 V step 50 40 MHz NOISE DISTORTION PERFORMANCE Total Harmoni
29. yp Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G 1 Vout 0 2 V p p 70 110 85 160 MHz G 1 2 Vout 0 2 V p p 50 65 MHz Bandwidth for 0 1 dB Flatness G 2 Vout 0 2 V p p Ri 1500 Re 1 1 kO AD8051A 20 MHz AD8052A Rr 200 Q AD8054A 15 MHz Slew Rate G lt 1 Vour 2V step 105 170 150 190 V us Full Power Response G 1 Vout 2 V p p 40 50 MHz Settling Time to 0 1 G lt T Vout 2 V step 50 40 MHz NOISE DISTORTION PERFORMANCE Total Harmonic Distortion fc 5 MHz Vout 2 V p p 71 72 dB G 2 Input Voltage Noise f 10 kHz 16 16 nV VHz Input Current Noise f 10 kHz 900 900 fA Hz Differential Gain Error NTSC G 42 R 21500 0 02 96 RL 1kO 0 02 Differential Phase Error NTSC G 42 R 21500 0 11 Degrees RL lt 1 kO 0 02 Degrees Crosstalk 60 dB DC PERFOR Input Off 1 11 13 mV Tmn Tmax 27 32 mV Offset Drift 10 15 uV C Input Bias Current 14 2 6 2 4 5 HA Tmin Tmax 3 5 4 5 HA Input Offset Current 0 1 0 75 0 2 12 HA Open Loop Gain Ri lt 2 kQ 88 96 84 96 dB Tmn Tmax 96 96 dB RL 1500 78 82 76 82 dB Twin Tmax 80 80 dB INPUT CHARACTERISTICS Input Resistance 290 300 ko Input Capacitance 14 1 5 pF Input Common Mode Voltage Range 5 2 to 5 2 to V 4 4 Common Mode Rejection Ratio Vem 5 V to 3 5V 72 88 70 86 dB OUTPUT CHARACTERISTICS Output Voltage Swing R 2 10 kO 498 to 4 97 to V 4 98 4 97 R 2kQ 485to 497to 48to 49to V 4 85 4 97 4 8 4 9
30. z S O Z lt x H 10 I o a gt x E o EB 2 1 ES 1 2 3 4 5 6 7 8 910 10 100 1k 10k 100k 1M 10M amp FUNDAMENTAL FREQUENCY MHz z FREQUENCY Hz lt Figure 19 Total Harmonic Distortion Figure 22 Input Voltage Noise vs Frequency 50 10MHz a SJ d N CURRENT NOISE pA Hz WORST HARMONIC dBc 40 100 1k 10k 100k 1M 10M FREQUENCY Hz 0 05 10 15 20 25 30 35 40 45 5 0 OUTPUT VOLTAGE V p p 01062 020 01062 023 Figure 20 Worst Harmonic vs Output Voltage Figure 23 Input Current Noise vs Frequency 0 10 0 10 0 08 NTSC SUBSCRIBER 3 58MHz EEG j as lt 9 006 a Zo 004 E Q UE 0 02 FA W Lu W Lu Q 0 00 uz ga 002 Vg 5V G 2 EG Vs 5V G 2 0 04 Rp 2kO RL AS SHOWN o RF 2kO R AS SHOWN HR a o 20 0 Aa o e0 a EKV ETI 4ST 2ND 3RD 4TH 5TH 6TH 7TH gTH 9TH 10TH 44TH o1 03 4m 005 RL 1kQ z p 0 2 BA 0 00 EO 01 RL 1kQ Zu z 29 d RL 1500 E 9 00 Hg T CB 0 1 RL 1500 Z u 0 15 Vs 5V G 2 Gu 0 2 Vs 5V G 2 0 20 Rp 2kO RL AS SHOWN 2 Rp 2kO RL AS SHOWN I 4 T 0 i a 25 0 10 20 30 40 50 60 70 80 90 100

ANALOG DEVICES AD8054 handbook

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