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ANALOG DEVICES AD8295 datasheet

1. 10 100 1k FREQUENCV Hz 10k Figure 19 CMRR vs Frequencv RTI 1 kO Source Imbalance Vs 0 0 4 0 8 1 2 FROM V 1 6 2 0 2 0 1 6 FROM V INPUT VOLTAGE LIMIT V 1 2 0 8 REFERRED TO SUPPLY VOLTAGES 0 4 Vg 0 07343 044 10 SUPPLY VOLTAGE V 14 18 Figure 20 Input Voltage Limit vs Supply Voltage G 1 Rev 0 Page 11 of 28 07343 020 AD8295 NONLINEARITY 1ppm DIV 40 8 OUTPUT VOLTAGE SWING V REFERRED TO SUPPLV VOLTAGES 0 4 Vg 0 07343 021 07343 024 SUPPLY VOLTAGE V Vour V Figure 21 Output Voltage Swing vs Supply Voltage G 1 Figure 24 Gain Nonlinearity G 1 30 N e NONLINEARITY 10ppm DIV OUTPUT VOLTAGE SWING V p p Vour V Figure 22 Output Voltage Swing vs Load Resistance Figure 25 Gain Nonlinearity G 100 07343 022 07343 025 LOAD RESISTANCE Q 1k lt o b SOURCING b 100 3 GAIN 10 43 GAIN 100 o 42 GAIN 1000 VOLTAGE NOISE RTI nVA Hz SINKING OUTPUT VOLTAGE SWING V REFERRED TO SUPPLY VOLTAGES
2. serene 19 yp 20 Input Protectioni urca 21 Input Bias Current Return Path sss 21 RE Interferences sciiti 21 Differential Output sma 22 Applications Information iene 23 Creating a Reference Voltage at Midscale 23 High Accuracy G 1 Configuration with Low Pass Filter 23 2 Pole Sallen Key Filter eerte 24 AC Coupled Instrumentation Amplifier Driving Differential ADCS 25 Outline Dimensions salam RR 26 Ordering Guide cene den io needed 26 C com AL Rev 0 Page 2 of 28 SPECIFICATIONS INSTRUMENTATION AMPLIFIER SPECIFICATIONS SINGLE ENDED AND DIFFERENTIAL OUTPUT AD8295 CONFIGURATIONS Vs 15 V Vrer 0 V Ta 25 C G 1 Ri 2 kO unless otherwise noted The differential configuration is shown in Figure 59 Table 2 A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit COMMON MODE REJECTION Vom 10 V to 10 V RATIO CMRR CMRR DC to 60 Hz 1 KQ source imbalance G 1 80 90 dB G 10 100 110 dB G 100 120 130 dB G 1000 130 140 dB CMRR at 8 kHz G 1 80 80 dB G 10 90 100 dB G 100 100 120 dB G 1000 110 120 dB NOISE Voltage Noise 1 kHz RTI noise ew eno G Input Voltage Noise ew 8 8 nV VHz Output V i 75 nV VHz m WV CO G 1 UV p p G 10 0 5 0 5 UV p p G 100 to 1000 0 25 0 25 uV p
3. 1 GAIN 1000 BW LIMIT I lt o o E 1 10 100 1k 10k 100k FREQUENCV Hz o N 3 4 5 6 7 8 9 10 11 12 OUTPUT CURRENT mA 07343 023 07343 027 Figure 23 Output Voltage Swing vs Output Current G 1 Figure 26 Voltage Noise Spectral Density vs Frequency G 1 to 1000 Rev 0 Page 12 of 28 CURRENT NOISE fA Hz 2uVIDIV 1s DIV Figure 27 0 1 Hz to 10 Hz RTI Voltage Noise G 1 Figure 28 0 1 Hz to 10 Hz RTI Voltage Noise G 1000 07343 028 07343 029 100 1 10 100 1k 10k FREQUENCY Hz Figure 29 Current Noise Spectral Density vs Frequency 100k MAX OUTPUT VOLTAGE V p p 07343 030 Rev 0 Page 13 of 28 AD8295 07343 031 5pA DIV 1s DIV Figure 30 0 1 Hz to 10 Hz Current Noise GAIN 10 100 1000 GAIN 1 1k 10k 100k 1M FREQUENCY Hz Figure 31 Large Signal Frequency Response Aus TO 0 01 FT 3us TO 0 001 EMEN Miri mera L L RER 07343 033 Figure 32 Large Signal Pulse Response and Set
4. Table 4 A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit Nominal Resistor Value 20 20 kQ Resistor Matching 0 1 0 03 Matching Temperature Coefficient Ta 40 C to 85 C 5 1 ppm C Absolute Resistor Accuracy 0 2 0 1 Absolute Temperature Coefficient Ta 40 C to 85 C 50 50 ppm C POWER AND TEMPERATURE SPECIFICATIONS Vs 15 V Vrer 0 V Ta 25 C unless otherwise noted Table 5 A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit POWER SUPPLY Operating Range 2 3 18 2 3 18 V Quiescent Current In amp two op amps 2 2 3 2 2 3 mA Over Temperature Ta 40 C to 85 C 2 5 2 5 mA TEMPERATURE RANGE Specified Performance 40 485 40 C C Operational Perf 40 1 See the Typical Peri a a istiegisectio erationifrom 8 Rev 0 Page 6 of 28 ABSOLUTE MAXIMUM RATINGS Table 6 THERMAL CHARACTERISTICS Parameter Rating Specifications are provided for a device in free air Supplv Voltage 18V PRY d TE DE Table 7 Output Short Circuit Current Indefinite Input Voltage Package Osa Unit Common Mode Vs 16 Lead LFCSP VO 86 C W Differential Vs Storage Temperature Range 65 C to 130 C ESD CAUTION Operating Temperature Range 40 C to 125 C gt Lead T ture Soldering 10 sec 300 C ESD electrostatic discharge sensitive device ead temperature oldermg MV Sec Charged devices and circuit boards can discharge J
5. 1 21r 20kQ C1 07343 011 Figure 62 Single Pole Output Filter Using a Single External Capacitor If the connections to Pin 10 and Pin 11 in Figure 62 are changed so that Pin 10 connects to ground and Pin 11 connects to the in amp output the result is a G 2 circuit also with excellent gain accuracy and drift In the G 2 configuration Capacitor C1 lowers the gain from 2 to 1 at higher frequencies Rev 0 Page 23 of 28 AD8295 2 POLE SALLEN KEY FILTER Figure 63 shows the in amp output section of the AD8295 being low pass filtered using a 2 pole Sallen Key filter The filter section consists of Op Amp A2 External Resistors R1 and R2 as well as Capacitors C1 and C2 Resistor R3 compensates for input offset current errors and is equal to the parallel combination of RI and R2 The ratio of capacitance between C1 and C2 sets the filter quality factor Q For most applications a filter Q of 0 5 to 0 7 provides a good trade off between performance and stability High Q non polarized capacitors such as NPO ceramic should be used The exact pole frequencies are dependent on the tolerance of the resistors and capacitors used The design equations for a Sallen Key filter can be greatly simplified if the resistors and capacitors are made equal When C1 C2 and RI R2 Q is 0 5 and the design equation simplifies to f 1 2nRC where R is in ohms and C is in farads For example with R1 R2 10 kO and C1 C2 22 nF f 7 2 kH
6. Page 24 of 28 DRIVING DIFFERENTIAL ADCs Figure 65 shows how to configure the AD8295 to drive a differ ential ADC The circuit shown uses verv little board space and consumes little power With the AD7690 this configuration gives excellent dc performance and a THD of 83 dB 10 kHz input For applications that need better distortion performance a dedicated ADC driver such as the ADA4941 1 or ADA4922 1 is recommended The 500 Q resistors and the 2 2 nF capacitors form a low pass antialiasing filter at 144 kHz The four elements of the filter also prevent the switching transients produced by a typical SAR converter from destabilizing the AD8295 The capacitors provide charge to the switched capacitor front end of the ADC and the resistors shield the AD8295 from driving any sharp current AD8295 changes If the application requires a lower frequency anti aliasing filter than the one shown increasing the capacitor values produces much better distortion results than increasing the resistor values The 500 O resistors also give the ADC protection against over voltage Because the AD8295 runs on wider supply voltages than a typical ADC there is a possibility of overdriving some converters This is not an issue with a PulSAR ADC such as the AD7690 because its input can handle a 130 mA overdrive which is much higher than the short circuit limit of the AD8295 However other converters have less robust inputs and may benefit from
7. Ta 25 C Ri 10 kO Op Amp Al and Op Amp A2 unless otherwise noted GAIN dB PSRR dB NOISE nVNHz 80 70 60 50 40 30 20 1 10 100 1k 10k 100k 1M 10M FREQUENCY Hz 100M Figure 42 Closed Loop Gain vs Frequency G 1 to 1000 140 120 100 PSRR 80 60 40 20 0 1 1 10 100 1k 10k 100k 1M FREQUENCY Hz Figure 43 PSRR vs Frequencv 1k 100 10 1 10 100 1k 10k 100k FREGUENCY Hz Figure 44 Voltage Noise Density vs Freguency VOLTAGE NOISE uV 07343 065 CURRENT nA 07343 066 8 4 5 86 7 8 9 10 TIME Sec Figure 45 0 1 Hz to 10 Hz Noise o N TEMPERATURE C 07343 068 07343 069 Figure 46 Input Bias Current and Input Offset Current vs Temperature GAIN ERROR ppm 07343 067 Rev 0 Page 16 of 28 40 30 40 20 0 20 40 60 80 100 120 140 TEMPERATURE C Figure 47 Gain Drift Using
8. 59 Minimum Component Connections for Differential Output An alternative differential output configuration which also requires no external components is shown in Figure 60 Unlike the previous circuit this configuration uses an inverting op amp configuration to double the gain from the instrumentation amplifier Because this configuration requires less gain from the instrumentation amplifier it can have a wider frequency ponse and a wider input common ew att i includes the effors from the op amp and the resistor network When using the internal precision components of the AD8295 these errors have a minimal effect on overall accuracv This configuration is not specified in this data sheet HIN Ri R2 20k0 20kQ Ro Veer INPUT OUT OUT 07343 043 Figure 60 Alternative Differential Output Configuration Rev 0 Page 22 of 28 APPLICATIONS INFORMATION CREATING A REFERENCE VOLTAGE AT MIDSCALE A reference voltage other than ground is often useful for example when driving a single supplv ADC Creating a reference voltage derived from a voltage divider is straight forward with the AD8295 see Figure 61 In this configuration Op Amp A2 is used to provide a buffered Vs 2 reference for the in amp section This configuration is verv similar to the one described in the Reference Terminal section Note that the internal resistors of Op Amp Al are not used to provide Vs 2 Instead external 1 or be
9. C to 85 C Vs 1 6 4Vs 1 5 Vs 1 6 Vs 1 5 V Short Circuit Current 18 18 mA 1 One input grounded G 1 OP AMP SPECIFICATIONS Vs 15 V Ta 25 C Ri 2 KO unless otherwise noted Table 3 A Grade B Grade Parameter Typ Max T ax Unit INPUT CHA SAU CO s Average C 4 uV C Input Bias Current 10 8 nA Ta 40 C 20 16 nA Ta 85 C 10 8 nA Input Offset Current 2 0 5 nA Over Temperature Ta 40 C to 85 C 2 0 5 nA Input Voltage Range Vs 12 4Vs 12 Vs 1 2 4Vs 1 2 V Open Loop Gain 100 125 116 125 dB Common Mode Rejection Ratio 100 100 dB Power Supply Rejection Ratio 90 110 94 110 dB Voltage Noise Density 40 40 nVv VHz Voltage Noise f 0 1 Hz to 10 Hz 2 2 2 2 HV p p DYNAMIC PERFORMANCE Gain Bandwidth Product 1 MHz Slew Rate 2 6 2 6 V us OUTPUT CHARACTERISTICS Output Swing Vs 2 3 V to 5 V Vs 1 1 Vs 1 2 Vs 1 1 Vs 1 2 V Over Temperature Ta 40 C to 85 C Vs 1 4 Vs 1 3 Vs 1 4 Vs 1 3 V Output Swing Vs 5 V to 18 V Vs 1 2 Vs 1 4 Vs 12 is 14 V Over Temperature Ta 40 C to 85 C Vs 1 6 Vs 1 5 Vs 1 6 Vs 1 5 V Short Circuit Current 18 18 mA 1 Op amp uses an npn input stage so input bias current always flows into the inputs Rev 0 Page 5 of 28 AD8295 INTERNAL RESISTOR NETWORK When used with internal Op Amp A1 Ta 25 C unless otherwise noted Use in external op amp feedback loops is not recommended
10. p Current Noise f 1kHz 40 40 fA VHz f 0 1 Hz to 10 Hz 6 6 pA p p VOLTAGE OFFSET RTI Vos Vosi Voso G Input Offset Vosi Vs 5Vto 15V 120 60 UV Over Temperature Ta 40 C to 85 C 150 80 UV Average TC 0 4 0 3 UV C Output Offset Voso Vs 5Vto 15V 500 350 uV Over Temperature Ta 40 C to 85 C 0 8 0 5 mV Average TC 9 5 uV C Offset RTI vs Supply PSR Vs 23 V to 18 V G 1 90 110 94 110 dB G 10 110 120 114 130 dB G 100 124 130 130 140 dB G 1000 130 140 140 150 dB INPUT CURRENT Input Bias Current 0 5 2 0 0 2 0 8 nA Over Temperature Ta 40 C to 85 C 3 0 1 5 nA Average TC 1 1 pA C Input Offset Current 0 2 1 0 1 0 5 nA Over Temperature Ta 40 C to 85 C 1 5 0 6 nA Average TC 1 0 5 2 pA C Rev 0 Page 3 of 28 AD8295 A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit GAIN G 1 49 4 kO Ro Gain Range 1 1000 1 1000 VIN Gain Error Vour 10V G 1 0 05 0 02 G 10 0 3 0 1 G 100 0 3 0 1 G 1000 0 3 0 1 Gain Nonlinearity Vout 10V to 10 V G 1 3 10 5 ppm G 10 7 20 7 20 ppm G 100 7 20 7 20 ppm Gain vs Temperature G 1 5 1 ppm C G 1 50 50 ppm C DYNAMIC RESPONSE SINGLE ENDED CONFIGURATION Small Signal 3 dB Bandwidth G 1 1200 1200 kHz G 10 750 750 kHz G 100 140 140 kHz G 1000 15 15 kHz Settling Time 0 01 10V step G 1to 100 10 1 us G 1000 80 HS Settling meg AA fe C O G 1to 100 13 13 us G 1000 110 11
11. the resistive protection Ga A S R S Figure 65 Driving a Differential ADC Rev 0 Page 25 of 28 AD8295 OUTLINE DIMENSIONS ORDERING GUIDE PIN 1 INDICATOR BCS SQ TOP VIEW 12 MAX 0 80 MAX ba Ee 0 65 TYP EE 0 05 MAX 080 Li old do nom SEATING E 0 35 L COPLANARITY man 0 08 SEANG e 0 30 0 20 REF 040908 A COMPLIANT TO JEDEC STANDARDS MO 263 VBBC Figure 66 16 Lead Lead Frame Chip Scale Package LFCSP_VQ 4 mm x 4 mm Body Very Thin Quad with Hidden Paddle CP 16 19 Dimensions shown in millimeters Model Temperature Range Package Description Package Option AD8295ACPZ R7 AD8295ACPZ R AD8295ACPZ W AD8295BCPZ R7 AD8295BCPZ RL AD8295BCPZ WP 40 C to 4 85 to 85 85 40 C to 85 40 C to 85 C 40 C to 85 C VO 7 Inch Tape and Reel LFCSP VQ 127 Leaa LFCSP VQ Greka Lead VQ 7 Tape and Re 16 Lead LFCSP_VQ 13 Inch Tape and Reel 16 Lead LFCSP_VQ Waffle Pack CP 16 19 CP 16 19 1 Z RoHS Compliant Part Rev 0 Page 26 of 28 AD8295 NOTES ww BDI C com AD AD8295 NOTES ww BOM C Com AD 2008 Analog Devices Inc All rights reserved Trademarks and AN ALOG registered trademarks are the property of their respective owners DU1543 0 10 0840 DEVICES www analog com Rev 0 Page 28 of 28
12. 0 HS Slew Rate G 1 1 5 2 1 5 2 V us G 5 to 1000 2 2 5 2 2 5 V us DYNAMIC RESPONSE DIFFERENTIAL OUTPUT CONFIGURATION Small Signal 3 dB Bandwidth G 1 1200 1200 kHz G 10 1000 1000 kHz G 100 140 140 kHz G 1000 15 15 kHz Settling Time 0 01 10V step G 1to 100 10 10 us G 1000 80 80 us Settling Time 0 001 10V step G 1 to 100 13 13 us G 1000 110 110 us Slew Rate G 1 1 5 2 1 5 2 V us G 5 to 1000 2 2 5 2 2 5 V us REFERENCE INPUT Rin 20 20 ko lin Vin Vin Veer OV 50 60 50 60 HA Voltage Range Vs Vs Vs TVs V Gain to Output 1 0 0001 1 x 0 0001 VIN Rev 0 Page 4 of 28 AD8295 A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit INPUT Input Impedance Differential 100j 2 100jj2 GO pF Common Mode 100 2 100jj2 GO pF Input Operating Voltage Range Vs 42 3V to 5 V Vs 1 9 4Vs 1 1 Vs 1 9 Vs 1 1 V Over Temperature Ta 40 C to 85 C Vs 2 0 4Vs 1 2 Vs 2 0 Vs 1 2 V Input Operating Voltage Range Vs 5 V to 18 V Vs 1 9 4Vs 1 2 Vs 1 9 Vs 1 2 V Over Temperature Ta 40 C to 85 C Vs 2 0 4Vs 1 2 Vs 2 0 Vs 1 2 V OUTPUT R 10kQ Output Swing Vs 2 3 V to 5 V Vs 1 1 4Vs 1 2 Vs 1 1 Vs 1 2 V Over Temperature Ta 40 C to 85 C Vs 1 4 4Vs 1 3 Vs 14 Vs 1 3 V Output Swing Vs 5 V to 18 V Vs 12 4Vs 1 4 Vs 1 2 Vs 14 V Over Temperature Ta 40
13. 160 GAIN 1000 140 GAIN 100 120 GAIN 10 100 LEANE 1 80 60 40 20 0 1 1 10 100 1k 100k FREQUENCY Hz Figure 14 Positive PSRR vs Frequency RTI G 1 to 1000 1M 07343 062 07343 063 07343 049 NEGATIVE PSRR dB GAIN ERROR ppm GAIN dB 180 160 GAIN 1000 140 GAIN 100 120 GAIN 10 100 GAIN 1 80 60 40 20 0 1 1 10 100 1k 10k 100k 1M FREQUENCY Hz Figure 15 Negative PSRR vs Frequency RTI G 1 to 1000 40 20 0 20 40 60 80 100 120 140 TEMPERATURE C Figure 16 Gain Error vs Temperature G 1 GAIN 1000 GAIN 100 GAIN 10 GAIN 1 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 17 Gain vs Frequency 180 170 160 AD8295 GAIN 150 140 FGAIN 130 120 GAIN 110 100 GAIN CMRR dB 07343 050 10 100 1k FREQUENCY Hz Figure 18 CMRR vs Frequency RTI 10k 150 GAIN GAIN 120 FGAIN CMRR dB H 100 FGAIN 07343 064
14. ANALOG DEVICES Precision Instrumentation Amplifier with Signal Processing Amplifiers AD8295 FEATURES Saves board space Includes precision in amp 2 op amps and 2 matched resistors 4mm x 4 mm LFCSP No heat slug for more routing room Differential output fully specified In amp specifications Gain set with 1 external resistor gain range 1 to 1000 8 nV VHz 1 kHz maximum input voltage noise 90 dB minimum CMRR G 1 0 8 nA maximum input bias current 1 2 MHz 3 dB bandwidth G 1 2 V us slew rate Wide power supply range 2 3 V to 18 V 1 ppm C 0 03 resistor matching APPLICATIONS Industrial process controls Wheatstone bridges Precision data acquisition systems Medical instr Transducer interfaces Differential output GENERAL DESCRIPTION The AD8295 contains all the components necessary for a precision instrumentation amplifier front end in one small 4mm x 4 mm package It contains a high performance instrumentation amplifier two general purpose operational amplifiers and two precisely matched 10 KQ resistors The AD8295 is designed to make PCB routing easy and efficient The AD8295 components are arranged in a logical way so that typical application circuits have short routes and few vias Unlike most chip scale packages the AD8295 does not have an exposed metal pad on the back of the part which frees additional space for routing and vias The AD8295 comes in a 4mm x 4 mm LFCSP that requires hal
15. On Chip Resistor Divider G 1 07343 070 GAIN ERROR ppm 40 20 0 20 40 60 80 100 120 140 TEMPERATURE C Figure 48 Gain Drift Using On Chip Resistor Divider G 2 07343 071 ww BDI C com AD Rev 0 Page 17 of 28 AD8295 AD8295 SYSTEM Vs 15 V Vre 0 V Ta 25 C unless otherwise noted 80 3 0 GAIN 1000 60 2 5 GAIN 100 ri 40 E 20 Z 5 GAIN 10 2 EIE z 40 C z 20 1 5 4 o gt GAIN 1 al 0 a 10 2 o 20 0 5 40 0 10 100 1k 10k 100k 1M 10M 2 4 6 8 10 12 14 FREQUENCY Hz SUPPLY VOLTAGE V Figure 49 Differential Output Configuration Gain vs Frequency Figure 51 Supply Current vs Supply Voltage 80 70 8 60 a E 50 2 o M 40 o z 30 o 5 20 o 10 0 fe 1 10 100 1k 10k 100k 1M 2 FREQUENCY Hz Figure 50 Differential Output Configuration Common Mode Output vs Frequency Rev 0 Page 18 of 28 07343 072 THEORV OF OPERATION As shown in Figure 52 the AD8295 contains a precision instrumentation amplifier two uncommitted op amps anda precision resistor arrav These components allow manv common applications to be wired using sim
16. The AD8295 defaults to G 1 when no gain resistor is used Gain accuracy is a combination of both the Re accuracy and the accuracy listed in the specifications in Table 2 including accuracy over temperature Gain error and gain drift are kept to a minimum when the gain resistor is not used ect E es gallh internally and mi Voltage TMerefore internal nodes in the AD8295 experience a combination of both the gained signal and the common mode signal This combined signal can be limited by the voltage supplies even when the individual input and output signals are not Figure 7 through Figure 10 show the allowable common mode input voltage ranges for various output voltages and supply voltages If Figure 7 through Figure 10 indicate that internal voltage limiting may be an issue the common mode range can be improved by lowering the gain in the instrumentation amplifier by one half and applying a second G 2 stage Figure 53 shows how to do this amplification with the internal circuitry of the AD8295 requiring no additional external components A1 TOTAL GAIN IN AMP x 2 A1 OUT 07343 019 Figure 53 Applying Gain in a Later Stage Allows Wider Input Common Mode Range Rev 0 Page 19 of 28 AD8295 Reference Terminal The output voltage of the AD8295 instrumentation amplifier is developed with respect to the potential on the reference terminal This is useful when the output signal needs to be offset to a precise dc lev
17. d be chosen so that the parasitic capacitance is as small as possible Unused Op Amps in a unitffgain connected to l hese connections ensure that the AD8295 op amp uses minimum power and does not disturb the internal power supplies of the AD8295 These connections are shown as dotted lines in several of the applications figures Reference The output voltage of the instrumentation amplifier section of the AD8295 is developed with respect to the potential on the reference terminal REF care should be taken to tie the REF pin to the appropriate local ground Rev 0 Page 20 of 28 Power Supplies A stable dc voltage should be used to power the instrumentation amplifier Noise on the supplv pins can adverselv affect perfor mance See the PSRR performance curves in Figure 14 and Figure 15 for more information A 0 1 uF capacitor should be placed as close as possible to each supply pin An additional capacitor a 10 uF tantalum for the lower frequencies can be used farther away from the IC In most cases the 10 uF bypass capacitor can be shared by other integrated circuits on the same PCB Vs AD8295 IN AMP lt o H m 4A 07343 005 INPUT PROTECTION All termina by diodes at We inputs lt anticipated resistors should be placed in series with the inputs to limit the current Resistors should be chosen so that current does not exceed 6 mA into the internal ESD diodes in the over load condit
18. el The reference pin input can be driven slightly beyond the rails The REF pin is protected with ESD diodes and the REF voltage should not exceed either Vs or Vs by more than 0 3 V For best performance the source impedance to the REF terminal should be kept below 1 Q Additional impedance at the REF terminal can significantly degrade the CMRR of the amplifier When the reference source has significant output impedance for example a resistive voltage divider buffer the signal before driving the REF pin Internal Op Amp Al or A2 can be used for this purpose as shown in Figure 54 INCORRECT CORRECT AD8295 Vs 2 REF RA Rg V Noise at the reference feeds directly to the output Therefore in Figure 54 Capacitor C is added to filter out any high frequency noise on the positive power supply line For very clean supplies the capacitor may not be needed The filter frequency is a trade off between noise rejection and start up time and is given by the following equation OP AMP BUFFER rowpass RR LAYOUT The AD8295 is a high precision device To ensure optimum performance at the PCB level care must be taken in the board layout The AD8295 pins are arranged in a logical manner to aid in this task Unlike most LFCSP packages the AD8295 package was designed without the thermal pad to allow routes and vias directly beneath the chip Careful board layout maximizes system performance Traces from the gain sett
19. f the board space of an 8 pin SOIC package Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners CONNECTION DIAGRAM Vs OUT A2 IN A2 IN Q G3 3 YO AD8295 to 3 A2 OUT Re 2 A1 IN Rg LA Ba MRI IN 4 BE A1 IN O _ 3 Vs REF A1OUT A1R2 Figure 1 Table 1 Instrumentation Amplifiers bv Categorv General Zero Militarv Low High Speed Purpose Drift Grade Power PGA AD8220 AD8231 AD620 AD627 AD8250 AD8 d AD8251 AD8222 Di AD8253 AD i 6 AD8228 AD8557 AD624 AD8295 AD8293 1 Rail to rail output The AD8295 includes a high performance programmable gain instrumentation amplifier Gain is set from 1 to 1000 with a single resistor The low noise and excellent common mode rejection of the AD8295 enable the part to easilv detect small signals even in the presence of large common mode interference For a similar instrumentation amplifier without the associated signal conditioning circuitrv see the AD8221 or AD8222 data sheet The AD8295 operates on bot
20. g equations 1 5 4l Femrer iff 2nR 2C C fos CM FILTER 2nRC where Cp gt 10Cc Rev 0 Page 21 of 28 AD8295 Vs AD8295 IN AMP 07343 007 Figure 57 RFI Suppression Lower cutoff frequencies improve RFI robustness Accuracy of the Cc capacitors is important because any mismatch between the R x Cc at the positive input and the R x Cc at the negative input degrades the CMRR of the AD8295 Keeping Cp at least 10 times larger than Cc is recommended DIFFERENTIAL OUTPUT The AD8295 can be pin strapped to provide a differential output the simplified schematic is shown in Figure 58 and the full pin connection is shown in Figure 59 This configuration uses the instrumentation amplifier to maintain the differential voltage while t Because the in a reference pin thi as the single ended output configuration The transfer function for the differential and common mode outputs are as follows Vpirr our Vour Vour G x Vins Vin Vem our Vour Vour 2 Vrer where 49 4 kO A Ra This configuration is fully specified see Table 2 Figure 49 and Figure 50 DC performance is the same as for the single ended configuration ac performance is slightly different IN OUT Veer INPUT LY Figure 58 Differential Output Using an Op Amp 07343 018 uo INPUT HIN INPUT NOTES 1 CONNECT AS SHOWN IF A2 IS NOT BEING USED 07343 008 Figure
21. h single and dual supplies and is well suited for applications where 10 V input voltages are encountered Performance is specified over the entire industrial temperature range of 40 C to 85 C for all grades The AD8295 is operational from 40 C to 125 C see the Typical Performance Characteristics section for expected operation up to 125 C One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2008 Analog Devices Inc All rights reserved AD8295 TABLE OF CONTENTS Features cse a Mer Applications cene OE RIP URN Connection Diagram uri General Description sissies Revision History iii Specifications Ti nani ra teh E Instrumentation Amplifier Specifications Single Ended and Differential Output Configurations eee Op Amp Specifications Internal ResistorNetwork eee Power and Temperature Specifications Absolute Maximum Ratings eee Thermal Characteristics eene ESD Cautioni cede pe ER ROSEO Pin Configuration and FunctionDescriptions Typical Performance Characteristics sse REVISION AA 10 08 Revision 0 Initial Version My 18 Thery of Operation eene RHOD RERO ai 19 Uncommitted Op Amps eerte 19 Instrumentation Amplifier
22. ing resistor to the Rc pins should be kept as short as possible to minimize parasitic inductance To ensure the most accurate output the trace from the REF pin should either be connected to the local ground of the AD8295 or to a voltage that is referenced to the local ground of the AD8295 Common Mode Rejection over Frequency The AD8295 has a higher CMRR over frequency than typical in amps which gives it greater immunity to disturbances such as line noise and its associated harmonics The AD8295 pinout and hidden paddle package were designed so that the board designer can take full advantage of this performance with a well implemented layout Poor layout can cause some of the common mode signal to be converted to a differential signal before it reaches the in amp Such conversions occur when one input path has a frequency response that is different from the other To keep CMRR across frequency high the input source impedance and capacitance of each path should be closely matched Additional source resistance in the input path for example for input protection should be placed close to the in amp inputs to minimize their interaction with parasitic capacitance from the PCB traces Parasitic capacitance at the gain setting pins can also affect CMRR over frequency The traces to the Rc resistor should be kept as short as possible If the board design has a component at the gain setting pins for example a switch or jumper the part shoul
23. ion These resistors can be the same as those used for RFI protection See the RF Interference section for more information For applications where the AD8295 encounters extreme overload voltages as in cardiac defibrillators external series resistors and low leakage diode clamps such as BAV199Ls FJH1100s or SP720s can be used INPUT BIAS CURRENT RETURN PATH The input bias currents of the AD8295 must have a return path to common When the source such as a thermocouple cannot provide a return current path one should be created as shown in Figure 56 Otherwise the input currents charge up the input capacitance until the in amp is turned off or saturated AD8295 INCORRECT CORRECT Ws Vs AD8295 IN AMP Vs TRANSFORMER TRANSFORMER Vs Vs AD8295 IN AMP AD8295 IN AMP Vs Vs THERMOCOUPLE THERMOCOUPLE Vs Vs 07343 006 CAPACITIVELY COUPLED CAPACITIVELY COUPLED Figure 56 Creating an Input Bias Current Return Path RF INTERFERENCE RF interference is often a problem when amplifiers are used in applications where there are strong RF signals The precision circuits in the AD8295 can rectify the RF signals so that they appear as a dc offset voltage error To avoid this rectification place a low pass filter before the input Figure 57 shows such a network in front of the instrumentation amplifier The filter limits both the differential and common mode bandwidth as shown in the followin
24. on of Input Bias Current Figure 8 Input Common Mode Range vs Output Voltage G 1 Vs 15V REF 0V Rev 0 Page 9 of 28 AD8295 INPUT COMMON MODE VOLTAGE V CHANGE IN INPUT OFFSET VOLTAGE uV 5 4 3 2 4 0 1 2 3 4 OUTPUT VOLTAGE V a 07343 047 Figure 9 Input Common Mode Range vs Output Voltage G 100 Vs 2 5 V 5 V REFZ0V 15 G 100 Vs 15V 10 ul z 5 o 5 zs gt H g o z r4 6 r4 3 3 5 o o amp amp 10 15 15 10 5 0 5 10 15 07343 048 OUTPUT VOLTAGE V Figure 10 Input Common Mode Range vs Output Voltage G 100 Vs 15 V REF 0V 0 100 0 150 0 200 POSITIVE PSRR dB 0 250 INPUT BIAS CURRENT nA 0 300 15 10 0 5 10 15 COMMON MODE VOLTAGE V 07343 061 Figure 11 Input Bias Current vs Common Mode Voltage Rev 0 Page 10 of 28 0 2 4 6 WARM UP TIME Min Figure 12 Change in Input Offset Voltage vs Warm Up Time NEGATIVE BIAS POSITIVE BIAS 40 20 0 20 40 TEMPERATURE C 60 80 100 120 140 Figure 13 Input Bias Current and Offset Current vs Temperature 180
25. ple pin strapping directly at the IC This not only saves printed circuit board PCB space but also improves circuit performance because both temperature drift and resistor tolerance errors are reduced Vs OUT A24 N A2 IN 07343 004 Ns REF ATOUT A1R2 Figure 52 Functional Block Diagram UNCOMMITTED OP AMPS The AD8295 has two uncommitted op amps that can be used r reGision 2 1 voltage divider resistor network Because this network is internal to the IC these resistors are closely matched and also track each other with temperature variations Op Amp Al and the associated resistor network can be used to create either a noninverting gain stage of 2 or an inverting gain stage of 1 with excellent gain accuracy and gain drift Op Amp A2 is a more conventional op amp with standard inverting and noninverting inputs and an output INSTRUMENTATION AMPLIFIER Gain Selection The transfer function of the AD8295 is Vour G x Vins Vin Vrer where placing a resistor across the Rc terminals sets the gain of the AD8295 according to the following equation 49 4 kO fn Ra AD8295 Resistor values can be obtained by referring to Table 9 or by using the following gain equation 49 4 kO fel Table 9 Gains Achieved Using 100 Resistors 1 Standard Table Value of Rc Calculated Gain 49 9 kO 1 990 12 4 kO 4 984 5 49 kQ 9 998 2 61 kQ 19 93 1 00 kO 50 40 4990 100 2490 199 4 1000 495 4990 991
26. tling Time G 1 07343 032 AD8295 4 8us TO 0 01 6 6us TO 0 001 0 002 DIV 20mV DIV 4us DIV 07343 034 07343 037 Figure 33 Large Signal Pulse Response and Settling Time G 10 Figure 36 Small Signal Pulse Response G 1 R 2 kQ C 100 pF 2us TO 0 01 16 2us TO 0 001 07343 038 83us TO 0 01 2yus TO 0 001 0 002 DIV 200us DIV 07343 036 07343 039 Figure 35 Large Signal Pulse Response and Settling Time G 1000 Figure 38 Small Signal Pulse Response G 100 Ri 2 kQ C 100 pF Rev 0 Page 14 of 28 AD8295 SETTLING TIME us 1k 100 SETTLED TO 0 001 10 SETTLED TO 0 01 100us DIV GAIN 07343 040 07343 042 Figure 39 Small Signal Pulse Response G 1000 Ri 2 kO C 100 pF Figure 41 Settling Time vs Gain for a 10 V Step SETTLED TO 0 001 SETTLING TIME us C comALI 0 5 10 15 20 OUTPUT VOLTAGE STEP SIZE V 07343 041 Figure 40 Settling Time vs Step Size G 1 Rev 0 Page 15 of 28 AD8295 OP AMPS Vs 15 V
27. to this pin 7 A1 OUT Op Amp A1 Output 8 A1R2 Resistor R2 Terminal Connected internally to Op Amp AT inverting input 9 A1 IN Op Amp A1 Inverting Input Midpoint of resistor divider 10 A1 RI Resistor Wh m ed int to Op Amp A1 inverting inpgt MNNSBEJIT C COM AD 12 Amp b 13 A I p Amp A2 Inverting Input 14 A2 IN Op Amp A2 Noninverting Input 15 OUT In Amp Output 16 Vs Positive Supply Rev 0 Page 8 of 28 AD8295 TYPICAL PERFORMANCE CHARACTERISTICS IN AMP Vs 15 V REF 0 V Ta 25 C Ri 10 kO unless otherwise noted 800 800 600 600 400 400 200 200 1 0 0 5 0 0 5 1 0 HITS HITS 0 0 100 50 0 50 100 8 8 CMRR V V INPUT OFFSET CURRENT nA Figure 3 Typical Distribution for CMRR G 1 Figure 6 Typical Distribution of Input Offset Current Ww A Dj En 9 e DL rI z o o O IM z 2 n T 100 50 0 50 100 5 4 3 2 A 0 1 2 3 4 58 Vosi HV OUTPUT VOLTAGE V Figure 4 Tvpical Distribution of Input Offset Voltage Figure 7 Input Common Mode Range vs Output Voltage G 1 Vs 22 5V 5 V REF 0V HITS N a e e e e e e e INPUT COMMON MODE VOLTAGE V l a e a LLL 10 100 0 15 2 A 0 1 28 15 10 5 0 5 10 15 INPUT BIAS CURRENT nA OUTPUT VOLTAGE V Figure 5 Typical Distributi
28. tter resistors are used Because the negative input of Op Amp AI is permanentiv connected to the junction of internal resistors RI and R2 Op Amp Al operates as a low voltage clamp preventing the resistor string from providing a convenient Vs 2 voltage Noise at the reference feeds directly to the output so if the reference voltage is derived from a noisy source filtering is required In Figure 61 Capacitor C1 has been added to filter out high frequency noise on the positive power supply line The 10 uF capacitor and the 100 kO resistors shown in Figure 61 roll off noise starting at 0 3 Hz The filter frequency is a trade off between noise rejection and start up time Vs N INPUT Vg 2 BUFFERED 07343 009 Figure 61 Single Supplv Connection with Buffered Reference AD8295 HIGH ACCURACY G 1 CONFIGURATION WITH LOW PASS FILTER The circuit in Figure 62 uses Op Amp A1 and the resistor string to provide a precise G 1 configuration Because no external resistors are used to set the gain gain accuracy and gain drift depend only on the internally matched resistors yielding excel lent performance Adding a capacitor across Resistor R2 is a simple way to provide a single pole low pass filter that rolls off at 20 dB per decade This capacitor is shown as C1 in Figure 62 Vs N INPUT Rc OUT Rc HIN 5 d AD8295 au aC INPUT LP FILTERED OUTPUT NOT 1 flow pass
29. unction Temperature 130 C A without detection Although this product features ESD H B M 2000 V patented or proprietary protection circuitry damage uman ody Sed p dy may occur on devices subjected to high energy ESD ESD Charge Device Model 500V Therefore proper ESD precautions should be taken to ESD Machine Model 200V avoid performance degradation or loss of functionality AD8295 1 Temperature range for specified performance is 40 C to 85 C See the Typical Performance Characteristics section for expected operation from 85 C to 125 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied maximum fati r ktende device relial Rev 0 Page 7 of 28 C com AL AD8295 PIN CONFIGURATION AND FUNCTION DESCR 16 Vs 15 OUT PIN 1 o TEM AD8295 TOP VIEW Not to Scale OUT 7 A1R2 8 07343 017 A1 Figure 2 Pin Configuration Table 8 Pin Function Descriptions Pin No Mnemonic Description 1 IN In Amp Negative Input 2 3 Re In Amp Gain Setting Resistor Terminals 4 HIN In Amp Positive Input 5 Vs Negative Supply 6 REF In Amp Reference Terminal Drive with a low impedance source Output is referred
30. z When CI is not equal to C2 and RI is not equal to R2 the values of Q and the cutoff frequency are calculated as follows RIR JRIRACI62 ET 2nVRIR2C1C2 LP FILTERED SA NO 07343 012 Figure 63 2 Pole Sallen Key Filter AC COUPLED INSTRUMENTATION AMPLIFIER The circuit in Figure 64 provides a one pole high pass filter using only one external capacitor At low frequencies Capacitor C1 has a high impedance thus operating Op Amp Al at high gain G Xc 20 kO Because of its high gain Op Amp Al is able to drive the in amp reference pin until it forces the output of the in amp to 0 V Therefore no signal appears at the circuit output At higher frequencies the gain of Op Amp A1 drops and the op amp is no longer able to maintain the in amp output at 0 V Therefore at frequencies above the RC filter bandwidth the in amp operates in a normal manner and the signal appears at the output The 3 dB corner frequency is set by Internal Resistor R1 and External Capacitor CI as follows f 1 2nx 20 kO x CI The precision of RI better than 0 290 means that the filter bandwidth depends mainly on the tolerance of Capacitor C1 At low frequencies Op Amp A1 drives the appropriate voltage on the reference pin to null out the original signal Voltage supplies should be chosen so that Op Amp A1 has enough output headroom to produce the nulling voltage w E A EA R S Figure 64 AC Coupled Connection Rev 0

ANALOG DEVICES AD8295 datasheet

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