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ANALOG DEVICES ADA4938-1/ADA4938-2 handbook

1. i 1 10 100 FREQUENCY MHz 8 FREQUENCY MHz 8 Figure 26 Harmonic Distortion vs Frequency Gain Figure 29 Harmonic Distortion vs Frequency for Various Loads 40 HD2 10MHz HD2 10MHz 50 HD3 10MHz HD3 10MHz 02 70MHz HD2 70MHz 70 2 HD3 70MHz 60 y 1 1 70 HN 1 5 Ll 4 LE I j 2 2 5 2 z 80 z o o 3 o 9 o o o 8 100 a ST 110 120 130 3 3 2 7 2 1 1 5 0 9 03 0 3 09 15 21 27 3 3 V 1 7 1 9 2 1 2 3 2 5 2 7 2 9 3 1 3 3 V 06592 128 06592 125 Figure 27 Harmonic Distortion vs and Frequency Figure 30 Harmonic Distortion vs and Frequency Vs 5 V Rev 0 Page 12 of 28 ADA4938 1 ADA4938 2 10 0 0 5 10 10 15 20 20 25 ae 30 40 35 5 5
2. 55 100 50 5 lt 45 8 10 8 4 x 2 o amp 35 30 5 1 10 100 10 100 1 10k 100k 1M 10M 100M FREQUENCY MHz FREQUENCY Hz Figure 49 IP3 vs Frequency Figure 51 Input Current Noise vs Frequency 40 ALL CURVES ARE NORMALIZED TO Vocy 0V 55 0 60 amp INPUT1 OUTPUT2 _ 70 z h m 5 5 lt 3 4 Z 4 3E 17 80 ph 3 E 9 J rd 5 90 FAT 100 E 3 7V M 5 INPUT2 OUTPUT1 9 3 5V b 1 o 3V LE 9 n 120 3V 3 5V 130 3 7V 12 140 5 1 10 100 1000 8 0 3 1 10 100 1000 FREQUENCY MHz 8 FREQUENCY MHz 8 Figure 50 Vout Large Signal Frequency Response for Various Vocm Figure 52 Crosstalk vs Frequency for ADA4938 2 Rev 0 Page 16 of 28 ADA4938 1 ADA4938 2 TEST CIRCUTS 2000 06592 246 06592 247 2000 Figure 54 Test Circuit for Output Balance FILTER 06592 248 2000 Figure 55 Test Circuit for Distortion Measurements Rev 0 Page 17 of 28 ADA4938 1 ADA4938 2 OPERATIONAL DESCRIPTION DEFINITION OF TERMS Common Mode Voltage The common mode voltage is the average of two node voltages The output common mode voltage is defined as Vout om V our V ovr 2 Balance Balance is a measu
3. 06592 043 HH 5 VOLTAGE V e 1 1 n m 1 Y mm MEUSE Eden TIME 1ns DIV 2 5 3 0 06592 145 Figure 46 Large Signal Transient Response VOLTAGE V e 4 5 Wu 2 0 i TIME 2ns DIV 5 2 5 8 2 8 Figure 47 Large Signal Transient Response 60 85 ALL CURVES ARE 25 NORMALIZED Vocy 0V oc 50 T 40 gt lt 3 30 5 ui 4 A 6 3 7V 9 gt 9 lt 3 5 2 Vocm 3V Q Vocm 0V 10 9 T 3V 3 5V 3 7 0 12 20 22 24 26 28 30 32 34 36 38 40 1 10 100 1000 5 VOLTAGE V 8 FREQUENCY MHz Figure 45 Supply Current vs Power Down Voltage and Temperature Vs 5 V Figure 48 Vout am Small Signal Frequency Response for Various Vour 0 1 V p p Rev 0 Page 15 of 28 ADA4938 1 ADA4938 2
4. 1 30 06592 060 Figure 66 Recommended Thermal Attach Pad ADA4938 1 Dimensions in Millimeters i ih AN 2 77 08 BOTTOM METAL 2 06592 061 Figure 67 Cross Section of a 4 Layer ADA4938 1 Showing Thermal Via Connection to the Buried Ground Plane Dimensions in Millimeters Rev 0 Page 23 of 28 ADA4938 1 ADA4938 2 HIGH PERFORMANCE ADC DRIVING The ADA4938 is ideally suited for dc coupled baseband applications The circuit in Figure 68 shows a front end connection for an ADA4938 driving an AD9446 16 bit 80 MSPS ADC The AD9446 achieves its optimum performance when it is driven differentially The ADA4938 eliminates the need for a transformer to drive the ADC performs a single ended to differential conversion buffers the driving signal and provides appropriate level shifting for dc coupling The ADA4938 is configured with a single 10 V supply and unity gain for a single ended input to differential output The 61 9 termination resistor in parallel with the single ended input impedance of 267 provides 50 termination for the source The additional 26 226 total at the inverting input balances the parallel impedance of the 50 source and the termination resistor driving the noninverting input The signal generator has a symmetric ground referenced bipolar output The pin of the ADA4938 is biased with an exte
5. 3mm x 3mm Body CP 16 2 Dimensions shown in millimeters 0 60 MAX INDICATOR 0 80 MAX I 2 50 REF 1 00 12 MAX 0 65 TYP 0 85 be 0 05 MAX 0 80 0 02 NOM 0 30 1 COPLANARITY 023 0 20 REF 0 08 SEATING 23 0 18 COMPLIANT TO JEDEC STANDARDS MO 220 VGGD 2 Figure 71 24 Lead Lead Frame Chip Scale Package LFCSP VO 4mm x 4 mm Body Very Thin Quad CP 24 1 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Quantity Branding ADA4938 1ACPZ R2 40 to 85 16 Lead LFCSP VQ CP 16 2 5 000 H11 ADA4938 1ACPZ RL 40 to 85 16 Lead LFCSP VQ CP 16 2 1 500 H11 ADA4938 1ACPZ R7 40 to 85 16 Lead LFCSP VQ CP 16 2 250 H11 ADA4938 2ACPZ R2 40 to 85 24 Lead LFCSP VO CP 24 1 5 000 ADA4938 2ACPZ RL 40 to 85 24 Lead LFCSP VQ CP 24 1 1 500 ADA4938 2ACPZ R7 40 to 85 24 Lead LFCSP VQ CP 24 1 250 1 RoHS Compliant Part Rev 0 Page 25 of 28 ADA4938 1 ADA4938 2 NOTES ww C conh ADA4938 1 ADA4938 2 NOTES ww C conh ADA4938 1 ADA4938 2 NOTES INN D ALI 2007 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D06592 0 11 07 0 DEVICES www analog com Rev 0 Page 28 of 28
6. 40 E 45 60 50 PSRR o 70 55 60 PSRR 80 65 90 i 70 100 s 1 80 110 85 29 5 29 6 29 7 29 8 29 9 30 0 30 1 30 2 30 3 30 4 30 5 0 1 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz 8 Figure 31 Intermodulation Distortion Figure 34 PSRR vs Frequency 20 0 25 5 30 35 40 di 8 45 5 20 z 2 50 25 9 522 55 E cas 9 Vs 5 B 60 P gt 35 Vs 5 70 a S11 45 75 7 80 50 85 2 55 E 0 1 1 10 100 1000 2 1 10 100 1000 FREQUENCY MHz 8 FREQUENCY MHz Figure 32 Vin CMRR vs Frequency Figure 35 Return Loss S11 522 vs Frequency 15 2000 R 1kQ 20 2000 R 1000 25 8 30 35 5 z a 3 40 8 5 45 n 5 50 o 55 60 65 1 10 100 1000 2 1 10 100 2 FREQUENCY MHz FREQUENCY MHz Figure 33 Output Balance vs Frequency Figure 36 SFDR vs Frequency for Various Loads Rev 0 Page 13 of 28 ADA4938 1 ADA4938 2 t a M 20 5 G
7. 2 2 O 18 aij G 4 z 46 9 gt a 14 z z 12 10 10 100 500 8 10 100 1 10k 100k 1M 10M 100 8 FREQUENCY MHz FREQUENCY Hz 8 Figure 37 Noise Figure vs Frequency Figure 40 Input Voltage Noise vs Frequency 4 0 3 5 PD INPUT 3 0 2 5 5 5 2 0 5 5 15 o gt gt 1 0 1 a 0 5 SINGLE GUTPUT Vin 3 16 0 Vout dm e 5 0 5 0 5 10 15 20 25 30 35 40 45 50 55 60 2 TIME 200ns DIV 8 TIME 5ns DIV 5 Figure 38 Overdrive Recovery Time Pulse Input Figure 41 Power Down Response Time 12 45 40 8 35 6 4 _ 30 lt 2 25 E lt 0 2 20 2 gt 2 E 9 45 10 8 Vin 3 16 5 V dm 42 907 CE 0 50 100 150 200 250 300 350 400 450 500 20 22 24 26 28 30 32 34 36 38 40 TIME 50ns DIV VOLTAGE V 8 Figure 39 Overdrive Amplitude Characteristics Triangle Wave Input Figure 42 Supply Current vs Power Down Voltage and Temperature Rev 0 Page 14 of 28 ADA4938 1 ADA4938 2 0 20 V e o a VOLTAGE 06592 142 TIME 1ns DIV Figure 43 Small Signal Transient Response Vour 0 1 V p p VOLTAGE V 0 02 0 04 0 06 0 08 0 10 TIME 2ns DIV Figure 44 Vocu Small Signal Transient Response Vout 0 1 V p p
8. ADA4938 1 Pin Configuration Figure 6 ADA4938 2 Pin Configuration Table 7 ADA4938 1 Pin Function Descriptions Table 8 ADA4938 2 Pin Function Descriptions Pin No Mnemonic Description Pin No Mnemonic Description 1 Negative Output Feedback Pin 1 IN1 Negative Input Summing Node 1 2 IN Positive Input Summing Node 2 FB1 Positive Output Feedback Pin 1 3 Negative Input Summing Node 3 4 TVsi Positive Supply Voltage 1 4 FB Positive Output Feedback Pin 5 FB2 Negative Output Feedback Pin 2 5to8 Vs Positive Supply Voltage _ 6 IN2 Positive Input Summing Node 2 9 Output Gommon Mode Voltage 7 IN2 a Negative Input Summing Node 2 10 OUT Positive 0 Connection 8 2 Feedback Pin 2 11 OUT Negative Output for Load Connection 9 10 Vs2 Positive Supply Voltage 2 12 PD Power Down Pin 11 Output Common Mode Voltage 2 13to16 Vs Negative Supply Voltage 12 OUT2 Positive Output 2 13 OUT2 Negative Output 2 14 PD2 Power Down Pin 2 15 16 Vs2 Negative Supply Voltage 2 17 1 Output Common Mode Voltage 1 18 OUT1 Positive Output 1 19 OUT1 Negative Output 1 20 Power Down Pin 1 21 22 Vsi Negative Supply Voltage 1 23 FB1 Negative Output Feedback Pin 1 24 IN1 Positive Input Summing Node 1 Rev 0 Page 8 of 28 ADA4938 1 ADA4938 2 TYPICAL PERFORMANCE CHARACTERISTICS 25 C Vs 5 V Vs 5 V 0 V Rr
9. Response Vour 0 1 V Figure 23 Large Signal Frequency Response 1 0 1 5 0 9 14 0 8 13 0 7 12 0 6 1 1 g 05 1 0 8 04 0 9 gt 03 0 8 lt 02 97 O 0 1 1 056 o z 05 N 0 1 lt 04 lt 0 2 9 03 I 2 0 2 0 4 0 1 05 0 0 6 0 1 07 Ru am 1 0 02 RL dm 1 0 8 RL dm 1000 0 3 RL am 1000 09 R 2000 0 4 R 2000 210 L dm i 205 1 dm 1 10 100 1000 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz Figure 21 0 1 dB Flatness Response for Various Loads ADA4938 1 Figure 24 0 1 dB Flatness Response for Various Loads ADA4938 2 Vour 0 1 V p p 0 1 V p p Rev 0 Page 11 of 28 ADA4938 1 ADA4938 2 40 2 Vs 5V HD2 5V HD3 Vs 5V so 777 HD3 tv HD2 Vs 5 7 HD2 5 Vs 5V HD3 5V 60 8 8 5 70 5 5 80 5 5 5 ip 90 a a 100 110 120 0 1 2 3 4 5 6 7 8 9 8 FREQUENCY MHz am V 8 Figure 25 Harmonic Distortion vs Frequency and Supply Voltage Figure 28 Harmonic Distortion vs Vour and Supply Voltage HD2 1kO 1kO HD2 2000 R 2000 HD2 R 1000 HD3 R 1000 DISTORTION dBc DISTORTION dBc
10. Slew Rate Vout 2 V p p 4700 V us Overdrive Recovery Time 5 V to 0 V step G 2 4 ns NOISE HARMONIC PERFORMANCE Second Harmonic Vour 2 V p p 10 MHz 106 dBc 2 V p p 50 MHz 82 dBc Third Harmonic Vour 2 V p p 10 MHz 109 dBc 2 V p p 50 MHz 82 dBc IMD f 30 0 MHz f 30 1 MHz 89 dBc IP3 30 MHz Ream 100 Q 45 Input Voltage Noise f 10 MHz 2 6 2 Noise Figure G 244 f 10 MHz 15 8 dB Input Current Noise 10 MHz 4 8 pA VHz Crosstalk ADA4938 2 f 100 MHz INPUT CHARACTERISTICS i Offset Voltage Vos dm Vout dm 2 VpiN Vom 1 4 mV to Tmax Variation 4 uV C Input Bias Current 18 13 to Tmax Variation 0 01 Input Resistance Differential 6 Common mode 3 MO Input Capacitance 1 pF Input Common Mode Voltage Vs 0 3 to V TVs 1 6 CMRR AVour dm cm AVi 1 V f 1 MHz 75 OUTPUT CHARACTERISTICS Output Voltage Swing Maximum AVour single ended output Vs 1 2 to V 1 2 Linear Output Current Per amplifier 95 mA Output Balance Error cm AVour AVout 1 V f 10 MHz 60 dB Rev 0 Page 3 of 28 ADA4938 1 ADA4938 2 Table 2 to OUT Performance Parameter Conditions Min Typ Max Unit Vocm DYNAMIC PERFORMANCE 3 dB Bandwidth 230 MHz Slew Rate Vin 3 4 V to 43 4 V 25 to 75 1700 V us Input Voltage Noise
11. X N 41 h 6 G ELI G 2 N G 43 16 M G 5 12 1 10 100 1000 FREQUENCY MHz Figure 18 Large Signal Response for Various Gains Rr 402 06592 116 ADA4938 1 ADA4938 2 6 6 3 3 a a 5 5 w ni gt 3 NN 3 N by 8 8 N VIN d A M d p B7 OK lt MI M 9 _ G 1 N 9 G 1 Y G 2 3 6 2 G 3 16 NA G 3 16 M 6 5 G 5 12 12 2 1 10 100 1000 t 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz 8 Figure 19 Small Signal Frequency Response for Various Gains Rr 402 Figure 22 Large Signal Frequency Response for Various Gains Rr 402 Vs 5 0 1 Vp p Vs 5V 3 0 3 m m z z lt lt O 6 o 1 9 Vs 5V Vs 5V Vs 5 vs 5V 12 5 1 10 100 1000 1 10 100 1000 FREQUENCY MHz 8 2 5 Figure 20 Vout Small Signal Frequency
12. and prevents peaking of the response of the amplifier at high frequencies The thermal resistance is specified for the device including the exposed pad soldered to a high thermal conductivity 4 layer circuit board as described in EIA JESD 51 7 The exposed pad is electrically isolated from the device therefore it may be connected to a ground plane using vias Examples of the thermal attach pad and via structure for the ADA4938 1 are shown in Figure 66 and Figure 67 06592 008 Figure 65 Ground and Power Plane Voiding in Vicinity of Rr and Rc The power supply pins should be bypassed as close to the device as possible and directly to a nearby ground plane High frequency ceramic chip capacitors should be used It is recommended that two parallel bypass capacitors 1000 pF and 0 1 uF be used for each supply The 1000 pF capacitor should be placed closer to the device Further away low frequency bypassing should be provided using 10 uF tantalum capacitors from each supply to ground Signal routing should be short and direct to avoid parasitic effects Wherever complementary signals exist a symmetrical layout should be provided to maximize balanced performance When routing differential signals over a long distance PCB traces should be close together and any differential wiring should be twisted such that loop area is minimized Doing this reduces radiated energy and makes the circuit less susceptible to interference
13. determines the closed loop gain of the amplifier The ADA4938 is fabricated using the Analog Devices Inc proprietary third generation high voltage XFCB process enabling it to achieve very low levels of distortion with an input voltage noise of only 2 6 nV VHz The low dc offset and excellent dynamic performance of the ADA4938 make it well suited for a wide variety of data acquisition and signal processing applications Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAMS 06592 001 18 OUT1 17 16 Vs2 15 Vso 14 PD2 13 OUT2 9 AN 8 TEE 28 gt 8 Figure 2 ADAJe38 Functional Block Diagram 50 G 2 Vo am 5V G 2 Vo am 32V 60 G 2 Vo dm 2V p p 6 2 Vo am 1V M 70 y 2 80 8 20 4 P 100 r I 4 110 a a 4 2 120 130 10 1
14. mode voltage and the voltage applied to can also be assumed to be zero Starting from these two assumptions any application circuit can be analyzed Table 9 Output Noise Voltage Density Calculations SETTING THE CLOSED LOOP GAIN The differential mode gain of the circuit in Figure 56 can be determined by dm E R Vy dm RG This assumes the input resistors Rc and feedback resistors Rr on each side are equal ESTIMATING THE OUTPUT NOISE VOLTAGE The differential output noise of the ADA4938 can be estimated using the noise model in Figure 57 The input referred noise voltage density vi is modeled as a differential input and the noise currents inn and appear between each input and ground The noise currents are assumed to be equal and produce a voltage across the parallel combination of the gain and feedback resistances vscw is the noise voltage density at the pin Each of the four resistors contributes Table 9 summarizes the input noise sources the multiplication factors and the output referred noise density terms VnRG1 R VnRF1 06592 005 Figure 57 ADA4938 Noise Model Input Noise Output Output Noise Input Noise Contribution Input Noise Term Voltage Density Multiplication Factor Voltage Density Term Differential Input VnIN VniN Gn Vno1 Gn Vnin Inverting Input nin inn X GN Vno2 Gnlinn Rea Re2 Noninverting Input in
15. 0 V us Overdrive Recovery Time 2 5 V to step G 2 4 ns NOISE HARMONIC PERFORMANCE Second Harmonic Vour 2 V p p 10 MHz 110 dBc Vour 2 V p p 50 MHz 79 dBc Third Harmonic Vour 2 V p p 10 MHz 100 dBc Vout 2 V p p 50 MHz 79 dBc Input Voltage Noise f 10 MHz 2 6 2 Noise Figure G 4 10 MHz 15 8 Input Current Noise f 10 MHz 4 8 pA VHz Crosstalk ADA4938 2 f 100 MHz 85 INPUT CHARACTERISTICS Offset Voltage Vos dm 2 2 5 V 1 4 to Tmax variation 4 uV C Input Bias Current 18 uA Tun to Thx variation 0 01 Input Resistance Differential 6 MO Common mode 3 MO Input Capacitance 1 pF Input Common Mode Voltage Vs 0 3 to V TVs 1 6 CMRR AVout dm AVin cm AVin 1 V 80 dB OUTPUT CHARACTERISTICS Output Voltage Swing Maximum AVour single ended output Vs 1 2 to Vs 1 2 Linear Output Current Per amplifier 95 mA Output Balance Error cm AVour AVour dm 1 V 60 dB Rev 0 Page 5 of 28 ADA4938 1 ADA4938 2 Table 4 to OUT Performance Parameter Conditions Min Typ Max Unit Vocm DYNAMIC PERFORMANCE 3 dB Bandwidth 400 MHz Slew Rate Vin 1 6 V to 3 4 V 25 to 75 1700 V us Input Voltage Noise RTI 7 5 nV 4Hz INPUT CHARACTERISTICS Input Voltage Range Vs 1 3 to V TVs 1 3 Input Resistance 10 kQ Input Offset Volta
16. 00 FREQUENCY MHz 06592 Figure 3 SFDR vs Frequency and Output Voltage The ADA4938 1 single amplifier is available in a Pb free 3 mm x 3 mm 16 lead LFCSP The ADA4938 2 dual amplifier is available in a Pb free 4 mm x 4 mm 24 lead LFCSP The pinouts have been optimized to facilitate layout and minimize distortion The parts are specified to operate over the extended industrial temperature range of 40 C to 85 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2007 Analog Devices Inc rights reserved ADA4938 1 ADA4938 2 TABLE OF CONTENTS apas aaa 1 Applications mper tite ete Heri e AE AR aT 1 General edet 1 Functional Block 1 Revision HIStory eee au qus 2 Sp cifications eese 3 Dual Supply Operation a 3 Single Supply Operation seen 5 Absolute Maximum Ratings a a 7 Thermal Resistance ERI ee 7 ESD Caution aerae 7 Pin Configurations and Function Descriptions 8 Typical Performance Characteristics 9 o ome ence 4 27 Operational Description asss 18 Definition oft Terms 18 REVISION HISTORY 11 07 Revision 0 Initial V
17. 61 9 Re Re 200 G 1 Ri am 1 unless otherwise noted All measurements were performed with single ended input and differential output unless otherwise noted For gains other than G 1 values for Rr and Rc are shown in Table 11 3 Z lt lt d m lt lt Z gt 2 2 100 100 FREQUENCY MHz 8 FREQUENCY MHz Figure 7 Small Signal Frequency Response for Various Gains Vout 0 1 V Figure 10 Large Signal Frequency Response for Various Gains 1 T t lt lt 8 100 2 FREQUENCY MHz 8 FREQUENCY MHz 8 Figure 8 Small Signal Response for Various Supplies Vour 0 1 V p p Figure 11 Large Signal Response for Various Supplies m m Z Z z lt lt al a lt lt a 2 2 40 C 40 25 25 85 85 C 10 100 FREQUENCY MHz FREQUENCY MHz Figure 9 Small Signal Frequency Response for Figure 12 Large Signal Frequency Response for Various Temperatures Various Temperatures Vour 0 1 V p
18. ANALOG DEVICES Ultralow Distortion Differential ADC Driver ADA4938 1 ADA4938 2 FEATURES Extremely low harmonic distortion 106 dBc HD2 10 MHz 82 dBc HD2 50 MHz 109 dBc HD3 10 MHz 82 dBc HD3 50 MHz Low input voltage noise 2 6 nV VHz High speed 3 dB bandwidth of 1000 MHz G 1 Slew rate 4700 V us 0 1 dB gain flatness to 150 MHz Fast overdrive recovery of 4 ns 1 mV typical offset voltage Externally adjustable gain Differential to differential or single ended to differential operation Adjustable output common mode voltage Wide supply voltage range 5 V to 5 V Single or dual amplifier configuration available APPLICATIONS ADC drivers Single ended to differential IF and baseband gain blocks Differential buffers Line drivers GENERAL DESCRIPTION The ADA4938 is a low noise ultralow distortion high speed differential amplifier It is an ideal choice for driving high performance ADCs with resolutions up to 16 bits from dc to 27 MHz or up to 12 bits from dc to 74 MHz The output common mode voltage is adjustable over a wide range allowing the ADA4938 to match the input of the ADC The internal common mode feedback loop also provides exceptional output balance as well as suppression of even order harmonic distortion products Full differential and single ended to differential gain configurations are easily realized with the ADA4938 A simple external feedback network of four resistors
19. RTI 7 5 nV 4Hz INPUT CHARACTERISTICS Input Voltage Range Vs 1 3 to V TVs 1 3 Input Resistance 10 kQ Input Offset Voltage Vos cm Vout Voin 3 mV Input Bias Current 0 5 uA Vocm CMRR AVour am AVocm AVocm 1 V 81 Gain AVout 1 V 0 95 1 00 1 05 V A POWER SUPPLY Operating Range 4 5 11 V Quiescent Current Per amplifier 37 40 mA to Variation 40 Powered down 2 0 3 0 mA Power Supply Rejection Ratio AVout am AVs 1 V 80 dB POWER DOWN PD PD Input Voltage Powered down 2 5 V Enabled 23 V Turn Off Time 1 us Turn On Time x 1 200 ns PD Bias Current i i Enabled PD 54 Disabled PD 5V 760 OPERATING TEMPERATURE RANGE 40 85 Rev 0 Page 4 of 28 ADA4938 1 ADA4938 2 SINGLE SUPPLY OPERATION 25 C Vs 5 V Vs 0 V Vs 2 Rr 61 9 Re Re 200 G 1 Ri am 1 unless otherwise noted All specifications refer to single ended input and differential output unless otherwise noted For gains other than 1 values for Rr and are shown in Table 11 Table 3 Dis to OUT Performance Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth Vout 0 1 V p p 1000 MHz Bandwidth for 0 1 dB Flatness Vour 2 V p p 150 MHz Large Signal Bandwidth 2 V p p 750 MHz Slew Rate Vour 2V p p 390
20. als Also like an op amp the ADA4938 has high input impedance and low output impedance Two feedback loops are employed to control the differential and common mode output voltages The differential feedback set with external resistors controls only the differential output voltage The common mode feedback controls only the common mode output voltage This architecture makes it easy to set the output common mode level to any arbitrary value It is forced by internal common mode feedback to be equal to the voltage applied to the input without affecting the differential output voltage The ADA4938 architecture results in outputs that are highly balanced over a wide frequency range without requiring tightly matched external components The common mode feedback loop forces the signal component of the output common mode voltage to zero which results in nearly perfectly balanced differential outputs that are amplitude and are exactly 180 apart in phase ANALYZING AN APPLICATION CIRCUIT The ADA4938 uses open loop gain and negative feedback to force its differential and common mode output voltages in such a way as to minimize the differential and common mode error voltages The differential error voltage is defined as the voltage between the differential inputs labeled IN and IN see Figure 56 For most purposes this voltage can be assumed to be zero Similarly the difference between the actual output common
21. eferenced Input DC Coupled Rs 50 See Figure 59 Common Mode Swing at IN IN V Overall Noise Vs 10V Vs 0V Vs 5V Vs 5V Nominal Re Ra Rr Rinse Re Gain Density Vout am 2 0 V Vout dm 2 0 V Gain V V Q Q Q Q Q V V nV VHz Vom 2 5V Vom 3 5V 0 2 0V 1 200 200 60 4 267 226 0 9 6 21 1 00 to 1 50 1 30 to 200 0 25 to 0 25 0 75 to 1 25 2 402 200 60 4 P 226 F8 j 9 8 0 66 to 1 00 1 00 07 33 0 17 to 0 17 0 50 to 0 83 3 16 402 127 66 5 205 158 25 11 8 0 4846 072 07216099 20 12 to 0 12 0 36 to 0 60 5 402 80 6 768 138 110 3 6 14 7 0 33 to 0 50 0 50 to 0 67 0 08to 0 08 0 25 to 0 42 2 Rai Rrs ncludes effects of termination match Rev 0 Page 22 of 28 ADA4938 1 ADA4938 2 LAYOUT GROUNDING AND BYPASSING As a high speed device the ADA4938 is sensitive to the PCB environment in which it operates Realizing its superior performance requires attention to the details of high speed PCB design The first requirement is a solid ground plane that covers as much of the board area around the ADA4938 as possible However the area near the feedback resistors Rr gain resistors and the input summing nodes should be cleared of all ground and power planes see Figure 65 Clearing the ground and power planes minimizes any stray capacitance at these nodes
22. ersion Theory of OpeFatloDi e ee ttes 19 Analyzing an Application Circuit sse 19 Setting the Closed Loop Gain seen 19 Estimating the Output Noise Voltage sss 19 The Impact of Mismatches in the Feedback Networks 20 Calculating the Input Impedance of an Application Circuit 20 Input Common Mode Voltage Range in Single Supply Applicat eee eee I 20 Terminating a Single Ended Input sss 21 Setting the Output Common Mode Voltage 21 Layout Grounding and Bypassing sse 23 High Performance ADC Driving sse 24 Outline Dimensions Ordering Guide ose u u uuu i iii 25 Rev 0 Page 2 of 28 ADA4938 1 ADA4938 2 SPECIFICATIONS DUAL SUPPLY OPERATION Ta 25 C Vs 5 V Vs 5 V 0 V Rr 61 9 Re 200 G 1 Ri am 1 unless otherwise noted All specifications refer to single ended input and differential output unless otherwise noted For gains other than G 1 values for Rr and are shown in Table 11 Table 1 Dis to OUT Performance Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth Vout 0 1 V p p 1000 MHz Bandwidth for 0 1 dB Flatness Vout 2 V p p 150 MHz Large Signal Bandwidth Vour 2 V p p 800 MHz
23. ge Vos cm Vout cm VpIN Von 2 5 V 3 Input Bias Current 0 5 CMRR AVour dm AVocm AVocm 1 V 89 Gain AVout cm AVocm 1 V 0 95 1 00 1 05 V V POWER SUPPLY Operating Range 4 5 11 V Quiescent Current 34 36 5 mA to variation 40 uHA C Powered down 1 0 1 7 mA Power Supply Rejection Ratio AVour dm AVs 1 V 80 POWER DOWN PD PD Input Voltage Powered down 2 5 V Enabled 23 V Turn Off Time 1 us Turn On Time x 1 200 ns PD Bias Current i V Enabled 5 V 4 Disabled PD 0V 260 OPERATING TEMPERATURE RANGE 40 85 Rev 0 Page 6 of 28 ADA4938 1 ADA4938 2 ABSOLUTE MAXIMUM RATINGS Table 5 Parameter Rating Supply Voltage 12V Power Dissipation See Figure 4 Storage Temperature Range 65 C to 125 C Operating Temperature Range 40 C to 85 C Lead Temperature Soldering 10 sec 300 C Junction Temperature 150 C Stresses above those listed under Absolute Maximum Rating may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE is specified for the device including exposed pad soldered to a h
24. igh thermal conductivity 4 layer circuit board as described in EIA JESD 51 7 The exposed pad is not electrically connected to the device It is typically soldered to a pad on the PCB that is thermally and electrically connected to an internal sound plane I Table 6 Thermal Resistance Unit 16 Lead LFCSP Exposed Pad 95 C W 24 Lead LFCSP Exposed Pad 65 C W Maximum Power Dissipation The maximum safe power dissipation in the ADA4938 package is limited by the associated rise in junction temperature Tj on the die At approximately 150 C which is the glass transition temperature the plastic changes its properties Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die permanently shifting the parametric performance of the ADA4938 Exceeding a junction temperature of 150 C for an extended period can result in changes in the silicon devices potentially causing failure The power dissipated in the package Pp is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive The quiescent power is the voltage between the supply pins Vs times the quiescent current Is The power dissipated due to the load drive depends upon the particular application The power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device RMS voltages a
25. mpedance of the 50 source and the termination resistor driving the noninverting input The signal generator has a symmetric ground referenced bipolar output The pin of the ADA4938 is connected to the CML pin of the AD9246 to set the output common mode level at the appropriate point A portion of this is fed back to the summing nodes biasing IN and IN at 0 55 V For common mode voltage of 0 9 V each ADA4938 output swings between 0 4 and 1 4 V providing a 2 V differential output The output is dc coupled to a single pole low pass filter The filter reduces the noise bandwidth oftheamplifier and provides some level 1 the switched pacitor inputs of the ADC The AB924648 Set for a 2 V p P fatf scale input by connecting the SENSE pin to AGND The inputs of the AD9246 are biased at 1 V by connecting the CML output as shown in Figure 69 5V A 3 3V A 3 3V D 06592 054 Figure 68 ADA4938 Driving an AD9446 16 Bit 80 MSPS ADC 2000 omo ra Q 06592 056 Figure 69 ADA4938 Driving an AD9246 a 14 Bit 125 MSPS ADC Rev 0 Page 24 of 28 ADA4938 1 ADA4938 2 OUTLINE DIMENSIONS 0 60 MAX 0 30 PIN 1 INDICATOR 12 MAX gt 1 00 F 0 85 0 80 2 99 gt 0 02 NOM SEATING 0 30 PLANE 023 0 20 REF COMPLIANT TO JEDEC STANDARDS MO 220 VEED 2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 70 16 Lead Lead Frame Chip Scale Package LFCSP VO
26. nd currents must be used in these calculations Airflow increases heat dissipation which effectively reducing In addition more metal directly in contact with the package leads exposed pad from metal traces through holes ground and power planes reduces the Figure 4 shows the maximum safe power dissipation in the package vs the ambient temperature for the 16 lead LFCSP 95 C W and the 24 lead LFCSP 65 C W JEDEC standard 4 layer board 3 5 3 0 2 5 4938 2 2 0 1 5 1 0 MAXIMUM POWER DISSIPATION W L 0 5 0 40 30 20 10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE 06592 103 Figure 4 Maximum Power Dissipation vs Temperature for a 4 Layer Board ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 7 of 28 ADA4938 1 ADA4938 2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS IN1 18 0011 Sa FB1 17 Vs1 ADA4938 2 116 Vs2 w ADA493844 our HESS EE zn 3 IN2 13 OUT2 FB 4 Notto Scale 19 Vocy Figure 5
27. p Rev 0 Page 9 of 28 ADA4938 1 ADA4938 2 NORMALIZED GAIN dB 1000 FREQUENCY MHz Figure 13 Small Signal Frequency Response for Various Loads Vour 0 1 V p p a lt E lt amp 6 2 G 3 16 6 5 1 10 100 1000 FREQUENCY MHz Figure 14 Small Signal Frequency Response for Various Gains Vs 5 V 0 1 Vp p a lt E lt amp 1 10 100 1000 FREQUENCY MHz 06592 111 06592 112 06592 113 NORMALIZED GAIN dB NORMALIZED GAIN dB R 1 0 R 1000 R 2000 1000 FREQUENCY MHz Figure 16 Large Signal Frequency Response for Various Loads 1 2 G 3 16 5 100 1000 FREQUENCY MHz 06592 114 06592 115 Figure 17 Large Signal Frequency Response for Various Gains Vs 5 V Figure 15 Small Signal Response for Various Gains Rr 402 0 1 V p p Rev 0 Page 10 of 28 NORMALIZED GAIN dB 6 3 0 3
28. puts For an unbalanced single ended input signal see Figure 59 the input impedance is 06592 007 Figure 59 ADA4938 Configured for Unbalanced Single Ended Input The input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common mode signal partially bootstrapping the voltage across the input resistor Rc INPUT COMMON MODE VOLTAGE RANGE IN SINGLE SUPPLY APPLICATIONS The ADA4938 is optimized for level shifting ground referenced input signals As such the center of the input common mode range is shifted approximately 1 V down from midsupply The input common mode range at the summing nodes of the amplifier is from 0 3 V above Vs to 1 6 V below Vs To avoid clipping at the outputs the voltage swing at the IN and IN terminals must be confined to these ranges Rev 0 Page 20 of 28 ADA4938 1 ADA4938 2 TERMINATING A SINGLE ENDED INPUT Using an example with an input source of 2 V a source resistance of 50 Q and an overall gain of 1 V V four simple steps must be followed to terminate a single ended input to the ADA4938 1 The input impedance is calculated using the formula R 200 Re 500 2670 2x R R 2x 200 200 Vo 06592 081 2000 Figure 60 Single Ended Input Impedance 2 To provide a 50 termination for the source the Re
29. re of how well differential signals are matched in amplitude and are exactly 180 apart in phase Balance is most easily determined by placing a well matched resistor divider 06592 004 Figure 56 Circuit Definitions Differential Voltage between the differential voltage nodes and comparing the The differential voltage is the difference between two node magnitude of the signal at the midpoint of the divider with voltages For example the output differential voltage or the magnitude of the differential signal By this definition equivalently output differential mode voltage is defined as output balance is the magnitude of the output common mode voltage divided by the magnitude of the output differential Vout V ovr mode voltage where V our and refer to the voltages at the OUT and OUT terminals with respect to a common reference Output Balance Error OUT dm TY DII C 0 18 28 ADA4938 1 ADA4938 2 THEORY OF OPERATION The ADA4938 differs from conventional op amps in that it has two outputs whose voltages move in opposite directions Like an op amp it relies on open loop gain and negative feedback to force these outputs to the desired voltages The ADA4938 behaves much like a standard voltage feedback op amp and makes it easier to perform single ended to differential conversions common mode level shifting and amplifications of differential sign
30. rential mode gain vari s proportionately to the feedback mismatch but the output balance is unaffected As well as causing a noise contribution from ratio matching errors in the external resistors result in a degradation of the ability of the circuit to reject input common mode signals much the same as for a four resistor difference amplifier made from a conventional op amp In addition if the dc levels of the input and output common mode voltages are different matching errors result in a small differential mode output offset voltage When G 1 with a ground referenced input signal and the output common mode level set to 2 5 V an output offset of as much as 25 mV 1 of the difference in common mode levels can result if 1 tolerance resistors are used Resistors of 1 tolerance result in a worst case input CMRR of about 40 dB a worst case differential mode output offset of 25 mV due to 2 5 V level shift and no significant degradation in output balance error CALCULATING THE INPUT IMPEDANCE OF AN APPLICATION CIRCUIT The effective input impedance of a circuit depends on whether the amplifier is being driven by a single ended or differential signal source For balanced differential input signals as shown in Figure 58 the input impedance Ru am between the inputs Dm and Dn is simply Run am 2 x Re Rr ADA4938 Vs Vout 06592 006 Figure 58 ADA4938 Configured for Balanced Differential In
31. rnal resistor divider to obtain the desired 3 5 V output common mode One half of the common mode voltage is fed back to the summing nodes biasing IN and IN at 1 75 V For common mode voltage of 3 5 V each ADA4938 output swings between 2 7 V and 4 3 V providing a 3 2 V p p differential output The output of the amplifier is dc coupled to the AD throughya second order low pass filter 79 iy fiwq e cy oF50 MHz The filter reduces the noise bandwidth of the amplifier and isolates the driver outputs from the ADC inputs The AD9446 is configured for a 4 0 V p p full scale input by setting 1 R2 1 between the VREF pin and SENSE pin in Figure 68 tov SIGNAL GENERATOR The circuit in Figure 69 shows a simplified front end connection for an ADA4938 driving an AD9246 14 bit 125 MSPS ADC The AD9246 achieves its optimum performance when it is driven differentially The ADA4938 eliminates the need for a transformer to drive the ADC performs a single ended to differential conversion buffers the driving signal and provides appropriate level shifting for dc coupling The ADA4938 is configured with dual 5 V supplies and a gain of 2 V V for a single ended input to differential output The 76 8 termination resistor in parallel with the single ended input impedance of 137 provides a 50 dc termination for the source The additional 30 1 120 total at the inverting input balances the parallel dc i
32. sistor Rr is calculated such that 50 Q 819 OT Vo 06592 082 2000 Figure 61 Adding Termination Resistor 3 To compensate for the imbalance of the gain resistors a correction resistor Rrs is added in series with the inverting input gain resistor Rc Rrs is equal to the Thevenin equivalent of the source resistance Rs Rr Rs RTH 06592 083 Figure 62 Calculating Thevenin Equivalent Rrs Rs Rr 27 4 Q Note that Vra is not equal to Vs 2 which would be the case if the amplifier circuit did not affect the termination 27 40 2000 V Vocm RL 097 06592 084 2000 Figure 63 Balancing Gain Resistor Rc 4 Finally the feedback resistor is recalculated to adjust the output voltage to the desired level a make the output voltage Vo 1 V Rr is calculated using R Vo x Ro ROO 7 1 1 b To get the overall gain back to 1 V V Vo Vs 2 V Rr should be Re Vo x Re 2200 279 as 1 1 06592 085 Figure 64 Complete Single Ended to Differential System SETTING THE OUTPUT COMMON MODE VOLTAGE The pin of the ADA4938 is internally biased at a voltage approximately equal to the midsupply point average value of the voltages on and Relying on this internal bias results in an output common mode voltage that is within about 100 mV of the expected value In cases where more accurate con
33. trol of the output common mode level is required it is recommended that an external source or resistor divider 10 or greater resistors be used It is also possible to connect the input to a common mode level CML output of an ADC However care must be taken to assure that the output has sufficient drive capability The input impedance of the pin is approximately 10 If multiple ADA4938 devices share one reference output it is recommended that a buffer be used Rev 0 Page 21 of 28 ADA4938 1 ADA4938 2 Table 10 and Table 11 list several common gain settings associated resistor values input impedances and output noise densities for both balanced and unbalanced input configurations Also shown are the input common mode voltages under the given conditions for different Vocw settings for both a 10 V single supply and 5 V dual supplies Table 10 Differential Ground Referenced Input DC Coupled See Figure 58 Differential Common Mode Level at IN IN V Output Vs 10V Vs 0V Vs 5V Vs 5V Nominal Noise Density Vout am 2 0 V Vout am 2 0 V Gain V V Rr Q Rc Q Rin dm nV VHz 2 5 V 3 5 V Vocm 1 0 32 V 1 200 200 400 6 5 1 25 1 75 0 50 1 60 2 402 200 400 10 4 0 83 1 16 0 33 1 06 3 16 402 127 254 13 4 0 60 0 84 0 24 0 77 5 402 80 6 161 18 2 0 42 0 58 0 17 0 53 Table 11 Single Ended Ground R
34. ve X Ra Rr GN Vnos X 1 Input VnCM VnCM Gn Bi B2 Gn Bi 32 Gain Resistor Rc VnRGI 4kTRei 2 1 B2 Vnos Gn 1 B3 AKTRa Gain Resistor VnRG2 AkTRa 1 1 Vnos 1 B1 4KTRe2 2 Feedback Resistor Rr VnREI 2 1 Vno7 4kKTRe1 2 Feedback Resistor Rr2 VnRF2 AkTRej 2 1 Vnos 4kTRe 2 Rev 0 Page 19 of 28 ADA4938 1 ADA4938 2 Similar to the case of a conventional op amp the output noise voltage densities can be estimated by multiplying the input referred terms at IN and IN by the appropriate output factor where Gy XD 2 8 is the circuit noise gain 8 Rep the feedback factors Ry Re Re Rep When Ru Rai 1 2 B and the noise gain becomes Gy 1 R Note that the output noise from Vocm goes to zero in this case The total differential output noise density is the root sum square of the individual output noise terms 8 2 gt 1 1 THE IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS As previously mentioned even if the external feedback networks are mismatched the internal common mode feedback loop still forces the outputs to remain balanced The amplitudes of the signals at each output remain equal and 180 out ef phase The input to output diffe

ANALOG DEVICES ADA4938-1/ADA4938-2 handbook

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