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ANALOG DEVICES ADCMP607 handbook

1. 90 of PWin Output Skew Q to Q TpirFskew 5096 20 ps POWER SUPPLY Input Supply Voltage Range Vca 2 5 5 5 V Output Supply Voltage Range Vcco 2 5 5 5 V Positive Supply Differential ADCMP607 Vca Veco Operating 3 0 13 0 V Vca Vcco Nonoperating 6 6 V Positive Supply Current ADCMP606 lvccuvcco Vca Veco 2 5 V 11 17 5 21 mA Vca Vcco 5 5 V 16 20 5 26 mA Input Section Supply Current ADCMP607 lvca Ver 2 2 5V 0 5 1 1 1 5 mA Output Section Supply Current ADCMP607 Iveco a Meco 2 5 V 10 15 8 18 mA i i Iveco Vcto 515 V Te 1 25 mA Power Dissipation E Pp Va Veto t2 5 V 30 M 55 mW Pp Vca Veco 5 5 V 90 110 150 mW Power Supply Rejection Ratio PSRR Vca 2 5 V to 5V 50 dB Shutdown Mode lca Vca Vcco 2 5 V to 5 V 200 240 800 uA Shutdown Mode Icco Vca Vcco 2 5 V to 5 V 30 30 uA Vy 100 mV square input at 50 MHz Vcm 2 5 V Vca Veco 2 5 V unless otherwise noted Rev A Page 4 of 16 ADCMP606 ADCMP607 TIMING INFORMATION Figure 2 illustrates the ADCMP606 ADCMP607 latch timing relationships Table 2 provides definitions of the terms shown in Figure 2 LATCH ENABLE DIFFERENTIAL INPUT VOLTAGE Q OUTPUT Q OUTPUT UM Table 2 Timing Descriptions 05917 025 tg sFiqure2 System timing Diagram Symbol Timing Description tr Output fall time Amount of time required to transition from a high to a low output as measured at the 2096 and 8096 points tH
2. Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2006 2007 Analog Devices Inc All rights reserved ADCMP606 ADCMP607 TABLE OF CONTENTS Feat res bests re ioi s oe tei vo und 1 Application Information seen 10 Applications 25 E ter the ie tb ebore ER CURIE 1 Power Ground Layout and Bypassing ses 10 General Description eite teste aee eet deb etit o dete 1 CML Compatible Output Stage sse 10 Functional Block Diagram seen 1 Using Disabling the Latch Feature sss 10 REVISION History eese REIR p E RR NIE qns 2 Optimizing Performance essent 10 Specifications sostenuto cto Eel 3 Comparator Propagation Delay Dispersion 11 Electrical Characteristics seen 3 Comparator Hysteresis cssssseeeeeeessessessesseseeseeeesesesees 11 Timing Informatio sasasi asi 5 Crossover Bias Points sse 12 Absolute Maximum Ratings seen 6 Minimum Input Slew Rate Requirement 12 Thermal Resistance c eei p NERENS 6 Typical Application Circuits see 13 ESD Caution eee eee e etate 6 Outline Dimensions eorr enne 14 Pin Configurations and Function Descriptions 7 Ordering Guides i e erento titres ista 14 Ty
3. At this point normally VCCI 2 the direction of the bias current reverses and the measured offset voltages and currents change W The ADCMP606 ADCMP607 comparators slightly elaborate on this scheme Crossover points are found at approximately 0 6 V and 1 6 V common mode MINIMUM INPUT SLEW RATE REQUIREMENT With the rated load capacitance and normal good PCB design practice as discussed in the Optimizing Performance section these comparators should be stable at any input slew rate with no hysteresis Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators With additional capacitive loading or poor bypassing oscillation is observed This oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics in the package and PC board In many applications chattering is not harmful Rev A Page 12 of 16 ADCMP606 ADCMP607 TYPICAL APPLICATION CIRCUITS 2 5V TO 5V o 500 INPUT O o CML 2kQ OUTPUT O 05917 018 05917 022 05917 019 Figure 20 LVDS to CML Figure 23 Oscillator and Pulse Width Modulator 2 5V TO 5V CONTROL 05917 020 o CONTROL g CURRENT 10kO VOLTAGE 5 OV TO 2 5V 150kO 8 Figure 21 Current Controlled Oscillator Figure 24 Hysteresis Adjustment with Latch 2 5V 3V Veci O 05917 021 2 5V VEE Figure 22 Fake PECL Levels Using a Series Diode Figure 25
4. CP 12 1 GOH ADCMP607BCPZ WP 40 C to 125 C 12 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 12 1 GOH ZZ RoHS Compliant Part Rev A Page 14 of 16 ADCMP606 ADCMP607 NOTES ww BDI C conh ALI ADCMP606 ADCMP607 NOTES INN D ALI 2006 2007 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D05917 0 8 07 A DEVICES www analog com Rev A Page 16 of 16
5. Ground Referenced CML with 3 V Input Range 05917 024 Rev A Page 13 of 16 ADCMP606 ADCMP607 OUTLINE DIMENSIONS 220 2 00 1 80 1 35 ene jt 2 40 1 25 as ae 2 10 1 15 lei 2 3 1 80 PiN 1 7 E h tes BSC 1 30 BSC 1 00 0 40 Us 1 10 0 40 0 90 0 80 0 10 y 0 70 Ti Y 0 46 gt je 0 36 0 30 0 22 mE 0 10 MAX 030 le SEATING tez 0 26 PLANE 0 10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO 203 AB Figure 26 6 Lead Thin Shrink Small Outline Transistor Package SC70 KS 6 Dimensions shown in millimeters SE ATING oa QURREE COPLANARITY 18 COMPLIANT TO JEDEC STANDARDS MO 220 VEED 1 EXCEPT FOR EXPOSED PAD DIMENSION Figure 27 12 Lead Lead Frame Chip Scale Package LFCSP_VQ 3mm x 3 mm Body Very Thin Quad CP 12 1 Dimensions shown in millimeters ORDERING GUIDE Package Model Temperature Range Package Description Option Branding ADCMP606BKSZ R2 40 C to 125 C 6 Lead Thin Shrink Small Outline Transistor Package SC70 KS 6 GOS ADCMP606BKSZ RL 40 C to 125 C 6 Lead Thin Shrink Small Outline Transistor Package SC70 KS 6 GOS ADCMP606BKSZ REEL7 40 C to 125 C 6 Lead Thin Shrink Small Outline Transistor Package SC70 KS 6 GOS ADCMP607BCPZ R2 40 C to 125 C 12 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 12 1 GOH ADCMP607BCPZ R7 40 C to 125 C 12 Lead Lead Frame Chip Scale Package LFCSP_VQ
6. Voltage Figure 8 Hysteresis vs LE HYS Pin Current g g g y E z 1 E z n z i ui iv Ji 5 D o gt lt 2 50 100 150 200 250 300 350 400 450 500 550 600 650 id Spy PIN V 8 HYS RESISTOR kQ 8 Figure 6 Son Pin Current vs Voltage Figure 9 Hysteresis vs Hysteresis Resistor 10 3 5 8 6 3 0 g x a 2 u 25 p a o A o E E 2 amp 20 4 o v4 E E PROPAGATION DELAY FALL 8 7 o 4 0 LPROPAGATION DELAY RISE 1 0 05 0 05 10 15 20 25 30 35 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Vom AT Vec 2 5V a OVERDRIVE mV 3 Figure 7 Input Bias Current vs Input Common Mode Voltage Figure 10 Propagation Delay vs Input Overdrive Rev A Page 8 of 16 ADCMP606 ADCMP607 N DELAY F t a l W a o z i n 9 u ROPAGATION 02 02 06 10 14 18 22 26 30 8 Vom AT Vcc 2 5V 8 Figure 11 Propagation Delay vs Input Common Mode Voltage Figure 13 Output Waveform at Vcc 5 5 V 2 550V 05917 011 2 050V 1 000ns DIV Figure 12 Output Waveform at Vcc 2 5 V Rev A Page 9 of 16 ADCMP606 ADCMP607 APPLICATION INFORMATION POWER GROUND LAYOUT AND BYPASSING The ADCMP606 ADCMP607 comparators are very high speed devices Despite the low noise output stage it is essential to use proper high speed design techniques to achieve the specified per
7. input overdrive range of 5 mV to Vca 1 V Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate that is how far or how fast the input signal exceeds the switching threshold Propagation delay dispersion is a specification that becomes important in high speed time critical applications such as data communication automatic test and measurement and instru mentation It is also important in event driven applications such as pulse spectroscopy nuclear instrumentation and medical imaging Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed Figure 15 and Figure 16 The device dispersion is typically 2 3 ns as the overdrive varies from 10 mV to 125 mV This specification applies to both positive and negative signals because each device has very closely matched delays for positive going and negative going inputs as well as very low output skews 500mV OVERDRIVE INPUT VOLTAGE i n 10mV OVERDRIVI Vy t Vos Q Q OUTPUT 05917 014 Figure 15 Propagation Delay Overdrive Dispersion INPUT VOLTAGE Vy Vos 05917 015 Q Q OUTPUT Figure 16 Propagation Delay Slew Rate Dispersion COMPARATOR HYSTERESIS The addition of hysteresis to a comparator is often desirable in a noisy environment or when the differential input amplitudes are relatively small or slow moving Figure
8. 145 1 25 1 35 V Minimum Resistor Value Hysteresis 120 mV 55 75 110 kQ Latch Setup Time ts Vop 50 mV 1 5 ns Latch Hold Time tH Vop 50 mV 2 3 ns Latch to Output Delay tpLon trou Voo 50 mV 30 ns Latch Minimum Pulse Width tpi Vop 50 mV 25 ns SHUTDOWN PIN CHARACTERISTICS ADCMP607 Only Vin Comparator is operating 2 0 Veco V Vit Shutdown guaranteed 0 2 40 4 40 6 V lin Vin Vcco 6 6 uA li Vi OV 0 1 mA Sleep Time tsp 1096 output swing 1 ns Wake Up Time tu Vop 100 mV output valid 35 ns DC OUTPUT CHARACTERISTICS Vcco 25 V to 5 5 V Output Voltage High Level Von 50 Q terminate to Vcco Vcco 0 1 Veco 0 05 Veco V Output Voltage Low Level VoL 50 Q terminate to Vcco Veco 0 6 Veco 045 Vc o 03 V Output Voltage Differential 50 Q terminate to Vcco 300 400 500 mV Rev A Page 3 of 16 ADCMP606 ADCMP607 Parameter Symbol Conditions Min Typ Max Unit AC PERFORMANCE Rise Time Fall time tr tF 10 to 90 160 ps Vca Vcco 2 5 V to 5 5 V Propagation Delay tpo Vca Vcco 2 5 V to 5 5 V 1 2 ns Vop 50 mV Vca Veco 2 5 V 2 1 ns Vopn 10 mV Propagation Delay Skew Rising to Teinskew Vop 50 mV 40 ps Falling Transition Overdrive Dispersion 10 mV lt Voo lt 125 mV 2 3 ns Common Mode Dispersion 0 2 V lt Vau lt Vcc 0 2 V 150 ps Input Stage Bandwidth 750 MHz RMS Random Jitter RJ Vop 200 mV 0 5 V ns 2 ps Minimum Pulse Width PWwin Vca Veco 5 5 V 1 1 ns PWour
9. 17 shows the transfer function for a comparator with hysteresis As the input voltage approaches the threshold 0 V in this example from below the threshold region in a positive direction the comparator switches from low to high when the input crosses Vw 2 and the new switching threshold becomes Vu 2 The comparator remains in the high state until the new threshold Vu 2 is crossed from below the threshold region in a negative direction In this manner noise or feedback output signals centered on 0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by Vu 2 i i i i i m Vy 2 2 05917 016 Figure 17 Comparator Hysteresis Transfer Function The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input One limitation of this approach is that the amount of hysteresis varies with the output logic levels resulting in hysteresis that is not symmetric about the threshold The external feedback networkeean also introduce significant parasitics that feduc high so performance and induce oseillation in some Cases This ADCMP607 comparator offers a programmable hysteresis feature that can significantly improve accuracy and stability Connecting an external pull down resistor or a current source from the LE HYS pin to GND varies the amount of hysteresis in a predictable stable manner Leaving the LE HYS pin discon nect
10. ANALOG Rail to Rail Very Fast 2 5 V to 5 5 V DEVICES Single Supply CML Comparators ADCMP606 ADCMP607 FEATURES GENERAL DESCRIPTION Fully specified rail to rail at Vca 2 5 V to 5 5 V The ADCMP606 and ADCMP607 are very fast comparators Input common mode voltage from 0 2 V to Vca 0 2 V fabricated on XFCB2 an Analog Devices Inc proprietary CML compatible output stage process These comparators are exceptionally versatile and easy 1 25 ns propagation delay to use Features include an input range from Vex 0 5 V to 50 mW Q 2 5 V power supply Voca 0 2 V low noise CML compatible output drivers and Shutdown pin TTL CMOS compatible latch inputs with adjustable hysteresis Single pin control for programmable hysteresis and latch and or shutdown inputs ADCMP607 only Power supply rejection gt 60 dB 40 C to 125 C operation The devices offer 1 25 ns propagation delay with 2 5 ps rms random jitter RJ Overdrive and slew rate dispersion are typically less than 50 ps APPLICATIONS A flexible power supply scheme allows the devices to operate High speed instrumentation with a single 2 5 V positive supply and a 0 5 V to 2 7 V Clock and data signal restoration input signal range up to a 5 5 V positive supply with a 0 5 V Logic level shifting or translation to 5 7 V input signal range The ADCMP607 features split Pulse spectroscopy input output supplies with no sequencing restrictions to High speed line receivers supp
11. Minimum hold time Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs teon Input to output high delay Propagation delay measured from the time the input signal crosses the reference the input offset voltage to the 50 point of an output low to high transition te Input to output low delay Propagation delay measured from the time the input signal crosses the reference the input offset voltage to the 5096 point of an output high to low transition te Minimum latch enable pulse width Minimum time that the latch enable signal must be high to acquire an input signal change teLoH Latch enable to output high delay Propagation delay measured from the 5096 point of the latch enable signal low to high transition to the 5096 point of an output low to high transition teLoL Latch enable to output low delay Propagation delay measured from the 5096 point of the latch enable signal low to high transition to the 5096 point of an output high to low transition tr Output rise time Amount of time required to transition from a low to a high output as measured at the 20 and 80 points ts Minimum setup time Minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs Vop Voltage overdrive Difference between the input voltages V4 and Vs Rev A Pag
12. Q referenced to Veco The CML output stage is shown in the simplified schematic diagram in Figure 14 Each output is back terminated with 50 Q for best transmission line matching Veco 500 16mA 05917 013 GND Figure 14 Simplified Schematic Diagram of CML Compatible Output Stage If these high speed signals must be routed more than a centimeter then either microstrip or strip line techniques are required to ensure proper transition times and to prevent excessive output ringing and pulse width dependent propagation delay dispersion It is also possible to operate the outputs with the internal termination only if greater output swing is desired This can be especially useful for driving inputs on CMOS devices intended for full swing ECL and PECL or for generating pseudo PECL levels To avoid deep saturation of the outputs and resulting pulse dispersion Vcco must be kept above the specified minimum output low level see the Electrical Characteristics section The line length driven should be kept as short as possible USING DISABLING THE LATCH FEATURE The latch input is designed for maximum versatility It can safely be left floating or it can be driven low by any standard TTL CMOS device as a high speed latch In addition the pin can be operated as a hysteresis control pin with a bias voltage of 1 25 V nominal and an input resistance of approximately 70 kQ This allows the comparator hysteresis to be easily controlled by
13. e 5 of 16 ADCMP606 ADCMP607 ABSOLUTE MAXIMUM RATINGS Table 3 Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device This is a stress Supply Voltages rating only functional operation of the device at these or any Input Supply Voltage Vca to GND 0 5 V to 6 0V other conditions above those indicated in the operational Output Supply Voltage 0 5V to 6 0V section of this specification is not implied Exposure to absolute Vcco to GND maximum rating conditions for extended periods may affect Positive Supply Differential 6 0 V to 6 0V device reliability Vca Vcco Input Voltages THERMAL RESISTANCE Input Voltage 0 5 V to Vca 0 5 V Oya is specified for the worst case conditions that is a device Differential Input Voltage Vca 0 5 V soldered in a circuit board for surface mount packages Maximum Input Output Current 50 mA Table 4 Thermal Resistance Shutdown Control Pin Applied Voltage Son to GND 0 5 V to Vcco 0 5 V Package Type Bua unit Maximum Input Output Current 50 mA ADCMP606 6 Lead SC70 426 CWN Latch Hysteresis Control Pin ADCMP607 12 Lead LFCSP 62 KSAN Applied Voltage HYS to GND 0 5 V to Vcco 0 5 V Measurement in still air Maximum Input Output Current 50 mA Output Current 50 mA Temperature ESD CAUTION Operating Temperature Ambient 40 C to 125 C ESD electrostatic discharge sensitive device Operat
14. ed or driving this pin high removes hysteresis The maximum hysteresis that can be applied using this pin is approximately 160 mV Figure 18 illustrates typical hysteresis applied as a function of the external resistor value and Figure 7 illustrates typical hysteresis as a function of the current 400 a e HYSTERESIS mV N eo ES e eo a eo 0 50 100 150 200 250 300 350 400 450 500 550 600 650 HYS RESISTOR kO 05917 017 Figure 18 Hysteresis vs Ruys Control Resistor Rev A Page 11 of 16 ADCMP606 ADCMP607 The hysteresis control pin appears as a 1 25 V bias voltage seen through a series resistance of 70 kQ 20 throughout the hysteresis control range The advantages of applying hysteresis in this manner are improved accuracy improved stability reduced component count and maximum versatility An external bypass capacitor is not recommended on the LE HYS pin because it impairs the latch function and often degrades the jitter perform ance of the device As described in the Using Disabling the Latch Feature section hysteresis control need not compromise the latch function CROSSOVER BIAS POINTS In both op amps and comparators rail to rail inputs of this type have a dual front end design Certain devices are active near the Vcc rail and others are active near the Vr rail At some predeter mined point in the common mode range a crossover occurs
15. either a resistor or an inexpensive CMOS DAC Driving this pi high or floating the pin removes all hysteresis i Hysteresis control and latch mode can be used together if an open drain an open collector or a three state driver is con nected parallel to the hysteresis control resistor or current source Due to the programmable hysteresis feature the logic threshold of the latch pin is approximately 1 1 V regardless of Vcco OPTIMIZING PERFORMANCE As with any high speed comparator proper design and layout techniques are essential for obtaining the specified performance Stray capacitance inductance inductive power and ground impedances or other layout issues can severely limit performance and often cause oscillation Large discontinuities along input and output transmission lines can also limit the specified pulse width dispersion performance The source impedance should be minimized as much as is practicable High source impedance in combination with the parasitic input capacitance of the comparator causes an undesirable degradation in bandwidth at the input thus degrading the overall response Thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals higher impedances encourage undesired coupling Rev A Page 10 of 16 ADCMP606 ADCMP607 COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP606 ADCMP607 comparators are designed to reduce propagation delay dispersion over a wide
16. formance Because comparators are uncompensated amplifiers feedback in any phase relationship is likely to cause oscillations or undesired hysteresis Of critical importance is the use of low impedance supply planes particularly the output supply plane Vcco and the ground plane GND Individual supply planes are recommended as part of a multilayer board Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application It is also important to adequately bypass the input and output supplies Multiple high quality 0 01 uF bypass capacitors should be placed as close as possible to each of the Vcci and Vcco supply pins and should be connected to the GND plane with redundant vias At least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the Vccr and Vcco pins High frequency bypass capacitors should be carefully selected for minimum inductance and ESR Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies CML COMPATIBLE OUTPUT STAGE s Specified propagation delay dispefsidh Pebfotyhance cali be achieved by using proper transmission line terminations The outputs of the ADCMP606 and ADCMP607 are designed to drive 400 mV directly into a 50 Q cable or into transmission lines terminated using either microstrip or strip line techniques with 50
17. ing Temperature Junction 150 S rs Storage Temperature Range 65 C to 150 C patented or proprietary protection circuitry damage gt may ogcur om devices subjected to high energy ESD i i Avs Therefore proper si precautions should be taken to avoid performance degradation or loss of functionality Rev A Page 6 of 16 ADCMP606 ADCMP607 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADCMP607 iHs Leys Top view 8 Vee 34 ot to 7 Son 8 E j Figure 3 ADCMP606 Pin Configuration Figure 4 ADCMP607 Pin Configuration Table 5 ADCMP606 6 Lead SC70 Pin Function Descriptions Pin No Mnemonic Description 1 Q Noninverting Output Q is at logic high if the analog voltage at the noninverting input Vr is greater than the analog voltage at the inverting input Vw 2 Vee Negative Supply Voltage 3 Vp Noninverting Analog Input 4 VN Inverting Analog Input 5 Vco Vcco Input Section Supply Output Section Supply Shared pin 6 Q Inverting Output Q is at logic low if the analog voltage at the noninverting input Ve is greater than the analog voltage at the inverting input Vin 1 a Table 6 ADCMP607 12 Lead LFCSP Pin Function Descriptions i Pin No Mnemonic Description l 1 Vcco Output Section Supply 2 Vca Input Section Supply 3 Vee Negative Supply Voltage 4 Vp Noninverting Analog Input 5 Ve Negative Supply Voltage 6 VN Inverting Analog Input 7 Son Shu
18. ort a wide input signal range with independent output Threshold detection swing control and power savings Peak and ZerOncrossing s The CML compatible output stage is fully back matched for High speed trigger circuitry z a superior performance Be Comparator input stage offers robust Pulse width modulators i f j protection against large inputlbverdrive and the outputs do not Current voltage controlled Wis I phase reverse when the valid input signal range is exceeded On the ADCMP607 latch and programmable hysteresis features are also provided with a unique single pin control option The ADCMP606 is available in a 6 lead SC70 package and the ADCMP607 is available in a 12 lead LFCSP package Automatic test equipment ATE FUNCTIONAL BLOCK DIAGRAM V cco Vcci ADCMP607 ONLY O Vp NONINVERTING INPUT O Q OUTPUT ADCMP606 ADCMP607 O Q OUTPUT Vy INVERTING 6 INPUT O LE HYS INPUT ADCMP607 ONLY O Spy INPUT ADCMP607 ONLY 05917 001 Figure 1 Rev A Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of
19. pical Performance Characteristics sse 8 REVISION HISTORY 8 07 Rev 0 to Rev A Changes to Specifications Section sse 3 Changes to Table3 notet emt edd 6 Changes to Ordering Guide ss gre pr s 144 J 10 06 Revision 0 Initial Version r 1 Rev A Page 2 of 16 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Vca Vcco 2 5 V Ta 40 C to 125 C typical at TA 25 C unless otherwise noted ADCMP606 ADCMP607 Table 1 Parameter Symbol Conditions Min Typ Max Unit DC INPUT CHARACTERISTICS Voltage Range Ve VN Vea 2 5 V to 5 5 V 0 5 Vei 0 2 V Common Mode Range Vea 2 5 V to 5 5 V 0 2 Vei 0 2 V Differential Voltage Vca 2 5 V to 5 5 V Vca V Offset Voltage Vos 5 0 45 0 mV Bias Current Ip In 5 0 2 5 0 uA Offset Current 2 0 2 0 uA Capacitance Cp Cn 1 pF Resistance Differential Mode 0 1 V to Vca 200 700 kQ Resistance Common Mode 0 5 V to Vca 0 5 V 100 350 kQ Active Gain Av 85 dB Common Mode Rejection Ratio CMRR Vca 2 5 V Vcco 2 5 V 50 dB Vom 0 2 V to 2 7 V Vca 2 5 V Vcco 5 5 V 50 dB Hysteresis Ruvs co 0 1 mV LATCH ENABLE PIN CHARACTERISTICS ADCMP607 Only Vin Hysteresis is shut off 2 0 Veco V Vit Latefmode guaranteed 20 2 40 4 40 8 V lin Vii Vcco 6 6 uA li Vi 02v 0 7 0 1 mA HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Current sink 0 pA 1
20. tdown Drive this pin low to shut down the device 8 LE HYS Latch Hysteresis Control Bias with resistor or current for hysteresis adjustment drive low to latch 9 Vee Negative Supply Voltage 10 Q Inverting Output Q is at logic low if the analog voltage at the noninverting input Ve is greater than the analog voltage at the inverting input Vn if the comparator is in compare mode 11 Vee Negative Supply Voltage 12 Q Noninverting Output Q is at logic high if the analog voltage at the noninverting input Vr is greater than the analog voltage at the inverting input Vn if the comparator is in compare mode Heat Sink Vee The metallic back surface of the package is electrically connected to VEE It can be left floating because Paddle Pin 3 Pin 5 Pin 9 and Pin 11 provide adequate electrical connection It can also be soldered to the application board if improved thermal and or mechanical stability is desired Rev A Page 7 of 16 ADCMP606 ADCMP607 TYPICAL PERFORMANCE CHARACTERISTICS Vca Veco 2 5 V Ta 25 C unless otherwise noted 250 200 ad z lt E 150 o z w 2 5 ui 5 5 100 o gt lt 50 Es 0 E ki 0 2 4 6 8 10 12 14 16 18 7 LE HYS PIN V 8 LE HYS PIN CURRENT pA 8 Figure 5 LE HYS Pin Current vs

ANALOG DEVICES ADCMP607 handbook

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