ANALOG DEVICES ADCMP566 handbook(1)
Contents
1. cccessesssssessesssesesseesesseesseessesseenes 5 Comparator Hysteresis scessssssseeeeeesessessessesseseesessesesesees 10 ESD Ca ation vce sessed pr E E E ER 5 Minimum Input Slew Rate Requirement 10 Pin Configuration and Function Descriptions 6 Typical Application Circuits oc ceeesesseesessessessesseesseeseenes 11 Timing Information 0 esseesessesssessessessesssessesseessessessesseeseess 8 Typical Performance Characteristics 0 12 Application Information cscsesessesssesesseessessesseessessesseessesseens 9 Outline Dimensions snin a E E KET 14 Clock Timing RECOVELY sesesiisecsessassissseccscsssnoasesessecseesioeassvosesscdunbes 9 Ordering GUE sissies ccs scsssassvesnscidessusaderaicoasen ssschacedocascvcseastatenes 14 REVISION HISTORY Revision 0 Initial Version Rev 0 Page 2 of 16 ADCMP566 SPECIFICATIONS Table 1 ADCMP566 ELECTRICAL CHARACTERISTICS Vcc 5 0 V Ve 5 2 V Ta 25 C unless otherwise noted Parameter Symbol Condition Min Typ Max Unit DC INPUT CHARACTERISTICS See Note Input Common Mode Range Vem 2 0 3 0 V Input Differential Voltage 5 5 V Input Offset Voltage Vos 5 0 1 0 5 0 mV Input Offset Voltage Channel Matching 1 0 mV Offset Voltage Tempco DVos dr 10 0 uV C Input Bias Current lsc 10 24 42 uA Input Bias Current Tempco 10 0 nA C Input Offset Current 8 0 0 5 8 0 uA Input Capacitance Cin 0 75 pF Input Resistance Differential Mode 1002. 65 C to 150 C Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Rev 0 Page 5 of 16 ADCMP566 THERMAL CONSIDERATIONS The ADCMP566 LFCSP 32 lead package option has a Oja junction to ambient thermal resistance of 27 2 C W in still air we ESD SENSITIVE DEVICE ADCMP566 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 PIN 1 INA 2 INA 3 INDICATOR Vec 4 ADCMP566 weg TOP VIEW INR Not to Scale GND 8 NC NO CONNECT 03633 0 002 Figure 2 ADCMP566 Pin Configuration Table 3 ADCMP566 Pin Descriptions Pin No Mnemonic Function
3. 1 GND Analog Ground 2 INA Inverting analog input of the differential input stage for Channel A The inverting A input must be driven in conjunction with the noninverting A input 3 INA Noninverting analog input of the differential input stage for Channel A The noninverting A input must be driven in conjunction with the inverting A input 4 Vcc Positive Supply Terminal 5 Vcc Positive Supply Terminal 6 INB Noninverting analog input of the differential input stage for Channel B The noninverting B input must be driven in conjunction with the inverting B input 7 INB Inverting analog input of the differential input stage for Channel B The inverting B input must be driven in conjunction with the noninverting B input 8 GND Analog Ground 9 GND Analog Ground 10 LEB One of two complementary inputs for Channel B Latch Enable In the compare mode logic low the output will track changes at the input of the comparator In the latch mode logic high the output will reflect the input state just prior to the comparator s being placed in the latch mode LEB must be driven in conjunction with LEB 11 LEB One of two complementary inputs for Channel B Latch Enable In the compare mode logic high the output will track changes at the input of the comparator In the latch mode logic low the output will reflect the input state just prior to the comparator s being placed in the latch mode LEB must be driven in conjunction with LEB 12 NC No
4. 30 20 10 0 60 TEMPERATURE C Figure 18 Propagation Delay vs Temperature 10 20 30 40 50 60 70 80 90 0 Figure 19 Propagation Delay Error vs Overdrive Voltage 50 40 30 20 10 A Ael 0 0 2 0 4 0 6 0 8 1 0 1 2 OVERDRIVE VOLTAGE V 1 4 1 6 114 12 13 14 15 16 17 18 TIME ns Figure 20 Rise and Fall of Outputs vs Time PROPAGATION DELAY ps 03633 0 019 PROPAGATION DELAY ERROR ps 03633 0 020 03633 0 021 Rev 0 Page 13 of 16 239 238 ADCMP566 237 236 235 234 233 232 231 2 Figure 21 Propagation Delay vs Common Mode Voltage 1 0 1 2 INPUT COMMON MODE VOLTAGE V 2 15 4 15 6 15 8 15 PULSEWIDTH ns Figure 22 Propagation Delay Error vs Pulsewidth 03633 0 022 03633 0 023 ADCMP566 OUTLINE DIMENSIONS PIN 1 0 50 INDICATOR sse q E BOTTOM VIEW F 0 50 0 40 5 En 030 LC 0 05 MAX 0 02 NOM COPLANARITY 0 0 20 REF 0 08 PLANE COMPLIANT TO JEDEC STANDARDS MO 220 VHHD 2 Figure 23 32 Lead Lead Frame Chip Scale Package LFCSP CP 32 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADCMP566BCP 40 C to 85 C LFCSP 32 CP 32 Rev 0 Page 14 of 16 ADCMP566 Notes Rev 0 Page 15 of
5. noninverting input is greater than the analog voltage at the inverting input provided the comparator is in the compare mode See the LEA description Pin 30 for more information 28 GND Digital Ground 29 NC No Connect Leave pin unconnected 30 LEA One of two complementary inputs for Channel A Latch Enable In the compare mode logic high the output will track changes at the input of the comparator In the latch mode logic low the output will reflect the input state just prior to the comparator s being placed in the latch mode LEA must be driven in conjunction with LEA 31 LEA One of two complementary inputs for Channel A Latch Enable In the compare mode logic low the output will track changes at the input of the comparator In the latch mode logic high the output will reflect the input state just prior to the comparator s being placed in the latch mode LEA must be driven in conjunction with LEA 32 GND Analog Ground Rev 0 Page 7 of 16 ADCMP566 TIMING INFORMATION The timing diagram in Figure 3 shows the ADCMP566 compare LATCH ENABLE LATCH ENABLE DIFFERENTIAL INPUT VOLTAGE Q OUTPUT Q OUTPUT Figure 3 System Timing Diagram and latch features Table 4 describes the terms in the diagram Table 4 Timing Descriptions Symbol Timing Description tPoH Input to output Propagation delay measured from high delay the time the input signal crosses the reference the input offset
6. stray capacitance and inductance Poor layout or improper termination can also cause reflections on the transmission line further distorting the signal waveform A high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator amplifier proper design and layout techniques should be used to ensure optimal perform ance from the ADCMP566 The performance limits of high speed circuitry can easily be a result of stray capacitance improper ground impedance or other layout issues Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the ADCMP566 Source resistance in combination with equivalent input capacitance could cause a lagged response at the input thus delaying the output The input capacitance of the ADCMP566 in combination with stray capacitance from an input pin to ground could result in several picofarads of equivalent capacitance A combination of 3 kQ source resistance and 5 pF of input capacitance yields a time constant of 15 ns which is significantly slower than the sub 500 ps capability of the ADCMP566 Source impedances should be significantly less than 100 Q for best performance Sockets should be avoided due to stray capacitance and induc tance If proper high speed techniques are used the ADCMP566 should be free from oscillation when the comparat
7. voltage to the 50 point of an output low to high transition tPoL Input to output Propagation delay measured from low delay the time the input signal crosses the reference the input offset voltage to the 50 point of an output high to low transition tPLoH Latch enable Propagation delay measured from to output high the 50 point of the Latch Enable delay signal low to high transition to the 50 point of an output low to high transition teLoL Latch enable Propagation delay measured from to output low delay the 50 point of the Latch Enable signal low to high transition to the 50 point of an output high to low transition Vrer Vos tr 03633 0 003 Symbol Timing Description tH Minimum Minimum time after the negative hold time transition of the Latch Enable signal that the input signal must remain unchanged to be acquired and held at the outputs te Minimum Minimum time that the Latch latch enable Enable signal must be high to pulsewidth acquire an input signal change ts Minimum Minimum time before the setup time negative transition of the Latch Enable signal that an input signal change must be present to be acquired and held at the outputs tr Output rise Amount of time required to time transition from a low to a high output as measured at the 20 and 80 points tF Output fall Amount of time required to time transition from a high to a low output as measured at the 20 and 80 points Von Vo
8. 5 2 V Ta 25 C unless otherwise noted OFFSET VOLTAGE mV INPUT BIAS CURRENT uA TIME ps 30 25 20 15 10 0 2 5 1 5 0 5 0 5 1 5 2 5 3 5 NONINVERTING INPUT VOLTAGE INVERTING VOLTAGE 0 5V 2 0 1 8 Figure 12 Input Bias Current vs Input Voltage 20 0 20 40 60 80 TEMPERATURE C Figure 13 Input Offset Voltage vs Temperature 195 185 175 165 155 145 135 125 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE C Figure 14 Rise Time vs Temperature IN INPUT BIAS CURRENT uA 03633 0 013 HYSTERESIS mV 03633 0 014 TIME ps 03633 0 015 Rev 0 Page 12 of 16 22 8 22 6 60 50 TEMPERATURE C Figure 15 Input Bias Current vs Temperature 40 30 20 10 0 2 195 185 175 165 155 145 135 125 0 15 10 5 0 5 10 15 A LATCH LE LEB mV Figure 16 Hysteresis vs ALatch 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE C Figure 17 Fall Time vs Temperature 03633 0 016 03633 0 017 03633 0 018 PROPAGATION DELAY ps PROPAGATION DELAY ERROR ps OUTPUT RISE AND FALL V 242 240 238 236 234 232 230 228 226 40
9. The addition of hysteresis to a comparator is often useful in a noisy environment or where it is not desirable for the compara tor to toggle between states when the input signal is at the switching threshold The transfer function for a comparator with hysteresis is shown in Figure 5 If the input voltage approaches the threshold from the negative direction the comparator will switch from a 0 to a 1 when the input crosses Vu 2 The new switching threshold becomes Vu 2 The comparator will remain in a 1 state until the threshold Vu 2 is crossed coming from the positive direction In this manner noise centered on 0 V input will not cause the comparator to switch states unless it exceeds the region bounded by Vu 2 Positive feedback from the output to the input is often used to produce hysteresis in a comparator Figure 9 The major problem with this approach is that the amount of hysteresis varies with the output logic levels resulting in a hysteresis that is not symmetrical around zero Another method to implement hysteresis is generated by introducing a differential voltage between LATCH ENABLE and LATCH ENABLE inputs Figure 10 Hysteresis generated in this manner is independent of output swing and is symmetri cal around zero The variation of hysteresis with input voltage is shown in Figure 6 03633 0 005 Figure 5 Comparator Hysteresis Transfer Function 60 50 40 gt E 2 n 30
10. 16 ADCMP566 Notes 2003 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www ana l 0 g om ceases al DEVICES Rev 0 Page 16 of 16
11. ANALOG DEVICES Dual Ultrafast Voltage Comparator ADCMP566 FEATURES 250 ps propagation delay input to output 50 ps propagation delay dispersion Differential ECL compatible outputs Differential latch control Robust input protection Input common mode range 2 0 V to 3 0 V Input differential range 5 V ESD protection gt 3 kV HBM gt 200 V MM Power supply sensitivity gt 65 dB 200 ps minimum pulsewidth 5 GHz equivalent input rise time bandwidth Typical output rise fall of 165 ps APPLICATIONS High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers and signal restoration Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand held test instruments Zero crossing detectors Clock drivers Automatic test equipment Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM NONINVERTING INPUT O Q OUTPUT INVERTING INPUT O Q OUTPUT LATCH ENABL
12. Connect Leave pin unconnected 13 GND Digital Ground 14 QB One of two complementary outputs for Channel B QB will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input provided the comparator is in the compare mode See the LEB description Pin 11 for more information 15 QB One of two complementary outputs for Channel B QB will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input provided the comparator is in the compare mode See the LEB description Pin 11 for more information 16 GND Digital Ground 17 Vee Negative Supply Terminal 18 NC No Connect Leave pin unconnected 19 Vee Negative Supply Terminal 20 Vcc Positive Supply Terminal 21 Vcc Positive Supply Terminal Rev 0 Page 6 of 16 ADCMP566 Pin No Mnemonic Function 22 Vee Negative Supply Terminal 23 NC No Connect Leave pin unconnected 24 Vee Negative Supply Terminal 25 GND Digital Ground 26 QA One of two complementary outputs for Channel A QA will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input provided the comparator is in the compare mode See the LEA description Pin 30 for more information 27 QA One of two complementary outputs for Channel A QA will be at logic low if the analog voltage at the
13. EO O LATCH ENABLE INPUT INPUT 03633 0 001 Figure 1 GENERAL DESCRIPTION The ADCMP566 is an ultrafast voltage comparator fabricated on Analog Devices proprietary XFCB process The device features 250 ps propagation delay with less than 35 ps overdrive dispersion Overdrive dispersion a particularly important characteristic of high speed comparators is a measure of the difference in propagation delay under differing overdrive conditions A fast high precision differential input stage permits consis tent propagation delay with a wide variety of signals in the common mode range from 2 0 V to 3 0 V Outputs are complementary digital signals fully compatible with ECL 10 K and 10 KH logic families The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Q to 2 V A latch input is included which permits tracking track and hold or sample and hold modes of operation The ADCMP566 is available in a 32 lead LFCSP package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved ADCMP566 TABLE OF CONTENTS Specifications aori a R a E E ERE 3 Optimizing High Speed Performance cesesessseseeeseestesseene 9 Absolute Maximum RatingS ccccessessesesseessessesseesessessneseeseens 5 Comparator Propagation Delay Dispersion csseseseeees 9 Thermal Considerations
14. W W D gt 20 x 10 0 8 20 15 10 5 0 5 10 15 3 A LATCH LE LEB mV Figure 6 Comparator Hysteresis Transfer Function Using Latch Enable Input MINIMUM INPUT SLEW RATE REQUIREMENT As for all high speed comparators a minimum slew rate must be met to ensure that the device does not oscillate when the input crosses the threshold This oscillation is due in part to the high input bandwidth of the comparator and the parasitics of the package Analog Devices recommends a slew rate of 5 V s or faster to ensure a clean output transition If slew rates less than 5 V us are used then hysteresis should be added to reduce the oscillation Rev 0 Page 10 of 16 TYPICAL APPLICATION CIRCUITS OUTPUTS O O LATCH 20V ENABLE INPUTS ALL RESISTORS 509 03633 0 007 Figure 7 High Speed Sampling Circuits OUTPUTS O O LATCH 20v ENABLE INPUTS ALL RESISTORS 509 03633 0 008 Figure 8 High Speed Window Comparator OUTPUTS 2 0V ALL RESISTORS 509 03633 0 009 Figure 9 Hysteresis Using Positive Feedback Rev 0 Page 11 of 16 ADCMP566 _ 6 z OUTPUTS O HYSTERESIS VOLTAGE ALL RESISTORS 509 UNLESS OTHERWISE NOTED 03633 0 010 Figure 10 Hysteresis Using Latch Enable Input 5 2V 03633 0 011 Figure 11 How to Interface an ECL Output to an Instrument with a 50 Q to Ground Input ADCMP566 TYPICAL PERFORMANCE CHARACTERISTICS Vcc 5 0 V Ve
15. atching function is not used the LATCH ENABLE input should be grounded ground is an ECL logic high and the complementary input LATCH ENABLE should be tied to 2 0 V This will disable the latching function Occasionally one of the two comparator stages within the ADCMP566 will not be used The inputs of the unused comparator should not be allowed to float The high internal gain may cause the output to oscillate possibly affecting the comparator that is being used unless the output is forced into a fixed state This is easily accomplished by ensuring that the two inputs are at least one diode drop apart while also appropriately connecting the LATCH ENABLE and LATCH ENABLE inputs as described above The best performance is achieved with the use of proper ECL terminations The open emitter outputs of the ADCMP566 are designed to be terminated through 50 Q resistors to 2 0 V or any other equivalent ECL termination If a 2 0 V supply is not available an 82 Q resistor to ground and a 130 Q resistor to 5 2 V provide a suitable equivalent If high speed ECL signals must be routed more than a centimeter microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing ADCMP566 CLOCK TIMING RECOVERY Comparators are often used in digital systems to recover clock timing signals High speed square waves transmitted over a distance even tens of centimeters can become distorted due to
16. kQ Input Resistance Common Mode 600 kQ Open Loop Gain 60 dB Common Mode Rejection Ratio CMRR Vcm 2 0 V to 3 0 V 69 dB Hysteresis 1 0 mV LATCH ENABLE CHARACTERISTICS Latch Enable Common Mode Range Vicm 2 0 0 V Latch Enable Differential Input Voltage Vio 0 4 2 0 V Input High Current 0 0 V 12 6 12 uA Input Low Current 2 0 V 12 6 12 uA Latch Setup Time ts 250 mV overdrive 50 ps Latch to Output Delay teLon tPLoL 250 mV overdrive 250 ps Latch Pulsewidth teL 250 mV overdrive 150 ps Latch Hold Time tH 250 mV overdrive 75 ps OUTPUT CHARACTERISTICS Output Voltage High Level Vou ECL 50 Q to 2 0 V 1 06 0 81 V Output Voltage Low Level VoL ECL 50 Q to 2 0 V 1 95 1 65 V Rise Time tr 20 to 80 170 ps Fall Time tF 20 to 80 140 ps AC PERFORMANCE Propagation Delay ted 1 V overdrive 240 ps Propagation Delay ted 20 mV overdrive 290 ps Propagation Delay Tempco 0 5 ps C Prop Delay Skew Rising Transition to 10 ps Falling Transition Within Device Propagation Delay Skew 10 ps Channel to Channel Propagation Delay Dispersion vs 1 MHz 1 ns tr tr 10 ps Duty Cycle Propagation Delay Dispersion vs 50 mV to 1 5 V 35 ps Overdrive Propagation Delay Dispersion vs 20 mV to 1 5 V 50 ps Overdrive Propagation Delay Dispersion vs 0V to 1 V swing 50 ps Slew Rate 20 to 80 50 and 600 ps tr tr Propagation Delay Dispersion vs 1 V swing 5 ps Common Mode Voltage 1 5 V to 2 5 Vem Equivalent Input Rise Time Band
17. ltage Difference between the overdrive differential input and reference input voltages Rev 0 Page 8 of 16 APPLICATION INFORMATION The ADCMP566 comparators are very high speed devices Consequently high speed design techniques must be employed to achieve the best performance The most critical aspect of any ADCMP566 design is the use of a low impedance ground plane A ground plane as part of a multilayer board is recommended for proper high speed performance Using a continuous conductive plane over the surface of the circuit board can create this allowing breaks in the plane only for necessary signal paths The ground plane provides a low inductance ground eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce A proper ground plane also minimizes the effects of stray capacitance on the circuit board It is also important to provide bypass capacitors for the power supply in a high speed application A 1uF electrolytic bypass capacitor should be placed within 0 5 inches of each power supply pin to ground These capacitors will reduce any potential voltage ripples from the power supply In addition a 10 nF ceramic capacitor should be placed as close as possible from the power supply pins on the ADCMP566 to ground These capacitors act as a charge reservoir for the device during high frequency switching The LATCH ENABLE input is active low latched If the l
18. or input signal passes through the switching threshold COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP566 has been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1 V Propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive how far the switching point is exceeded by the input The overall result is a higher degree of timing accuracy since the ADCMP566 is far less sensitive to input variations than most comparator designs Propagation delay dispersion is a specification that is important in critical timing applications such as ATE bench instruments and nuclear instrumentation Overdrive dispersion is defined Rev 0 Page 9 of 16 ADCMP566 as the variation in propagation delay as the input overdrive conditions are changed Figure 4 For the ADCMP566 overdrive dispersion is typically 35 ps as the overdrive is changed from 100 mV to 1 V This specification applies for both positive and negative overdrive since the ADCMP566 has equal delays for positive and negative going inputs The 35 ps propagation delay overdrive dispersion of the ADCMP566 offers considerable improvement of the 100 ps dispersion of other similar series comparators 1 5V OVERDRIVE INPUT VOLTAGE 20mV OVERDRIVE Vrer Vos Q OUTPUT 03633 0 004 Figure 4 Propagation Delay Dispersion COMPARATOR HYSTERESIS
19. width BW OV to 1V swing 5000 MHz 20 to 80 50 ps tr tr Rev 0 Page 3 of 16 ADCMP566 Parameter Symbol Condition Min Typ Max Unit AC PERFORMANCE continued Toggle Rate gt 50 output swing 5 Gbps Minimum Pulsewidth PW Atpa from 10 ns to 200 ps 200 ps lt 25 ps Unit to Unit Propagation Delay Skew 10 ps POWER SUPPLY Positive Supply Current Vee 5 0V 9 13 18 mA Negative Supply Current Wee 5 2V 60 70 85 mA Positive Supply Voltage Vcc Dual 4 75 5 0 5 25 V Negative Supply Voltage Vee Dual 4 96 5 2 5 45 V Power Dissipation Dual without load 375 450 525 mW Power Dissipation Dual with load 550 mW Power Supply Sensitivity Vcc PSSv c 68 dB Power Supply Sensitivity Vee PSSv 85 dB NOTE Under no circumstances should the input voltages exceed the supply voltages Rev 0 Page 4 of 16 ABSOLUTE MAXIMUM RATINGS Table 2 ADCMP566 Absolute Maximum Ratings Parameter Rating Supply Positive Supply Voltage 0 5 V to 6 0 V Voltages Vcc to GND Negative Supply Voltage 6 0 V to 0 5 V Ve to GND Ground Voltage Differential 0 5 V to 0 5 V Input Input Common Mode 3 0 V to 4 0 V Voltages Voltage Differential Input Voltage 7 0 V to 7 0 V Input Voltage Ve to 0 5 V Latch Controls Output Output Current 30 mA Temperature Operating Temperature 40 C to 85 C Ambient Operating Temperature 125 C Junction Storage Temperature Range
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ANALOG DEVICES ADCMP566 handbook(1)