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ANALOG DEVICES AD790 handbook

1. 1 70 i E 1 10 20 30 4D 50 OVERDRIVE mV TPC 1 Propagation Delay vs Overdrive 90 80 70 60 50 40 30 20 10 Lil 10 100 tk 10k SOURCE RESISTANCE Ohms TPC 4 Propagation Delay vs Source Resistance 2 3 gt 1 LU o lt 5 o gt gt e l E 2 n E 2 o 0 2 4 6 8 10 ISource MA TPC 7 Output High Voltage vs Source Current REV D PROPAGATION DELAY na 0 20 40 60 80 LOAD CAPACITANCE pF TPC 2 Propagation Delay vs Load Capacitance ROP GATION DELAY ns P he a 0 50 n 50 100 TEMPERATURE TPC 5 Propagation Delay vs Temperature 20 T ag AW eet u 15Y V og 5Y SUPPLY CURRENT mA 20 0 W Go TEMPERATURE C TPC 8 Total Supply Current vs Temperature BO 70 ED PROPAGATION DELAY ns PUT LOW VOLTAGE Volts FAN OUT Gates TPC 3 Propagation Delay vs Fanout LSTTL and CMOS IsiNK mA TPC 6 Output Low Voltage vs Sink Current tpp Von OUTPUT X VoL tg SETUP TIME ty HOLD TIME tpp COMPARATOR RESPONSE TIME Figure 4 Latch Timing AD790 CIRCUIT DESCRIPTION The AD790 possesses the overall characteristics of a standard monolithic comparator differential inputs high gain and a logic outp
2. 60 60 60 mW TEMPERATURE RANGE Rated Performance Tmn to Tmax 0 to 70 40 to 85 0 to 70 40 to 85 55 to 125 SG NOTES Pin 1 tied to Pin 8 and Pin 4 tied to Pin 6 Defined as the average of the input voltages at the low to high and high to low transition points Refer to Figure 6 3Defined as half the magnitude between the input voltages at the low to high and high to low transition points Refer to Figure 6 Vs must not be connected above ground All min and max specifications are guaranteed Specifications shown in boldface are tested on all production units at final test Specifications subject to change without notice REV D AD790 ABSOLUTE MAXIMUM RATINGS Supply Voltage duis cadet urea ae 18 V Internal Power Dissipation 00 500 mW Differential Input Voltage oooooomoooo o 16 5 V Output Short Circuit Duration Indefinite Storage Temperature Range NR cai e ea aaa i 65 C to 125 C 0o 65 C to 150 C Lead Temperature Range Soldering 60 sec 300 C Logic Supply Voltage 0 0 dinoas ak e TV NOTES IStresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating cond
3. Its controlled switching reduces power supply disturbances that can feed back to the input and cause undesired oscillations The AD790 also has a latching function which makes it suitable for applications requiring synchronous operation The AD790 is available in five performance grades The AD790J and the AD790K are rated over the commercial tem perature range of 0 C to 70 C The AD790A and AD790B are rated over the industrial temperature range of 40 C to 85 C The AD790S is rated over the military temperature range of 55 C to 125 C REV D Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices suitable as a general purpose compara tor in analog signal processing and data acquisition systems 2 Built in hysteresis and a low glitch output stage minimize the chance of unwanted oscillations making the AD790 easier to use than standard open loop comparators 3 The hysteresis combined with a wide input voltage range enables the AD790 to respond to both slow low level e g 10 mV signals and fast large amplitude e g 10 V signals 4 A wide variety of supply voltages is acceptable for operation of the AD790 ranging from sin
4. 33 0 0130 0 25 0 0098 1 27 0 0500 0 19 0 0075 0 41 0 0160 REV D CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS 012 AA AD790 Revision History Location Page Data Sheet changed from REV C to REV D Edits to SOIC R 8 Package lilla ac A Ra Po ee dii tone dala dee 9 03 02 Data Sheet changed from REV B to REV C Editsto FEATURES sisa tn a M EAT E TE PEE ese ee 1 Edits t PRODUCT DESCRIPTION 23 5 sa ea es es a A deal 1 Deleted ME FALIZA TION PHOTOGRAPH vassa meno enea en in na 4 Edits to ORDERING GUIDE 4 0 nee 4 10 REV D ww BDI C Com AD C Z0 5 0 tt78009 ww BDI C Com AD V SA NI CILNIYd 12
5. 90 dB Tmn to Tmax 76 88 85 93 76 85 dB Input Voltage Range Differential Voltage Vs lt t15 V Vs tVs tVs V Common Mode Vs 2 V Vs Vs 2 V Vs Vs 2 V V Common Mode Rejection Ratio 8 0 80 5 dB 6 an Input Impedance 0 2 MQ pF LATCH CHARACTERISTICS Latch Hold Time ty 25 35 25 35 25 35 ns Latch Setup Time ts 5 10 5 10 5 10 ns LOW Input Level Vi Tmn to Tmax 0 8 0 8 0 8 V HIGH Input Level Vr Tmn to Tmax 1 6 1 6 1 6 V Latch Input Current 2 3 5 2 3 3 5 2 3 5 uA Tym to Tax 7 5 8 uA SUPPLY CHARACTERISTICS Diff Supply Voltage Viocic 5 V Tmn to Tmax 4 5 33 4 5 33 4 7 33 V Logic Supply Tmn to Tmax 4 0 7 4 0 7 4 2 7 V Quiescent Current Vs Vs 15 V 8 10 8 10 8 10 mA Vs Vs 15 V 4 5 4 5 4 5 mA Viocic Viocic 5 V 2 3 3 2 3 3 2 3 3 mA Power Dissipation 242 242 242 mW TEMPERATURE RANGE Rated Performance Tmn to Tmax 0 to 70 40 to 85 0 to 70 40 to 85 55 to 125 C NOTES Defined as the average of the input voltages at the low to high and high to low transition points Refer to Figure 6 Defined as half the magnitude between the input voltages at the low to high and high to low transition points Refer to Figure 6 3 Vs must be no lower than Vrogic 0 5 V in any supply operating conditions except during power up All min and max specifications are guaranteed Specifications shown in boldface are tested on all production units at final test Specifications subject to change without notice REV D SING L
6. ANALOG DEVICES Fast Precision Comparator AD790 CONNECTION DIAGRAMS 8 Pin Plastic Mini DIP N and Cerdip Q Packages FEATURES 45 ns max Propagation Delay Single 5 V or Dual 15 V Supply Operation CMOS or TTL Compatible Output 250 uV max Input Offset Voltage 500 uV max Input Hysteresis Voltage 15 V max Differential Input Voltage Onboard Latch 60 mW Power Dissipation Available in 8 Pin Plastic and Hermetic Cerdip Packages Available in Tape and Reel in Accordance with EIA 481A Standard APPLICATIONS Zero Crossing Detectors Overvoltage Detectors Pulse Width Modulators Precision Rectifiers Discrete A D Converters Delta Sigma Modulator A Ds y to use The AD790 may operate from either a single 5 V supply or a dual 15 V supply In the single supply mode the AD790 s inputs may be referred to ground a feature not found in other comparators In the dual supply mode it has the unique ability of handling a maximum differential voltage of 15 V across its in put terminals easing their interfacing to large amplitude and dynamic signals This device is fabricated using Analog Devices Complementary Bipolar CB process which gives the AD790 s combination of fast response time and outstanding input voltage resolution 1 mV max To preserve its speed and accuracy the AD790 incorporates a low glitch output stage that does not exhibit the large current spikes normally found in TTL or CMOS output stages
7. E SUPPLY Operation 25 C and Vs Viggic 5 V Vs 0 V unless otherwise noted AD790J A AD790K B AD790S Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit RESPONSE CHARACTERISTIC 100 mV Step Propagation Delay tpp 5 mV Overdrive 45 50 45 50 45 50 ns Tmn to Tmax 50 60 50 60 65 ns OUTPUT CHARACTERISTICS Output HIGH Voltage Von 1 6 mA Source 4 65 4 65 4 65 6 4 mA Source 4 3 4 45 4 3 4 45 4 3 4 45 V Tmn to Tmax 4 3 4 3 4 3 V Output LOW Voltage Vor 1 6 mA Sink 0 35 0 35 0 35 V 6 4 mA Sink 0 44 0 5 0 44 0 5 0 44 0 5 V Tmn to Tmax 0 5 0 5 0 5 V INPUT CHARACTERISTICS Offset Voltage 0 45 1 5 0 35 0 6 0 45 1 5 mV Tmn to Tmax 2 0 0 85 2 0 mV Hysteresis Tmn to Tmax 0 3 0 5 0 75 0 3 0 5 0 65 0 3 0 7 1 0 mV Bias Current Either Input 2 7 5 2 0 3 5 2 7 5 HA Tmn to Tmax 7 5 8 uA Offset Current 0 04 0 25 0 02 0 15 0 04 0 25 uA Tmn to Tmax 0 3 0 2 0 4 HA Power Supplv Rejection Ratio DC 4 5 VSVg lt 5 5 V 80 90 86 100 80 90 dB Tmn to Tmax 76 76 88 82 93 76 85 dB Input Voltage Range Differential Voltage Vs Vs Vs V Common Mode 0 Vs 2V JO Vs 2V 0 Vs 2 V V Input Impedance 20 20 12 MQ pF LATCH C Latch Hold Ti 35 ns Latch Setup Time ts 5 ns LOW Input Level Vir Tmn to Tmax 0 8 0 8 V HIGH Input Level Vim Tmn to Tmax 1 6 1 6 V Latch Input Current 2 3 5 2 3 3 5 uA Tmn to Tmax 7 5 uA SUPPLY CHARACTERISTICS Supply Voltage Tmn to Tmax 4 5 7 4 5 7 4 7 7 V Quiescent Current 10 12 10 12 10 12 mA Power Dissipation
8. currents to the device during comparator switching The AD790 has three supply voltage pins Vs Vs and Vrocic It is important to have a common ground lead on the board for the supply grounds and the GND pin of the AD790 to provide the proper return path for the supply current LATCH OPERATION The AD790 has a latch function for retaining input information at the output The comparator decision is latched and the output state is held when Pin 5 is brought low As long as Pin 5 is kept low the output remains in the high or low state and does not respond to changing inputs Proper capture of the input signal requires that the timing relationships shown in Figure 4 are followed Pin 5 should be driven with CMOS or TTL logic levels The output of the AD790 will respond to the input when Pin 5 is at a high logic level When not in use Pin 5 should be connected to the positive logic supply When using dual supplies it is rec ommended that a 510 Q resistor be placed in series with Pin 5 and the driving logic gate to limit input currents during powerup 6 REV D Applying the AD790 0 1uF Vg 12V V OV TIEN v 4Vg 45V Vs 15V V Logic 5V Logic 5V V 45V V 5V V Loaic 5V Figure 7 Typical Power Supply Connections N O Package Pinout Window Comparator for Overvoltage Detection The wide differential input range of the AD790 makes it suitable for monitoring large amplitude signal
9. gle 5 V to dual 5 V 12 V 5 V or 5 V 15 V supplies 5 The AD790 s power dissipation is the lowest of any compara tor in its speed range 6 The AD790 s output swing is symmetric between Vi ocic and ground thus providing a predictable output under a wide range of input and output conditions One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2002 AD790 SPECIFICATIONS DUAL SUPPLY Operation 25 C and V 15 V Vs 15 V Viogic 5 V unless otherwise noted AD790J A AD790K B AD790S Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit RESPONSE CHARACTERISTIC 100 mV Step Propagation Delay tpp 5 mV Overdrive 40 45 40 45 40 45 ns Tmn to Tmax 45 50 45 50 60 ns OUTPUT CHARACTERISTICS Output HIGH Voltage Voy 1 6 mA Source 4 65 4 65 4 65 6 4 mA Source 4 3 4 45 4 3 4 45 4 3 4 45 V Tmn to Tmax 4 3 4 3 4 3 4 3 V Output LOW Voltage Vor 1 6 mA Sink 0 35 0 35 0 35 V 6 4 mA Sink 0 44 0 5 0 44 Q 5 0 44 0 5 V Tmn to Tmax 0 5 0 5 0 5 0 5 V INPUT CHARACTERISTICS Offset Voltage 0 2 1 0 0 05 0 25 0 2 1 0 mV Tmn to Tmax 1 5 0 5 1 5 mV Hysteresis Tmn to Tmax 0 3 0 4 0 6 0 3 0 4 0 5 0 3 0 4 0 65 mV Bias Current Either Input 2 5 5 1 8 3 5 2 5 5 uA Tmn to Tmax 6 5 4 5 7 uA Offset Current 0 04 0 25 0 02 0 15 0 04 0 25 uA Tmn to Tmax 0 3 0 2 0 4 uA Power Supply Rejection Ratio DC Vs 20 80 90 88 100 80
10. ible with TTL and CMOS logic require ments The fanout of the output stage is shown in TPC 3 for standard LSTTL or HCMOS gates Output drive behavior vs capacitive load is shown in TPC 2 HYSTERESIS The AD790 uses internal feedback to develop hysteresis about the input reference voltage Figure 6 shows how the input offset voltage and hysteresis terms are defined Input offset voltage Vos is the difference between the center of the hysteresis range and the ground level This can be either positive or nega tive The hysteresis voltage Vy is one half the width of the V4 HYSTERESIS VOLTAGE Vos INPUT OFFSET VOLTAGE IN 2 7 Vout GND NV Figure 6 Hysteresis Definitions N O Package Pinout hysteresis range This built in hysteresis allows the AD790 to avoid oscillation when an input signal slowly crosses the ground level SUPPLY VOLTAGE CONNECTIONS The AD790 may be operated from either single or dual supply voltages Internally the Vr oic circuitry and the analog front end of the AD790 are connected to separate supply pins If dual ies are used any combination of a in which Vs gt Vioc c 0 operation BYPASSING AND GROUNDING Although the AD790 is designed to be stable and free from oscillations it is important to properly bypass and ground the power supplies Ceramic 0 1 uF capacitors are recommended and should be connected directly at the AD790 s supply pins These capacitors provide transient
11. itions for extended periods may affect device reliability Thermal characteristics plastic N 8 package 0j 90 C watt ceramic Q 8 package ja 110 C watt 61c 30 C watt SOIC R 8 package 0j 160 C watt 61c 42 C watt LATCH OPTIONAL 15V Figure 1 Basic Dual Supply Configuration N O Package Pinout PULSE GENERATOR HP8112 ORDERING GUIDE Temperature Package Package Model Range Description Option AD790 N 0 C to 70 C Plastic DIP N 8 AD790JR 0 C to 70 C SOIC SO 8 AD790JR REEL 0 C to 70 C Reel AD790JR REEL7 0 C to 70 C SOIC R 8 AD790KN 0 C to 70 C Plastic DIP N 8 AD790AQ 40 C to 85 C Cerdip Q 8 AD790BQ 40 C to 85 C Cerdip Q 8 AD790SQ 55 C to 125 C Cerdip Q 8 Not for new designs obsolete April 2002 For military processed devices please refer to the standard Mi crocircuit Drawing SMD available at www dscc dla mil programs milspec default asp SMD Part Number ADI Equivalent 5962 9150501MPA Not for new designs obsolete April 2002 AD790 SQ 883 5V LATCH OPTIONAL Figure 2 Basic Single Supply Configuration N O Package Pinout 0 1pF 15V 45V 0 1pF 5V VOLTAGE SOURCE Figure 3 Response Time Test Circuit N Q Package Pinout REV D Typical Performace Characteristics AD790 PAGPAGATION DELAY ns PROPAGATION GELAY ns 80
12. s The simple overvoltage detection circuit shown in Figure 8 illustrates direct connection of the input signal to the high impedance inputs of the comparator without the need for special clamp diodes to limit the differen tial input voltage across the inputs SIGN 1 HIGH 0 LOW OVERRANGE 1 Vin 15V 0 1pF gt 7 Figure 8 Overvoltage Detector N O Package Pinout Single Supply Ground Referred Overload Detector The AD790 is useful as an overload detector for sensitive loads that must be powered from a single supply A simple ground referenced overload detector is shown in Figure 8 The com parator senses a voltage across a PC board trace and compares that to a reference trip voltage established by the comparator s minus supply current through a 2 7 Q resistor This sets up a 10 mV reference level that is compared to the sense voltage REV D The minus supply current is proportional to absolute tempera ture and compensates for the change in the sense resistance with temperature The width and length of the PC board trace determine the resistance of the trace and consequently the trip current level ILiurr 10 mV Rsense Rsense rho trace length trace width rho resistance of a unit square of trace Vs PC BOARD TRACE OUTPUT Rsense 10mV 100mA ector Circuit Precision Full Wave Rectifier The high speed and precision of the AD790 make it suitable for use in the wide dynamic range f
13. t perform this task Figure 11 shows a 1 kQ resistor in series with the input signal which is then clamped by a Schottky diode holding the input of the comparator at 0 4 V below ground Although the comparator is specified for a common mode range down to Vs in this case ground it is permissible to bring one of the inputs a few hundred mV below ground The comparator switches around this level and produces a CMOS TTL compatible swing The circuit will operate to switching frequencies of 20 MHz ww BDI C comi AD 8 REV D AD790 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Pin Plastic Mini DIP N 8 Package 025 031 16 35 17 87 i 0 30 7 621 MAX REF 7 0 035 0 01 0165 0 01 0 88 0 25 14 18 0 25 SEATING t AS o PLANE 2513183 Foo s 1457 0 16 MIN f ao 0h a le 1254 0 011 9 003 WE 0 15 10 28 08 9 018 0 003 0 03340 841 10 46 008 NOM 8 Pin Cerdip Q 8 Package 0 005 10 13 0 056 11 35 MIN MAK 22015 59 enim DESDE l 7 0 015 18 38 920 5 08 0 06 11 52 MAX SEATING NANI PLANE 0 125 3 18 LI TE EAN 0 29 7 371 0 200 5 08 032 18 13 uN er e 2 54 d 008 19 20 BSE 18 8 015 0 381 0 014 10 36 003 10 761 0 023 10 58 8 07 11 78 SOIC R 8 Package 5 00 0 1968 80 0 1 sso 0 2284 om 0 25 0 0099 COPLANARITY 1 75 0 0688 0 25 0 0098 y 1 35 0 0532 y 0 10 0 0040 gt 8 je SEATING 0 51 0 0201 PLANE 0
14. ull wave rectifier shown in Figure 10 This circuit is capable of rectifying low level signals as small as a few mV or as high as 10 V Input resolution propaga tion delay and op amp settling will ultimately limit the maximum input frequency for a given accuracy level Total comparator plus switch delay is approximately 100 ns which limits the maximum input frequency to 1 MHz for clean rectification 10kQ FET SWITCHES THE GAIN FROM 1 TO 1 NMOS FET V7 Roy lt 200 Figure 10 Precision Full Wave Rectifier N Q Package Pinout AD790 5V BIPOLAR an L I sIGNAL INPUT gan TTL STANDARD O LEVEL OUTPUT SCHOTTKY A DIODE A RESISTOR UP TO 10kO MAYBE USED TO REDUCE THE SOURCE AND SINK CURRENT OF THE DRIVER HOWEVER THIS WILL SLIGHTLY LOWER THE MAXIMUM USABLE CLOCK RATE Figure 11 A Bipolar to CMOS TTL Line Receiver N Q Package Pinout Bipolar to CMOS TTL It is sometimes desirable to translate a bipolar signal e g 5 V coming from a communications cable or another section of the system to CMOS TTL logic levels such an application is referred to as a line receiver Previously the interface to the bipolar signal required either a dual power supply or a refer ence voltage level about which the line receiver would switch The AD790 may be used in a simple circuit to provide a unique capability the ability to receive a bipolar signal while powered from a single 5 V supply Other comparators canno
15. ut However its function is implemented with an architec ture which offers several advantages over previous comparator designs Specifically the output stage alleviates some of the limi tations of classic TTL comparators and provides a symmetric output A simplified representation of the AD790 circuitry is shown in Figure 5 VLocic OUTPUT GAIN STAGE The output stage t i i converts it to a defined by the pull u t duce inherent rail to rail output levels compatible with CMOS logic as well as TTL without the need for clamping to internal bias levels Furthermore the pull up and pull down levels are symmetric about the center of the supply range and are refer enced off the Vi ocic supply and ground The output stage has nearly symmetric dynamic drive capability yielding equal rise and fall times into subsequent logic gates Unlike classic TTL or CMOS output stages the AD790 circuit does not exhibit large current spikes due to unwanted current flow between the output transistors The AD790 output stage has a controlled switching scheme in which amplifiers Al and A2 drive the output transistors in a manner designed to reduce the current flow between Q1 and Q2 This also helps minimize the disturbances feeding back to the input which can cause troublesome oscillations The output high and low levels are well controlled values defined by Vioc c 5 V ground and the transistor equivalent Schottky clamps and are compat

ANALOG DEVICES AD790 handbook

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