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ELAN EM78257 MASK ROM Manual

1. TCC INT ROM STACK 0 c OSCO RESET Dar STACK 1 SES d STACK2 Y Y y STACK 3 Oscillator Timing Y Y STACK 4 Control 4 8 7 Y STIR Interrupt Instruction STACK controller Register STACK 7 RAM i Built in RI TCC ALU OSC 3 nstruction R4 i decoder R3 DATA amp CONTROL BUS TCC4 CIN1 P50 1 51 2 CO2 P52 Iocs Comparators COUNTER IOC6 ip CIN2 4P53 Uo Uo 2 TCC CIN2 P54 PORTS lt ng PORTS OSCI CIN1 P55 R5 aes 2 P67 IR OUT TCC6 P57 Fig 3 Functional block diagram 4 1 Operational Registers 1 RO Indirect Addressing Register RO is not a physically implemented register Its major function is to be an indirect addressing pointer Any instruction using RO as a pointer actually accesses data pointed by the RAM Select Register R4 2 R1 Time Clock Counter TCC Increased by an external signal edge which is defined by the TE bit CONT 4 through the TCC pin or by the instruction cycle clock Writable and readable as any other registers The prescaler RC is assigned to TCC This specification is subject to change without prior notice 7 2002 05 06 EM78257 MASK ROM contents of the prescaler counter is cleared only when a value is written to TCC register
2. e Bit 0 Bit 6 Not used Bit 7 MOUSEN Mouse application Enable bit 0 Disable MOUSEN TCCA TCCB and TCCC are increment counters 1 Enable MOUSEN RA disable BitO TCCATE Bit1 TCCATS is 1 Bit2 TCCAIE is 0 RB disable BitO TCCCTE Bit1 TCCCTS is 1 Bit2 TCCCIE is 0 Bi disable Bit4 TCCBTE BitS TCCBTS is 1 Bit6 TCCBIE is 0 and TCCA TCCBL and TCCC work as up down counters For other pin assignments refer to 80 4 MOUSE mode Timing 1 Photo couples pulse width X1 Y1 7 X2 Y2 Tr Tf Counter increment if the rising falling edge of X1 is leading the one on X2 Counter decrement if the rising falling edge of X1 is falling behind the on X2 2 Sending DATA data from EM78257A B to system 1st 2nd 10th 11th Start bit Bit0 Bit7 Parity Bit Stop bit If CLK is low inhibit status no data transmission occurs If CLK is high and DATA is low request to send data is updated Data is received from the system and no transmission is started by EM78A B until CLK DATA are both high IF CLK and DATA are both high the transmission is ready DATA is valid prior to the falling edge of CLK and This specification is subject to change without prior notice 52 2002 05 06 EM78257 MASK ROM beyond the rising edge of CLK During transmission EM78257A
3. TCF RF o o o ISR RESET and WDT RORE Wake Up from Pin Change RESET and WDT Wake Up from Pin Change P X not used U unknown or don t care P previous value before reset t check Table 5 4 11 Power On Considerations Any microcontroller is not warranted to start proper operation before the power supply reaches its steady state EM78257A B is equipped with Power On Voltage Detector POVD with a detecting level of 1 4 V to 2 0 V The extra external reset circuit will work well if Vdd rises fast enough 50 ms or less In many critical applications however extra devices are still required to assist in solving power on problems 1 Programmable Oscillator Set Up Time The Option word SUT is used to define the oscillator Set Up time 18ms or 1ms Theoretically the range is from 1 ms to 18 ms For most of crystal or ceramic resonators the lower the operation frequency the longer is the required Set up time 2 External Power 0n Reset Circuit This specification is subject to change without prior notice 42 2002 05 06 EM78257 MASK ROM The circuit shown in Fig 18 implements an external RC to produce the reset pulse The pulse width time constant should be kept long enough for Vdd to reach minimum operation voltage This circuit is used when the power supply has slow rise time Because the current leakage from the RESET pin is ab
4. 2 RESET WDT Wake Up from Pin Change Rao RESET WDT Wake Up from Pin Change 3 9 IOCS Raen RESET and WDT Wake Up from Pin Change RESET and WDT Wake Up from Pin Change Power On Wake Up from Pin Change RESET and WDT Wake Up from Pin Change U RESET and WDT P This specification is subject to change without prior notice 41 2002 05 06 P m RESET and WDT Ox7 x8 BS P56 1 1 1 1 U 0 U pr o e BS x fo e e e gt e e ep e P56 P55 m 1 e e Pee Pes 4 4 Te fe fe ep e e NEM o EM78257 MASK ROM Wake Up from Pin Change P P Pe PPP BiName CMPOUT4 CMPOUT3 CMPOUT2 CMPOUT1 TCCCIF TCCBIF m Poweron o o o o o o f 8 ReseTanowotr P e P ep ep P ms RA TCCSR1 RESET and WDT RB Wake Up from Pin Change TCCBEN TCCBIE TCCBTS TCCBTE TCCCEN TCCCIE TCCCTS TCCCTE Poe o o o o o o o o TCCSTR2 RC reer M RESET and WDT Wake Up from Pin Change OxF CMP4IF CMP3IF CMP2IF
5. Define pin4 EM78257A or 5 78257 as a reset pin 0 RESET enable 1 RESET disable Bit 10 ENWTD Watchdog timer enable bit 0 Enable 1 Disable e Bit 9 CLKS Instruction period option bit 0 Two clocks 1 Four clocks Refer to the section on Instruction Set Bit 8 7 and 6 OSC2 0SC1 and OSCO Oscillator Modes Selection bits Table 31 Oscillator Modes Defined by OSC2 0SC1 and OSCO OSC2 05017 osco IC Internal C oscillator mode 1 1 o0 ERC External RC oscillator mode 1 0 1 HXT High XTAL oscillator mode 0 0 1 LXT Low XTAL oscillator mode 0 o o Note The transient point of system frequency between HXT and LXY is around 400 KHz Bit 5 SUT Set Up Time of device bits pul mmc Theoretical values for reference only Bit 4 Type selection for EM78257A or EM78257B TYPE 0 EM78257B EM78257A Bit 3 RCOUT A selecting bit of High or Low frequency for internal RC Oscillator RCOUT This specification is subject to change without prior notice 61 2002 05 06 4 16 EM78257 MASK ROM Bit 2 and Bit 1 RCM1 RCMO RC mode selection bits RCM 1 RCM 0 Frequency MHz NEN A 0 1 255 sj 32 T68kHz Note Theoretical values for reference only In fact the values may be inaccurate by 35 Bit 0 CLAMP Operating Voltage 0
6. EM78257 MASK ROM 1 GENERAL DESCRIPTION EM78257A B is an 8 bit microprocessors with low power high speed CMOS technology It features a 2K 13 bits Read Only Memory ROM and provides 12 Option bits to accommodate user s requirements This specification is subject to change without prior notice 1 2002 05 06 EM78257 MASK ROM 2 FEATURES 18 lead packages EM78257A 20 lead packages EM78257B Operating voltage range 2 3V 5 5V Operating temperature range 0 C 70 C commercial 40 C 85 C industrial Operating frequency range Base 2 clocks Crystal mode DC 20MHZ 2clks 5V DC 8MHz 2clks 3V RC mode DC 4MHz 2clks 5V DC 4MHz 2clks 3V Low power consumption less then 1 5 mA at 5V 4MHz typical of 15 uA at 3V 32KHz typical of 1 uA during the sleep mode Built in RC oscillator 4MHz 1MHz 455KHz 32 768KHz RC oscillator mode with Internal Capacitor Programmable oscillator set up time 1ms 18ms Independent Programmable prescaler of WDT One configuration register to match the user s requirements 80x 8 on chip registers SRAM general purpose register 2Kx 13 on chip ROM Bi directional I O ports 8 level stacks for subroutine nesting 8 bit real time clock counter TCC with selective signal sources trigger edges and overflow interrupt 4 sets of comparators Easy implemented IR Infrared remote control application circuit Easy implemented MOUSE application
7. then the choice is decided by TCCBTS of RB Pin 18 can choose P50 or TCC4 only If MOUSEN is 1 and TCC4E of IOC80 is 1 also then choose TCC4 otherwise choose P50 Pin 17 can choose P55 or OSCI only and the choice is decided by Bit 9 8 7 of CODE option When choice is 1 1 1 then Pin 17 is defined as P55 otherwise the status is defined as OSCI 1 Comparator CO1 is on For EM78257A Pin 18 can choose P51 or CO1 only and the choice is decided by COIE1 of IOC90 Pin 17 can choose CIN1 only Pin 16 can choose P55 CIN1 OSCI and is decided by IOCAO If CIN1 was not chosen as comparator1 input then this pin s status will be decided by Bit 9 8 7 of CODE option When choice is 1 1 1 then Pin 16 is defined as P55 otherwise the status is defined as OSCI For EM78257B Pin 19 can choose P51 or CO1 only and the choice is decided by COIE10f IOC90 Pin 18 can choose CIN1 only Pin 17 can choose P55 CIN1 OSCI and is decided by IOCAO If CIN1 was not chosen as comparator1 input then this pin s status will be decided by Bit 9 8 7 of CODE option When choice is 1 1 1 then Pin 17 is defined as P55 otherwise the status is defined as OSCI Bit 1 CE2 Comparator CO2 enable bit 0 Comparator is CO2 off default value For EM78257A Pin 1 can choose P52 only Pin 2 can choose P53 only Pin 3 can choose P54 or TCC only and is decided by Bit 5 of Control Register CONT 5 When TS is 1
8. 0 TCCCTS 0 TCCCTE O OXOE MCRRE jMOUSEENO 0 0 o jo o 0 0 Note name initial value Table 21 Related Status Data Register of the MOUSE Mode Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 0x01 TCC R1 0x09 9 CMPOUT4 CMPOUT3 CMPOUT2 CMPOUT1 0 0X05 51 TCCA7 TCCA6 TCCAS TCCA4 TCCA3 TCCA2 TCCA1 TCCAO TCC7 TCC6 TCC5 TCC4 TCC3 2 TCC1 TCCO 0x06 TCCBL IOC61 TCCB7 TCCB6 TCCB5 TCCB4 TCCB2 TCCB1 TCCBO TCCA An eight bit time clock counter A In MOUSE mode it will load X axis data into TCCA it is defined as an increment decrement counter TCCB An eight bit time clock counter B In MOUSE mode it will load Y axis data into TCCB it is defined as an increment decrement counter TCCC An eight bit time clock counter C In MOUSE mode it will load Z axis data into TCCC it is defined as an increment decrement counter Table 22 TCCX Status Register 1 7 6 5 4 3 2 1 0 TCCAIE TCCATS signal edge This specification is subject to change without prior notice 50 2002 05 06 EM78257 MASK ROM 0 TCCAIE O TCCATS O TCCATE O EM78257 MASK ROM 0 increment if the transition from low to high leading edge takes place on the TCC2 pin 1 increment if the transition from hi
9. then Pin 3 is defined as TCC otherwise the status is defined as P54 For EM78257B Pin 2 can choose P52 only Pin 3 can choose P53 only Pin 4 can choose P54 or TCC only and is decided by Bit 5 of Control Register CONT 5 When TS is 1 then Pin 4 is defined as TCC otherwise the status is defined as P54 This specification is subject to change without prior notice 18 2002 05 06 EM78257 MASK ROM 1 Comparator is CO2 on For EM78257A Pin 1 can choose P52 2 only and decided by COIE2 of IOC90 Pin 2 can choose CIN2 only Pin 3 can choose P54 CIN2 or TCC and is decided by IOCAO If CIN2 was not chosen as comparator1 input then this pin will be decided by Bit 5 of Control Register CONT 5 When TS is 1 then Pin 3 is defined as TCC otherwise status is defined as P54 For EM78257B Pin 2 can choose P52 or CC2 only and decided by COIE2 of IOC90 Pin can choose CIN2 only Pin 4 can choose P54 CIN2 TCC as decided by IOCAO If CIN2 was not chosen as comparator1 input then this pin will be decided by Bit 5 of Control Register CONT 5 When TS is 1 then Pin 4 is defined as TCC otherwise status defined as P54 Bit 2 CE3 Comparator CO3 enable bit 0 Comparator is off default value For EM78257A Pin 9 can choose P63 only Pin 8 can choose P62 only Pin 7 can choose P61 or TCC1 only If MOUSEN is 1 define pin as an input of TCCA TCC1 If MOUSEN is 0
10. 0 0011 0 0 XORAR 2 0011 rrr 03r XORRA 27 0100 00 rr MOVAR 2 0 0100 rrr MOVRR 272 0100 0r rr 272 0 0100 iir rr 2 0 0101 OOrr 0 272 O 0101 rr 2 0 0110 017 rrr RRC R AG 2 RE This specification is subject to change without prior notice 63 2002 05 06 EM78257 MASK ROM _ nach 7 gt gt A 0 SUE 7 gt C C gt R 0 R 0 3 4 7 LOT SWAPAR R 4 7 gt A 0 3 R 0 3 lt gt R 4 7 if R b 0 skip if R b 1 skip PC 1 gt SP Page KA 1 1100 kkkk kkkk 1Ckk RETL k Top of Stack gt PC 1 1101 kkkk kkkk 1Dkk SUB A k Z C DC 1 SP Note 1 gt This instruction is applicable to IOC50 1OC60 IOCBO IOCFO only Note 2 This instruction is not recommended for RF operation Note 3 This instruction cannot operate under RF This specification is subject to change without prior notice 64 2002 05 06 EM78257 MASK ROM 4 17 Timing Diagrams AC Test Input Output Waveform 2 4 2 0 2 0 TEST POINTS mS AC Testing Input is driven at 2 4V for logic 1 and 0 4V for logic 0 Timing measurements are made at 2 0V for logic 1 and 0 8V for logic 0 RESET Timing CLK
11. P50 to P57 1 4 17 20 Standard I O Port lines generally used for keypad sensing P67 IR OUT Pulse train output pin capable of sinking 30mA OSCI External clock signal input Vdd Power supply OSCO External clock signal input 4 Programmed the Related Registers When defining IR mode is defined refer to the related register of its operation as shown in the Table 26 and Table 27 below This specification is subject to change without prior notice 57 2002 05 06 EM78257 MASK ROM Table 26 Related Control Registers of the IR Mode Address Name 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit 0 0x0B TCR 2 RB 0 5 0 0 0 j TCCCIE O TCCCTS O TCCCTE O 0 08 TCCCR IOC80 TCC4E TCC6E TCCBE PWM O Note Bit name initial value Table 27 Related status data register of the IR mode Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 0 06 TCCBL IOC61 TCCBL7 TCCBL6 TCCBL5 TCCBL4 TCCBL3 TCCBL2 TCCBL1 TCCBLO TCCBH IOC71 TCCBH7 TCCBH6 TCCBH5 TCCBH4 TCCBH3 TCCBH2 TCCBH1 TCCBHO LTR IOC91 LTR7 LTR6 LTR5 LTR4 LTR3 LTR2 LTR1 LTRO HTR IOCA1 HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTRO OXOB PTR IOCB1 PTR7 PTR6 PTR5 PTR4 PTR3 PTR2 PTR1 PTRO TCCBL An eight bit clock counter is for the least significant byte of TCCBX TCCBL which can be read written and cleared at any reset condition TCCBH
12. Timer1 TCCA and Timer3 TCCC are eight bit clock counters with programmable prescalers Timer2 TCCB is a 16 bit clock counter with a programmable prescaler TCCA TCCB and TCCC can be read and written and cleared at every reset condition 2 Function Description Fig 14 shows the TIMER block diagram Each signal and block is described as follows Set predict value Set predict value Set predict value TCCAEN TCCBEN TCCCEN Set TCCCIF Set TCCAIF Set TCCBIF V Osci input or Osci input or Osci input or External input External input External input Fig 14 TIMER Block Diagram Osci input Input clock TCCX Timer 1 3 register TCCX increases until it matches with zero and then reload the previous value If TCCXIE is enabled TCCXIF will be set at the same time 3 Programming the Related Registers When defining TCCX refer to the related registers of its operation as shown in the Table 7 and Table 8 below This specification is subject to change without prior notice 35 2002 05 06 EM78257 MASK ROM Table 8 Related Control Registers of the TCCX Address Bit 7 Bit 6 Bit 5 OxOA Name Bit 4 Bit3 Bit2 Bit 1 Bit 0 TCR 1 RA Ls i TGCHERITCOPTSH TEOBTEN o TOCOERTOOOISDTCCOTER reces o o o Table 9 Related Status Data Registers of TCCX 0x09 TCCSR RQ_ CMP
13. An eight bit clock counter is for the most significant byte of TCCBX TCCBH which can be read written and cleared at any reset condition Low time Register 8 bit Low time register that controls the active or Low period of the pulse The High time register controls the inactive or High period of the cycle The decimal value of its contents determines the number of oscillator cycles indicating that the IR OUT pin is active The active period of IR OUT can be calculated as follow tio decimal value held in Low time register fosco High time Register The 8 bit High time register control the inactive or High period of the pulse The decimal value of its contents determines the number of oscillator cycles indicating that the IR OUT pin is active The inactive period of IR OUT can be calculated as follow tuign decimal value held in High time register fosco e Pulse timer Register The contents of the Low time and High time registers which are loaded alternately into the Pulse timer When loaded the Pulse timer contents are decremented by 1 every oscillator cycle Upon reaching zero the Pulse timer will be loaded with the contents of the other register Table 28 TCCX Status Register 2 7 6 5 4 3 2 1 0 TCCBIE TCCBTS TCCBTE TCCCIE TCCCTS TCCCTE Bit 6 TCCBIE TCCBIF interrupt enable bit 0 disable TCCBIF interrupt 1 enable TCCBIF interrupt This specification is subject to change without prior notice 5
14. then the choice is decided by TCCATS of RA For EM78257B Pin 10 can choose P63 only Pin 9 can choose P62 only Pin 8 can choose P61 or TCC1 only If MOUSEN is 1 defined pin as an input of TCCA TCC1 if MOUSEN is 0 then the choice is decided by TCCATS of RA 1 Comparator is on For EM78257A Pin 9 can choose P63 or only and decided by COIE3 of IOC90 Pin 8 can choose CIN3 only This specification is subject to change without prior notice 19 2002 05 06 EM78257 MASK ROM Pin 7 can choose P61 CIN3 TCC1 and the choice is decided by IOCAO If CIN3 was not chosen as comparator1 input then this pin s status will be decided by TCCATS of RA When TCCATS is 1 then Pin 7 is defined as TCC1 otherwise the status is defined as P61 For EM78257B Pin 10 can choose P63 only and decided by COIE3 of IOC90 Pin 9 can choose CIN3 only Pin 8 can choose P61 CIN3 or TCC1 and is decided by IOCAO If CIN3 was not chosen as comparator1 input then this pin s status will be decided by TCCATS of RA When TCCATS is 1 then Pin 8 is defined as TCC1 otherwise the status is defined as P61 Bit 3 CE4 Comparator CO4 enable bit 0 Comparator is 4 off default value For EM78257A Pin 10 can choice P64 only Pin 11 can choose P65 only Pin 12 can choose P66 or TCC2 only If MOUSEN is 1 and TCC2E of IOC80 is also 1 then set pin to TCC2 otherwise set t
15. 2002 05 06
16. 3 R2 Program Counter amp Stack PC Depending on the device type R2 and hardware stack are 11 bits wide The structure is depicted Fig 4 Generates 2Kx13 on chip ROM addresses to the relative programming instruction codes One program page is 1K words long e R2 is set as all 0 s when under RESET condition e IMP instruction allows direct loading of the lower 10 program counter bits Thus JMP allows PC go to any location within a page CALL instruction loads the lower 10 bits of the PC and then PC 1 is pushed into the stack Thus the subroutine entry address can be located anywhere within a page RET RETL k RETI instruction loads the program counter with the contents of the top level stack ADD R2 A allows the contents of A to be added to the current PC and the ninth and tenth bits of the PC are cleared MOV R2 A allows to load an address from the A register to the lower 8 bits of the PC and the ninth and tenth bits of the PC are cleared Any instruction that is written to R2 e g ADD R2 A MOV R2 A BC R2 6 will cause the ninth and tenth bits A8 A9 of the PC to be cleared Thus the computed jump is limited to the first 256 locations of a page In case of EM78257A B the second most significant bit A10 will be loaded with the content of bit PSO in the status register R3 upon the execution of a JMP CALL or any other instructions which write to R2 Al
17. 5 TCCBTS TCCB signal source 0 internal instruction cycle clock 1 transition on the TCC3 pin Bit 6 TCCBIE TCCBIF interrupt enable bit 0 disable the TCCBIF interrupt 1 enable the TCCBIF interrupt Bit 7 Not used 11 RC TCC Prescaler Counter TCC prescaler counter can be read and written V valid value This specification is subject to change without prior notice 13 2002 05 06 EM78257 MASK ROM 12 RD IR Control Register 7 6 5 4 3 2 1 0 DP1 DPO MF1 MFO IRE HF LGP PWM Bit 0 PWM Pulse Width Modulation When PWM 1 and LGP the LSB Counter and MSB Counter are disabled a continuous pulse train is generated and the output signal is actually a PWM waveform format of PWM Bit 1 LGP Long Pulse When LGP 1 the contents of the High time register are ignored A single pulse is generated its pulse is high Pulse width Contents of On time register x number of pulse x 1 Fosc If HF 1 this pulse is modulated with a frequency Fosco selected by MF1 MFO 2 HF High Frequency When HF 1 the Low time part of the generated pulse is modulated with a frequency Fosco Bit 3 IRE Infrared Remote Enable bit 0 Disable IRE Disable H W Modulator Function 1 Enable IRE Disable RB Bit4 TCCBTE and Bits TCCBTS and TCCBX acts as a down counter Enable H W Modulator Function Port 5 and pin60 66 set as normal I O pin Pin 67 defined as IR OUT Bit 4 Bit 5 0 1 Modu
18. B are independent options that is they can be selected separetely Note that once the 4 oscillator periods within one instruction cycle is selected under Case A the internal clock source to TCC will be CLK Fosc 4 not Fosc 2 as illustrated in Fig 6 In addition the instruction set has the following features 1 Every bit of any register can be set cleared or tested directly This specification is subject to change without prior notice 62 2002 05 06 EM78257 MASK ROM 2 The I O register can be regarded as general register That is the same instruction can operate on I O register The symbol R represents a register designator that specifies which one of the registers including operational registers and general purpose registers is to be utilized by the instruction b represents a bit field designator that selects the value for the bit which is located in the register and affects the operation k represents an 8 or 10 bit constant or literal value Table 32 The List of the Instruction Set of EM78P257A B Enable Interrupt 0 0000 0001 0100 0 0000 0001 rrrr oor IOCR gt A None lt Note1 gt R2 A gt R2 0 0000 0010 0000 0020 Bit8 9 do not clear Z C DC 0001 rr DECR 2 0 0010 O r ORAR AvVRGA 2 O 0010 rr ORRA AvVROR 2 0 0010 10 rr ANDAR A amp ROGA 2 O 0010 1 rr rr ANDRA A amp ROR 2
19. Pulse Timer The contents of the Low time and High time Latch registers are loaded alternately into the Pulse timer When loaded the Pulse timer contents are decremented by 1 every oscillator cycle and upon reaching zero the Pulse timer will be loaded with the contents of the other register IR control register Contains the bits that control various possibilities for the output pulse LSB Counter Loaded by software with the number of pulses required in a pulse burst MSB Counter loading 0 is not allowed IRE Infrared Remote Enable bit IR output port ligour 20mA when the output voltage drops to 2 4V at Vdd IR OUT 5V 2 1 Operation of the Hardware Modulator 1 Enable IRE set parameter for IR RD 2 Load Low time register IOC91 3 Load High time register IOCA1 4 Load MSB and LSB Counter register IOC61 IOC71 The Low time High time MSB Counter and LSB Counter register are loaded by software The following instructions is an example for generating five pulses train MOV A 0B00001000 MOV 0x0D A Enable IR MOV A 0x10 IOW 0x08 Enable TCCBH BS 0x03 6 Select control register segment 1 MOV A 0x10 IOW 0x09 Set Low Time Register 10h This specification is subject to change without prior notice 56 2002 05 06 EM78257 MASK ROM MOV A 0x20 IOW 0x0A Set High Time Register 20h MOV A 0x5 pulse number 5 gt LSB 5 MSB 0 IOW 0x06 115 5 M
20. Register 1 7 6 5 4 3 2 1 0 5 TCCAIE TCCATS 0 TCCATE TCCA signal edge 0 increment if the transition from low to high leading edge takes place on the TCC1 pin 1 increment if the transition from high to low leading edge takes place on TCC1 e Bit 1 5 TCCA signal source 0 internal instruction cycle clock 1 transition on the TCC1 pin Bit 2 TCCAIE TCCAIF interrupt enable bit 0 disable TCCAIF interrupt 1 enable TCCAIF interrupt Bit 3 Bit 7 Not used read as 0 This specification is subject to change without prior notice 12 2002 05 06 EM78257 MASK ROM 10 RB TCC Control Register 2 7 6 5 4 3 2 1 0 TCCBIE TCCBTS TCCCIE TCCCTS e Bit TCCC signal edge 0 increment if the transition from low to high leading edge takes place on the 5 1 increment if the transition from high to low leading edge takes place on the TCC5 e Bit 1 TCCCTS TCCC signal source 0 internal instruction cycle clock 1 transition on the TCC5 Bit 2 TCCCIE TCCCIF interrupt enable bit 0 disable the TCCCIF interrupt 1 enable the TCCCIF interrupt Bit 3 Not used Bit 4 TCCBTE TCCB signal edge 0 increment if the transition from low to high leading edge takes place on the TCC3 pin 1 increment if the transition from high to low leading edge takes place on the TCC3 pin Bit
21. Status changed interrupt flag Set as change occurred in the output of Comparator COA and reset by software RF can be cleared by instruction but cannot be set e OCFO is the relative interrupt mask register e Note that the result of reading RF is the logic AND of RF and IOCOF 15 R10 R3F All of these are the 8 bit general purpose registers 4 2 Special Purpose Registers 1 A Accumulator Internal data transfer or instruction operand holding can not be addressed 2 CONT Control Register TEE INTE INT 15 TE PSR2 PsR1 PSRO Bit 0 PSRO Bit 2 PSR2 TCC prescaler bits This specification is subject to change without prior notice 15 2002 05 06 EM78257 MASK ROM Bit 4 TE TCC signal edge 0 increment if the transition from low to high takes place on TCC pin 1 increment if the transition from high to low takes place on TCC pin Bit 5 TS TCC signal source 0 internal instruction cycle clock 1 transition on TCC pin Bit 6 INT Interrupt enable 0 masked by DISI or hardware interrupt 1 enabled by ENI RETI instructions Bit 7 INTE INT signal edge 0 interrupt occurs at the rising edge on the INT pin 1 interrupt occurs at the falling edge on the INT pin The CONT register is both readable and writable Bit 6 is read only 3 IOC50 10C70 I O Port Control Registers 1 put the relative I O pin into h
22. a duration of one instruction cycle clock signal input Default value after a power on reset m General purpose pin Open drain Default value after a power on reset 55 1 3 General purpose pin 16 18 Pull_high pull_down Wake up from sleep mode when the status of the pin changes Default value after a power on reset R OUT 13 O IR mode output pin capable of sinking 30mA INT 26 1 External interrupt pin triggered by falling edge 4 gt the input pin of Vin of a comparator the input pin of Vin of a comparator Pin CO1 4 are the outputs of the comparators This specification is subject to change without prior notice 4 2002 05 06 EM78257 MASK ROM External Counter input 7 18 17 RESET If set as RESET and remains at logic low the device will be reset Voltage on RESET Vpp must not exceed Vdd during the normal mode Pull high is on if defined as RESET Ground vss 5 5 56 57 6 CO2 P52 P51 CO1 TCC3 CIN2 P53 PS0 CINI TCC4 TCC CIN2 P54 P55 CIN1 OSCI RESET P71 Z P70 0SCO VSS VDD INT P60 P67 IR OUT TCC1 CIN3 P61 P66 CIN4 TCC2 CIN3 P62 P65 CIN4 CO3 P63 64 4 Fig 2 Pin Assignment EM78257B Table 2 Pin Description EM78257B aa EN XTAL type Crystal input terminal or external clock input pin EN RC type RC
23. oscillator input pin XTAL type output terminal for crystal oscillator or external clock input pin RC type clock output with a duration of one instruction cycle External clock signal input P70 P71 16 5 General purpose I O P71 is input pin only Default value after a power on reset P60 P67 7 14 General purpose I O pin Open_drain Default value after a power on reset P50 P57 General purpose pin ua Pull high pull down Wake up from sleep mode when the status of the pin changes Default value after a power on reset IR OUT 14 O IR mode output pin capable of sinking 30mA INT 7 External interrupt pin triggered by falling edge CIN1 CIN1 m 18 t gt the input pin of Vin of a comparator This specification is subject to change without prior notice 5 2002 05 06 EM78257 MASK ROM the input pin of Vin of a comparator Pin CO1 4 are the outputs of the comparators External Counter input If set as RESET and remains at logic low the device will be reset Voltage on RESET Vpp must not exceed Vdd during the normal mode Pull high is on if defined as RESET This specification is subject to change without prior notice 6 2002 05 06 EM78257 MASK ROM 4 FUNCTION DESCRIPTION
24. remains active and the interrupt stays functional during SLEEP mode If a mismatch occurs the interrupt will wake up the device from SLEEP mode 2002 05 06 This specification is subject to change without prior notice 39 EM78257 MASK ROM power consumption should be taken into consideration for the sake of power saving If the function is unemployed during the SLEEP mode turn off comparators before entering into sleep mode 4 10 The Initialized Values after Reset Table 13 Summary of the Initialized Values for Registers pen Wake Up from Pin Change P P P P j P P j P j P RESET and WDT 1 1 1 1 1 1 1 1 Wake Up tromPinChange P Pe Pe P P P j P Bit Name octo e a ep Wake up from Pin Change P P P P P P oco Power On o o jo jo jo o o o TCCCR mesTamawoT o o o o o o o o Wake Up from Pin Change P P P P j P P j P o o jo o j o o j o j o o o o o o j o o j o m p T m gt X ui ox 6989 Wake Up from Pin Change Power RESET and WDT 1 PD5 PD56 PD55 PD54 PD53 PD52 PD51 PD50 IOCBO NIA PDCR Wake Up from Pin Change i N RESET and WDT ODCR Wake Up from Pin Change 1 1 1 1 RESET WDT 1 Wake Up from Pin Cha
25. 0 Instruction 1 NOR cut i TCC Input Timing CLKS 0 Bec ax J LJ LI LI rice This specification is subject to change without prior notice 65 2002 05 06 EM78257 MASK ROM 5 ABSOLUTE MAXIMUM RATINGS 0 C 70 C Storage temperature 65 C to 150 C Input voltage 0 3V to 6 0V 2 3 t 60V This specification is subject to change without prior notice 66 2002 05 06 EM78257 MASK ROM 6 ELECTRICAL CHARACTERISTICS 6 1 DC Electrical Characteristic Ta 0 C 70 C VDD 5 0V 5 VSS 0V XTAL VDDto3V A VDD to 3V Two cycle with two clocks Fxt XTAL VDD to 5V y RC VDD to 5V 5 1 100 pF 20 KHz X Input Leakage Current for VIN VDD VSS input pins ojo VIH1 Input High Voltage Ports 5 6 VIL1 Input Low Voltage Ports 5 6 VIHT1 Input High Threshold RESET TCC Voltage VILT1 Input Low Threshold RESET TCC Voltage Input High Threshold RESET TCC 5 VILT2 Input Low Threshold RESET TCC Voltage VDD 3V Clock Input High OSCI A Clock Input Low OSCI Output High Voltage E VOH1 Ports 5 6 IOH 9 0 mA 2 Output Low Voltage VOL1 Ports 5 6 IOL 9 0 mA Pull high current Pull high active input pin at VSS 50 Pull down current Pull down active input pin at VDD 25 ISB Power down current All input and pins at VDD output floating WDT enabled SB floating WDT disabled Operating supply current RES
26. 05 06 EM78257 MASK ROM 5 IR mode timing rose DU UA AAA AUI UTAH Eno LI dH E start start IROUT 2 Software time E Low time Register 3 High time Register 2 Interrupt to CPU Number of pulses 2 IR OUT CASE 2 L Fig 30 CASE 1shows a typical pulse train DP 00 MF 10 HF 0 LGP 0 PWM 0 CASE 2 shows the same pulse train after being modulated with a frequency of 1 4Fosc DP 00 MF 10 HF 1 LGP 0 PWM 0 rose UUM L ww 1 4 del e ub ee Le G start L start 1 gt lt Interrupt to CPU Software time 4 Number of pulses 3 ow Se BIRDS Low time Register 3 Fig 31 CASE 1 shows a typical long pulse DP 00 MF 10 HF 1 LGP 1 PWM 0 CASE 2 shows the same long pulse after being modulated with a frequency of 1 4Fosc DP 00 MF 10 HF 1 LGP 1 PWM 0 re AUTE UU eo t OUT 2 22 2 Low time ister High time egister 2 Fig 32 Continuous pulse train DP 00 MF 10 HF 0 LGP 0 PWM 1 This specification is subject to change without prior notice 60 2002 05 06 EM78257 e Bit 11
27. 1 3F Fig 5 Data memory configuration This specification is subject to change without prior notice 10 EM78257 MASK ROM 4 R3 Status Register RST ocs PSO T P z pc Bit 0 C Carry flag Bit 1 DC Auxiliary carry flag Bit 2 Z Zero flag Set to 1 if the result of an arithmetic or logic operation is zero e Bit 3 P Power down bit Set to 1 during power on or by a WDTC command and reset to 0 by a SLEP command Bit 4 T Time out bit Set to 1 with the SLEP and WDTC command or during power on and reset to 0 by WDT time out e Bit5 PS0 Page select bits PSO is used to select a program memory page When executing a JMP CALL or other instructions that causes the program counter to change e g MOV R2 A 50 is loaded into the 11th bit of the program counter selecting one of the available program memory pages Note that RET RETL RETI instruction does not change the 50 bits That is the return will always be back to the page from where the subroutine was called regardless of the current PSO bit setting PSO Program memory page Address 0 Page 0 000 3FF Page 1 400 7FF Bit6 IOCS Select the Segment of the control register 0 Segment 0 IOC50 IOCFO selected 1 Segment 1 OC51 IOCF1 selected Bit 7 RST Bit for reset type Set to 1 if wake up from sleep on pin change or comparator status change Set to 0 if wake up from other
28. 8 2002 05 06 EM78257 MASK ROM Table 29 TCCX Control Register 7 6 5 4 3 2 1 0 2 TCC4E TCC6E TCCBE Bit 4 TCCBE Control bit which is used to enable most significant byte of counter 1 Enable most significant byte of TCCBH 0 Disable most significant byte of TCCBH default value Table 30 IR Control Register 7 6 5 4 3 2 1 0 DP1 DPO MF1 MFO IRE HF LGP PWM e Bit Pulse Width Modulation When PWM 1 and the LSB Counter amp MSB Counter are disabled a continuous pulse train is generated and the output signal is actually a PWM waveform format of PWM e Bit 1 LGP Long Pulse When LGP 1 the contents of the High time register are ignored A single pulse is generated Its pulse is determined as shown below Pulse width Contents of Low time register x number of pulse x 1 Fosco If HF 1 this pulse is modulated with Frequency Fosco selected by 1 0 2 HF High Frequency When HF 1 the Low time part of the generated pulse is modulated with Frequency Fosco Bit 3 IRE Infrared Remote Enable bit 0 Disable IRE Disable H W Modulator Function 1 Enable IRE Ignored RB Bit4 TCCBTE Bits TCCBTS and TCCBX set as decrement counter Enable H W Modulator Function Bit 4 Bit 5 MF0 MF1 Modulated frequency Fosco Fosc 1 NEM MEN CHE This specification is subject to change without prior notice 59 2002
29. B check for line contention by checking for an inactive level on CLK at interval not to exceed 100u seconds Contention occurs when the system lowers CLK to inhibit EM78257A B output after EM78257A B has started a transmission If this occurs before the rising edge of the tenth clock EM78257A B internally stores its buffer and returns DATA and CLK to an active level If the contention does not occur by the tenth clock the transmission is completed Following a transmission the system inhibits EM78257A B by holding CLK low until it can service the input or until the system receives a request to send a response from 78257 3 Receiving DATA from system to EM78257A B Inhibit ist 2nd 9th 10th 11th CLK CLK CLK CLK CLK CLK Tmea DATA Start bit Bit0 Bit7 Parity Bit Stop bit Line 5 Bit System first checks if EM78257A B is transmitting data If transmitting the system can override the output by forcing CLK to an inactive level prior to the tenth clock If EM78257A B transmission is beyond the tenth clock the system receives the data If EM78257A B is not transmitting or if the system choose to override the output the system forces CLK to an inactive level for a period of not less than 100us while preparing for output When the system is ready to output start bit 0 it allows CLK to go to active level If request to send is detected EM78257A B clocks 11 bits Following the tenth clock EM78257A
30. B checks for an active level on the DATA line and if found forces DATA to low and clock once more If framing error occurs EM78257A B continues to clock until DATA is high then clocks the line control bit and requests for a Resend When the system sends out a command or data transmission that requires a response the system waits for EM78257A B to respond before sending its next output This specification is subject to change without prior notice 53 2002 05 06 EM78257 MASK ROM 1 2 1 2 71 22 INPUT IMPEDANCE MAX 8 4 TYP MN amp A A amp amp A A MP 52 S 9 ae 42 a WP ae ae ge oe 2 lt VOLTS LIN In Oscillating Frequency 34 3 KHz 4 14 INFRARED REMOTE APPLICATION MODE 1 Overview amp Features Overview EM78257A B is designed for use in universal infrared remote commander applications Fig 29 shows the hardware modulator of EM78257A B It can generate programmable pulse trains for driving an infrared LED Features Power saving Idle and Stop modes are provided This specification is subject to change without prior notice 54 2002 05 06 EM78257 MASK ROM Hardware Modulator providing pulse bursts with programmable duty factor for each pulse programmable number of pulse Watchdog timer to keep the transmitter from being locked or malfunction On chip oscillator 455kHz to 24MHz ae en
31. ET High Fosc 32KHz Crystal ICC1 VDD 3V at two clocks type two clocks output pin floating WDT disabled Operating supply current RESET High Fosc 32KHz Crystal ICC2 VDD 3V at two clocks type two clocks output pin floating WDT enabled ICC3 Operating supply current RESET High 2 2 Crystal VDD 5 0V at two clocks type two clocks output pin floating ICC4 Operating supply current RESET High Fosc 4MHz Crystal VDD 5 0V at two clocks type two clocks output pin floating gt fe HERREN This specification is subject to change without prior notice 67 2002 05 06 EM78257 MASK ROM 6 2 AC Electrical Characteristic 0 70 C VDD 5V 5 VSS 0V Symbo Parameter Condiios Min Typ 2 Instruction cycle time Crystal type CLKS 0 RC type 500 Ttce TCCinpuperod Tins 20yN Device reset hold time Ta 25C 29 Tset Inputpinsetuptime Thold Inputpinholdtime Output pin delay time N selected prescaler ratio Input CLK dutycycle 4 50 p EE 8 10 20 1 50 This specification is subject to change without prior notice 68 2002 05 06 EM78257 MASK ROM APPENDIX Package Types OTP MCU Package Type Pin Count Package Size EM78257AP DIP 300mil EM78257BM SOP 300mil This specification is subject to change without prior notice 69
32. Low voltage 2 3 4V 1 High voltage 4 5 5V Bit 12 Not used Instruction Set Each instruction in the instruction set is a 13 bit word divided into an OP code and one or more operands Normally all instructions are executed within one single instruction cycle one instruction consists of 2 oscillator periods unless the program counter is changed by instruction MOV R2 A ADD 2 or by instructions of arithmetic or logic operation on R2 e g SUB R2 A BS C R2 6 CLR R2 In this case the execution takes two instruction cycles If for some reasons the specification of the instruction cycle is not suitable for certain applications try modifying the instruction as follows A Modify one instruction cycle to consist of 4 oscillator periods B Execute within two instruction cycles the JMP CALL RET RETL RETI commands or the conditional skip JBS JBC JZ JZA DJZ DJZA which were tested to be true The instructions that are written to the program counter should also take two instruction cycles Case A is selected by the CODE Option bit called CLKS One instruction cycle consists of two oscillator clocks if CLKS is low and four oscillator clocks if CLKS is high Case B is selected by another CODE Option bit called CYES Execution of the instructions listed in Case B takes one instruction cycle if CYES is low and takes two instruction cycles if CYES is high Case A and Case
33. MOUSEN MOUSEN ZI TCC5 MOUSEN After MCU process send data to PC TCCC UP DOWN Counter Fig 27 Mouse Function Diagram This specification is subject to change without prior notice 49 2002 05 06 2 Function Description The following describes the function of each block and signal of Fig 27 depicting how to complete a Mouse function P61 X1 Use current comparator to measure photo couples ON or OFF P66 X2 Four photo couple singles denoting UP DOWN LEFT and RIGHT states P51 Y1 During scanning period as long as the photo couples state changes the value of P50 Y2 vertical or horizontal counter will increase or decrease accordingly 56 21 Z axis inputs P57 Z2 Photo mode Current comparator input Comparator Output level is decided by comparing the value of its two pins Counter Recording the horizontal vertical or rolling shifting values 3 Programming the Related Registers When defining MOUSE mode refer to the related register of its operation as shown in the Table 20and Table 21 below Table 20 Related Control Registers of the MOUSE Mode Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit3 Bit 2 Bit1 Bit 0 CONT INTE O INT O TS O TE O 0 PSR2 0 PSR1 0 PSRO O 0x08 INTC IOC80 2 0 TCC4E 0 6 0 TCCBE O 0 Ox0A TCR I RA 0 _ 0 v 0o OXOB TCR2JRB 0 0 TCCBTS 0 0 0
34. OUT4 CMPOUT3 CMPOUT2 CMPOUT1 0 TCCCIF TCCBIF TCCAIF 4 9 Comparator EM78257A B has four comparators consisting of two analog inputs and one output The comparators can be employed to wake up from sleep mode Fig 15 and Fig 16 show the circuit of the comparator CO2 COI CIN2 CO2 ce CIN2 CIN2 __ L 2 78257 LJ EM78257B CIN3 CIN4 CIN3 CIN4 CIN3 CIN4 CO3 4 CIN3 CIN4 LY CO4 Fig 15 Comparator Pin Assignments This specification is subject to change without prior notice 2002 05 06 EM78257 MASK ROM Fig 16 Comparator Operating Modes 1 External Reference Signal The analog signal that is presented at Cin compares to the signal at Cin and the digital output CO of the comparator is adjusted accordingly reference signal must be between Vss and Vdd reference voltage can be applied to either pin of a comparator Threshold detector applications may use the same references comparator can operate from the same or different reference sources There are 16 combinations of the negative inputs of the four comparators 2 CIO CO Input combine status Comment 1 2 3 and 4 gt negative inputs ofofo i 12 Eme negate in
35. OV A 0x00 IOW 0x07 MSB 0 As soon as the LSB Counter Register is loaded the Hardware Modulator is started and IR OUT becomes active LOW Simultaneously the contents of the Low time register are loaded into the Pulse Timer which is then decremented by 1 every oscillator clock cycle When the value held in the Pulse Timer becomes zero the contents of the LSB amp MSB Counter are decremented by 1 and IR OUT become inactive HIGH The contents of the High time register are now loaded into the Pulse Timer which is decremented by 1 every oscillator clock cycle When the value held in the Pulse Timer becomes zero IR OUT becomes active LOW One pulse cycle has now been generated The process of alternately loading the contents of the Low time register and High time register into the Pulse Timer continues until the contents of the LSB amp MSB Counter become zero When this occurs TCCBIF is asserted an interrupt to the CPU is generated and the interrupt flag is raised stopping the operation of the Hardware Modulator If TCCBIF want to be clear the IR must be disable firstly The programmed pulse train has now been generated If the Hardware Modulator want to be restarted we must disable IR in advance and then enable IR again The time delay between two pulse trains is determined by software 3 Pin Description SYMBOL PIN DESCRIPTION P60 to P66 7 13 Standard I O Port lines generally used for keypad scanning
36. S a serial resistor may be necessary for AT strip cut crystal or low frequency mode OSCI 78 257 RS C2 Fig 22 Circuit for Crystal Resonator Table 16 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators Oscillator Type Frequency Mode C1 pF C2 pF Ceramic Resonators HXT a E 200KHz Crystal Oscillator 455KHz 20 40 20 150 1 0MHz 15 30 15 30 2 0MHz 4 0MHz This specification is subject to change without prior notice 45 2002 05 06 EM78257 MASK ROM OSCI EM78257A B EM78257A B Fig 24 Circuit for Crystal Resonator Parallel Mode 3 External RC Oscillator Mode For some applications that do not need to have its timing to be calculated precisely the RC oscillator IV 12 3 1 offers a lot of cost savings Nevertheless it should be noted that the frequency of the RC oscillator is influenced by the supply voltage the values of the resistor Rext the capacitor Cext and even by the operation temperature Moreover the frequency also changes slightly from one chip to another due to the manufacturing process variation In order to maintain a stable system frequency the values of the Cext should not be less than 20pF and that the value of Rext should not be greater than 1 M ohm If they cannot be kept in this range the frequency is easily affected by noise humidity and leakage The smaller the Rext in the RC oscillator the faster its frequ
37. WDTE PWRO PWR2 in IOCE WDT timeout Fig 6 Block Diagram of TCC and WDT 4 4 Ports The I O registers Port 5 Port 6 and Port 7 are bi directional tri state I O ports Port 5 is pulled high internally by software Likewise P6 has its open drain output also through software Port 5 features an input status changed interrupt or wake up function and is pulled down by software Each I O can be defined as input or output pin by the I O control register IOC5 IOC7 The I O registers and I O control registers are both readable and writable The I O interface circuits for Port 5 Port 6 and Port are shown in Fig 7 Fig 8 and Fig 9 respectively This specification is subject to change without prior notice 27 2002 05 06 EM78257 MASK ROM PCRD c clk PCWR ea L PORT m Q E D IOD c iE PDRD v 0 M 1 U gt X NOTE Open drain is not shown in the figure Fig 7 The circuit of I O port and I O control register for Port 6 and Port7 PCRD Pg 4 ae PCWR L P60 INT d oO P lt PORT D M R x a L Bit6 of IOCEO 9 db P 0 D Qi gt M E TM 1U en a gt 5 L a x INT NOTE Open drain is not shown
38. bject to change without prior notice 38 2002 05 06 EM78257 MASK ROM Toce COIEX e e From OP I O a Q D Q D To CMPOUT COIEX LN To LL CMPXIF CMPXIE Fig 17 The Output Configuration of a Comparator 3 Programming the Related Registers When defining Comparators refer to the related registers of its operation as shown in Table 11 and Table 12 below Table 11 Related Control Registers of the Comparators Bits Bits Bit2 Bit1 Bito 4 0 CE3 0 2 0 CE1 0 o o o o cia 20 Table 12 Related Status Data Registers of Comparators Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CMPOUT R9 CMPOUT4 0 CMPOUT3 0 CMPOUT2 0 CMPOUT1 0 0 TCCCIF O TCCBIF O TCCAIF O Address Name Bit 7 0x09 CMPCR IOC90 4 0 COIE3 0 COIE2 0 COIE1 0 Bit 2 Bit 1 Bit 0 0x09 ISR RF 0 0 2 0 CMP1IF O 0 EXIF O ICIF O TCIF O 4 Interrupt INT and CMPXIE must be enable Interrupt occurs whenever a change takes place on the output pin of the comparators actual changes on the pins be determined by reading the bits CMPOUTX R9 lt P7 P4 gt CMPXIF the comparator interrupt flag can only be cleared by software 5 Wake Up from SLEEP mode If enabled the comparators
39. ce 21 2002 05 06 EM78257 MASK ROM Example 2 1 0 1010 gt Comparator 4 combined together with Comparator 3 and Comparator 2 and both CIN2 and CIN3 work as normal I O pins CIN1 col CINI gt CIN2 CIN2 Normal I O CIN3 CIN3 Normal I O CO3 CIN4 CO4 CIN4 7 IOCBO Pull down Control Register eS ew EE E Bit 0 PD50 Control bit is used to enable the pull down of P50 pin 0 Enable internal pull down 1 Disable internal pull down Bit 1 PD51 Use to enable the pull down of P51 pin Bit 2 PD52 Use to enable the pull down of P52 pin Bit 3 PD53 Use to enable the pull down of P53 pin Bit 4 PD54 Use to enable the pull down of P54 pin Bit 5 PD55 Use to enable the pull down of P55 pin Bit 6 PD56 Use to enable the pull down of P56 pin for EM78257B only Bit 7 PD57 Use to enable the pull down of P57 pin for EM78257B only e OCBO Register is both readable and writable 8 IOCCO Open drain Control Register ge epe ze e e e Bit 0 OD60 Use to enable the open drain of P60 pin This specification is subject to change without prior notice 22 2002 05 06 EM78257 MASK ROM 0 Disable open drain output 1 Enable open drain output Bit 1 OD61 Use to enable the open drain of P61 pin Bit 2 OD62 Use to enable the open drain of P62 pin Bit 3 OD63 Use to enable the ope
40. circuit Power down SLEEP mode Five interrupt sources TCC overflow interrupt Input port status changed interrupt wake up from the sleep mode External interrupt OUT interrupt This specification is subject to change without prior notice 2 2002 05 06 EM78257 MASK ROM Comparators status change interrupt Programmable free running watchdog timer 8 programmable pull high I O pins 8 programmable open drain I O pins e 8 programmable pull down I O pins Two clocks per instruction cycle Package types 18 pin DIP 300mil EM78257AP 20 pin DIP 300mil EM78257BP 18 pin SOP 300mil EM78257AM 20 pin SOP 300mil EM78257BM Power on voltage detector available for both EM78257A and EM78257B This specification is subject to change without prior notice 3 2002 05 06 EM78257 MASK ROM 3 ASSIGNMENT CO2 P52 P51 CO1 TCC3 CIN2 P53 P50 CIN1 TCC4 TCC CIN2 P54 P55 CIN1 OSCI RESET P71 P70 OSCO VSS S VDD INT P60 gt P67 IR OUT TCC1 CIN3 P61 P66 CIN4 TCC2 CIN3 P62 P65 CIN4 63 64 4 Fig 1 Pin Assignment EM78257A Table 1 Pin Description EM78257A Symbol PinNo Type ie 1 1 TA eC apt ia oma amp scr XTAL type Crystal input terminal or external clock input pin RC type RC oscillator input pin a lO XTAL type output terminal for crystal oscillator or external clock input pin RC type clock output with
41. ctional I O pin 0 Define P50 as a bi directional I O pin Bit 7 TCC2E Control bit used to enable the second input of counter For EM78257A 1 If MOUSEN equal to 1 pin 12 is defined as another input pin of TCCA If MOUSEN equal to 0 pin 12 is a bi directional pin 0 Define P66 as a bi directional I O pin For EM78257B 1 If MOUSEN equal to 1 pin 13 is defined as another input pin of TCCA If MOUSEN equal to 0 pin 13 is a bi directional I O pin 0 Define P66 as a bi directional I O pin 5 1 90 CMP Control Register 7 6 5 4 3 2 1 0 COIE4 COIE3 COIE2 COIE1 CE4 CE3 CE2 CE1 e Bit 0 CE1 Comparator CO1 enable bit 0 Comparator is off default value For EM78257A Pin 18 can choose P51 TCC3 only If MOUSEN is 1 define as an input of TCCB TCC3 If MOUSEN is 0 then the choice is decided by TCCBTS of RB Pin 17 can choose P50 or TCC4 only If MOUSEN is 1 and TCC4E of IOC80 is 1 also then choose TCC4 otherwise choose P50 Pin 16 can choose P55 or OSCI only and the choice is decided by Bit 9 8 7 of CODE option When choice is 1 1 1 then Pin 16 is defined as P55 otherwise the status is defined as OSCI For EM78257B This specification is subject to change without prior notice 17 2002 05 06 EM78257 MASK ROM Pin 19 can choose P51 TCC3 only If MOUSEN is 1 define as an input of TCCB TCC3 if MOUSEN is 0
42. d start Elapse time by software d Low time interrupt gt pulse 1 pulse 2 pulse 3 Low time 2 Low time register 2 High time 4 High time register 4 number of pulse 3 Fig 28 Example Pulse Train Output of IR OUT Pin High Time Register TCCBH MSB Counter TCCBL LSB Counter Note In software design Low time and High time registers cannot set 0 at initial state H W Modulator TCCBIF 1 overflow Fig 29 Hardware Modulator This specification is subject to change without prior notice 55 2002 05 06 EM78257 MASK ROM 2 Function Description The following describes the function of each block and single for Fig 29 which depicts how to complete IR kernel hardware modulator Low time Register The 8 bit Low time register controls the active or Low period of the pulse The decimal value of its contents determines the number of oscillator cycles indicating that the IR OUT pin is active The active period of IR OUT can be calculated as follow tLow decimal value held Low time register fosco High time Register 8 bit High time register control the inactive or High period of the pulse The decimal value of its contents determines the number of oscillator cycles indicating that the IR OUT pin is active The inactive period of IR OUT can be calculated as follow tuigh decimal value held in High time register fosco
43. ency will be On the contrary for very low Rext values for instance 1 KQ the oscillator becomes unstable because the NMOS cannot discharge the current of the capacitance correctly Based on the reasons above it must be kept in mind that all of the supply voltage the operation temperature the components of the RC oscillator the package types the way the PCB is layout will affect the system frequency This specification is subject to change without prior notice 46 2002 05 06 EM78257 MASK ROM e Vcc gt Rext osci EM78257A B Cext Fig 25 Circuit for External RC Oscillator Mode Table 17 RC Oscillator Frequencies Average Fosc 5V 25 C Average Fosc 3V 25 C 3 18 MHz 2 75 2 20 pF 2 1 MHz 2 0MHz 1 14 MHz 1 12 MHz 100k 118 KHz 121 KHz 1 25 MHz 1 20 KHz 100 pF 830 KHz 815 KHz 435 KHz 440 KHz 100k 46KHz 48 KHz 560 KHz 545 KHz 300 pF 370 KHz 360 KHz 10k 195 KHz 195 KHz 100k 20 KHz 21 KHz Note 1 Measured on DIP packages 2 Design reference only the frequency value vary with temperature VDD and process 3 The frequency drift about 30 4 RC Oscillator Mode with Internal Capacitor If both precision and cost are taken into consideration EM78257A B also offers a special oscillation mode which is equipped with an internal capacitor and an external resistor connected to Vcc The internal capacitor functions as temperature compensator In order to obtain more accurate frequency a precise resis
44. errupt 2 Port 5 Input Status Changed Interrupt 3 External interrupt P60 INT pin 4 Comparators status change 5 5 IR OUT interrupt Before the Port 5 Input Status Change Interrupt is enabled reading Port 5 e g MOV R5 R5 is necessary Each Port 5 pin will have this feature if its status changes The Port 5 Input Status Change Interrupt will wake up the EM78257A B from the sleep mode if it is enabled prior to going into the sleep mode by executing SLEP instruction When wake up occurs the controller will continue to execute program in line if the global interrupt is disabled If the global interrupt is enabled it will branch out to the interrupt vector 3FEH RF is the interrupt status register that records the interrupt requests in the relative flags bits IOCFO is an interrupt mask register The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction Once in the interrupt service routine the source of an interrupt can be determined by polling the flag bits in RF The interrupt flag bit must be cleared by instructions before leaving the This specification is subject to change without prior notice 33 2002 05 06 EM78257 MASK ROM interrupt service routine to avoid recursive interrupts The flag except ICIF bit in the Interrupt Status Register RF is set regardless of the status of its mask bit or the execution of ENI Note that the outcome of RF will be the logic AND o
45. f RF and IOCFO refer to Fig 12 The RETI instruction ends the interrupt routine and enables the global interrupt the execution of When an interrupt is generated by the Timer clock counter when enabled the next instruction will be fetched from address 3FA 3F8 3F6 and 3F4H TCC TCCA TCCB and TCCC When an interrupt is generated by the Comparators when enabled the next instruction will be fetched from address 3F2 3F0 3EE or 3ECH individually CO1 CO2 CO3 or CO4 Before the interrupt subroutine is executed the contents of ACC and the R3 register will be saved by hardware If another interrupt occurred the ACC and R3 will be replaced by the new interrupt After the interrupt service routine is finished ACC and R3 will be pushed back L p E 228 IRQn CLK P NN _ INT RFRD IRQm E E a RF DISI E D CLK lt ar IOCFWR RESET IOCF F Fig 12 Interrupt input circuit Interrupt occurs Interrupt sources ENI DISI Fig 13 Interrupt backup diagram In 78257 each individual interrupt source has its own interrupt vector as depicted in Table 7 This specification is subject to change without prior notice 34 2002 05 06 EM78257 MASK ROM Table 7 Interrupt vector Interrupt vector Interrupt status Comparator CO4 interrupt 4 8 Timer Counter 1 Overview
46. gh to low leading edge takes place on the TCC2 pin Bit 1 TCCATS TCCA signal source 0 internal instruction cycle clock 1 transition on the TCC1 pin Bit 2 TCCAIE TCCAIF interrupt enable bit 0 disable TCCAIF interrupt 1 enable TCCAIF interrupt Bit 3 Bit 7 Not used read as 0 Table 23 TCCX Status Register 2 7 6 5 4 3 2 1 0 TCCBIE TCCBTS TCCCIE TCCCTS Bit 0 TCCCTE TCCC signal edge 0 increment if the transition from low to high leading edge takes place on the TCC6 pin 1 increment if the transition from high to low leading edge takes place on the TCC6 pin Bit 1 TCCCTS TCCC signal source 0 internal instruction cycle clock 1 transition on the TCC5 pin Bit 2 TCCCIE TCCCIF interrupt enable bit 0 disable the TCCCIF interrupt 1 enable the TCCCIF interrupt Bit 3 Not used Bit 4 TCCBTE TCCB signal edge 0 increment if the transition from low to high leading edge takes place on the TCC4 pin 1 increment if the transition from high to low leading edge takes place on the TCCA pin Bit 5 TCCBTS TCCB signal source 0 internal instruction cycle clock 1 transition on the TCC3 pin Bit 6 TCCBIE TCCBIF interrupt enable bit 0 disable the TCCBIF interrupt 1 enable the TCCBIF interrupt Bit 7 Not used This specification is subject to change without prior notice 51 2002 05 06 EM78257 MASK ROM Table 24 MOUSE Control Register
47. hange interrupt 4 Enable interrupt Set IOCF 1 Interrupt vector 3FEH 5 Execute SLEP instruction b After Wake up 1 IF ENI 2 Interrupt vector 3FEH 2 IF DISI Next instruction 4 5 RESET and Wake up 1 RESET A RESET is initiated by one of the following events 1 Power on reset 2 RESET pin input low or 3 Watch dog timer time out if enabled The device is kept in a RESET condition for a period of approximately 18ms or 1ms one oscillator start up timer period after the reset is detected The initial address is 000h Once the RESET occurs the following events are performed The oscillator is running or will be started Program Counter R2 is set to all All I O port pins are configured as input mode high impedance state The Watchdog timer and prescaler are cleared When power is switched on the upper 3 bits of R3 are cleared The bits of the CONT register are set to all 1 except for the Bit 6 INT flag bits of the IOCBO register are set to all 1 IOCCO register is cleared The bits of the IOCDO register are set to all 1 Bit 7 of the IOCEO register is set to 1 and the others are cleared RF and IOCFO register are cleared The sleep power down mode is attained by executing the SLEP instruction While entering sleep mode WDT if enabled is cleared but keeps on running The controller can be awakened by 1 externa
48. ice 23 2002 05 06 EM78257 MASK ROM When EIS is 0 the path of INT is masked When EIS is 1 the status of INT pin can also be read by way of reading Port 6 R6 Refer to Fig 8 EIS is both readable and writable Bit3 5 Not used e Bit 0 PSWO Bit 2 PSW2 WDT prescaler bits 11 IOCFO Interrupt Mask Register 7 6 5 4 3 2 1 0 CMP4IE CMP2IE 1 PPC CMP EXIE ICIE TCIE Bit 0 TCIE TCIF interrupt enable bit 0 disable TCIF interrupt 1 enable TCIF interrupt Bit 1 ICIE ICIF interrupt enable bit 0 disable ICIF interrupt 1 enable ICIF interrupt Bit 2 EXIE EXIF interrupt enable bit 0 disable EXIF interrupt 1 enable EXIF interrupt Bit 3 CMP PPC Wake up by which Interrupt sources 0 PPC wake up by Port 5 input status change if enabled 1 CMP wake up by comparators status change if enabled Bit 4 CMP1IE CMP1IF interrupt enable bit 0 disable CMP1IF interrupt 1 enable CMP1IF interrupt Bit 5 CMP2IE CMP2IF interrupt enable bit 0 disable CMP2IF interrupt 1 enable CMP2IF interrupt Bit 6 CMP3IF interrupt enable bit This specification is subject to change without prior notice 24 2002 05 06 EM78257 MASK ROM 0 disable CMP3IF interrupt 1 enable CMP3IF interrupt Bit 7 CMP4IE CMP3IF interrupt enable bit 0 disable CMPAIF interrupt 1 enable CMPAIF interrupt Individual interrupt is enabled by setting its associa
49. igh impedance while defines the relative I O pin as output Only the higher 2 bits of IOC5 can be defined for EM78257B only e Only the lower 2 bits of IOC7 be defined the others bits are not available 5 6 and IOC7 are both readable and writable 4 OC80 Control Register 7 6 5 4 3 2 1 0 2 TCC4E TCC6E TCCBE Bit O Bit 3 Not used e Bit 4 TCCBE Control bit is used to enable the most significant byte of counter 1 Enable the most significant byte of TCCBH TCCB is a 16 bits counter 0 Disable the most significant byte of TCCBH default value TCCB is 8 bits counter Bit 5 TCC6E Control bit used to enable the second input of counter for EM78257B only For EM78257B 1 If MOUSEN equal to 1 pin 20 is defined as another input pin of TCCC If MOUSEN equal to 0 pin 20 is a bi directional I O pin This specification is subject to change without prior notice 16 2002 05 06 EM78257 MASK ROM 0 Define P57 as a bi directional I O pin Bit 6 TCC4E Control bit used to enable the second input of counter For EM78257A 1 If MOUSEN equal to 1 pin 17 is defined as another input pin of TCCB If MOUSEN equal to 0 pin 17 is a bi directional I O pin 0 Define P50 as a bi directional I O pin For EM78257B 1 If MOUSEN equal to 1 pin 18 is defined as another input pin of TCCB If MOUSEN equal to 0 pin 18 is a bi dire
50. in the figure Fig 8 The Circuit of I O Port and I O Control Register for P60 INT This specification is subject to change without prior notice 28 2002 05 06 PCRD lt PCWR EM78257 MASK ROM P50 P57 d IOD PORT PDWR lt 4 PDRD mo NOTE Pull high down is not shown in the figure Fig 9 The Circuit of I O Port and I O Control Register for P50 P57 IOCF 1 0 P K Interrupt F L a instruction TIo gt 1 gt 7 7 N p R yo OWN 7 CLK op D B N 1 pm L 4 2 gt 2 8 fo DISI instruction N I pup Ec Bc Interrupt Wake up from SLEEP P Next Instruction Wake up from SLEEP Fig 10 Block Diagram of I O Port 5 with Input Change Interrupt Wake up This specification is subject to change without prior notice 29 2002 05 06 EM78257 MASK ROM Table 4 Usage of Port 5 Input Status Changed Wake up Interrupt Function 1 Wake up from Port 5 Input Status Change Port 5 Input Status Change Interrupt a Before SLEEP 1 Read I O Port 5 MOV R5 R5 1 Disable WDT 2 Execute ENI 2 Read I O Port 5 MOV R5 R5 3 Enable interrupt Set IOCF 1 3 Execute or DISI 4 IF Port 5 c
51. l instructions are single cycle fclk 2 or fclk 4 except for the instructions that would change the contents of R2 This instruction will need one more instruction cycle This specification is subject to change without prior notice 8 2002 05 06 EM78257 MASK ROM Stack 0 Stack 1 Stack 2 Stack 3 RET K Stack 4 gt Page 0 Stack 5 SRF Stack 6 400 Stack 7 1 Fig 4 Program counter organization This specification is subject to change without prior notice 9 2002 05 06 00 01 02 03 04 05 06 07 08 09 0 0B oc oD 0 OF 10 11 1E 1F 20 21 3F RO R1 TCC R3 Status R2 PC R4 RSR R5 Port5 R6 Port6 R9 CMPOUT R7 Port RA TCR 1 RC TCCPC RB TCR 2 RD IRCR RE MCR RF ISR 16x8 Common Register STACK 0 STACK 1 STACK 2 STACK 3 STACK 4 STACK 5 STACK 6 STACK 7 R3 lt 6 gt IOCS IOC50 I O CR EM78257 MASK ROM IOC60 I O CR IOC51 TCCA IOC61 TCCBL IOC70 I O CR IOC80 TCCCR IOC90 CMPCR 5 10C71 TCCBH 10C81 TCCC IOC91 LTR IOCBO PDCR IOCCO OPCR IOCDO PHCR IOCA1 HTR IOCB1 PTR IOCEO WDTCR IOCFO IMR 20 32x8 Bank Register Bank 0 3F 20 32x8 Bank Register Bank
52. l reset input on RESET pin 2 WDT time out if enabled This specification is subject to change without prior notice 30 2002 05 06 EM78257 MASK ROM 3 Port 5 input status changed if enabled 4 Comparator status changed The first two cases will cause the EM78257A B to reset The T and P flags of R3 can be used to determine the source of the reset wake up Case 3 is considered the continuation of program execution and the global interrupt ENI or DISI being executed decides whether or not the controller branches to the interrupt vector following wake up If ENI is executed before SLEP the instruction will begin to execute from the address 3FEH after wake up If DISI is executed before SLEP the operation will restart from the instruction right next to SLEP after wake up Only one of Cases 2 and 3 can be enabled before entering the sleep mode That is a if Port 5 input status changed interrupt is enabled before SLEP WDT must be disabled by software However the WDT bit in the option register remains enabled Hence the EM78257A B be awakened only by Case 1 or 3 Similarly the same procedures should be applied if comparator status change interrupt is used The device can be awakened only by Case 1 or 4 b if WDT is enabled before SLEP Port 5 Input Status Change Interrupt must be disabled Hence the EM78257A B can be awakened only by Case 1 or 2 Refer to the section on Interrupt If Port 5 Input Sta
53. lated frequency MF 1 MFO Fosco 0 0 Fosc 1 L0 1 1 0 4 e Bit6 Bit7 DP0 DP1 Ratios of duty and period of modulated frequency MOUSEN Bit O Bit 6 Not used Bit 7 MOUSEN Mouse application Enable bit 0 Disable MOUSEN TCCA TCCB and are increment counters 1 Enable MOUSEN TCCA TCCBL and TCCC work as up down counters The other pin assignment refers to IOC80 and 90 This specification is subject to change without prior notice 14 2002 05 06 EM78257 MASK ROM 14 RF Interrupt Status Register 7 6 5 4 3 2 1 0 CMP4IF CMP3IF CMP2IF CMP1IF EXIF ICIF TCIF 1 means interrupt request and 0 means no interrupt occurs Bit 0 TCIF TCC overflowing interrupt flag Set when TCC overflows and reset by software Bit 1 ICIF Port 5 input status changed interrupt flag Set when Port 5 input changes and reset by software Bit 2 EXIF External interrupt flag Set by on INT pin and reset by software e Bit 3 Unemployed read as 0 Bit 4 CMP1IF Status changed interrupt flag Set as change occurred in the output of Comparator CO1 and reset by software Bit 5 CMP2IF Status changed interrupt flag Set as change occurred in the output of Comparator CO2 and reset by software Bit 6 CMP3IF Status changed interrupt flag Set as change occurred in the output of Comparator and reset by software Bit 7 CMP4IF
54. n drain of P63 pin Bit 4 OD64 Use to enable the open drain of P64 pin Bit 5 OD65 Use to enable the open drain of P65 pin Bit 6 OD66 Use to enable the open drain of P66 pin Bit 7 OD67 Use to enable the open drain of P67 pin e OCCO Register is both readable and writable 9 IOCDO Pull high Control Register ee ee N ee See Bit 0 PH50 Use to enable the pull high of P50 pin 0 Enable internal pull high 1 Disable internal pull high Bit 1 PH51 Use to enable the pull high of P51 pin Bit 2 PH52 Use to enable the pull high of P52 pin Bit 3 PH53 Use to enable the pull high of P53 pin Bit 4 PH54 Use to enable the pull high of P54 pin Bit 5 PH55 Use to enable the pull high of P55 pin Bit 6 PH56 Use to enable the pull high of P56 pin for EM78257B only Bit 7 PH57 Use to enable the pull high of P57 pin for EM78257B only e OCDO Register is both readable and writable 10 IOCEO WDT Control Register wore EIS PSW2 PSW PSWO Bit 7 WDTE Control bit is used to enable Watchdog timer 0 Disable WDT 1 Enable WDT WDTE is both readable and writable e Bit 6 EIS Control bit is used to define the function of P60 INT pin 0 P60 bi directional I O pin 1 INT external interrupt pin In this case the I O control bit of P60 bit of IOC6 must be set to 1 This specification is subject to change without prior not
55. nge TS Bad RESET and WDT Wake Up from Pin Change CMP2IE wa ioco P PD55 P 0 0 55 P z 4j Oo IOC51 TCCA N A IOC61 On On On PH5 PH56 55 IOCDO PHCR On On 4 CCBL7 This specification is subject to change without prior notice 40 2002 05 06 EM78257 MASK ROM RESET and WDT Lo o J o o o o o o Wake Up fom Change e e e e e p pe LCS Bit Name och Power On o o o o o o o j o TCCBH REsETandwoT_ o o o o o o j o o Wake Up from Pin Change P P P P P P P P TCCC6 TCCC5 4 2 1 TCCCO Poweo o o o o o o o o mRESETadWDT o o o o o o o o Wake Up from Pin Change P P P P Pe P P P IOCo1 Power On 0 0 0 0 0 0 0 0 LTR mesetandwoT o o o o o o o o Wake Up from Pin Change P P P P P P P P IOCA1 NIA HTR N A Poweron o o o o o o f o o RESETandwoT o o o o o o o o Wake Up from Pin Change P P P j P j P j P PTR7 PTR6 PTR5 PTR4 PTR3 PTR2 PTR1 PTRO IOCB1 0 N A PTR RESET and WDT Wake Up from Pin Change or INTE PSR2 PSR1 PSRO N A CONT rede sce s gt gt gt T
56. nput edge selectable from the TCC pin If TCC signal source is from internal clock TCC will increase by 1 at every instruction cycle without prescaler As illustrated in Fig 6 selection of CLK Fosc 2 or CLK Fosc 4 depends on the CODE Option bit lt CLKS gt CLK Fosc 2 is selected if the CLKS bit is 0 and CLK Fosc 4 is selected if the CLKS bitis 1 If TCC signal source is from external clock input TCC will increase by 1 at every falling edge or rising edge of the TCC pin The watchdog timer is a free running on chip RC oscillator The WDT will keep on running even after the oscillator driver has been turned off i e in sleep mode During the normal operation or the sleep mode a WDT time out if enabled will cause the device to reset The WDT can be enabled or disabled at any time during the normal mode by software programming Refer to WDTE bit of IOCEO register With no prescaler the WDT time out period is approximately 18 ms NOTE VDD 5V Setup time period 16 5ms 5 VDD 3V Setup time period 18ms 5 This specification is subject to change without prior notice 26 2002 05 06 EM78257 MASK ROM CLK Fosc 2 or Fosc 4 Data Bus t 0 Y M 1 TCC Swn u SYNC TCC RI Pin B gt x 2 cycles J TS TCC overflow interrupt 8 bit Counter RC I PSRO PSR2 WDT 8 bit Counter 8 to 1 MUX 8 to 1 MUX
57. o P66 For EM78257B Pin 11 can choose P64 only Pin 12 can choose P65 only Pin 13 can choose P66 or TCC2 only If MOUSEN is 1 and TCC2E of IOC80 is 1 also then set pin to TCC2 otherwise set to P66 1 Comparator is 4 on For EM78257A Pin 10 can choose P64 or CO4 only and decided by COIE4 of IOC90 Pin 11 can choose CIN4 only Pin 12 can choose P66 4 or 2 and the choice is decided by If CINA was not chosen as comparator1 input this pin will decide to set MOUSEN as 1 and TCC2E of IOC80 is also set as 1 then set the pin to TCC2 otherwise set the pin to P66 For EM78257B Pin 11 can choose P64 or CO4 only and decided by COIE4 of IOC90 Pin 12 can choose CIN3 only This specification is subject to change without prior notice 20 2002 05 06 EM78257 MASK ROM Pin 13 can choose P66 CIN4 or TCC2 and the choice is decided by IOCAO If CIN4 was not chosen as comparator input this pin will decide to set MOUSEN as 1 and TCC2E of IOC80 is also set as 1 then set the pin to TCC2 otherwise set the pin to P66 Bit 4 COIE1 Set P51 as the output of the comparator CO1 CE1 must be enabled 1 output enabled 0 output disabled and carry out the function of P51 Bit 5 COIE2 Set P52 as the output of the comparator CO2 CE2 must be enabled 1 output enabled 0 output disabled and carry out the function of P52 Bit 6 COIE3 Set P63 as the outpu
58. one of them by programming OSC2 0CS1 and OSCO in the CODE Option register Table14 depicts how these five modes are defined The up limited operation frequency of crystal resonator on the different VDDs is listed in Table 15 Table 14 Oscillator Modes defined by OSC2 0SC1 and OSCO 2 Moe OSC2 osc osco IRC Internal RC oscillator mode IC Internal C oscillator mode p 1 o O ERC External RC oscillator mode 1 Lt 0o L HXT High XTAL oscillator mode 0 0 1 LXT Low XTAL oscillator mode o 0 0 lt Note gt The transient point of system frequency between and LXT is around 400 KHz Table 15 The summary of maximum operating speeds Conditions Fxt max MHz Two clocks 2 Crystal Oscillator Ceramic Resonators XTAL EM78257A B can be driven by an external clock signal through the OSCI as shown Fig 21 below This specification is subject to change without prior notice 44 2002 05 06 EM78257 MASK ROM EM78257A B OSCO Fig 21 Circuit for External Clock Input In most applications pin OSCI and pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation Fig 22 depicts such circuit The same thing applies whether it is in the HXT mode or in the LXT mode Table 16 provides the recommended values of C1 and C2 Since each resonator has its own attribute user should refer to its specification for appropriate values of C1 and C2 R
59. out 5 it is recommended that R should not be greater than 40 In this way the voltage in pin RESET will be held below 0 2V The diode D acts as a short circuit at the moment of power down The capacitor C will discharge rapidly and fully Rin the current limited resistor will prevent high current discharge or ESD electrostatic discharge from flowing to pin RESET Vdd e EM78257A B lt 5 IRESET AA e Rin Fig 18 External Power on Reset Circuit 3 Residue Voltage Protection When battery is replaced device power Vdd is taken off but residue voltage remains The residue voltage may trips below Vdd minimum but not to zero This condition may cause a poor power on reset Fig 19 and Fig 20 show how to build a residue voltage protection circuit e e Vee EM78257A B TS E LN IRESET 1N4684 Fig 19 Circuit 1 for the residue voltage protection This specification is subject to change without prior notice 43 2002 05 06 EM78257 MASK ROM e e Vdd EM78257A B Rh IRESET M R2 Fig 20 Circuit 2 for the residue voltage protection 4 12 Oscillator 1 Oscillator Modes 78257 can be operated in the five different oscillator modes such as Internal RC oscillator mode IRC RC oscillator with Internal capacitor mode IC External RC oscillator mode ERC High XTAL oscillator mode HXT and Low XTAL oscillator mode LXT User can select
60. put CIN romal TO pn CIN3 gt negative input CIN 1 2 gt normal O pin This specification is subject to change without prior notice 37 2002 05 06 EM78257 MASK ROM 1 01010 124 CIN4 negative input CIN 1 2 gt normal I O gt negative input CIN 1 3 gt normal VO pin 1 0 1 0 234 CIN4 negative input CIN 2 3 gt normal 11 0 11 1 1 2 3 4 4 gt negative input 2 3 gt normal VO tft foto 32 __ _CIN2 gt negative input CINS gt normal VO pint CIN2 gt negative BUE CIN4 gt normal I O a RR CIN2 gt negative input CIN 3 4 gt normal I O pin ajailli 143 CIN3 gt negative input CIN 1 4 gt normal I O pin Example 2 1 0 1010 gt Comparator 4 combine together with Comparator 3 and Comparator 2 and both of CIN3 CIN2 work as normal I O pins C1 CIN1 col CINI gt CIN2 CIN2 Normal I O CIN3 CIN3 Normal I O CO3 CIN4 CO4 CIN4 2 Comparator Outputs The compared result are stored in the CMPOUT of R9 The comparator outputs can output to P51 P52 P63 and P64 by programming Bits 4 5 6 and 7 lt 90 gt of the CMP control register to 1 P52 P51 P63 and P64 must be configured as output if implemented Fig 17 shows the comparator output block diagram This specification is su
61. reset types R4 RAM Select Register Bits 0 5 are used to select a register address 00 10 3F in the indirect addressing mode Bit 6 is used to select bank 0 or bank 1 Bits 7 is General purpose read write bit See the configuration of the data memory in Fig 5 R5 R6 Port 5 Port 6 R5 and R6 are registers This specification is subject to change without prior notice 11 2002 05 06 EM78257 MASK ROM Only the lower 6 bits of R5 are available applicable to EM78257A upper 2 bits of R5 are fixed to 0 if EM78257A is selected 7 R7 Port 7 7 6 5 4 3 2 1 0 R7 is I O registers Only the lower 2 bits of R7 are available 8 R9 CMPOUT Status Register amp TCC Status Register 7 6 5 4 3 2 1 0 CMPOUT4 CMPOUT2 CMPOUT1 TCCCIF TCCBIF TCCAIF Bit 0 TCCAIF overflowing interrupt flag Set when TCCA overflow reset by software Bit 1 TCCBIF TCCB overflowing interrupt flag Set when TCCB overflow reset by software e Bit 2 TCCCIF TCCC overflowing interrupt flag Set when TCCC overflow reset by software Bit 3 Not used read as 0 Bit 4 CMPOUT1 The output result of the comparator1 Bit 5 CMPOUT2 The output result of the comparator2 Bit 6 The output result of the comparator3 Bit CMPOUTA The output result of the comparator4 Bit 4 Bit 7 are read only 9 RA TCC Control
62. rnal RESET is enabled When programmed to 1 the internal RESET is enabled tied to the internal Vdd and the pin is defined as P71 Setup time Fig 11 Block Diagram of Reset of Controller 4 6 The status of RST T and P of STATUS register A RESET condition is initiated by one of the following events 1 A power on condition 2 A high low high pulse on the RESET pin or 3 Watchdog timer time out The values of RST T and P as listed in Table 5 below are used to check how the processor wakes up This specification is subject to change without prior notice 32 2002 05 06 EM78257 MASK ROM Table 5 shows the events which may affect the status of RST T and P Table 5 The Values of RST T and P after RESET ResetTye RST T Powron 7 Ooa 1 RESET during Operatingmode 0 P P RESET wake up during SLEEP mode o 1 9 WDT during Operating mode o 0 1 WDT wake up during SLEEP mode o 0 9 Wake Up on pin change during SLEEP mode 1 1 0 P Previous status before reset Table 6 The Status of RST T and P being Affected by Events 7 4 RI T Poweron 105011111 WoT instructo P 1 WoT meot 9 9 SLEP instruction P 1 9 Wake Up on pin change during SLEEP mode 1 1 o P Previous value before reset 4 7 Interrupt The EM78257A B has five interrupt sources as listed below 1 TCC overflow int
63. s ti o7 decimal value held Low time register fosc 17 1 High time Register The 8 bit High time register controls the inactive or High period of the pulse This specification is subject to change without prior notice 25 2002 05 06 EM78257 MASK ROM The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is inactive The inactive period of IR OUT can be calculated as follows trig decimal value held High time register fosc 18 IOCB1 Pulse timer Register The contents of the Low time and High time register are loaded alternately into the Pulse timer When loaded the contents of Pulse timer are decremented on every oscillator cycle Upon reaching zero the Pulse timer will be loaded with the contents of the other 4 3 TCC WDT amp Prescaler There are two 8 bit counters available as prescalers for the TCC and WDT respectively The PSRO PSRZ2 bits of the CONT register are used to determine the ratio of the prescaler of TCC Likewise the PWRO PWR2 bits of the IOCEO register are used to determine the prescaler of WDT The prescaler PSRO PSR2 will be cleared by the instructions each time they are written into TCC The WDT and prescaler will be cleared by the WDTC and SLEP instructions Fig 6 depicts the circuit diagram of TCC WDT e R1 TCC is an 8 bit timer counter The clock source of TCC can be internal clock or external singal i
64. t of the comparator must be enabled 1 output enabled 0 output disabled and carry out the function of P63 Bit 7 COIE7 Set P64 as the output of the comparator CO4 CE4 must be enabled 1 output enabled 0 7 output disabled and carry out the function of P64 6 IOCAO0 CO INPUT Combine sequence There are 16 combinations of the negative inputs of the four comparators Table 3 The list of CO INPUT combine sequence CI3 CI2 CI1 CIO CO Input combine status Comment N A 1 2 3 and 4 gt negative inputs 122 CIN2 negative input CIN1 normal I O pin 13 CIN3 negative input CIN1 gt normal I O pin 14 CIN4 negative input CIN1 gt normal I O pin 23 7 CIN3 gt negative input CIN2 gt normal I O pin 24 in 84 O in 2 3 4 3 4 A 2 2 32 2 gt negative input CIN3 gt normal I O pin 42 2 gt negative input CIN4 gt normal I O pin 143 gt negative input CIN 1 4 gt normal I O pin 1 1 i 1 i 2 i 2 i 3 i 124 4 gt negative input CIN 1 2 gt normal I O 3 4 0 0 0 0 f 0 0 1 1 Lo x p 0 EGNESE SEU 0 1 1 0 EBENE NEN 1 1 0 90 141 peg pa This specification is subject to change without prior noti
65. ted control bit in the IOCFO to 1 Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction Refer to Fig 10 e OCFO register is both readable and writable 12 IOC51 TCCA Counter An eight bit clock counter It can be read written and cleared on any reset condition When in Mouse Mode it is Up Down Counter else it is UP Counter 13 IOC61 TCCBL Counter LSB Counter An eight bit clock counter is for the least significant byte of TCCBX TCCBL It can be read written and cleared on any reset condition When in Mouse Mode it is Up Down Counter When in IR Mode it is Down Counter else it is Up Counter 14 IOC71 TCCBH Counter MSB Counter An eight bit clock counter is for the most significant byte of TCCBX TCCBH It can be read written and cleared on any reset condition When TCCBE IOC80 is 0 THEN TCCBH is disable TCCBE is 1 then TCCB is 16 bit length counter When it is in IR Mode it is Down Counter else it is UP Counter 15 81 TCCC Counter An eight bit clock counter It can be read written and cleared on any reset condition When in Mouse Mode it is Up Down Counter else it is UP Counter 16 IOC91 Low time Register The 8 bit Low time register controls the active or Low period of the pulse The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is active The active period of IR OUT can be calculated as follow
66. tor is recommended e Vcc a Rext OSCI EM78257A B This specification is subject to change without prior notice 47 2002 05 06 EM78257 MASK ROM Fig 26 Circuit for Internal C Oscillator Mode Table 18 R Oscillator Frequencies Rext Average Fosc 5V 25 C Average Fosc 3V 25 C Note 1 Measured on DIP packages 2 Design reference only 5 Internal RC Oscillator Mode EM78257A B offers a versatile internal RC mode with default frequency of 4MHz The frequency can be configured by programming the bit RCMO and bit RCM1 of the Option code Table 19 describes a typical instance of the calibration Table 19 Calibration Selection for Internal RC Mode RCM 1 RCM 0 Frequency MHz pp C A 0 2 455kHz RENNES NN 32 768kHz Note 1 Measured DIP packages 2 Design reference only the frequency value vary with temperature VDD and process 3 The frequency drift about 30 4 13 MOUSE APPLICATION MODE 1 Overview amp Features Overview Fig 27 shows how EM78257A B communicates with PS 2 connector of PC Features RC oscillation Six photo couples input This specification is subject to change without prior notice 48 2002 05 06 EM78257 MASK ROM MOUSEN X1 TCC1 MOUSEN After MCU process send data to PC TCCA UP DOWN Counter MOUSEN After MCU process send data to PC TCCB UP DOWN Counter i VCC
67. tus Change Interrupt is used to wake up the EM78257A B the following instructions must be executed before SLEP MOV A 8 xx0001 10b Select internal TCC clock CONTW CLR R1 Clear TCC and prescaler MOV A xxxx1110b Select WDT prescaler CONTW WDTC Clear WDT and prescaler MOV A 0xxxxxxxb Disable WDT IOW RE MOV R5 R5 Read Port 5 MOV A 00000x1xb Enable Port 5 input change interrupt IOW RF ENI or DISI Enable or disable global interrupt SLEP Sleep NOP In a similar way if the Comparator Status Changed Interrupt is used to wake up the 78257 the following instructions must be executed before SLEP MOV A 0bxx000110 Select internal TCC clock CONTW CLR R1 Clear TCC and prescaler MOV A 06 1110 Select WDT prescaler CONTW WDTC Clear WDT and prescaler This specification is subject to change without prior notice 31 2002 05 06 EM78257 MASK ROM MOV A 060 Disable WDT IOW RE MOV A 0b1111xxxx Enable comparator high interrupt IOW RF ENI or DISI Enable or disable global interrupt SLEP Sleep NOP One problem user must be aware of is that after waking up from the sleep mode WDT will enable automatically The WDT operation being enabled or disabled should be handled appropriately by software after waking up from the sleep mode 2 IRESET Configure Refer to Fig 11 When the RESET bit in the OPTION word is programmed to 0 the exte

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