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ELAN EM78P257 OTP ROM Manual(1)(1)

1. 78 257 ROM 0 Disable IRE Disable H W Modulator Function 1 Enable IRE Ignored RB Bit4 TCCBTE Bits TCCBTS and TCCBX set as decrement counter Enable H W Modulator Function e Bit 4 Bit 5 MF0 MF1 Modulated frequency 5 IR mode timing UU te L1dd HIIIDLELEPLEIEETIJg A start start L P Software time Interrupt to CPU Low time Register 3 High time Register 2 Number of pulses 2 IR OUT CASE 2 Fig 30 CASE 1shows typical pulse train DP 00 MF 10 HF 0 LGP 0 PWM 0 CASE 2 shows the same pulse train after being modulated with a frequency of 1 4Fosc DP 00 MF 10 HF 1 LGP 0 PWM 0 This specification is subject to change without prior notice 60 2002 05 06 78 257 ROM me O LI LILI LI LI LI WU LI LU UL start start IR OUT 7 1 4 9 Low time Register 3 ET Interrupt to CPU Software time 4 Number of pulses 3 d mor 7211111 1 1 1 1 1 1 7 1 Fig 31 CASE 1 shows a typical long pulse DP 00 MF 10 HF 1 LGP 1 PWM 0 CASE 2 shows the same long pulse after being modulated with a frequency of 1 4Fosc DP 00 MF 10 HF 1 LGP 1 PWM 0 Fosco LI LJ start IR OUT ee Low time Register 3 High time Register 2 Fig 32 Continuous pul
2. 78 257 ROM 1 GENERAL DESCRIPTION EM78P257A B is 8 bit microprocessors with low power high speed CMOS technology It features a 2K 13 bits Electrical One Time Programmable Read Only Memory OTP ROM and provides a protect bit to prevent from intruding on code as well as 12 Option bits to accommodate user s requirements This specification is subject to change without prior notice 1 2002 05 06 78 257 2 FEATURES 18 lead packages 78 257 20 lead packages EM78P257B Operating voltage range 2 3V 5 5V Operating temperature range 0 C 70 C commercial 40 C 85 C industrial Operating frequency range Base on 2 clocks Crystal mode DC 20MHZz 2clks 5V DC 8MHz 2clks 3V mode DC 4MHz 2clks 5V DC 4MHz 2clks 3V Low power consumption less then 1 5 mA at 5V 4MHz typical of 15 uA at 3V 32KHz typical of 1 uA during the sleep mode Built in RC oscillator 4MHz 1MHz 455KHz 32 768KHz RC oscillator mode with Internal Capacitor Programmable oscillator set up time 1ms 18ms Independent Programmable prescaler of WDT One configuration register to match the user s requirements and provide user s ID code for customer use 80x 8 on chip registers SRAM general purpose register 2Kx 13 on chip ROM Bi directional 1 ports 8 level stacks for subroutine nesting 8 bit real time clock counter TCC with selective signal sources trigge
3. 10C70 V 0 CR IOC80 TCCCR IOC90 CMPCR 5 10C71 TCCBH 10C81 TCCC IOC91 LTR IOCBO PDCR IOCCO OPCR IOCDO PHCR IOCA1 HTR IOCB1 PTR IOCEO WDTCR IOCFO IMR 20 32x8 Bank Register Bank 0 3F Fig 5 Data memory configuration This specification is subject to change without prior notice 20 32x8 Bank Register Bank 1 3F 9 78 257 4 Status Register PS SUN pso T z Bit 0 C Carry flag Bit 1 DC Auxiliary carry flag Bit 2 Z Zero flag Set to 1 if the result of an arithmetic or logic operation is zero e Bit 3 P Power down bit Set to 1 during power on or by a WDTC command and reset to 0 by a SLEP command Bit 4 T Time out bit Set to 1 with the SLEP and WDTC command or during power on and reset to 0 by WDT time out e Bit5 PS0 Page select bits PSO is used to select a program memory page When executing a JMP CALL or other instructions that causes the program counter to change e g MOV R2 A PSO is loaded into the 11th bit of the program counter selecting one of the available program memory pages Note that RET RETI instruction does not change the PSO bits That is the return will always be back to the pag
4. 78 257 6 ELECTRICAL CHARACTERISTICS 6 1 DC Electrical Characteristic Ta 0 C 70 C VDD 5 0V4 5 VSS 0V Symbol Parameter Condition Min Typ Unit XTAL VDD to 3V Two cycle with two clocks DC 8 MH Fxt XTAL VDD to 5V DC 20 MH RC VDD to 5V R 5 1KQ C 100 pF 20 Input Leakage Current for VIN VDD VSS input pins VIH1 Input High Voltage VDD 5V Ports 5 6 VIL1 Input Low Voltage VDD 5V Ports 5 6 1 Voltage VDD 5V Voltage VDD 5V 20 Clock Input High OSCI Clock Input Low OSCI VIH2 Input High Voltage VDD 3V Ports 5 6 15 i 04 VIHT2 Input High Threshold RESET TCC Voltage VDD 3V VILT2 Input Low Threshold RESET TCC Voltage VDD 3V Clock Input High OSCI Clock Input Low OSCI Output High Voltage VOH1 Ports 5 6 9 0 mA Output Low Voltage VOL1 Ports 5 6 IOL 9 0 mA 2 0 2 0 2 5 1 5 VIL2 Input Low Voltage VDD 3V Ports 5 6 o 1 5 1 5 2 4 5 25 Pull high current 240 Pulkdown current _Pull down active input pin at VDD 25 50 se WOT enabled floating WDT enabled 1 se Fre floating disabled Ic gt Operating supply current RESET Fosc 32KHz Crystal ICC1 VDD 3V at two clocks type two clocks output pin floating WDT disabled Operating supply current RESET Fosc 32KHz
5. 1 1 0 Previous status before reset Table 6 The Status of RST T and P being Affected by Events Ee Poweron WTC instruction tt SLEP instruction Wake Up on pin change during SLEEP mode 9 ee Previous value before reset 4 7 Interrupt The 78 257 has five interrupt sources as listed below 1 TCC overflow interrupt 2 Port 5 Input Status Changed Interrupt 3 External interrupt INT pin 4 Comparators status change 5 IR OUT interrupt Before the Port 5 Input Status Change Interrupt is enabled reading Port 5 e g MOV R5 R5 is necessary Each Port 5 pin will have this feature if its status changes The Port 5 Input Status Change Interrupt will wake up the EM78P257A B from the sleep mode if it is enabled prior to going into the sleep mode by executing SLEP instruction When wake up occurs the controller will continue to execute program in line if the global interrupt is disabled If the global interrupt is enabled it will branch out to the interrupt vector 3FEH This specification is subject to change without prior notice 32 2002 05 06 78 257 ROM RF is the interrupt status register that records the interrupt requests in the relative flags bits IOCFO is an interrupt mask register The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction Onc
6. Fig 7 The circuit of I O port and I O control register for Port 6 and Port7 PCRD 4 41 PCWR L P60 INT 2 9 lt PORT i EM R x 1 g Bit6 of IOCEO 0 s gt M E gt CLK 9 5 x INT NOTE Open drain is not shown in the figure Fig 8 The Circuit of I O Port and I O Control Register for P60 INT This specification is subject to change without prior notice 27 2002 05 06 78 257 ROM PCRD lt PCWR P50 P57 5 PORT lt IOD CLK lt q PDWR lt 4 PDRD NOTE Pull high down is shown in the figure Fig 9 The Circuit of I O Port and I O Control Register for P50 P57 IOCF 1 P R k Interrupt zx ra m 1 RF 1 instruction TIO gt 11 gt CLK QPD 2 5s j 21 c R 2 000 CLK lt af gt a DISI instruction ET hs SCE E Interrupt 4 B Wake up from SLEEP 227 Next Instruction Wake up from SLEEP Fig 10 Block Diagram of I O Port 5 with Input Change Interrupt Wake up This specification is su
7. 7 6 5 2 1 TCCBL An eight bit clock counter is for the least significant byte of TCCBX TCCBL which can be read written and cleared at any reset condition TCCBH An eight bit clock counter is for the most significant byte of TCCBX TCCBH which can be read written and cleared at any reset condition Low time Register The 8 bit Low time register that controls the active or Low period of the pulse The High time register controls the inactive or High period of the cycle The decimal value of its contents determines the number of oscillator cycles indicating that the IR OUT pin is active The active period of IR OUT can be calculated as follow This specification is subject to change without prior notice 58 2002 05 06 78 257 ROM ti ow decimal value held in Low time register fosco High time Register The 8 bit High time register control the inactive or High period of the pulse The decimal value of its contents determines the number of oscillator cycles indicating that the IR OUT pin is active The inactive period of IR OUT can be calculated as follow tuig decimal value held in High time register fosco Pulse timer Register The contents of the Low time and High time registers which are loaded alternately into the Pulse timer When loaded the Pulse timer contents are decremented by 1 every
8. Bit 6 INT Interrupt enable 0 masked by DISI or hardware interrupt 1 enabled by ENI RETI instructions Bit 7 INTE INT signal edge 0 interrupt occurs at the rising edge on the INT pin 1 interrupt occurs at the falling edge on the INT pin The CONT register is both readable and writable Bit 6 is read only 3 IOC50 IOC70 I O Port Control Registers e 1 put the relative I O pin into high impedance while 0 defines the relative I O pin as output e Only the higher 2 bits of IOC5 can be defined for EM78P257B only e Only the lower 2 bits of IOC7 can be defined the others bits are not available 1 5 1 6 and IOC7 are both readable and writable 4 lIOC80 Control Register 7 6 5 4 3 2 1 0 2 TCC6E TCCBE Bit O Bit 3 Not used e Bit 4 TCCBE Control bit is used to enable the most significant byte of counter 1 Enable the most significant byte of TCCBH TCCB is a 16 bits counter 0 Disable the most significant byte of TCCBH default value TCCB is an 8 bits counter Bit 5 TCC6E Control bit used to enable the second input of counter for EM78P257B only For EM78P257B 1 If MOUSEN equal to 1 pin 20 is defined as another input pin of TCCC If MOUSEN equal to 0 pin 20 is a bi directional I O pin This specification is subject to change without prior notice 15 2002 05 06 78 257 ROM 0 Define P57 as a bi directional I O pin
9. PSW2 PSWO Bit 7 WDTE Control bit is used to enable Watchdog timer 0 Disable WDT 1 Enable WDT WDTE is both readable and writable e Bit 6 EIS Control bit is used to define the function of PeO INT pin 0 P60 bi directional I O pin 1 INT external interrupt pin In this case the I O control bit of P60 bit 0 of IOC6 must be set to 1 This specification is subject to change without prior notice 22 2002 05 06 78 257 ROM When EIS is 0 the path of INT is masked When EIS is 1 the status of INT pin can also be read by way of reading Port 6 R6 Refer to Fig 8 EIS is both readable and writable Bit3 5 Not used Bit 0 PSWO Bit 2 PSW2 WDT prescaler bits 11 IOCFO Interrupt Mask Register 7 6 5 4 3 2 1 0 CMP4IE 2 PPC CMP EXIE ICIE TCIE Bit 0 TCIE TCIF interrupt enable bit 0 disable TCIF interrupt 1 enable TCIF interrupt Bit 1 ICIE ICIF interrupt enable bit 0 disable ICIF interrupt 1 enable ICIF interrupt Bit 2 EXIE EXIF interrupt enable bit 0 disable EXIF interrupt 1 enable EXIF interrupt Bit 3 CMP PPC Wake up by which Interrupt sources 0 PPC wake up by Port 5 input status change if enabled 1 wake up by comparators status change if enabled Bit 4 CMP1IE CMP1IF interrupt enable bit 0 disable CMP1IF interrupt 1 enable CMP1IF interrupt Bit 5 CMP2IE CMP2IF inter
10. NT INTE This specification is subject to change without prior notice 40 2002 05 06 z z 2 HTR6 A PTR6 PTR5 PTR4 PTR3 2 PTR1 PTRO 79 I 4 5 5 78 257 ROM wor ow wo v e gt BitName 201 1 RESETandwoT P P BitName 2142 1255 4 24 9315 p 0 01 x Poweron o o o o R1 TCC RESETandwoT 0 o o o o me BitName 1 1 1 1 Power on o 0 o 0x02 R2 PC iREseTandwoT o o o o o o o Power On RESET and WDT Wake Up from Pin Change me Power On RESET and WDT Wake Up from Pin Change Bit Name Power On RESET and WDT Wake Up from Pin Change Bit Name Power On RESET and WDT Wake Up from Pin Change Bit Name Power On R7 RESET and WDT Wake Up from Pin 00 2 70 1 CMPOU CMPOU CMPOU This specification is subject to change without prior notice 41 2002 05 06 Bit Name Power On RESET and WDT Wake Up from Pin Change 0 P66 a c x Bit Name
11. TCCB An eight bit time clock counter B In MOUSE mode it will load Y axis data into TCCB it is defined as an increment decrement counter TCCC An eight bit time clock counter C In MOUSE mode it will load Z axis data into TCCC it is defined as an increment decrement counter Table 22 TCCX Status Register 1 1 0 TCCAIE TCCATS TCCATE 0 TCCATE signal edge 0 increment if the transition from low to high leading edge takes place on the TCC2 pin 1 increment if the transition from high to low leading edge takes place on the TCC2 pin e Bit 1 TCCATS TCCA signal source 0 internal instruction cycle clock 1 transition on the TCC1 pin Bit 2 TCCAIE TCCAIF interrupt enable bit 0 disable TCCAIF interrupt 1 enable TCCAIF interrupt Bit 3 Bit 7 Not used read as 0 Table 23 TCCX Status Register 2 7 6 5 4 3 2 1 0 TCCBIE TCCBTS TCCBTE TCCCIE TCCCTS TCCCTE Bit TCCC signal edge 0 increment if the transition from low to high leading edge takes place the TCC6 pin 1 increment if the transition from high to low leading edge takes place on the TCC6 pin e Bit 1 TCCCTS TCCC signal source 0 internal instruction cycle clock 1 transition on the TCC5 pin Bit 2 TCCCIE TCCCIF interrupt enable bit This specification is subject to change without prior notice 51 2002 05 06 78 257 ROM 0 disable the TCCCIF interrupt 1 enable t
12. input then this pin s status will be decided by Bit 9 8 7 of CODE option When choice is 1 1 1 then Pin 17 is defined as P55 otherwise the status is defined as OSCI Bit 1 CE2 Comparator CO2 enable bit 0 Comparator is CO2 off default value For EM78P257A Pin 1 can choose P52 only Pin 2 can choose P53 only Pin 3 can choose P54 or TCC only and is decided by Bit 5 of Control Register CONT 5 When TS is 1 then Pin 3 is defined as TCC otherwise the status is defined as P54 For EM78P257B Pin 2 can choose P52 only Pin 3 can choose P53 only Pin 4 can choose P54 or TCC only and is decided by Bit 5 of Control Register CONT 5 When TS is 1 then Pin 4 is defined as TCC otherwise the status is defined as P54 This specification is subject to change without prior notice 17 2002 05 06 78 257 ROM 1 Comparator is CO2 on For EM78P257A Pin 1 can choose P52 CO2 only and decided by COIE2 of IOC90 Pin 2 can choose CIN2 only Pin 3 can choose P54 CIN2 or TCC and is decided by IOCAO If CIN2 was not chosen as comparator1 input then this pin will be decided by Bit 5 of Control Register CONT 5 When TS is 1 then Pin 3 is defined as TCC otherwise status is defined as P54 For EM78P257B Pin 2 can choose P52 or CO2 only and decided by COIE2 of IOC90 Pin can choose CIN2 only Pin 4 can choose P54 CIN2 TCC as decided by IOCAO If CIN2 was not chosen a
13. 16 Comparator Operating Modes 1 External Reference Signal The analog signal that is presented at Cin compares to the signal at Cin and the digital output CO of the comparator is adjusted accordingly The reference signal must be between Vss and Vdd The reference voltage can be applied to either pin of a comparator Threshold detector applications may use the same references The comparator can operate from the same or different reference sources There are 16 combinations of the negative inputs of the four comparators 2 CIO CO Input combine status Comment N A 1 2 3 and 4 gt negative inputs ofofo 12 Eme negate input CN roma VO pn CIN3 gt negative input CIN 1 2 gt normal O pin This specification is subject to change without prior notice 36 2002 05 06 78 257 1 ojo o 124 CIN4 gt negative input CIN 1 2 gt normal pin 1 0 0 1 34 gt negative input CIN 1 3 normal VO pin 1 0 1 0 234 CIN4 gt negative input CIN 2 3 gt normal 11101111 1 2 3 4 4 gt negative input 2 3 gt normal VO tft foto 32 OIN2 gt negative input CINS gt normal VO pim CIN2 gt negative CIN4 gt normal I O SEME CIN2 gt negative input CIN 3 4 gt normal I O pin 714221 1 3 negative input C
14. TCC4E IOC80 Power On o o o o o o RESET and WDT o o 0 10 9 Tr re Pe Pr Change Bit Name 0 o 90 Power On IOC Bit Name Power On 1 Wake Up from Pin Change Bit Name PD57 Power On RESET and Wake Up from Pin Change OD67 Power On N A RESET WDT ODCR Wake Up from Pin Change IOCDO Bit Name 57 PH56 54 PHOR Power On This specification is subject to change without prior notice 39 2002 05 06 78 257 ROM RESET and WOT 1 T 1 1 1 111 1 Wake Up from Pin Change Bit Name X 2 PSW1 PSWO oe D TE Wake Up from Pin Change PPC C Bit Name P4IE CMP3IE CMP2IE CPM1IE MP EXIE ICIE TCIE IOCFO RESET 2 0 Wake Up from Pin Change TCCAG Wake Up from Pin Change S lb bon L ne IOC61 Sa TCCBL RESET WDE Wake Up from Pin Change IOC71 7008 RESET and WOT Change TCCCA TCCC3 TCCC2 TCCC1 TCCCO e 0 o Change LTR7 LTR6 LTR4 LTR3 pe fete e 1 iw is 2 Change Change om Wake Up from Pin Change
15. When HF 1 the Low time part of the generated pulse is modulated with a frequency Fosco Bit 3 IRE Infrared Remote Enable bit 0 Disable IRE Disable H W Modulator Function 1 Enable IRE Disable RB Bit4 TCCBTE and Bits TCCBTS and TCCBX acts as a down counter Enable H W Modulator Function Port 5 and pin60 66 set as normal I O pin Pin 67 defined as IR OUT Bit 4 Bit 5 MF0 MF1 Modulated frequency 0 0 Fosc 1 Ca spo 1 0 Fos Bit6 Bit7 DP0 DP1 Ratios of duty and period of modulated frequency MOUSEN Bit 0 Bit 6 Not used Bit 7 MOUSEN Mouse application Enable bit 0 Disable MOUSEN TCCA TCCB and TCCC are increment counters 1 Enable MOUSEN TCCA TCCBL and TCCC work as up down counters The other pin assignment refers to 80 and 1 90 This specification is subject to change without prior notice 13 2002 05 06 78 257 ROM 14 RF Interrupt Status Register 7 6 5 4 3 2 1 0 CMP4IF CMP2IF CMP1IF EXIF ICIF TCIF 1 means interrupt request and 0 means no interrupt occurs Bit 0 TCIF TCC overflowing interrupt flag Set when TCC overflows and reset by software Bit 1 ICIF Port 5 input status changed interrupt flag Set when Port 5 input changes and reset by software Bit 2 EXIF External interrupt flag Set by INT pin and reset by software e Bit 3 Unemployed read as 0 Bit 4 CM
16. e Bit 6 TCC4E Control bit used to enable the second input of counter For EM78P257A 1 If MOUSEN equal to 1 pin 17 is defined as another input pin of TCCB If MOUSEN equal to 0 pin 17 is a bi directional I O pin 0 Define P50 as a bi directional I O pin For EM78P257B 1 If MOUSEN equal to 1 pin 18 is defined as another input pin of TCCB If MOUSEN equal to 0 pin 18 is a bi directional I O pin 0 Define P50 as a bi directional I O pin Bit 7 TCC2E Control bit used to enable the second input of counter For EM78P257A 1 If MOUSEN equal to 1 pin 12 is defined as another input pin of TCCA If MOUSEN equal to 0 pin 12 is a bi directional I O pin 0 Define P66 as a bi directional I O pin For EM78P257B 1 If MOUSEN equal to 1 pin 13 is defined as another input pin of TCCA If MOUSEN equal to 0 pin 13 is a bi directional I O pin 0 Define P66 as a bi directional I O pin 5 0 90 CMP Control Register 7 6 5 4 3 2 1 0 COIE4 COIE3 COIE2 COIE1 CE4 CE3 CE2 CE1 Bit 0 CE1 Comparator CO1 enable bit 0 Comparator 1 is off default value For EM78P257A Pin 18 can choose P51 TCC3 only If MOUSEN is 1 define as an input of TCCB TCC3 If MOUSEN is 0 then the choice is decided by TCCBTS of RB Pin 17 can choose P50 or TCC4 only If MOUSEN is 1 and TCC4E of IOC80 is 1 also then choose TCC4 otherwise choose P50 Pin 16
17. ninth and tenth bits A8 A9 of the PC to be cleared Thus the computed jump is limited to the first 256 locations of a page In case of EM78P257A B the second most significant bit A10 will be loaded with the content of bit PSO in the status register R3 upon the execution of a JMP CALL or any other instructions which write to R2 All instructions are single cycle fclk 2 or fclk 4 except for the instructions that would change the contents of R2 This instruction will need one more instruction cycle A10 9 8 7 AO 3 Stack 0 CALE Stack 1 RET Stack 2 RETI 900 Stack 3 RETK gt 0 Stack 4 Stack 5 Stack 6 400 __ Stack 7 Page 1 gt 7FF Fig 4 Program counter organization This specification is subject to change without prior notice 8 2002 05 06 00 01 02 03 04 05 06 07 08 09 0A 0B oc OF 10 11 1E 1F 20 21 3F RO TCC R3 Status R2 PC R4 RSR R5 Port5 R6 Port6 R9 CMPOUT R7 Port RA TCR 1 RC TCCPC RB TCR 2 RD IRCR RE MCR RF ISR 16x8 Common Register STACK 0 STACK 1 STACK 2 STACK 3 STACK 4 STACK 5 STACK 6 STACK 7 R3 lt 6 gt IOCS IOC50 I O CR 78 257 IOC60 I O CR 10C51 TCCA 10C61 TCCBL
18. 1st 2nd 10th 11th Start bit Bit0 Bit7 Parity Bit Stop bit If CLK is low inhibit status no data transmission occurs If CLK is high and DATA is low request to send data is updated Data is received from the system and no transmission is started by 78 until CLK and DATA are both high IF CLK and DATA are both high the transmission is ready DATA is valid prior to the falling edge of CLK and beyond the rising edge of CLK During transmission EM78P257A B check for line contention by checking for an inactive level on CLK at interval not to exceed 100u seconds Contention occurs when the system lowers CLK to inhibit EM78P257A B output after EM78P257A B has started transmission If this occurs before the rising edge of the tenth clock EM78P257A B internally stores its buffer and returns DATA and CLK to an active level If the contention does not occur by the tenth clock the transmission is completed Following a transmission the system inhibits EM78P257A B by holding CLK low until it can service the input or until the system receives a request to send a response from 78 257 3 Receiving DATA from system to EM78P257A B Inhibit CLK Start bit Bit0 Bit7 Parity Bit Stop bit Line Control Bit System first checks if EM78P257A B is transmitting data If transmitting the system can override the output by forcing CLK to an inactive level prior to the tenth clock If EM78P257A B transmission is beyond th
19. Crystal ICC2 VDD 3V at two clocks type two clocks output pin floating WDT enabled ICC3 Operating supply current RESET High Fosc 2MHz Crystal VDD 5 0V at two clocks type two clocks output pin floating ICC4 Operating supply current RESET High Fosc 4MHz Crystal VDD 5 0V at two clocks type two clocks output pin floating This specification is subject to change without prior notice 68 2002 05 06 78 257 ROM 6 2 AC Electrical Characteristic Ta 0 C 70 VDD 5V 5 VSS 0V Symbol o meer Input CLK duty cycle 45 39 5 CLKS 0 RC type 500 DC Tee Te input pet tan Trst RESET pulse width Ta 25 C 2000 Watchdog timer period Ta 25 C Input setup time poms Thold Input pin hold time po ms Tdelay Output pin delay time Cload 20pF 50 ms N selected prescaler ratio This specification is subject to change without prior notice 69 2002 05 06 78 257 APPENDIX Package Types OTP MCU Package Type Pin Count Package Size EM78P257AP DIP 300mil EM78P257BM SOP 300mil This specification is subject to change without prior notice 70 2002 05 06
20. instruction cycle clock 1 transition on the TCC5 pin Bit 2 TCCCIE TCCCIF interrupt enable bit 0 disable the TCCCIF interrupt 1 enable the TCCCIF interrupt Bit 3 Not used Bit 4 TCCBTE TCCB signal edge 0 increment if the transition from low to high leading edge takes place on the TCC3 pin 1 increment if the transition from high to low leading edge takes place on the TCC3 pin Bit 5 TCCBTS TCCB signal source 0 internal instruction cycle clock 1 transition on the TCC3 pin Bit 6 TCCBIE TCCBIF interrupt enable bit 0 disable the TCCBIF interrupt 1 enable the TCCBIF interrupt Bit 7 Not used 11 RC TCC Prescaler Counter TCC prescaler counter can be read and written V valid value This specification is subject to change without prior notice 12 2002 05 06 78 257 ROM 12 RD IR Control Register 7 6 5 4 3 2 1 0 1 1 IRE HF LGP PWM Bit 0 PWM Pulse Width Modulation When PWM 1 and LGP 0 the LSB Counter and MSB Counter are disabled a continuous pulse train is generated and the output signal is actually a PWM waveform format of PWM Bit 1 LGP Long Pulse When LGP 1 the contents of the High time register are ignored A single pulse is generated its pulse is high Pulse width Contents of On time register x number of pulse x 1 Fosc If HF 1 this pulse is modulated with a frequency Fosco selected by MF1 MFO Bit 2 HF High Frequency
21. of EM78P257A B It can generate programmable pulse trains for driving an infrared LED Features Power saving Idle and Stop modes are provided Hardware Modulator providing pulse bursts with programmable duty factor for each pulse programmable number of pulse Watchdog timer to keep the transmitter from being locked or malfunction On chip oscillator 455kHz to 24MHz High time gt end IR OUT start Elapse time by software Low time interrupt gt pulse 1 pulse 2 pulse 3 Low time 2 Low time register 2 High time 4 High time register 4 number of pulse 3 Fig 28 Example Pulse Train Output of IR OUT Pin This specification is subject to change without prior notice 55 2002 05 06 78 257 ROM High Time Register H W Modulator TCCBIF 1 overflow lt Note gt In software design Low time and High time registers cannot set 0 at initial state Fig 29 Hardware Modulator 2 Function Description The following describes the function of each block and single for Fig 29 which depicts how to complete IR kernel hardware modulator Low time Register The 8 bit Low time register controls the active or Low period of the pulse The decimal value of its contents determines the number of oscillator cycles indicating that the IR OUT pin is active The active period of IR OUT can be calculated as follow tLow decimal value held
22. oscillator cycle Upon reaching zero the Pulse timer will be loaded with the contents of the other register Table 28 TCCX Status Register 2 7 6 5 4 3 2 1 0 TCCBIE TCCBTS TCCBTE TCCCIE TCCCTS TCCCTE Bit 6 TCCBIE TCCBIF interrupt enable bit 0 disable TCCBIF interrupt 1 enable TCCBIF interrupt Table 29 TCCX Control Register 7 6 5 4 3 2 1 0 TCC2E TCC6E TCCBE Bit 4 TCCBE Control bit which is used to enable most significant byte of counter 1 Enable most significant byte of TCCBH 0 Disable most significant byte of TCCBH default value Table 30 IR Control Register 7 6 5 4 3 2 1 0 DP1 DPO MF1 MFO IRE HF LGP PWM Bit O PWM Pulse Width Modulation When PWM 1 and LGP 0 the LSB Counter 8 MSB Counter are disabled a continuous pulse train is generated and the output signal is actually a PWM waveform format of PWM e Bit 1 LGP Long Pulse When 1 the contents of the High time register are ignored A single pulse is generated Its pulse is determined as shown below Pulse width Contents of Low time register x number of pulse x 1 Fosco If HF 1 this pulse is modulated with Frequency Fosco selected by 1 0 Bit 2 HF High Frequency When HF 1 the Low time part of the generated pulse is modulated with Frequency Fosco Bit 3 IRE Infrared Remote Enable bit This specification is subject to change without prior notice 59 2002 05 06
23. software e Bit 2 TCCCIF TCCC overflowing interrupt flag Set when TCCC overflow reset by software Bit 3 Not used read as 0 Bit 4 CMPOUT1 The output result of the comparator1 Bit 5 CMPOUT2 The output result of the comparator2 Bit 6 The output result of the comparator3 Bit 7 4 The output result of the comparator4 Bit 4 Bit 7 are read only 9 RA TCC Control Register 1 7 6 5 4 3 2 1 0 TCCAIE TCCATS 0 TCCATE signal edge 0 increment if the transition from low to high leading edge takes place on the TCC1 pin 1 increment if the transition from high to low leading edge takes place on TCC1 e Bit 1 TCCATS TCCA signal source 0 internal instruction cycle clock 1 transition on the TCC1 pin Bit 2 TCCAIE TCCAIF interrupt enable bit 0 disable TCCAIF interrupt 1 enable TCCAIF interrupt Bit 3 Bit 7 Not used read as 0 This specification is subject to change without prior notice 11 2002 05 06 78 257 ROM 10 RB TCC Control Register 2 7 6 5 4 3 2 1 0 TCCBIE TCCBTS TCCBTE TCCCIE TCCCTS TCCCTE e Bit TCCC signal edge 0 increment if the transition from low to high leading edge takes place on the TCC5 pin 1 increment if the transition from high to low leading edge takes place on the TCC5 pin e Bit 1 TCCCTS TCCC signal source 0 internal
24. 257 ROM Interrupt Interrupt sour upt sources occurs ENI DISI Fig 13 Interrupt backup diagram In 78 257 each individual interrupt source has its own interrupt vector as depicted in Table 7 Table 7 Interrupt vector Interrupt vector Interrupt status 3EC Comparator CO4 interrupt 4 8 Timer Counter 1 Overview Timer1 TCCA and Timer3 TCCC are eight bit clock counters with programmable prescalers Timer2 TCCB is a 16 bit clock counter with a programmable prescaler TCCA TCCB and TCCC can be read and written and cleared at every reset condition 2 Function Description Fig 14 shows the TIMER block diagram Each signal and block is described as follows Set predict value Set predict value Set predict value TCCAEN TCCBEN TCCCEN Set TCCAIF Set TCCBIF Set TCCCIF gt V NN Osci input or Osci input or Osci input or External input External input External input Fig 14 TIMER Block Diagram This specification is subject to change without prior notice 34 2002 05 06 78 257 ROM Osci input Input clock Timer 1 3 register TCCX increases until it matches with zero and then reload the previous value If TCCXIE is enabled TCCXIF will be set at the same time 3 Programming the Related Registers When defining TCCX refer to the related registers of its operation as shown in the Table 7 and Table 8 below Table
25. 435 KHz 440 KHz 100k 46KHz 48 KHz 560 KHz 545 KHz 300 pF 370 KHz 360 KHz 195 KHz 195 KHz 100k 20 KHz 21 KHz Note 1 Measured on DIP packages 2 Design reference only 4 RC Oscillator Mode with Internal Capacitor This specification is subject to change without prior notice 47 2002 05 06 78 257 ROM If both precision and cost are taken into consideration EM78P257A B also offers a special oscillation mode which is equipped with an internal capacitor and an external resistor connected to Vcc The internal capacitor functions as temperature compensator In order to obtain more accurate frequency a precise resistor is recommended e Rext OSCI 78 257 Fig 26 Circuit for Internal Oscillator Mode Table 18 R Oscillator Frequencies Average Fosc 5V 25 C Average Fosc 3V 25 C 4 3 MHz 4 3 MHz 100k 2 5 MHz 2 4 MHz 300k 800KHz 800 KHz Note 1 Measured on DIP packages 2 Design reference only 5 Internal RC Oscillator Mode EM78P257A B offers a versatile internal RC mode with default frequency of 4MHz The frequency can be configured by programming the bit RCMO and bit RCM1 of the Option code Table 19 describes a typical instance of the calibration Table 19 Calibration Selection for Internal RC Mode RCM 1 REM 0 rr 011 0 32 768 2 Note 1 Measured on DIP packages 2 Design reference only the frequency value vary wi
26. 57 ROM 1 SP 1 OOkk kkkk 1kkk CALL k Page k PC 1010 kkkk _ A amp K2A 2 1011 1Bk 27 None kA 1 1100 1Ckk RETL k of Stack gt PC 1101 1Dkk SUB A k kASA 4 1 SP 1 1111 1Fkk ADD Z C DC Note 1 This instruction is applicable to IOC50 1OC60 IOCBO IOCFO only Note 2 This instruction is not recommended for RF operation Note 3 This instruction cannot operate under RF This specification is subject to change without prior notice 65 2002 05 06 4 17 Timing Diagrams AC Test Input Output Waveform EM78P257 ROM 2 4 2 0 TEST POINTS 0 8 AC Testing Input is driven at 2 4V for logic 1 and 0 4V for logic 0 Timing measurements are made at 2 0V for logic 1 and 0 8V for logic 0 RESET Timing CLK 0 Instruction 1 Executed Bs 21171 4 TCC Input Timing CLKS 0 TA ox JLT LLU LW 4 4 E This specification is subject to change without prior notice 66 2002 05 06 78 257 5 ABSOLUTE MAXIMUM RATINGS 0 C 70 C Storage temperature 65 C to 150 C Input voltage 0 3V to 6 0V 03 t 607 This specification is subject to change without prior notice 67 2002 05 06
27. 57A Bit 3 RCOUT A selecting bit of High or Low frequency for internal RC Oscillator RCOUT Eu 32 768kHz Note Theoretical values for reference only In fact the values may be inaccurate by 35 Not used This specification is subject to change without prior notice 62 2002 05 06 2 4 16 78 257 ROM Customer Register Word 1 Bit12 BitO XXXXXXXXXXXXX 12 0 Customer s ID code Instruction Set Each instruction in the instruction set is a 13 bit word divided into an OP code and one or more operands Normally all instructions are executed within one single instruction cycle one instruction consists of 2 oscillator periods unless the program counter is changed by instruction MOV R2 A ADD 2 or by instructions of arithmetic or logic operation on R2 e g SUB R2 A BS C R2 6 CLR R2 In this case the execution takes two instruction cycles If for some reasons the specification of the instruction cycle is not suitable for certain applications try modifying the instruction as follows A Modify one instruction cycle to consist of 4 oscillator periods B Execute within two instruction cycles the JMP CALL RET RETL RETI commands or the conditional skip JBS JBC JZ JZA DJZ DJZA which were tested to be true The instructions that are written to the program counter should also take two instruct
28. 5ms 5 VDD 3V Setup time period 18ms 5 This specification is subject to change without prior notice 25 2002 05 06 78 257 ROM CLK Fosc 2 or Fosc 4 Data Bus TCC e ER 5 M SYNC TCC R1 2 cycles 2 1 4 1 v TE TCC overflow interrupt 8 bit Counter RC WDT 8 bit Counter PSRO PSR B r3 8 to 1 MUX 4 840 1 wore DROVE in IOCE WDT timeout Fig 6 Block Diagram of TCC and WDT 4 4 1 Ports The 1 registers Port 5 Port 6 and Port 7 are bi directional tri state 1 ports Port 5 is pulled high internally by software Likewise P6 has its open drain output also through software Port 5 features an input status changed interrupt or wake up function and is pulled down by software Each I O pin be defined as input or output pin by the I O control register IOC5 IOC7 The I O registers and I O control registers are both readable and writable The I O interface circuits for Port 5 Port 6 and Port are shown in Fig 7 Fig 8 and Fig 9 respectively This specification is subject to change without prior notice 26 2002 05 06 78 257 PCRD c CLK L PORT Q IOD iE PDRD v 0 M 1 U gt X NOTE Open drain is not shown in the figure
29. 63 64 4 Fig 2 Pin Assignment 78 257 Table 2 Pin Description EM78P257B aa ER XTAL type Crystal input terminal or external clock input pin ER RC type RC oscillator input pin XTAL type output terminal for crystal oscillator or external clock input pin RC type clock output with a duration of one instruction cycle External clock signal input P70 P71 16 5 General purpose I O pin P71 is input pin only Default value after a power on reset P60 P67 7 14 General purpose I O pin Open_drain Default value after a power on reset P50 P57 General purpose 1 pin 7 Pull_high pull_down Wake up from sleep mode when the status of the pin changes Default value after a power on reset IR OUT 14 O IR mode output pin capable of sinking 30mA INT 7 Externalinterrupt pin triggered by falling edge CIN1 CIN1 18 gt the input pin of Vin of a comparator This specification is subject to change without prior notice 5 2002 05 06 78 257 gt the input pin of Vin of a comparator Pin CO1 4 are the outputs of the comparators External Counter input If set as RESET and remains at logic low the device will be reset Voltage on RESET Vpp must not exceed Vdd during the normal mode Pull_high is on if defined as RESET This specification is subjec
30. 7 2002 05 06 78 257 ROM raised stopping the operation of the Hardware Modulator If TCCBIF want to be clear the IR must be disable firstly The programmed pulse train has now been generated If the Hardware Modulator want to be restarted we must disable IR in advance and then enable IR again The time delay between two pulse trains is determined by software 3 Pin Description SYMBOL PIN DESCRIPTION P60 to P66 7 13 Standard I O Port lines generally used for keypad scanning P50 to P57 1 4 17 20 Standard I O Port lines generally used for keypad sensing nal OSCI External clock signal input ws e 4 Programmed the Related Registers When defining IR mode is defined refer to the related register of its operation as shown in the Table 26 and Table 27 below Table 26 Related Control Registers of the IR Mode Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 0x0B TCR 2yRB 0 TCCBIE O 5 0 TCCBTE O 0 TCCCIE O TCCCTS O TCCCTE O 0x08 80 2 TCC4E TCC6E 1 IRCR RD DP1 0 DPO O MF 1 0 MFO O IRE O LGP O PWM O Note Bit name initial value Table 27 Related status data register of the IR mode Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 0 06 61 TCCBL7 TCCBL6 5 TCCBL4 TCCBL3 TCCBL2 TCCBL1 TCCBLO 71
31. 8 Related Control Registers of the TCCX Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit2 Bit 1 Bit 0 Ox0A TCR 1 RA 0 0 TRECE Tonys o TOCETED o recse reces o o Table 9 Related Status Data Registers of TCCX 0 09 TCCSR RO_ CMPOUT4 CMPOUT3 CMPOUT2 CMPOUT1 0 TCCBIF TCCAIF 4 9 Comparator EM78P257A B has four comparators consisting of two analog inputs and one output The comparators can be employed to wake up from sleep mode Fig 15 and Fig 16 show the circuit of the comparator 2 lt H CO1 CIN2 gt CIN1 2 1 CO1 CIN2 CIN1 CIN2 CIN1 CIN2 CIN1 EM78257A EM78257B CIN3 CIN4 CIN3 CIN4 CIN3 CIN4 CO3 gt CIN3 CIN4 lt 2x 4 Fig 15 Comparator Pin Assignments This specification is subject to change without prior notice 35 2002 05 06 78 257 ROM Fig
32. Enable comparator high interrupt IOW or DISI Enable or disable global interrupt SLEP Sleep NOP One problem user must be aware of is that after waking up from the sleep mode WDT will enable automatically The WDT operation being enabled or disabled should be handled appropriately by software after waking up from the sleep mode 2 IRESET Configure Refer to Fig 11 When the RESET bit in the OPTION word is programmed to 0 the external RESET is enabled When programmed to 1 the internal RESET is enabled tied to the internal Vdd and the pin is defined as P7 1 Setup time Fig 11 Block Diagram of Reset of Controller 4 6 The status of RST T and P of STATUS register A RESET condition is initiated by one of the following events 1 A power on condition 2 A high low high pulse on the RESET pin or This specification is subject to change without prior notice 31 2002 05 06 78 257 ROM 3 Watchdog timer time out The values of RST T and P as listed in Table 5 below are used to check how the processor wakes up Table 5 shows the events which may affect the status of RST T and P Table 5 The Values of RST T and P after RESET Reset Type T Powron 20 0 f 1 PRESET Operatngmage o f r E wake up during SLEEP mode WDT during Operating mode wake up during SLEEP made 00 07 Wake Up pin change during SLEEP mode
33. IN 1 4 gt normal I O pin Example 2 1 0 1010 gt Comparator 4 combine together with Comparator 3 and Comparator 2 and both of CIN3 CIN2 work as normal I O pins C1 CIN1 col CINI 2 gt CIN2 CIN2 Normal I O CIN3 CIN3 Normal I O CO3 CIN4 CO4 CIN4 2 Comparator Outputs The compared result are stored in the CMPOUT of R9 The comparator outputs can output to P51 P52 P63 and P64 by programming Bits 4 5 6 and 7 lt 90 gt of the CMP control register to 1 P52 P51 P63 and P64 must be configured as output if implemented Fig 17 shows the comparator output block diagram This specification is subject to change without prior notice 37 2002 05 06 78 257 COIEX e e From 1 E nni EN EN Q D 0 To CMPOUT RESET COIEX LN To LL CMPXIF CMPXIE Fig 17 The Output Configuration of a Comparator 3 Programming the Related Registers When defining Comparators refer to the related registers of its operation as shown in Table 11 and Table 12 below Table 11 Related Control Registers of the Comparators Address Bit7 Bie Bits Bit4 Bit2 Bit1 Bito 0x09 90 COIE4 0 COIE2 0 1 0 4 0 0 2 0 CE1 0 cocsmoce o o o
34. M78P257A B 0 0000 0000 rrrr None lt Note1 gt 0 0000 0001 0011 0013 RETI Top of Stack PC Enable None Interrupt 0 0000 0001 0100 0014 CONTR CONT gt A 0 0000 0001 rrrr 001 IORR IOCR gt A None lt Note1 gt R2 A gt R2 0 0000 0010 0000 0020 Bit8 9 do not clear Z C DC 0001 iir mr DEOR M R4oR 27 0 0010 00r rrr 0 AvVRGA 2 0010 rr 02r __ AvVROR 2 0 0010 10r rr O2r ANDAR 272 0010 tir rr ANDRA 2 0011 0 rr XORAR 2 0 0011 Otrr mr XORRA _ AOGRGR 7 0 0100 0 rr MOVAR ROGA 2 0100 rr MOVRR 2 0100 10 rr 2 0100 11 COMR 2 0 0101 Obr 2 0 0101 Otrr rr Obr 2 R n gt A n 1 0 0110 OOrr rrrr O6rr RRCAR R 0 gt C C C R n 2 R n 1 0 0110 O1rr rrrr O6rr RRCR R 0 gt C C gt R 7 C 0 0110 101 rrr O6rr RLCAR 522240 c gt 5 EZ R n 1 0 0110 11rr O6rr RLCR 7 3C C gt R O 3 gt 4 E 0 0111 OOrr rrrr O7rr SWAPA R R 4 7 A 0 3 None 0 0111 Otrr_rrrr SWAP R R 0 3 lt gt R 4 7 0 0111 10rr JZAR 1 A skip if zero 0 0111 117 R 1 gt R skip if zero This specification is subject to change without prior notice 64 2002 05 06 78 2
35. P1IF Status changed interrupt flag Set as change occurred in the output of Comparator CO1 and reset by software Bit 5 CMP2IF Status changed interrupt flag Set as change occurred in the output of Comparator CO2 and reset by software Bit 6 CMP3IF Status changed interrupt flag Set as change occurred in the output of Comparator CO3 and reset by software Bit 7 CMP4IF Status changed interrupt flag Set as change occurred in the output of Comparator COA and reset by software RF can be cleared by instruction but cannot be set e OCFO is the relative interrupt mask register e Note that the result of reading RF is the logic AND of RF and IOCOF 15 R10 R3F All of these are the 8 bit general purpose registers 4 2 Special Purpose Registers 1 A Accumulator Internal data transfer or instruction operand holding can not be addressed 2 CONT Control Register 1 110 INTE INT 15 PSR2 PSRO 0 PSRO 2 PSR2 TCC prescaler bits This specification is subject to change without prior notice 14 2002 05 06 78 257 Bit 4 TE TCC signal edge 0 increment if the transition from low to high takes place on TCC pin 1 increment if the transition from high to low takes place on TCC pin Bit 5 TS TCC signal source 0 internal instruction cycle clock 1 transition on TCC pin
36. TCCC Counter An eight bit clock counter It can be read written and cleared on any reset condition When in Mouse Mode it is Up Down Counter else it is UP Counter 16 IOC91 Low time Register The 8 bit Low time register controls the active or Low period of the pulse The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is active The active period of IR OUT can be calculated as follows ti ow decimal value held Low time register fosc 17 1 High time Register The 8 bit High time register controls the inactive or High period of the pulse This specification is subject to change without prior notice 24 2002 05 06 78 257 ROM The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is inactive The inactive period of IR OUT can be calculated as follows tuigh decimal value held in High time register fosc 18 IOCB1 Pulse timer Register The contents of the Low time and High time register are loaded alternately into the Pulse timer When loaded the contents of Pulse timer are decremented on every oscillator cycle Upon reaching zero the Pulse timer will be loaded with the contents of the other 4 3 TCC WDT amp Prescaler There are two 8 bit counters available as prescalers for the TCC and WDT respectively The PSRO PSR2 bits of the CONT register are used to determine
37. The summary of maximum operating speeds Conditions Two clocks 2 Crystal Oscillator Ceramic Resonators XTAL EM78P257A B can be driven by an external clock signal through the OSCI as shown in Fig 21 below OSCI 78 257 OSCO Fig 21 Circuit for External Clock Input In most applications pin OSCI and pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation Fig 22 depicts such circuit The same thing applies whether it is in the HXT mode or in the LXT mode Table 16 provides the recommended values of C1 and C2 Since each resonator has its own attribute user should refer to its specification for appropriate values of C1 and C2 RS a serial resistor may be necessary for AT strip cut crystal or low frequency mode OSCI EM78P257A B RS C2 Fig 22 Circuit for Crystal Resonator Table 16 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators This specification is subject to change without prior notice 45 2002 05 06 78 257 Oscillator Type Ee Ceramic Resonators HXT Crystal Oscillator 78 257 Fig 24 Circuit for Crystal Resonator Parallel Mode 3 External RC Oscillator Mode For some applications that do not need to have its timing to be calculated precisely the RC oscillator IV 12 3 1 offers a lot of cost savings Nevertheless it should be note
38. ain Control Register ec ege 4 8 7 1 1 10 Bit 0 OD60 Use to enable the open drain of P60 pin This specification is subject to change without prior notice 21 2002 05 06 78 257 ROM 0 Disable open drain output 1 Enable open drain output Bit 1 OD61 Use to enable the open drain of P61 pin Bit 2 OD62 Use to enable the open drain of P62 pin Bit 3 OD63 Use to enable the open drain of P63 pin Bit 4 OD64 Use to enable the open drain of P64 pin Bit 5 OD65 Use to enable the open drain of P65 pin Bit 6 OD66 Use to enable the open drain of P66 pin Bit 7 OD67 Use to enable the open drain of P67 pin e OCCO Register is both readable and writable 9 IOCDO Pull high Control Register N eee Bit 0 PH50 Use to enable the pull high of P50 pin 0 Enable internal pull high 1 Disable internal pull high Bit 1 PH51 Use to enable the pull high of P51 pin Bit 2 PH52 Use to enable the pull high of P52 pin Bit 3 PH53 Use to enable the pull high of P53 pin Bit 4 PH54 Use to enable the pull high of P54 pin Bit 5 PH55 Use to enable the pull high of P55 pin Bit 6 PH56 Use to enable the pull high of P56 pin for EM78P257B only Bit 7 PH57 Use to enable the pull high of P57 pin for EM78P257B only OCDO Register is both readable and writable 10 IOCEO WDT Control Register wore EIS
39. bject to change without prior notice 28 2002 05 06 78 257 ROM Table 4 Usage of Port 5 Input Status Changed Wake up Interrupt Function 0 Wake up from Port 5 Input Status Change 1 Port 5 Input Status Change Interrupt a Before SLEEP 1 Read I O Port 5 MOV R5 R5 1 Disable WDT 2 Execute ENI 2 Read I O Port 5 MOV R5 R5 3 Enable interrupt Set IOCF 1 3 Execute or DISI 4 IF Port 5 change interrupt 4 Enable interrupt Set IOCF 1 Interrupt vector 3FEH 5 Execute SLEP instruction b After Wake up 1 IF ENI 2 Interrupt vector 3FEH 2 IF DISI Next instruction 4 5 RESET and Wake up 1 RESET A RESET is initiated by one of the following events 1 Power on reset 2 RESET pin input low or 3 Watch dog timer time out if enabled The device is kept in a RESET condition for a period of approximately 18ms or 1ms one oscillator start up timer period after the reset is detected The initial address is 000h Once the RESET occurs the following events are performed The oscillator is running or will be started Program Counter R2 is set to all 0 All I O port pins are configured as input mode high impedance state The Watchdog timer and prescaler are cleared When power is switched on the upper 3 bits of R3 are cleared The bits of the CONT register are set to all 1 except for the Bit 6 INT flag The bits of the IOCBO register ar
40. can choose P55 or OSCI only and the choice is decided by Bit 9 8 7 of CODE option When choice is 1 1 1 then Pin 16 is defined as P55 otherwise the status is defined as OSCI For EM78P257B This specification is subject to change without prior notice 16 2002 05 06 78 257 ROM Pin 19 can choose P51 or only If MOUSEN is 1 define an input of if MOUSEN is 0 then the choice is decided by TCCBTS of RB Pin 18 can choose P50 TCC4 only If MOUSEN is 1 and TCC4E of IOC80 is 1 also then choose TCC4 otherwise choose P50 Pin 17 can choose P55 or OSCI only and the choice is decided by Bit 9 8 7 of CODE option When choice is 1 1 1 then Pin 17 is defined as P55 otherwise the status is defined as OSCI 1 Comparator CO1 is on For EM78P257A Pin 18 can choose P51 or CO1 only and the choice is decided by COIE1 of IOC90 Pin 17 can choose CIN1 only Pin 16 can choose P55 1 or OSCI and is decided by IOCAO If CIN1 was not chosen as comparator1 input then this pin s status will be decided by Bit 9 8 7 of CODE option When choice is 1 1 1 then Pin 16 is defined as P55 otherwise the status is defined as OSCI For EM78P257B Pin 19 can choose P51 or CO1 only and the choice is decided by COIE1of IOC90 Pin 18 can choose CIN1 only Pin 17 can choose P55 CIN1 or OSCI and is decided by IOCAO If CIN1 was not chosen as comparator1
41. d that the frequency of the RC oscillator is influenced by the supply voltage the values of the resistor Rext the capacitor Cext and even by the operation temperature Moreover the frequency also changes slightly from one chip to another due to the manufacturing process variation This specification is subject to change without prior notice 46 2002 05 06 78 257 ROM In order to maintain a stable system frequency the values of the Cext should not be less than 20pF and that the value of Rext should not be greater than 1 M ohm If they cannot be kept in this range the frequency is easily affected by noise humidity and leakage The smaller the Rext in the RC oscillator the faster its frequency will be On the contrary for very low Rext values for instance 1 KO the oscillator becomes unstable because the NMOS cannot discharge the current of the capacitance correctly Based on the reasons above it must be kept in mind that all of the supply voltage the operation temperature the components of the RC oscillator the package types the way the PCB is layout will affect the system frequency e Vcc j gt Rext OSCI 78 257 Fig 25 Circuit for External RC Oscillator Mode Table 17 RC Oscillator Frequencies Average Fosc 5V 25 C Average Fosc 3V 25 C 3 18 MHz 2 75MHz 20 pF 2 1 MHz 2 0MHz 1 14 MHz 1 12 MHz 100k 118 KHz 121 KHz 1 25 MHz 1 20 KHz 100 pF 830 KHz 815 KHz
42. e from where the subroutine was called regardless of the current PSO bit setting PSO Program memory page Address 0 Page 0 000 3FF e Bit6 IOCS Select the Segment of the control register 0 Segment 0 IOC50 IOCFO selected 1 Segment 1 IOC51 IOCF1 selected Bit 7 RST Bit for reset type Set to 1 if wake up from sleep on pin change or comparator status change Set to 0 if wake up from other reset types R4 RAM Select Register Bits 0 5 are used to select a register address 00 0 10 3 in the indirect addressing mode Bit 6 is used to select bank 0 or bank 1 Bits 7 is General purpose read write bit e See the configuration of the data memory in Fig 5 R5 R6 Port 5 Port 6 R5 and R6 are I O registers This specification is subject to change without prior notice 10 2002 05 06 78 257 Only the lower 6 bits of R5 are available applicable to EM78P257A The upper 2 bits of R5 are fixed to O if EM78P257A is selected 7 R7 Port 7 7 6 5 4 3 2 1 0 R7 is I O registers Only the lower 2 bits of R7 are available 8 R9 CMPOUT Status Register 8 TCC Status Register 7 6 5 4 3 2 1 0 CMPOUTA CMPOUT3 CMPOUT2 CMPOUT1 TCCCIF TCCBIF TCCAIF Bit 0 TCCAIF TCCA overflowing interrupt flag Set when TCCA overflow reset by software Bit 1 TCCBIF TCCB overflowing interrupt flag Set when TCCB overflow reset by
43. e in the interrupt service routine the source of an interrupt can be determined by polling the flag bits in RF The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts The flag except ICIF bit in the Interrupt Status Register RF is set regardless of the status of its mask bit or the execution of ENI Note that the outcome of RF will be the logic AND of RF and IOCFO refer to Fig 12 The RETI instruction ends the interrupt routine and enables the global interrupt the execution of ENI When an interrupt is generated by the Timer clock counter when enabled the next instruction will be fetched from address 3FA 3F8 3F6 and 3 4 and TCCC When an interrupt is generated by the Comparators when enabled the next instruction will be fetched from address 3F2 3F0 3EE or 3ECH individually CO1 CO2 CO3 or CO4 Before the interrupt subroutine is executed the contents of ACC and the R3 register will be saved by hardware If another interrupt occurred the ACC and R3 will be replaced by the new interrupt After the interrupt service routine is finished ACC and R3 will be pushed back RF gt DISI D RD e IOCFWR RESET IOCFRD 74 g US z RFWR Fig 12 Interrupt input circuit This specification is subject to change without prior notice 33 2002 05 06 78
44. e set to all 1 IOCCO register is cleared The bits of the IOCDO register are set to all 1 Bit 7 of the IOCEO register is set to 1 and the others are cleared RF and IOCFO register are cleared The sleep power down mode is attained by executing the SLEP instruction While entering sleep mode WDT if enabled is cleared but keeps on running The controller can be awakened by 1 external reset input on RESET pin 2 WDT time out if enabled This specification is subject to change without prior notice 29 2002 05 06 78 257 ROM 3 Port 5 input status changed if enabled 4 Comparator status changed The first two cases will cause the EM78P257A B to reset The T and P flags of can be used to determine the source of the reset wake up Case 3 is considered the continuation of program execution and the global interrupt ENI or DISI being executed decides whether or not the controller branches to the interrupt vector following wake up If ENI is executed before SLEP the instruction will begin to execute from the address 3FEH after wake up If DISI is executed before SLEP the operation will restart from the instruction right next to SLEP after wake up Only one of Cases 2 and 3 can be enabled before entering the sleep mode That is a if Port 5 input status changed interrupt is enabled before SLEP WDT must be disabled by software However the WDT bit in the option
45. e tenth clock the system receives the data If EM78P257A B is not transmitting or if the system choose to override the output the system forces CLK to an inactive This specification is subject to change without prior notice 53 2002 05 06 78 257 ROM level for a period of not less than 100 while preparing for output When the system is ready to output start bit 0 it allows CLK to go to active level If request to send is detected 78 257 clocks 11 bits Following the tenth clock EM78P257A B checks for an active level on the DATA line and if found forces DATA to low and clock once more If framing error occurs EM78P257A B continues to clock until DATA is high then clocks the line control bit and requests for a Resend When the system sends out a command or data transmission that requires a response the system waits for EM78P257A B to respond before sending its next output 1 2 1 2 71 22 INPUT IMPEDANCE ystem CLK Active Time ystem CLK Inactive Time ime from DATA Transition to Falling Edge of CLK In Oscillating Frequency 34 3 KHz This specification is subject to change without prior notice 54 2002 05 06 78 257 ROM 4 14 INFRARED REMOTE APPLICATION MODE 1 Overview amp Features Overview 78 257 is designed for use in universal infrared remote commander applications Fig 29 shows the hardware modulator
46. gh the pin or by the instruction cycle clock Writable and readable as any other registers The prescaler RC is assigned to TCC The contents of the prescaler counter is cleared only when a value is written to TCC register This specification is subject to change without prior notice 7 2002 05 06 78 257 ROM 3 R2 Program Counter amp Stack PC Depending on the device type R2 and hardware stack are 11 bits wide The structure is depicted in Fig 4 e Generates 2Kx13 on chip ROM addresses to the relative programming instruction codes One program page is 1K words long e R2 is set as all O s when under RESET condition e JMP instruction allows direct loading of the lower 10 program counter bits Thus JMP allows PC go to any location within a page CALL instruction loads the lower 10 bits of the PC and then PC 1 is pushed into the stack Thus the subroutine entry address can be located anywhere within a page RET RETL k RETI instruction loads the program counter with the contents of the top level stack ADD R2 A allows the contents of A to be added to the current PC and the ninth and tenth bits of the PC are cleared MOV R2 A allows to load an address from the A register to the lower 8 bits of the PC and the ninth and tenth bits of the PC are cleared Any instruction that is written to R2 e g ADD R2 A MOV R2 A BC R2 6 will cause the
47. he TCCCIF interrupt Bit 3 Not used Bit 4 TCCBTE TCCB signal edge 0 increment if the transition from low to high leading edge takes place on the TCCA pin 1 increment if the transition from high to low leading edge takes place on the TCC4 pin Bit 5 TCCBTS TCCB signal source 0 internal instruction cycle clock 1 transition on the TCC3 pin Bit 6 TCCBIE TCCBIF interrupt enable bit 0 disable the TCCBIF interrupt 1 enable the TCCBIF interrupt Bit 7 Not used Table 24 MOUSE Control Register 7 MOUSEN e Bit O Bit 6 Not used Bit 7 MOUSEN Mouse application Enable bit 0 Disable MOUSEN TCCA TCCB and TCCC are increment counters 1 Enable MOUSEN RA disable 5 is 1 Bit2 TCCAIE is 0 RB disable Bit1 TCCCTS is 1 Bit2 TCCCIE is 0 Bi disable Bit4 TCCBTE 5 5 is 1 is 0 and TCCA TCCBL TCCC work as up down counters For other pin assignments refer to OC80 4 MOUSE mode Timing 1 Photo couples pulse width X1 Y1 X2 Y2 Tr Tf Counter increment if the rising falling edge of X1 is leading the one on X2 This specification is subject to change without prior notice 52 2002 05 06 78 257 ROM Counter decrement if the rising falling edge of X1 is falling behind the one on X2 2 Sending DATA data from EM78P257A B to system
48. in 42 CIN2 gt negative input CIN4 gt normal I O pin 4 gt negative input CIN 1 4 gt normal I O pin 0 0 0 0 po f 0 0 1 1 Lo x p 0 EGNESE SEU 0 1 1 0 11110101 Pacer ENSESNBE This specification is subject to change without prior notice 20 2002 05 06 78 257 ROM Example 13 12 11 10 1010 gt Comparator 4 combined together with Comparator 3 and Comparator 2 and both CIN2 and CIN3 work as normal I O pins CIN1 col CINI gt CIN2 CIN2 Normal I O CIN3 CIN3 Normal I O CO3 CIN4 CO4 CIN4 7 IOCBO Pull down Control Register EE EE Ea ee ee Bit 0 PD50 Control bit is used to enable the pull down of P50 pin 0 Enable internal pull down 1 Disable internal pull down Bit 1 PD51 Use to enable the pull down of P51 pin Bit 2 PD52 Use to enable the pull down of P52 pin Bit 3 PD53 Use to enable the pull down of P53 pin Bit 4 PD54 Use to enable the pull down of P54 pin Bit 5 PD55 Use to enable the pull down of P55 pin Bit 6 PD56 Use to enable the pull down of P56 pin for EM78P257B only Bit 7 PD57 Use to enable the pull down of P57 pin for EM78P257B only e OCBO Register is both readable and writable 8 IOCCO Open dr
49. in Low time register fosco High time Register The 8 bit High time register control the inactive or High period of the pulse The decimal value of its contents determines the number of oscillator cycles indicating that the IR OUT pin is active The inactive period of IR OUT can be calculated as follow tuign decimal value held in High time register fosco Pulse Timer The contents of the Low time and High time Latch registers are loaded alternately into the Pulse timer When loaded the Pulse timer contents are decremented by 1 every oscillator cycle and upon reaching zero the Pulse This specification is subject to change without prior notice 56 2002 05 06 78 257 timer will be loaded with the contents of the other register IR control register Contains the bits that control various possibilities for the output pulse LSB Counter MSB Counter Loaded by software with the number of pulses required in a pulse burst loading 0 is not allowed IRE Infrared Remote Enable bit IR OUT IR output port ligour 20mA when the output voltage drops to 2 4V at Vdd 5V 2 1 Operation of the Hardware Modulator 1 Enable IRE set parameter for IR RD 2 Load Low time register IOC91 3 Load High time register IOCA1 4 Load MSB and LSB Counter register IOC61 IOC71 The Low time High time MSB Counter and LSB Counter register are loaded by s
50. inal or external clock input pin RC type RC oscillator input pin 2 XTAL type output terminal for crystal oscillator or external clock input pin RC type clock output with a duration of one instruction cycle clock signal input Default value after a power on reset General purpose 1 pin Open_drain Default value after a power on reset P55 1 3 General purpose pin 16 18 Pull_high pull_down Wake up from sleep mode when the status of the pin changes Default value after a power on reset R OUT 13 O 1 mode output pin capable of sinking 30mA INT 6 11 External interrupt pin triggered by falling edge 4 the input pin of Vin of a comparator the input pin of Vin of a comparator Pin CO1 4 are the outputs of the comparators This specification is subject to change without prior notice 4 2002 05 06 78 257 External Counter input 7 18 17 RESET If set as RESET and remains at logic low the device will be reset Voltage on RESET Vpp must not exceed Vdd during the normal mode Pull high is on if defined as RESET Ground vss 5 Ground TCC5 P56 P57 TCC6 CO2 P52 P51 CO1 TCC3 CIN2 P53 50 4 TCC CIN2 P54 P55 CIN1 OSCI RESET P71 Z 70 8 VSS VDD INT P60 P67 IR OUT TCCI CIN3 P61 P66 CIN4 TCC2 CIN3 P62 P65 CIN4 CO3 P
51. ion cycles Case A is selected by the CODE Option bit called CLKS One instruction cycle consists of two oscillator clocks if CLKS is low and four oscillator clocks if CLKS is high Case B is selected by another CODE Option bit called CYES Execution of the instructions listed in Case B takes one instruction cycle if CYES is low and takes two instruction cycles if CYES is high Case A and Case B are independent options that is they can be selected separetely Note that once the 4 oscillator periods within one instruction cycle is selected under Case A the internal clock source to TCC will be CLK Fosc 4 not Fosc 2 as illustrated in Fig 6 In addition the instruction set has the following features 1 Every bit of any register can be set cleared or tested directly 2 The 1 register can be regarded as general register That is the same instruction can operate on 1 register The symbol R represents a register designator that specifies which one of the registers including operational registers and general purpose registers is to be utilized by the instruction b represents a bit field designator that selects the value for the bit which is located in the register R and affects the operation k represents an 8 or 10 bit constant or literal value This specification is subject to change without prior notice 63 2002 05 06 78 257 ROM Table 32 The List of the Instruction Set of E
52. ition may cause a poor power on reset Fig 19 and Fig 20 show how to build a residue voltage protection circuit This specification is subject to change without prior notice 43 2002 05 06 78 257 ROM 33K gt 10 IRESET 100K 144684 Fig 19 Circuit 1 for the residue voltage protection M78P257A B IRESET Fig 20 Circuit 2 for the residue voltage protection 4 12 Oscillator 1 Oscillator Modes The 78 257 can be operated in the five different oscillator modes such as Internal RC oscillator mode IRC RC oscillator with Internal capacitor mode IC External RC oscillator mode ERC High XTAL oscillator mode HXT and Low XTAL oscillator mode LXT User can select one of them by programming 5 2 51 and OSCO in the CODE Option register Table14 depicts how these five modes are defined The up limited operation frequency of crystal resonator on the different VDDs is listed in Table 15 Table 14 Oscillator Modes defined by OSC2 0SC1 and OSCO 0502 5 osco IC Internal C oscillator mode 1 1 o ERC External RC oscillator mode 4 1 0 HXT High XTAL oscillator mode Co f oya 4 This specification is subject to change without prior notice 44 2002 05 06 78 257 ROM LXT Low XTAL oscillator mode 0 0 0 Note The transient point of system frequency between HXT and LXT is around 400 KHz Table 15
53. n as comparator1 input then this pin s status will be decided by TCCATS of RA When TCCATS is 1 then Pin 8 is defined as TCC1 otherwise the status is defined as P61 Bit 3 CE4 Comparator CO4 enable bit 0 Comparator is 4 off default value For EM78P257A Pin 10 can choice P64 only Pin 11 can choose P65 only Pin 12 can choose P66 or TCC2 only If MOUSEN is 1 and TCC2E of IOC80 is also 1 then set pin to TCC2 otherwise set to P66 For EM78P257B Pin 11 can choose P64 only Pin 12 can choose P65 only Pin 13 can choose P66 or TCC2 only If MOUSEN is 1 and TCC2E of IOC80 is 1 also then set pin to TCC2 otherwise set to P66 1 5 Comparator is 4 on For EM78P257A Pin 10 can choose P64 or CO4 only and decided by COIE4 of IOC90 Pin 11 can choose CIN4 only Pin 12 can choose P66 CIN4 or 2 and the choice is decided by IOCAO If CINA was not chosen as comparator1 input this pin will decide to set MOUSEN as 1 and TCC2E of IOC80 is also set as 1 then set the pin to TCC2 otherwise set the pin to P66 For EM78P257B Pin 11 can choose P64 or CO4 only and decided by COIE4 of IOC90 Pin 12 can choose CIN3 only This specification is subject to change without prior notice 19 2002 05 06 78 257 ROM Pin 13 can choose P66 CIN4 TCC2 and the choice is decided by IOCAO If CINA was not chosen as comparator input this pin will decide to
54. o GP1 EN P67 78 257 lRESETandwDT Wake Up from Pin Change eee wor P Wake Up from Pin Change n iy adn bod ird Bit Name E23 RESETandwoT P Chan ge rocer mesetandwor o o o o o RD Wake Up from Pin Change 29 zc U 0 MF1 MFO HF LGP PWM 0 o o o Lo o o o Bit Name OxE RE Power On TMR2L RESET and WDT Wake Up from Pin Change Bit Name MP4IF Power O OxF RESET and WoT Wake Up from Pin Change Bit Name Power O 0x10 0x R10 R3F Wake Up from Pin X not used U unknown or don t care P previous value before reset t check Table 5 4 11 Power On Considerations Any microcontroller is not warranted to start proper operation before the power supply reaches its steady state This specification is subject to change without prior notice 42 2002 05 06 78 257 ROM The EM78P257A B is equipped with Power On Voltage Detector with a detecting level of 1 4 V to 2 0 V The extra external reset circuit will work well if Vdd rises fa
55. o cao cuo Table 12 Related Status Data Registers of Comparators Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit2 Bit 1 Bit 0 0x09 9 4 0 CMPOUT3 0 CMPOUT2 0 CMPOUT1 0 0 TCCCIF O TCCBIF O TCCAIF O ISR RF CMP4IF O 21 0 CMP1IF O 0 TCIF O 4 Interrupt INT and CMPXIE must be enable Interrupt occurs whenever a change takes place on the output pin of the comparators The actual changes on the pins can be determined by reading the bits CMPOUTX and R9 lt P7 P4 gt CMPXIF the comparator interrupt flag can only be cleared by software 5 Wake Up from SLEEP mode If enabled the comparators remains active and the interrupt stays functional during SLEEP mode If a mismatch occurs the interrupt will wake up the device from SLEEP mode This specification is subject to change without prior notice 38 2002 05 06 78 257 ROM The power consumption should be taken into consideration for the sake of power saving If the function is unemployed during the SLEEP mode turn off comparators before entering into sleep mode 4 10 The Initialized Values after Reset Table 13 Summary of the Initialized Values for Registers Wake Up from Pin Change Bit Name 0060 RESET and WDT 10C70 RESET and WDT ira Change Bit Name TCC2E
56. oftware The following instructions is an example for generating five pulses train MOV A 0B00001000 MOV 0x0D A Enable IR MOV A 0 10 IOW 0x08 Enable TCCBH BS 0x03 6 Select control register segment 1 MOV 0 10 IOW 0x09 Set Low Time Register 10h MOV 0 20 IOW 0x0A Set High Time Register 20h MOV 0 5 Set pulse number 5 gt LSB 5 MSB 0 IOW 0x06 LSB 5 MOV A 0x00 IOW 0x07 MSB 0 As soon as the LSB Counter Register is loaded the Hardware Modulator is started and IR OUT becomes active LOW Simultaneously the contents of the Low time register are loaded into the Pulse Timer which is then decremented by 1 every oscillator clock cycle When the value held in the Pulse Timer becomes zero the contents of the LSB amp MSB Counter are decremented by 1 and IR OUT become inactive HIGH The contents of the High time register are now loaded into the Pulse Timer which is decremented by 1 every oscillator clock cycle When the value held in the Pulse Timer becomes zero IR OUT becomes active LOW One pulse cycle has now been generated The process of alternately loading the contents of the Low time register and High time register into the Pulse Timer continues until the contents of the LSB amp MSB Counter become zero When this occurs TCCBIF is asserted an interrupt to the CPU is generated and the interrupt flag is This specification is subject to change without prior notice 5
57. omparator input Comparator Output level is decided by comparing the value of its two pins Counter Recording the horizontal vertical or rolling shifting values 3 Programming the Related Registers When defining MOUSE mode refer to the related register of its operation as shown in the Table 20and Table 21 below Table 20 Related Control Registers of the MOUSE Mode Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit3 Bit 2 Bit1 Bit 0 CONT INTE O INT O 5 0 0 0 PSR2 0 PSR1 0 PSRO O 0x08 80 TCC2E 0 TCC4E 0 6 0 0 0 _ 9 0 0 0 90 0 0 TCCAIE o TCCATS O TCCATE O 2 0 0 5 0 TCCBTE O 0 0 5 0 TCCCTE O OXO MCRRE jMOUENO 0 0 0 0 0 o 0 lt Note gt Bit name initial value This specification is subject to change without prior notice 50 2002 05 06 78 257 ROM Table 21 Related Status Data Register of the MOUSE Mode Address Bit 7 Bit 6 Bit 5 2 Bit Bito 0x01 TCC R1 5 4 TCC2 0 09 TCCSR R9_ CMPOUT4 CMPOUT3 CMPOUT2 CMPOUT1 0 eight bit time clock counter A In MOUSE mode it will load X axis data into TCCA it is defined as an increment decrement counter
58. r edges and overflow interrupt 4 sets of comparators Easy implemented IR Infrared remote control application circuit Easy implemented MOUSE application circuit Power down SLEEP mode Five interrupt sources TCC overflow interrupt Input port status changed interrupt wake up from the sleep mode External interrupt This specification is subject to change without prior notice 2 2002 05 06 78 257 ROM R OUT interrupt Comparators status change interrupt Programmable free running watchdog timer e 8 programmable pull high I O pins 8 programmable open drain I O pins e 8 programmable pull down I O pins Two clocks per instruction cycle Package types 18 pin DIP 300mil EM78P257AP 20 pin DIP 300mil EM78P257BP 18 pin SOP 300mil EM78P257AM 20 pin SOP 300mil EM78P257BM Power on voltage detector available for both EM78P257A and EM78P257B This specification is subject to change without prior notice 3 2002 05 06 78 257 ROM 3 PIN ASSIGNMENT CO2 P52 P51 CO1 TCC3 CIN2 P53 PSO CINI TCC4 TCC CIN2 P54 P55 CIN1 OSCI RESET P71 Z 70 8 VSS VDD INT P60 2 P67 IR OUT TCC1 CIN3 P61 P66 CIN4 TCC2 CIN3 P62 P65 CIN4 CO3 P63 64 4 Fig 1 Pin Assignment EM78P257A Table 1 Pin Description EM78P257A Symbol PinNo Type Function sc ie 1 1 Df eC apt ao ooma XTAL type Crystal input term
59. register remains enabled Hence the EM78P257A B can be awakened only by Case 1 or 3 Similarly the same procedures should be applied if comparator status change interrupt is used The device can be awakened only by Case 1 or 4 b if WDT is enabled before SLEP Port 5 Input Status Change Interrupt must be disabled Hence the EM78P257A B can be awakened only by Case 1 or 2 Refer to the section on Interrupt If Port 5 Input Status Change Interrupt is used to wake up the EM78P257A B the following instructions must be executed before SLEP MOV A 8 xx0001 10b Select internal TCC clock CONTW CLR R1 Clear TCC and prescaler MOV A xxxx1110b Select WDT prescaler CONTW WDTC Clear WDT and prescaler MOV A Disable WDT IOW MOV 5 5 Read Port 5 MOV A 00000x1xb Enable Port 5 input change interrupt IOW RF or DISI Enable or disable global interrupt SLEP Sleep NOP In a similar way if the Comparator Status Changed Interrupt is used to wake up the 78 257 the following instructions must be executed before SLEP MOV A 0bxx000110 Select internal TCC clock CONTW CLR R1 Clear TCC and prescaler MOV A 06 1110 Select WDT prescaler CONTW WDTC Clear WDT and prescaler This specification is subject to change without prior notice 30 2002 05 06 78 257 ROM MOV A Disable WDT IOW RE MOV A 0b1111xxxx
60. rupt enable bit 0 disable CMP2IF interrupt 1 enable CMP2IF interrupt Bit 6 CMP3IE CMP3IF interrupt enable bit This specification is subject to change without prior notice 23 2002 05 06 78 257 0 disable interrupt 1 enable CMP3IF interrupt Bit 7 CMP4IE interrupt enable bit 0 disable CMPAIF interrupt 1 enable CMPAIF interrupt Individual interrupt is enabled by setting its associated control bit in the IOCFO to 1 Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction Refer to Fig 10 IOCFO register is both readable and writable 12 IOC51 TCCA Counter An eight bit clock counter It can be read written and cleared on any reset condition When in Mouse Mode it is Up Down Counter else it is UP Counter 13 IOC61 TCCBL Counter LSB Counter An eight bit clock counter is for the least significant byte of TCCBX TCCBL It can be read written and cleared on any reset condition When in Mouse Mode it is Up Down Counter When in IR Mode it is Down Counter else it is Up Counter 14 IOC71 TCCBH Counter MSB Counter An eight bit clock counter is for the most significant byte of TCCBX TCCBH It can be read written and cleared on any reset condition When TCCBE IOC80 is 0 THEN TCCBH is disable TCCBE is 1 then TCCB is 16 bit length counter When it is in IR Mode it is Down Counter else it is UP Counter 15 1OC81
61. s comparator1 input then this pin will be decided by Bit 5 of Control Register CONT 5 When TS is 1 then Pin 4 is defined as TCC otherwise status defined as P54 Bit 2 CE3 Comparator CO3 enable bit 0 Comparator is off default value For EM78P257A Pin 9 can choose P63 only Pin 8 can choose 2 only Pin 7 can choose P61 or TCC1 only If MOUSEN is 1 define pin as an input of TCCA TCC1 If MOUSEN is 0 then the choice is decided by TCCATS of RA For EM78P257B Pin 10 can choose P63 only Pin 9 can choose 2 only Pin 8 can choose P61 or TCC1 only If MOUSEN is 1 defined pin as an input of TCCA TCC1 if MOUSEN is 0 then the choice is decided by TCCATS of RA 1 Comparator is on For EM78P257A Pin 9 can choose P63 or only and decided by COIE3 of IOC90 Pin 8 can choose 1 only This specification is subject to change without prior notice 18 2002 05 06 78 257 ROM Pin 7 can choose P61 CIN3 TCC1 and the choice is decided by IOCAO If CIN3 was not chosen as comparator1 input then this pin s status will be decided by TCCATS of RA When TCCATS is 1 then Pin 7 is defined as TCC1 otherwise the status is defined as P61 For EM78P257B Pin 10 can choose P63 or only and decided by COIE3 of IOC90 Pin 9 can choose CIN3 only Pin 8 can choose P61 CIN3 or TCC1 and is decided by IOCAO If CIN3 was not chose
62. se train DP 00 MF 10 HF 0 LGP 0 PWM 1 4 15 CODE OPTION EM78P257A B has one CODE option word and one Customer ID word which are not a part of the normal program memory Word 0 Word 1 Bit12 BitO Bit12 BitO Code option12 0 Customer s ID 1 Code Option Register Word 0 Bit12 Bit11 RESETEN ENWDT Bit 12 RESETEN Define pin4 EM78P257A or 5 78 257 as a reset 0 RESET enable 1 RESET disable Bit 11 Watchdog timer enable bit 0 Enable This specification is subject to change without prior notice 61 2002 05 06 78 257 ROM 1 Disable Bit 10 CLKS Instruction period option bit 0 Two clocks 1 Four clocks Refer to the section on Instruction Set Bit 9 8 and 7 OSC2 0SC1 and OSCO Oscillator Modes Selection bits Table 31 Oscillator Modes Defined by OSC2 0SC1 and OSCO OSC2 0501 osco 1 1 0 IC Internal C oscillator mode ERC External RC oscillator mode 1 o f 141 HXT High XTAL oscillator mode o LXT Low XTAL oscillator mode 0 0o o Note The transient point of system frequency between HXT and is around 400 KHz Bit 6 PTB Protect bit 0 RESET enable 1 RESET disable Bit 5 SUT Set Up Time of device bits 1 8 2 Theoretical values for reference only Bit 4 TYP Type selection for EM78P257A or EM78P257B TYPE 0 EM78P257B EM78P2
63. set MOUSEN as 1 TCC2E of IOC80 is also set as 1 then set the pin to TCC2 otherwise set the pin to P66 Bit 4 COIE1 Set P51 as the output of the comparator CO1 CE1 must be enabled 1 output enabled 0 output disabled and carry out the function of P51 Bit 5 COIE2 Set P52 as the output of the comparator CO2 CE2 must be enabled 1 output enabled 0 output disabled and carry out the function of P52 Bit 6 COIE3 Set P63 as the output of the comparator CO3 CE3 must be enabled 1 output enabled 0 output disabled and carry out the function of P63 Bit 7 COIE7 Set P64 as the output of the comparator 4 4 must be enabled 1 output enabled 0 output disabled and carry out the function of P64 6 0 CO INPUT Combine sequence There are 16 combinations of the negative inputs of the four comparators Table 3 The list of CO INPUT combine sequence CI3 CI2 CI1 CIO CO Input combine status Comment N A 1 2 3 and 4 gt negative inputs i in 2 2 21232 3 input CIN 1 2 gt normal pin 124 J 4 gt negative input CIN 1 2 gt normal pin 234 CIM4 negative input CIN 2 3 gt normal I O pin 1 2 3 4 CIN4 gt negative input CIN 1 2 3 gt normal I O pin 1 1 1 2 2 3 3 4 32 CIN2 gt negative input gt normal I O p
64. st enough 50 ms or less In many critical applications however extra devices are still required to assist in solving power on problems 1 Programmable Oscillator Set Up Time The Option word SUT is used to define the oscillator Set Up time 18ms 1115 Theoretically the range is from 1 ms to 18 ms For most of crystal or ceramic resonators the lower the operation frequency the longer is the required Set up time 2 External Power On Reset Circuit The circuit shown in Fig 18 implements an external RC to produce the reset pulse The pulse width time constant should be kept long enough for Vdd to reach minimum operation voltage This circuit is used when the power supply has slow rise time Because the current leakage from the RESET pin is about 5 it is recommended that R should not be greater than 40 K In this way the voltage in pin RESET will be held below 0 2V The diode D acts as a short circuit at the moment of power down The capacitor C will discharge rapidly and fully Rin the current limited resistor will prevent high current discharge or ESD electrostatic discharge from flowing to pin RESET Vdd R gt EM78P257A B lt IRESET A A N 9 Rin e Fig 18 External Power on Reset Circuit 3 Residue Voltage Protection When battery is replaced device power Vdd is taken off but residue voltage remains The residue voltage may trips below Vdd minimum but not to zero This cond
65. t to change without prior notice 6 2002 05 06 4 FUNCTION DESCRIPTION WDT timer B RESET OSCI i p v v Y Oscillator Timing Y Y i Control be Pres aler 4 Interrupt Instruction controller Register RAM Built in i RI TCC Osc Instruction R4 decoder ROM R2 stack o R3 78 257 STACK I STACK 2 STACK 3 STACK 4 STACK 5 STACK 6 STACK 7 ACC DATA amp CONTROL BUS 50 51 CO2 P52 hocs Comparators ICOUNTER IOC6 CIN24 P53 Uo TCCICIN2 P54 pane OSCI CINI P55 R5 5 56 TCC6 P57 Fig 3 Functional block diagram 4 1 Operational Registers 1 RO Indirect Addressing Register E I O PORT6 P60 INT P61 CIN3 TCC1 P62 CIN3 P63 CO3 P64 CO4 P65 CIN4 P66 CIN4 TCC2 P67 IR OUT RO is not a physically implemented register Its major function is to be an indirect addressing pointer Any instruction using RO as a pointer actually accesses data pointed by the RAM Select Register R4 2 R1 Time Clock Counter TCC Increased by an external signal edge which is defined by the TE bit CONT 4 throu
66. th temperature VDD and process 3 The frequency drift about 30 This specification is subject to change without prior notice 48 2002 05 06 78 257 4 13 MOUSE APPLICATION MODE 1 Overview amp Features Overview Fig 27 shows how 78 257 communicates with PS 2 connector of PC Features RC oscillation Six photo couples input MOUSEN X1 TCC1 MOUSEN TCCA UP DOWN Counter After MCU process send data to PC MOUSEN 9 VCC Y1 TCC3 ES 4 5R C3 MOUSEN After MCU process R send data to PC 15K TCCB UP DOWN Counter _ This specification is subject to change without prior notice 49 2002 05 06 78 257 ROM MOUSEN 71 5 MOUSEN After MCU process send data to PC TCCC UP DOWN Counter MOUSEN 4 5R R 15K 4 ZXTCC6 Fig 27 Mouse Function Diagram 2 Function Description The following describes the function of each block and signal of Fig 27 depicting how to complete a Mouse function P61 X1 Use current comparator to measure photo couples OFF P66 X2 Four photo couple singles denoting UP DOWN LEFT and RIGHT states P51 Y1 During scanning period as long as the photo couples state changes the value of P50 Y2 vertical or horizontal counter will increase or decrease accordingly 56 21 Z axis inputs P57 Z2 Photo mode Current c
67. the ratio of the prescaler of TCC Likewise the PWRO PWR2 bits of the IOCEO register are used to determine the prescaler of WDT The prescaler PSRO PSR2 will be cleared by the instructions each time they are written into TCC The WDT and prescaler will be cleared by the WDTC and SLEP instructions Fig 6 depicts the circuit diagram of TCC WDT 1 is an 8 bit timer counter The clock source of can be internal clock or external singal input edge selectable from the TCC pin If TCC signal source is from internal clock TCC will increase by 1 at every instruction cycle without prescaler As illustrated in Fig 6 selection of CLK Fosc 2 or CLK Fosc 4 depends on the CODE Option bit lt CLKS gt CLK Fosc 2 is selected if the CLKS bit is 0 and CLK Fosc 4 is selected if the CLKS bitis 1 If TCC signal source is from external clock input TCC will increase by 1 at every falling edge or rising edge of the TCC pin The watchdog timer is a free running on chip RC oscillator The WDT will keep on running even after the oscillator driver has been turned off i e in sleep mode During the normal operation or the sleep mode a WDT time out if enabled will cause the device to reset The WDT can be enabled or disabled at any time during the normal mode by software programming Refer to WDTE bit of IOCEO register With no prescaler the WDT time out period is approximately 18 ms NOTE VDD 5V Setup time period 16

ELAN EM78P257 OTP ROM Manual(1)(1)

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