MAXIM MX7225/7226 Manual
Contents
1. AC Reference Input Circuit 10 CMOS Quad 8 Bit D A Converters Figure 14 Generating 5V for Vss MAXIM __MX7225 ADORESS DATA BUS Figure 15 MX7225 to 8085A 8088 Interface Double Buffered Figure 16 MX7225 to 6089 6502 Interface Single Buffered Mode Mode ADDRESS BUS Figure 17 MX7225 to Z 80 Interface Double Buffered Mode Figure 18 MX7225 to 68008 Interface Single Buffered Mode MAXIZA T 6 6 _ L LRREA 1 Sul 9TT4LXMI STTZXM MX7225 MX7226 CMOS Quad 8 Bit D A Converters ADDRESS BUS ADDRESS DATA BUS ADDRESS DECODE Figure 21 MX7226 to 6502 Interface 0 150 3 810mm VoutA VourB Vour VourD E i BOT anp i i 085 DB4 083 082 081 080 MX7225 EN o i MAXIM MX7226 ADDRESS BUS MAXIM MX7226 ADDRESS BUS gm ADRESS Li WA ECODE a MAXIM MX7226 Figure 22 MX7226 to Z 80 Interface Chip Topography VoutA VoutB Vour Vout MX7226 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 12 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 1993 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products2. 19 0932 Rev 1 4 93 MAXIM CMOS Quad 8 Bit D A Converters General Description Maxim s MX7225 and MX7226 each contain four 8 bit volt age output digital to analog converters DACs They include output buffer amplifiers and input logic for simple microprocessor and TTL CMOS interfaces 8 bit perfor mance is achieved over the full operating temperature range without external trimming The MX7225 contains double buffered logic inputs that allow all analog outputs to be simultaneously updated using one control signal There are also four separate ref erence inputs so that the range of each DAC can be independently set The MX7226 has separate input registers for each of its four DACs Data is transferred into an input register from a common 8 bit TTL CMOS compatible input port Address inputs AO and A1 determine which DAC is loaded when WR goes low All DACs share a common reference input For 7225 and 7226 designs utilizing a 5V supply see the MAX505 and MAX506 data sheet Applications Minimum Component Count Analog Systems Digital Offset Gain Adjustment Industrial Process Control Arbitrary Function Generators Automatic Test Equipment Microprocessor Controlled Calibration Functional Block Diagram MAXIA Features Buffered Voltage Output Double Buffered Inputs MX7225 Microprocessor and TTL CMOS Compatible Operate from Single or Dual Supplies Require No External Adjustments Ordering Informatio
3. A Converters POS STEP Vss 5V OR OV NEG STEP Vss 5V OR OV INPUT za SV div SU UT m 20mV div Figure 2 Positive and Negative Settling Times Vss OV or 5V DYNAMIC RESPONSE Vss 5V OR OV INPUT Figure 3 Dynamic Response Vss OV or 5V output circuitry incorporates a Maxim proprietary pull down circuit to actively drive Vout to within typically 15mV of the negative supply Vss The buffer circuitry allows each DAC output to sink as well as source up to 5mA This is especially important in single supply applications where Vss is connected to GND so that zero error is kept at or under 1 2LSB Vrer 10V A plot of output sink current versus output voltage is shown in the Typical Operating Characteristics section Digital Inputs and Interface Logic The digital inputs are compatible with both TTL and 5V CMOS logic however power supply currents Ipp and Iss are somewhat dependent on input logic level Supply currents are specified for TTL input levels worst case but are significantly reduced when the logic inputs are driven as close to DGND as possible or above 4 volts MITTER FROM PMOS FOLLOWER PULL UP t INVERTED yf _ Vout OUTPUT INPUTS NMOS ACTIVE PULL DOWN CIRCUIT Figure 4 Simplified Output Buffer Circuit Address lines AO and A1 select which DAC receives data from the input port When WR is low the input register of the addressed DAC is tra
4. D be tied together at the DAC and that this point be tied to the highest quality ground that is available If separate ground busses are used then two clamp diodes IN914 or equivalent should be connected between AGND and DGND to keep the two ground busses within one diode drop of each other To avoid parasitic device turn on AGND must not be allowed to be more negative than DGND DGND should be used as supply ground for bypassing purposes Careful PCB ground layout techniques should be used to minimize crosstalk between DAC outputs the reference input s and the digital inputs This is particularly important if the reference is driven from an AC source Figure 7 and 8 show suggested circuit board layouts for minimizing crosstalk Unipolar Output In unipolar operation the output voltages and the reference input s are the same polarity Unipolar circuit configurations are shown in Figure 9 and 10 for the MX7225 and MX7226 Both devices can be operated from a single supply with a slight increase in zero error see Output Buffer Amplifier section To avoid parasitic device turn on the voltage at Vref must always be positive with respect to DGND The unipolar code table is given in Table 3 Bipolar Output Each DAC output may be configured for bipolar operation using the circuit in Figure 11 One op amp and two resistors are required per channel With R1 R2 Vout Vrer 2Da 1 where Da is a fractional representation of t
5. KN BQ TQ All other devices 1 Full Scale Error ppm C Full Scale Temperature Coefficient Vrer 10V MX7225LN CQ UQ Ta 25 C i Over Temp Zero Code Error MX7225KN BQ TQ Ta 25 C All other devices Over Temp Zero Gode Temperature Cooticiont O Ooo w uwo REFERENCE INPUT Reference Input Capacitance Cr MX7225 100 F Code Dependent Note 3 EF MX7226 65 300 P Channel to Channel Isolation Vaer 10kHz 10Vp p Note 2 AC Feedthrough Vaer 10kHz 10Vp p Note 2 4 70 DIGITAL INPUTS Digital Input Leakage Current I VN OVOrVpp sd Digital Input Capacitance a DYNAMIC PERFORMANCE Voltage Output Settling Time to LSB Vper 10V Pos or Neg Full Scale Change 2k and 100pF Load Note 2 lt v An Voltage Output Slew Rate Vus nV s Digital Feedthrough and Crosstalk All O s to 1 s code change Note 4 Output Load Resistance Vour 10V Note 1 The outputs may be shorted to AGND provided that the power dissipation of the package is not exceeded Typical short circuit current to AGND is 25mA Note 2 Sample tested at 25 C to ensure compliance Note 3 Guaranteed by design Not production tested Note 4 Feedthrough is reduced by connecting the metal lid on the ceramic package suffix D to DGND MX7226 only 2 Fb CMOS Quad 8 Bit D A Converters ELECTRICAL CHARACTERISTICS Dual Supply Specifications continued C anamen svwsoL CONDITION
6. MX7226 Write Cycle Truth Table FUNCTION No operation Device deselected Input register of selected DAC transparent Latch the input register of selected DAC MX7225 only All four DAC registers transparent i e DAC outputs reflect the data held in their respective input registers Input registers are latched MX7225 only Latch the four DAC registers Input registers are latched MX7225 only DAC Registers and the selected input register transparent DAC output follows input data for selected channel DSAAXIM rising edge of LDAC Table 2 shows the truth table for WR and LDAC operation Figure 6 shows the write cycle timing for both the MX7225 and MX7226 Applications Information Power Supply and Reference Operating Ranges The MX7225 and MX7226 are fully specified to operate with Vpp between 12V 5 and 15V 10 11 4V to 16 5V and with Vss from OV to 5 5V 8 bit per formance is also guaranteed for single supply opera tion Vss OV however zero code error is reduced when Vss is 5V see Output Buffer Amplifier For adequate DAC and buffer operating range the Vref voltage must always be at least 4V below Vop Both the MX7225 and MX7226 are specified to operate with a reference input range of 2V to Vpp 4V Ground Management Digital or AC transient signals between AGND and DGND will create noise at the analog outputs It is recommended that AGND and DGN
7. S ww me max UNITS POWER SUPPLIES Yoo Range Positive Supply Current wresTaua Outputs Unloaded MX7226 MX7225KN B Negative Supply Current MEETU gt Outputs Unloaded MX7226 Address to Write Setup Time Address to Write Hold Time MX7228 MX7225 T 25 C A a Over Temp Data Valid to Write Setup Time MX7226 Ty 25 C Over Temp SWITCHING CHARACTERISTICS Over Temp MX7225 Data Valid to Write Hold Time toH Write Pulse Width MX7225 Ty 25 C MX7225KN BQ LN CQ Over Temp MX7225TQ UQ Over Temp MX7226 Ta 25 C Over Temp _ l MX7225 T 25 C 95 Load DAC LDAC Pulse Width MX7225KN BQ LN CQ Over Temp 120 MX7225 Only MX7225TQ UQ Over Temp 150 ELECTRICAL CHARACTERISTICS Single Supply Specifications Vop 15V 5 Vss AGND DGND OV Vper 10V Over Temperature unless otherwise stated PARAMETER SYMBOL CONDITIONS Win Tee MAX STATIC PERFORMANCE Total Unadjusted Error ee n 1 use Differential Nonlinearity iti Guaranteed Monotonic LS REFERENCE INPUT 11 2 Reference Input Capacitance Ca MX7225 100 Code Dependent Note 3 EF MX7226 65 300 Channel to Channel Isolation I Vaer 10kHz 10Vp p Note 2 ES AC Feedthrough o Vaer 10kHz 10Vp p Note 2 4 DIGITAL INPUTS All Specifications Are The Same as For Dual Supply Operation DYNAMIC PERFORMANCE All Specifications Are The Same as For Dual
8. Supply Operation POWER SUPPLIES For Specified Performance maz 71878 Positive Supply Current MIETO S Output Unloaded MX7226 v 9TT4LXM STZZXM MX7225 MX7226 CMOS Quad 8 Bit D A Converters Functional Block Diagram MX7226 _ Pin Configurations DIP SO DIP SO AGND 5 MX7226 MSB 0B7 7 Vss AGND DENO PLCC PIN NUMBERS MATCH DIP SO Typical Operating Characteristics RELATIVE ACCURACY ve Vage DIFFERENTIAL NONLINEARITY vs VREF 1 RELATIVE ACCURACY LSB gt g DIFFERENTIAL NONLINEARITY LSB CMOS Quad 8 Bit D A Converters OUTPUT SINK CURRENT Isimx mA SUPPLY CURRENT mA Detailed Description The MX7225 and MX7226 have four matched voltage output digital to analog converters DACs The DAC s are inverted R 2R ladder networks which convert 8 bit digital words into equivalent analog output volt ages in proportion to the applied reference voltage s Each DAC in the MX7225 has a separate reference input whereas in the MX7226 all reference inputs are tied together A simplified circuit diagram of one of the four DACS is provided in Figure 1 Vrer Input The voltage at Vrer sets the full scale output of the DAC The input impedance of the Vref input s is code dependent The lowest value approximately 11kO for the MX7225 and 2kN for the MX7226 occurs when the input code is 01010101 The maximum value is infinity which occur
9. he MX7225 Figure 11 Bipolar Output Circuit Offsetting AGND AGND can be biased above DGND to provide an arbitrary nonzero output voltage for a zero input code This is shown in Figure 12 The output voltage at VouTA is VoutA Veias DAVIN where Da is a fractional representation of the digital input word Since AGND is common to all four DAC s all outputs will be offset by Vgias in the same manner Using an AC Reference In applications where Vref has AC signal compo nents the MX7225 and MX7226 have multiplying cap ability within the limits of the Vrer input range specifications Figure 13 shows a technique for apply ing a sine wave signal to the reference input where the AC signal is biased up before being applied to Vrer Output distortion is typically less than 0 1 with input frequencies up to 50kHz and the typical 3dB frequency is 700kHz Note that Vrer must never be more negative than AGND MAXIM MX7225 AGNO OGNO Generating Vss The performance of the MX7225 7226 is specified for both dual and single supply Vss OV operation When the improved performance of dual supply operation is desired but only a single supply is available a 5V Vss supply can be generated using an ICL7660 in one of the circuits of figure 14 MAXIM MX7225 5V 0R GND 7 5V OR GND Digital Inputs Not Shown Figure 12 AGND Bias Circuits MX7226 DENO Digital Inputs Not Shown Figure 13
10. he digital word in register A Table 4 shows the digital code versus output voltage for the circuit in Figure 11 9TTLXM STTZXM MX7225 MX7226 CMOS Quad 8 Bit D A Converters ae I VO I tan gt gt I WA ten ov Mx722 x7225 ony LINE 5V ia ov tos Ta man adria ured from 10 er Vop ran nge e level is 2 3 oe azzo nly is activated o the rising edge prio n it must stay low for t 4 r longer after Wh ose Soh Figure 6 Write Cycle Timing Diagram SYSTEM GND SYSTEM GNO int _ vane Vour A Vourd Vss 9 C w l cla AGNO oeno M L COMPONENT SIDE MX7226 TOP VIEW Figure 7 Suggested MX7226 PCB Layout for Minimizing Figure 8 Suggested MX7225 PCB Layout for Minimizing Crosstalk Crosstalk 3 rl ee tin MAA DIGITAL INPUTS NOT SHOWN MAXIM MX7225 Wss AGND 5V OR GND Figure 9 MX7225 Unipolar Output Circuit Table 3 Unipolar Code Table CMOS Quad 8 Bit D A Converters DIGITAL INPUTS N NOT SHOW OGND MX7226 Vss AGNO 5V OR GND Figure 10 MX7226 Unipolar Output Circuit Table 4 Bipolar Code Table DAC CONTENTS ANALOG OUTPUT Note 1LSB Vper 278 VreF z 256 MAXIM 9TTLXM STTZZXM MX7225 MX7226 CMOS Quad 8 Bit D A Converters DAC OUTPUT FROM MX7225 15V OR MX7226 R Rp 10k 0 1 Note Vref is the Reference Input for the MX7226 or is the selected Reference Input for t
11. n ERROR LSB PART TEMP RANGE PIN PACKAGE MX7225LCWG MX7225KCWG MX7225LP MX7225KP 0 C to 70 C 24 Wide SO 0 C to 70 C 24 Wide SO 0 C to 70 C 28 PLCC 0 C to 70 C 28 PLCC MX7225K D 0 C to 70 C Dice MX7225LEWG 40 C to 85 C 24 Wide SO MX7225KEWG 40 C to 85 C 24 Wide SO MX7225KERG 40 C to 85 C 24 CERDIP MX7225CQ 40 C to 85 C 24 CERDIP MX7225BQ 40 C to 85 C 24 CERDIP MX7225UQ 55 C to 125 C 24 CERDIP MX7225TQ 55 C to 125 C 24 CERDIP MX7226KN 0 C to 70 C 20 Plastic DIP 2 MX7226KCWP 0 C to 70 C 20 Wide SO 2 MX7226KP 0 C to 70 C 20 PLCC MX7226K D 0 C to 70 C Dice MX7226KEWP 40 C to 85 C 20 Wide SO MX7226BQ 40 C to 85 C 20 CERDIP MX7226TE 55 C to 125 C 20 LCC MX7226TQ 55 C to 125 C 20 CERDIP MX7226TD 55 C to 125 C 20 Ceramic SB 2 Contact factory for availability and processing to MIL STD 883B Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com 9TTELXM STZZZXM MX7225 MX7226 CMOS Quad 8 Bit D A Converters ABSOLUTE MAXIMUM RATINGS Vop to AGND 5 50 ccrccalveevier eis sosesscdecee 0 3V 17V Power Dissipation Any Package to 75 C 500mW Vop to DGND bei 0 3V 17V Derating above 75 C eee eee ees 2mW C Meg tO AGND 5 ciciniars siciniste 6 oi
12. nsparent The data is then latched when WR goes high Figure 5 shows the input control logic for the MX7225 and MX7226 Table 1 lists the channel addresses The MX7226 s four DAC outputs represent the data held in four 8 bit input registers The MX7225 differs from the MX7226 in that in addition to the input registers there is a separate DAC register for each DAC as well A DAC s analog output is based only on the contents of its DAC register Data is transferred from the input registers to the DAC registers by the LDAC input When LDAC is LOW all four DAC reg isters are transparent to the input registers so that all DACs are updated simultaneously With LDAC held LOW the MX7225 interface behaves like the MX7226 Since LDAC_ MX7225 only is asynchronous with respect to WR care must be taken to assure that incorrect data is not latched through to the output If LDAC is brought LOW before or at the same time that WR goes HIGH then LDAC must remain LOW for at least ttp to ensure that the correct data is latched Data is latched into all four DAC registers on the MAXIM CMOS Quad 8 Bit D A Converters REGISTERS TO INPUT REGISTER A TO INPUT REGISTER B TO INPUT REGISTER C Figure 5 MX7225 MX7226 Input Control Logic Table 1 DAC Addressing AT ao _SELECTEDINPUTREGISTER DAC A Input Register DAC B Input Register DAC C Input Register DAC D Input Register Table 2 MX7225
13. s when the input code is 00000000 Because the input resistance at Vref is code dependent the DAC s reference sources must have an output impedance of no more than 200 for the MX7225 and 40 for the MX7226 to maintain output linearity The input Figure 1 Simplified DAC Circuit Diagram PAAXKXILAA POWER SUPPLY CURRENT vs TEMPERATURE 55 40 20 0 20 40 60 80 10 125 TEMPERATURE C ZERO CODE ERROR vs TEMPERATURE is PRR ZERO CODE ERROR mV e 15 Peach rs 55 40 20 0 20 40 8 8 100 125 TEMPERATURE C capacitance at Vref is also code dependent and typically varies from 15pF to 35pF for the MX7225 and 100pF to 250pF for the MX7226 VoutA B C or D can be represented by a digitally programmable voltage source as Vout Np Vrer 256 where Ng is the numeric value of the DAC s binary input code Output Buffer Amplifiers All MX7225 26 voltage outputs are internally buffered by precision unity gain followers which slew at greater than 3V us When driving 2kO in parallel with 100pF with full scale transitions OV to 10V or 10V to OV the output settles to 1 2LSB in less than 4ys Typical dynamic response and settling performance of the MX7225 and MX7226 is shown in Figure 2 and 3 Asimplified circuit diagram of an output buffer is shown in Figure 4 Input common mode range to AGND is provided by a PMOS input structure The improved 9TTLXM STTZXM MX7225 MX7226 CMOS Quad 8 Bit D
14. sinin irae Sie Cisteta oe eidie e wins 7V Voo Operating Temperature Ves to DGND 000 sce rrcrrrccrcsconono 7V Voo Commercial MX722XK L 0 C to 70 C Mop tO Veg E E A TEA 0 3V 24V Industrial MX722XB C 25 C to 85 C Digital Input Voltage to DGND 0 3V Voo Military MX722XT U 55 C to 125 C Vinge tO AGIND 0r3cririnedacicnerrins rire 0 3V Vop Storage Temperature 65 C to 150 C Vout to AGND Note 1 Vss Von Lead Temperature Soldering 10 secs 300 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS Dual Supply Specifications Voo 11 4V to 16 5V Vss 5V 10 AGND DGND OV Vrer 2V to Vpp 4V Over Temperature unless otherwise noted STATIC PERFORMANCE Resolution Vop 15V 5 MX7225LN CQ UQ Total Unadjusted Error Vai 10V All other devices CSB Relative Accuracy D AAN LSB N MX7225LN CQ UQ X j LSB MX7225
Download Pdf Manuals
Related Search
MAXIM MX7225/7226 Manual