MAXIM MAX792/820 Manual
Contents
1. MAX792 MAX820 PARAMETER CONDITIONS MIN TYP MAX UNITS OVERVOLTAGE COMPARATOR OVI Input Threshold Vcc 5V or Vcc 1 25 1 30 1 35 V OVI Leakage Current 0 01 25 nA 3 2mA 0 4 OVO Output Voltage 208 V ISOURCE 1pA Vcc 1 OVO Short Circuit Current Output source current Vcc 5 5V 10 50 UA OVI to OVO Del Vop 100mV OVI rising 13 ela d 100mV OVI falling 55 H CHIP ENABLE GATING V 0 75 x V Vec 4 25V ii ae CE IN Threshold Voltage HE Be i 9 ViH 0 75 x Vcc 2 55V VIL 0 2 CE IN Leakage Current Disabled mode 0 005 1 UA CE IN to CE OUT Resistance Enabled mode Vcc 5V d 150 Q 3V 150 300 CE OUT Short Circuit Current Disabled mode CEourT OV uiid Em mA o ME A i PER Voc 3V 0 05 02 04 Chip Enable Propagation Delay 500 source impedance driver VCC 5V 6 10 ns Note 3 CLOAD 50pF Vcc 3V 8 13 Chip Enable Output Voltage lour 100pA 1 High Reset Active loUT 100A Vcc 0 5 Reset Active to CE OUT High Vcc falling 15 us MANUAL RESET MR Minimum Pulse Width 25 us MR to RESET Propagation Delay 12 us MR Threshold Range 1 1 1 3 1 5 4 25V Z 5 23 80 R Pull Up Current to 5 5V uA Vcc 2 5V 1 Note 1 The minimum operating voltage is 2 75V however the MAX792R and MAX820R are guaranteed to operate down to their prese2. used 15 WDO Watchdog Output WDO goes low if WDI remains either high or low longer than the watchdog time out period WDO returns high on the next transition at WDI 16 WDPO Watchdog Pulse Output Upon the absence of a transition at WDI WDPO will pulse low for a mini mum of 500us WDPO precedes WDO by typically 70ns MAXIM 7 Of8XVIN C6ELXVIN MAX792 MAX820 Microprocessor and Nonvolatile Memory Supervisory Circuits Detailed Description Manual Reset Input Many uP based products require manual reset capabil ity allowing the operator to initiate a reset The manu al external reset input MR can connect directly to a switch without an external pull up resistor or debounc ing network MR internally connects to a 1 30V com parator and has a high impedance pull up to Vcc as shown in Figure 1 The propagation delay from assert ing MR to reset asserted is typically 12us Pulsing MR low for a minimum of 25us asserts the reset function see Reset Function section The reset output remains active as long as MR is held low and the reset timeout period begins after MR returns high Figure 2 To pro vide extra noise immunity in high noise environments pull MR up to Vcc with a 100kQ resistor Use MR as either a digital logic input or as a second low line comparator Normal TTL CMOS levels can be wire OR connected via pull down diodes Figure 3 and open drain collector outputs can be wire ORed di
3. 0 050 1 27 0 291 0 299 7 40 7 60 H 0 394 0 419 10 00 10 65 0 016 0 050 0 40 1 27 VARIATIONS INCHES MILLIMETERS DIM MIN MAX MIN MAX N MS013 D 0 398 0 413 10 10 10 50 16 AA D 0 447 0463 11 35 1175 18 AB D 0 496 0 512 12 60 13 00 20 AC D 0 598 0 614 15 20 15 60 24 AD D 0 697 0 713 17 70 18 10 28 AE 23 SIDE VIEW DDALLAS MVLAIXXLAVI PROPRIETARY INFORMATION TTE PACKAGE OUTLINE 300 SOIC APPROVAL DOCUMENT CONTROL NO REV 21 0042 B SOICW EPS E m i TOP VIEW MEETS JEDEC MS012 N NUMBER OF PINS 1 2 MOLD FLASH OR PROTRUSIONS TO EXCEED 0 15mm 006 3 LEADS TO BE COPLANAR WITHIN 0 10mm 004 4 CONTROLLING DIMENSION MILLIMETERS 5 6 INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0 053 0 069 1 35 1 75 A1 0 004 0 010 0 10 0 25 B 0 014 0 019 0 35 0 49 0 007 0 010 0 19 0 25 0 050 BSC 1 27 BSC 0 150 0 157 3 80 4 00 H 0 228 0 244 5 80 6 20 L 0 016 0 050 0 40 1 27 VARIATIONS INCHES MILLIMETERS DIM MIN MAX MIN MAX N MS012 D 0 189 0 197 4 80 5 00 8 AA D 0 337 0 344 8 55 875 14 AB D 0 38
4. Voltage Monitor for Overvoltage Warning 2 Reset and Low Line Threshold Accuracy MAX820 external programming mode Ordering Information PART TEMP RANGE PIN PACKAGE MAX792_CPE 0 C to 70 C 16 Plastic DIP MAX792 CSE 0 C to 70 C 16 Narrow SO MAX792_C D 0 C to 70 C Dice Ordering Information continued at end of data sheet Dice are tested at 25 C DC parameters only These parts offer a choice of five different reset threshold voltages Select the letter corresponding to the desired nominal reset threshold voltage and insert it into the blank to complete the part number Devices in PDIP SO and UMAX packages are available in both lead ed and lead free packaging Specify lead free by adding the sym bol at the end of the part number when ordering Lead free not avail able for CERDIP package SUFFIX RESET THRESHOLD V L 4 62 M 4 37 T 3 06 S 2 91 R 2 61 __ CEOUT RESET IN INT MAXIM MAX792 Maxim Integrated Products 1 For free samples and the latest literature visit www maxim ic com or phone 1 800 998 8800 For small orders phone 1 800 835 8769 Of8XVIN CEZLXVIN MAX792 MAX820 Microprocessor and Nonvolatile Memory Supervisory Circuits ABSOLUTE MAXIMUM RATINGS Input Voltage with respect to GND MG oett ee TU e ee Be 0 3V to 6V All Other Inputs o tees 0 3V to Vcc 0 3V Input Current epson
5. 61 2 70 ee eee vn MAX792S MAX820S 2 85 2 91 3 00 cml ae d MO MAX792T MAX820T 3 00 3 06 3 15 VTH MAX820L Ta 25 C Vcc falling 4 55 4 70 MAX820M Ta 25 C Vcc falling 4 30 4 45 AX820R Ta 25 C Vcc falling 2 55 2 66 MAX8208 Ta 25 C Vcc falling 2 85 2 96 MAX820T Ta 25 C Vcc falling 3 00 3 11 Reset Threshold Voltage AX792 Vcc 5V or Vcc 3V 1 25 1 30 1 35 External Threshold Mode VTH MAX820 Vcc 5V or Vcc 3V 1 274 1 30 1 326 id hee dh Moge Triresnoia Internal threshold mode 60 mV RESET IN INT Leakage Current 0 01 25 nA Reset Threshold Hysteresis 0 016 x VTH V Reset Comparator Delay Vcc falling 70 us Reset Active Timeout Period Vcc rising 140 200 280 ms ISINK 50pA Vcc 1V Vcc falling 0 01 0 3 ee ISINK 1 6mA 0 1 0 4 RESET Output Voltage SOURCE IA Ween V ISOURCE 100pA Vcc 0 5 ISINK 1 6mA 0 1 0 4 RESET Output Voltage ISOURCE 1mA Vcc 1 V ISOURCE 100 Vcc 0 5 2 MAKI Microprocessor and Nonvolatile Memory Supervisory Circuits ELECTRICAL CHARACTERISTICS continued Vcc 2 75V to 5 5V TA to Tmax unless otherwise noted PARAMETER CONDITIONS MIN TYP MAX UNITS LOW LINE COMPARATOR Low Line Threshold Voltage MAX792 MAX820L M 50 120 210 mV nternal Threshold Mode VTH MAX792 MAX820R S T 40 100 210 Low Line Threshold Voltag
6. a hardware shutdown if there are two successive watchdog faults Figure 8 When the MAX792 MAX820 are operated from a 5V supply WDO has a 2 x TTL output characteristic Watchdog Pulse Output As described in the preceding section WDPO can be used as the clock input to an external D flip flop Upon the absence of a watchdog edge or pulse at WDI at the end of a watchdog timeout period WDPO will pulse low for 1 7ms The falling edge of WDPO precedes WDO by 70ns Since WDO is high when goes low the flip flop s Q output remains high after WDO goes low Figure 8 If the watchdog timer is not reset by a transition at 12 Vcc MAXIMA MAX792 MAX820 CONSECUTIVE WATCHDOG FAULT INDICATION REACTIVATE FOR SYSTEM RESET ON EVERY WATCHDOG FAULT OMIT THE FLIP FLOP AND DIODE OR CONNECT WDO TO MR Figure 8 Two consecutive watchdog faults latch the system in reset WDI WDO remains low and the next WDPO following a second watchdog timeout period clocks a logic low to the Q output pulling MR low and causing the MAX792 MAX820 latch in reset If the watchdog timer is reset by a transition at WDI WDO will go high and the flip flop s Q output will remain high Thus a system shutdown is only caused by two successive watchdog faults Selecting an Alternative Watchdog Timeout Period The SWT input controls the watchdog timeout period Connecting SWT to Vcc selects the internal 1 6sec watchdog timeout per
7. a minimum 100ns pulse at WDI during the watchdog period resets the watchdog timer The watchdog timer 11 OC8XVMW C6Z2XVM MAX792 MAX820 Microprocessor and Nonvolatile Memory Supervisory Circuits MIN 100ns Vec 5V MIN 300ns Vec 3V ka 165 Figure 7 WDI WDO and WDPO Timing Diagram default is 1 6s Select alternative timeout periods by connecting an external capacitor from SWT to GND see Selecting an Alternative Watchdog Timeout sec tion When Vcc is below the reset threshold the watch dog function is disabled Watchdog Output WDO remains high if there is a transition or pulse at WDI during the watchdog timeout period The watchdog function is disabled and WDO is a logic high when Vcc is below the reset threshold If a system reset is desired on every watchdog fault simply diode OR connect WDO to MR Figure 8 When a watchdog fault occurs in this mode WDO goes low pulling MR low and causing a reset pulse to be issued As soon as reset is asserted the watchdog timer clears and WDO goes high With WDO connected to MR a continuous high or low on WDI will cause 200ms reset pulses to be issued every 1 6sec SWT connected to Vcc When reset is not asserted if no transition occurs at WDI during the watchdog timeout period WDO goes low 70ns after the falling edge of WDPO and remains low until the next tran sition at WDI Figure 7 A single additional flip flop can force the system into
8. goes 100mV below the reset threshold and lasts for 30us or less will not cause a reset pulse to be issued A 100nF bypass capacitor mounted close to the Vcc pin provides additional transient immunity MAX791 13 co MAXIMUM TRANSIENT DURATION 0 10 100 1000 10 000 RESET COMPARATOR OVERDRIVE Vru Vcc mV Figure 13 Maximum Transient Duration Without Causing a Reset Pulse vs Reset Comparator Overdrive MAXIM _Ordering Information continued Microprocessor and Nonvolatile Memory Supervisory Circuits PART TEMP RANGE PIN PACKAGE MAX792_EPE 40 C to 85 C 16 Plastic DIP MAX792_ESE 40 C to 85 C 16 Narrow SO MAX792_EJE 40 C to 85 C 16 CERDIP MAX792_MJE 55 C to 125 C 16 CERDIP MAX820_CPE 0 C to 70 C 16 Plastic DIP AX820_CSE 0 C to 70 C 16 Narrow SO AX820_EPE 40 C to 85 C 16 Plastic DIP AX820_ESE 40 C to 85 C 16 Narrow SO AX820_EJE 40 C to 85 C 16 CERDIP AX820_MJE 55 C to 125 C 16 CERDIP Dice are tested at Ta 25 C DC parameters only These parts offer a choice of five different reset threshold volt ages Select the letter corresponding to the desired nominal reset threshold voltage and insert it into the blank to complete the part number Devices in PDIP SO and MAX packages are available in both
9. is equivalent to 75Q in series with the source driving CE IN In the disabled mode the 75Q transmission gate is off and an active pull up connects from CE OUT to Vcc This source turns off when the transmission gate is enabled Applications Information Connect a 0 1uF ceramic capacitor from Vcc to GND as close to the device pins as possible This reduces the probability of resets due to high frequency power supply transients In a high noise environment addi tional bypass capacitance from Vcc to ground may be required If long leads connect to the chip inputs ensure that these lines are free from ringing etc which would forward bias the chip s protection diodes 13 Of8XVIN C6ELXVIN MAX792 MAX820 Microprocessor and Nonvolatile Memory Supervisory Circuits Voc MAXIMA MAXIMUM Rp VALUE DEPENDS ON THE NUMBER OF RAMS MINIMUM Rp VALUE IS 1kQ ACTIVE HIGH CE LINES FROM LOGIC Figure 11 Alternate CE Gating Alternative Chip Enable Gating Using memory devices with both CE and CE inputs allows the MAX792 MAX820 CE propagation delay to be bypassed To do this connect_CE IN to ground pull up CE OUT to Vcc and connect CE OUT to the CE input of each memory device Figure 11 The CE input of each memory device then connects directly to the chip select logic which does not have to be gated by the MAX792 MAX820 Interfacing to pPs with Bidirectional Reset Inputs uPs with bidirectional reset pin
10. 19 0147 Rev 4 11 05 Microprocessor and Nonvolatile Memory Supervisory Circuits General Description The MAX792 MAX820 microprocessor uP supervisory circuits provide the most functions for power supply and watchdog monitoring in systems without battery backup Built in features include the following uP reset Assertion of RESET and RESET outputs during power up power down and brownout conditions RESET is guaranteed valid for Vec down to 1V Manual reset input Two stage power fail warning A separate low line comparator compares Vcc to a preset threshold 120mV above the reset threshold the low line and reset thresholds can be programmed externally Watchdog fault output Assertion of WDO if the watchdog input is not toggled within a preset timeout period Pulsed watchdog output Advance warning of impending WDO assertion from watchdog timeout that causes hardware shutdown Write protection of CMOS RAM EEPROM or other memory devices The MAX792 and MAX820 are identical except the MAX820 guarantees higher low line and reset threshold accuracy 2 MAXIM Applications Computers Controllers Intelligent Instruments Critical uP Power Monitoring 9 9 Features Manual Reset Input 200ms Power OK Reset Time Delay Independent Watchdog Timer Preset or Adjustable On Board Gating of Chip Enable Signals Memory Write Cycle Completion 10ns max Chip Enable Gate Propagation Delay
11. 2 R2 1 30 x 5 5 4 4 x 5E 6 301kQ 23 95kQ The nearest 0 1 resistor value is 23 7kQ Finally sub stitute into equation 3 R1 5 5 5E 6 23 7kQ 301kQ 775kQ The nearest 0 1 value resistor is 787kQ Determine the actual low line threshold by rearranging equation 1 and plugging in the standard resistor values The actual low line threshold is 4 75V and the actual reset threshold is 4 40V An additional resistor allows the MAX792 MAX820 to monitor the unregulated supply and provide an NMI before the regulated supply begins to fall Figure 4c Both of these thresholds will vary from circuit to circuit with resistor tolerance reference variation and compara tor offset variation The initial thresholds for each circuit will also vary with temperature due to reference and off set drift For highest accuracy use the MAX820 MAXIM Microprocessor and Nonvolatile Memory Supervisory Circuits RESET GENERATOR LLIN REFOUT LOW LINE L_ COMPARATOR CHIP ENABLE m OUTPUT CONTROL MANUAL COMPARATOR INTERNAL EXTERNAL MODE CONTROL 60mV INTERNAL TIMEBASE FOR RESET AND WATCHDOG DOG ER MAXIMA Vec MAX792 OVERVOLTAGE MAX820 COMPARATOR SWITCHES ARE SHOWN IN INTERNAL THRESHOLD MODE POSITION Figure 1 MAX792 MAX820 Block Diagram MAXIM 9 Of8XVIN CELXVIN MAX792 MAX820 Microprocessor and Nonvolatil
12. 2 R3 MAX Figure 4b Connection for External Threshold Programming Mode When reset is asserted all the internal counters are reset the watchdog output WDO and watchdog pulse output WDPO are set high and the set watchdog time out input SWT is set to Vcc 0 6V if it is not already connected to Vcc for internal timeouts The chip enable transmission gate is also disabled while reset is asserted the chip enable input CE IN becomes high impedance and the chip enable output CE OUT is pulled up to Vcc MAXIM Microprocessor and Nonvolatile Memory Supervisory Circuits REGULATOR Voc RESET IN INT RESET 2 MAAXIAA MAX792 MAX820 LLIN REFOUT TO uP COWLINE 1 V TO uP NMI VLOW LINE 1 3 E 8 VRESET 1 3 8 8 Figure 4c Alternative Connection for External Programming Mode Reset Outputs RESET and RESET The RESET output is active low and typically sinks 1 6mA at 0 1V When deasserted RESET sources 1 6mA at typi cally Vcc 1 5V The RESET output is the inverse of RESET RESET is guaranteed to be valid down to Vcc 1V and an external 10kQ pull down resistor on RESET ensures that it will be valid with Vcc down to GND Figure 5 As Vcc goes below 1V the gate drive to the RESET output switch reduces accordingly increasing the rbs oN and the saturation voltage The 10k pull down resistor ensures that the parallel combination of switch plus resistor will be around 10kQ and the saturation v
13. 25mA All Other OUtpulss c eoe ete ter ertet ins 25mA Continuous Power Dissipation TA 70 C Plastic DIP derate 10 53mW C above 70 C 842mW Narrow SO derate 9 52mW C above 70 C 762mW CERDIP derate 10 00mW C above 70 800mW Operating Temperature Ranges 792_ __ 20_ __ 0 C to 70 C MAX792 E MAX820 E 40 C to 85 C MAX792_MJE__ MAX820_MJE 55 C to 125 C Storage Temperature Range 65 C to 160 C Lead Temperature soldering 105 300 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS Vcc 2 75V to 5 5V TA TMiN to Tmax unless otherwise noted PARAMETER CONDITIONS MIN TYP MAX UNITS NO Voltage Range 275 V Supply Current 70 150 pA RESET COMPARATOR MAX792L MAX820L 4 50 4 62 4 75 AX792M MAX820M 4 25 4 37 4 50 AX792R MAX820R 2 55 2
14. 6 0 394 9 80 10 00 16 AC M 3 E SIDE VIEW DALLAS VLAIXL VI PROPRIETARY INFORMATION TITLE PACKAGE OUTLINE 150 SOIC APPROVAL DOCUMENT CONTROL NO REV 21 0041 B A Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 16 2005 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products Inc SOICN EPS Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600
15. ATURE C PROPAGATION DELAY ns 20 150 0 30 60 90 120 150 TEMPERATURE C CHIP ENABLE PROPAGATION DELAY vs CE OUT LOAD CAPACITANCE Vec 5V VCE n OV TO 5V DRIVER SOURCE IMPEDANCE 500 92 11 0 25 50 75 100 125 150 175 200 225 250 CLoan pF MAXIM Microprocessor and Nonvolatile Memory Supervisory Circuits Pin Description PIN NAME FUNCTION Active Low Reset Output goes low whenever Vcc falls below the reset threshold in internal thresh 1 RESET old programming mode or RESET IN falls below 1 30V in external threshold programming mode RESET remains low for 200ms typ after the threshold is exceeded on power up 2 RESET Reset is the inverse of RESET 3 Input Supply Voltage ate Reset Input Internal Mode Select Connect this input to GND to select internal threshold mode 4 RESET IN INT Select external programming mode by pulling this input 600 or higher through an external volt age divider Low Line Input Reference Output connects directly to the low line comparator in external program 5 LLIN REF OUT ming mode RESET IN INT 2 600mV Connects directly to the internal 1 30V reference in internal threshold mode RESET IN INT lt 60mv Overvoltage Comparator Output goes low when OVI is greater than 1 30V This is an uncommitted 6 Ove comparator and
16. URE PERIOD vs Vcc 600 P 300 i 30 _ 500 il amp 25 200 1 5 Gi 400 A ex 2 150 20 2 30 p 100 a 15 200 Vec FALLING 50 15mV OVERDRIVE E GRAMMING MODE 100 0 10 60 30 0 30 60 90 120 150 60 30 0 30 60 90 120 150 2 3 4 5 TEMPERATURE C TEMPERATURE C Vec V MAXIM 5 Of8XVIN CELXVIN MAX792 MAX820 Microprocessor and Nonvolatile Memory Supervisory Circuits TA 25 C unless otherwise noted INTERNAL MODE RESET THRESHOLD vs TEMPERATURE NORMALIZED Typical Operating Characteristics continued REF OUT VOLTAGE vs TEMPERATURE MAX792 7 E Q CHIP ENABLE ON RESISTANCE vs TEMPERATURE MAX792 8 U ON RESISTAN 1 125 s 1 33 1 100 1 32 1 075 1 31 2 1 050 ca 8 1 025 5 1 29 1 000 Lu lu wn oo 0 975 1 28 0 950 1 27 THE RESET THRESHOLD IS SHOWN 0 925 NORMALIZED TO 1 REPRESENT 1 26 ALL AVAILABLE MAX792 MAX820 0 900 125 60 30 30 60 90 120 150 60 30 TEMPERATURE C WATCHDOG TIMEOUT PERIOD vs SWT LOAD CAPACITANCE 100 2 c 10 25V E Vcc 23V CD a 2 10 1 in 10n On im Cswr F 0 30 60 TEMPER
17. ansmission gate disables and CE IN immediately becomes high impedance if the volt age at CE IN is high If CE IN is low when reset is assert ed the CE transmission gate will disable at the moment CE IN goes high or 15us after reset is asserted whichever occurs first Figure 9 This permits the cur rent write cycle to complete during power down During a power up sequence the CE transmission gate remains disabled and CE IN remains high impedance regardless of CE IN activity until reset is deasserted fol lowing the reset timeout period While disabled CE IN is high impedance When the CE transmission gate is enabled the impedance of CE IN will appear as a 75Q Vcc 5V resistor in series with the load at CE OUT The propagation delay through the CE transmission gate depends on Vcc the source impedance of the drive connected to CE IN and the loading on CE OUT see the Chip Enable Propagation Delay vs CE OUT Load Capacitance graph in the Typical Operating Characteristics The CE propagation delay is produc tion tested from the 50 point on CE IN to the 50 point on CE OUT using a 500 driver and 5OpF of load capacitance Figure 10 For minimum propagation delay minimize the capacitive load at CE OUT and use a low output impedance driver MAXIM Voc THRESHOLD CEIN Figure 10 CE Propagation Delay Test Circuit Chip Enable Output When the CE transmission gate is enabled the imped ance of CE OUT
18. e Memory Supervisory Circuits ei 25us MIN i 12S TYP 41515 TYP OTHER MAXIM RESET MAX792 SOURCES MAX820 DIODES NOT REQUIRED ON OPEN DRAIN OUTPUTS Figure 3 Diode OR connections allow multiple reset sources to connect to MR Low Line Output In internal threshold mode the low line comparator monitors Vcc with a threshold voltage typically 120mV above the reset threshold and with 15mV of hysteresis For normal operation Vcc above the reset threshold LOWLINE is pulled to Vcc Use LOWLINE to provide an NMI to the uP as described in the previous section when Vcc begins to fall Figure 4 Reset Function The MAX792 MAX820 provide both RESET and RESET outputs The RESET and RESET outputs ensure that the UP powers up in a known state and prevent code exe cution errors during power up power down or brownout conditions The reset function will be asserted during the following conditions 1 Vcc less than the programmed reset threshold 2 MRless than 1 30V typ 3 Reset remains asserted for 200ms typ after Vcc rises above the reset threshold or after MR has exceeded 1 30V typ 10 4 RESET IN INT RESE MAXIM MAX792 __ LLIN REFOUT RESE RESET IN INT RESET MAXIM MAX792 LLIN REFOUT RESET R3 1 30V x Vcc VLOW LINE X R2 1 30V x Voc _ R3 Imax THE MAXIMUM DESIRED CURRENT VRESET X IMAX THROUGH THE VOLTAGE DIVIDED Rl VCC MAX R
19. e MAX792 Vcc 5V OR Vcc 1 25 1 30 1 35 V External Programming Mode MAX820 Vcc 5V OR Vcc 1 274 1 30 1 326 Low Line Hysteresis nternal Threshold Mode 29 my LLIN REFOUT Leakage Current 0 01 25 nA External Programming Mode Low Line Comparator Delay Vcc falling 450 us rA aues 3 2mA 0 4 LOWLINE Voltage SINK ISOURCE Vcc 1 LOWLINE Short Circuit Current Output source current Vcc 5 5V 10 50 WATCHDOG FUNCTION SWT connected to Vcc Vcc 5V 1 00 1 60 2 25 T SWT connected to Vcc Vcc 1 00 1 60 2 25 Watchdog Timeout Period 4 7nF capacitor connected from SWT to GND 70 Vcc 3V ms 4 7nF capacitor connected from SWT to GND 400 Vcc 5V Watchdog Input Pulse Width ViL OV Vin V nee OY 129 ns g np IL VIH VCC Voc 300 ISINK 50pA Vcc 1V Vcc falling 0 01 0 30 ISINK 1 6mA 0 1 0 4 WDO Output Voltage V 3 ISOURCE 1MA Vcc 1 ISOURCE 100A Vcc 0 5 WDPO to WDO Delay 70 ns WDPO Duration 0 5 1 7 6 0 ms ISINK 50pA Vcc 1V Vcc falling 0 01 0 3 WDPO Output Voltage 2 sA utpu ISOURCE 1mA Voc 1 ISOURCE 100 Vcc 0 5 V 75xV Voc 4 25V H LTS X Vee zm WDI Threshold Voltage IE i VIH 0 9 x Vcc Vcc 2 55V VIL 0 2 WDI Input Current 1 MAXIMA 3 Of8XVIN CELXVIN Microprocessor and Nonvolatile Memory Supervisory Circuits ELECTRICAL CHARACTERISTICS continued Vcc 2 75V to 5 5V TA to Tmax unless otherwise noted
20. has no effect on any other internal circuitry 7 OVI Inverting Input to the Overvoltage Comparator When OVI is greater than 1 30V OVO goes low Connect OVI to GND or Vcc when not used Set Watchdog Timeout Input Connect this input to Vcc to select the default 1 6sec watchdog 8 SWT imeout period Connect a capacitor between this input and GND to select another watchdog imeout period Watchdog timeout period k x capacitor value in nF mV where k 27 for Vcc 5V and k 16 2 for Vcc If the watchdog function is unused connect SWT to Vcc 9 MR anual Reset Input This input can be tied to an external momentary pushbutton switch or to a ogic gate output Internally pulled up to Vcc 10 TOW LINE Low Line Output LOW LINE goes low 120mV above the reset threshold in internal threshold mode or when LLIN REFOUT goes below 1 30V in external programming mode Watchdog Input If WDI remains either high or low for longer than the watchdog timeout period 11 WDI WDPO pulses low WDO goes low WDO remains low until the next transition at WDI Connect GND or Vcc if unused 12 GND Ground Chip Enable Output CE OUT goes low only when CE IN is low and reset is not asserted If CE IN is 13 CE OUT low when reset is asserted CE OUT will stay low for 15s or until CE IN goes high whichever occurs first Chip Enable Input the input to the chip enable transmission gate Connect to GND or Vcc if not
21. iod Select an alternative watch dog timeout period by connecting a capacitor between SWT and GND Do not leave SWT floating and do not connect it to ground The following formula determines the watchdog timeout period Watchdog Timeout Period k x capacitor value in nF ms where k 27 for Vcc and k 16 2 for Vcc 5V This applies for capacitor values in excess of 4 7nF If the watchdog function is unused connect SWT to Vcc MAXIM Microprocessor and Nonvolatile Memory Supervisory Circuits Chip Enable Signal Gating The MAX792 MAX820 provide internal gating of chip enable CE signals which prevents erroneous data from corrupting CMOS RAM in the event of an under voltage condition The MAX792 MAX820 use a series transmission gate from CE IN to CE OUT Figure 1 During normal operation reset not asserted the CE transmission gate is enabled and passes all CE transi tions When reset is asserted this path becomes dis abled preventing erroneous data from corrupting the CMOS RAM The 10ns max CE propagation delay from CE IN to CE OUT enables the MAX792 MAX820 to be used with most Ps If CE IN is low when reset asserts CE OUT remains low for a short period to permit com pletion of the current write cycle Chip Enable Input The CE transmission gate is disabled and CE IN is high impedance disabled mode while reset is asserted During a power down sequence when Vcc passes the reset threshold the CE tr
22. leaded and lead free packaging Specify lead free by adding the symbol at the end of the part number when ordering Lead free not available for CERDIP package SUFFIX RESET THRESHOLD V 4 62 4 37 3 06 2 91 2 61 DOA i TOP VIEW RESET RESET Voc RESET IN INT LLIN REFOUT ovo OVI SWT Pin Configuration MAXIMA MAX792 MAX820 WDI LOW LINE MR OC8XVW cC6ZXVM DIP SO Chip Topography RESET WDO Vcc A RESET IN ee INT N 4 0 078 ET D RE 1 981mm REF OUT 9 ll ovo de WDI MAXIM TRANSISTOR COUNT 950 SUBSTRATE CONNECTED TO Vcc SWTMR LOW LINE 0 070 1 778mm 15 MAX792 MAX820 Microprocessor and Nonvolatile Memory Supervisory Circuits Package Information HABA BABE Pied EEHH TOP VIEW MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0 15mm 006 H A q lii e ses mti FRONT VIEW NOTES 1 D amp E DO NOT INCLUDE MOLD FLASH 2 3 LEADS BE COPLANAR WITHIN 0 10mm 004 4 CONTROLLING DIMENSION MILLIMETERS 5 MEETS JEDEC MS013 6 N NUMBER OF PINS INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0 093 0 104 2 35 2 65 A1 0 004 0 012 0 10 0 30 B 0 014 0 019 0 35 0 49 0 009 0 013 0 23 0 32
23. oltage will be below 0 4V while sinking 40uA When using an external pull down resistor of 10kQ the high state for the RESET output with Voc 4 75V is typically 4 60V Overvoltage Comparator The overvoltage comparator is an uncommitted com parator that has no effect on the operation of other chip functions Use this input to provide overvoltage indica tion by connecting a voltage divider from the input sup ply as in Figure 6 Connect OVI to ground if the overvoltage function is not used OVO goes low when OVI goes above 1 30V With OVI below 1 30V OVO is actively pulled to Vcc and can source 1HA MAXIM RESET MAXIM MAX792 MAX820 Figure 5 Adding an external pull down resistor ensures RESET is valid with Vcc down to GND VOLTAGE REGULATOR Voc MAXIM MAX792 820 OVERVOLTAGE Figure 6 Detecting an Overvoltage Condition Watchdog Function The watchdog monitors uP activity via the watchdog input WDI If the uP becomes inactive WOO and WDPO are asserted To use the watchdog function connect WDI to a uP bus line or I O line If WDI remains high or low for longer than the watchdog timeout period 1 6s nominal WDPO and WDO are asserted indicating a soft ware fault condition see Watchdog Pulse Output and Watchdog Output sections Watchdog Input If the watchdog function is unused connect WDI to Vcc or GND A change of state high to low low to high or
24. rectly Monitoring the Regulated Supply The MAX792 MAX820 offer two modes for monitoring the regulated supply and providing reset and non maskable interrupt NMI signals to the uP internal threshold mode uses the factory preset low line and reset thresholds and external programming mode allows the low line and reset thresholds to be pro grammed externally using a resistor voltage divider Figure 4 Internal Threshold Mode Connecting the reset input internal mode select pin RESET IN INT to ground selects internal threshold mode Figure 4a In this mode the low line and reset thresholds are factory preset by an internal voltage divider Figure 1 to the threshold voltages specified in the Electrical Characteristics Reset Threshold Voltage and Low Line Threshold Voltage Connect the low line output LOWLINE to the uP NMI pin and connect the active high reset output RESET or active low reset output RESET to the uP reset input pin Additionally the low line input reference output pin LLIN REFOUT connects to the internal 1 30V refer ence in internal threshold mode Buffer LLIN REFOUT with a high impedance buffer to use it with external circuitry In this mode when Vcc is falling LOWLINE is guaranteed to be asserted prior to reset assertion External Programming Mode Connecting RESET IN INT to a voltage above 600mV selects external programming mode In this mode the low line and reset comparators disconnec
25. s such as the Motorola 68HC11 series can contend with the MAX792 MAX820 RESET output If for example the MAX792 MAX820 RESET output is asserted high and the uP wants to pull it low indeterminate logic levels may result To avoid this connect a 4 7kQ resistor between the MAX792 MAX820 RESET output and the uP reset 1 0 as in Figure 12 Buffer the MAX792 MAX820 RESET output to other sys tem components Negative Going Vcc Transients While issuing resets to the uP during power up power down and brownout conditions these supervisors are relatively immune to short duration negative going Vcc transients glitches It is usually undesirable to reset the uP when Vcc experiences only small glitches Figure 13 shows maximum transient duration vs reset comparator overdrive for which reset pulses are not generated The graph was produced using negative 14 TO OTHER SYSTEM RESET INPUTS Voc RESET MAXIM MAX792 MAX820 Figure 12 Interfacing to uPs with Bidirectional RESET Pins going Vcc pulses starting at 5V and ending below the reset threshold by the magnitude indicated reset comparator overdrive The graph shows the maximum pulse width a negative going Vcc transient may typi cally have without causing a reset pulse to be issued As the amplitude of the transient increases i e goes farther below the reset threshold the maximum allow able pulse width decreases Typically a Vcc transient that
26. t from the inter nal voltage divider and connect to LLIN REFOUT and RESET IN INT respectively Figure 1 This mode allows flexibility in determining where in the operating voltage range the NMI and reset are generated Set the low line and reset thresholds with an external resistor divider as in Figure 4b or Figure 4c RESET typically remains valid for Vcc down to 2 5V RESET is guaranteed to be valid with Vcc down to 1V Calculate the values for the resistor voltage divider in Figure 4b using the following equations 1 1 30 x Vcc MAX VLow LINE X Imax 2 R2 1 30 x Vcc MAX Vngser X Imax R3 3 R1 Vcc MAX Imax R2 First choose the desired maximum current through the voltage divider Imax when Vcc is at its highest Vcc MAX There are two things to consider here First Imax contributes to the overall supply current for the circuit so you would generally make it as small as possible Second Imax cannot be too small or leakage currents will adversely affect the programmed threshold voltages 5uA is often appropriate Determine R3 after you have chosen Imax Use the value for R3 to determine R2 then use both R2 and R3 to determine R1 For example to program a 4 75V low line threshold and a 4 4V reset threshold first choose Imax to be 5uA when Vcc 5 5V and substitute into equation 1 R3 1 30 x 5 5 4 75 x 5E 6 301 05kQ 301kQ is the nearest standard 0 1 value Substitute into equation
27. t reset thresholds Note 2 Pulling RESET IN INT below 60mvV selects internal threshold mode and connects the internal voltage divider to the reset and low line comparators External programming mode allows an external resistor divider to set the low line and reset thresholds see Figure 4 m m Note 3 The Chip Enable Propagation delay is measured from the 50 point at CE IN to the 50 point at CE OUT 4 MAXIM Microprocessor and Nonvolatile Memory Supervisory Circuits Typical Operating Characteristics TA 25 C unless otherwise noted OVERVOLTAGE COMPARATOR RESET COMPARATOR SUPPLY CURRENT vs TEMPERATURE PROPAGATION DELAY vs TEMPERATURE PROPAGATION DELAY vs TEMPERATURE 10 5 70 3 80 E SWT Vcc E E ALL OUTPUTS 7 d 2 8 UNLOADED t 2 60 2 70 3 7 gt 5 lt mob E 5 5 50 5 o E 1 4 pe amp amp 2 3 I amp 40 amp 50 2 Vin TO VoL Voc FALLING 1 Vin 20mV 15mV OVERDRIVE i OVERDRIVE 15mV EXTERNAL PROGRAMMING MODE 0 60 30 0 30 60 90 120 150 60 30 0 30 60 90 120 150 60 30 0 30 60 90 120 150 TEMPERATURE C TEMPERATURE C TEMPERATURE C LOW LINE COMPARATOR POWER UP RESET DELAY NOMINAL WATCHDOG TIMEOUT PROPAGATION DELAY vs TEMPERATURE vs TEMPERAT
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MAXIM MAX792/820 Manual