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PHILIPS P8xC591 Manual

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1. message 3 receive FIFO message 2 1 Sri 7 incoming 4 fa message 1 Messages 7 window da amp e 7 PE canat mtt A MHI019 Message 1 is now available in the Receive Buffer Note that message 2 should not be read until it has been shifted to address 96 by a Release Receive Buffer Command because this message may be in process now and due to this not fixed Fig 21 Example of the message storage within the RXFIFO 2000 Jul 26 58 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 12 5 19 1 Descriptor File of the Receive Buffer Preliminary Specification P8xC591 Identifier Frame Format Remote Transmission Request bit and Data Length Code have the same meaning as described in the Transmit Buffer Standard Frame Format SFF Extended Frame Format EFF Addr 96 RX Frame Information 7 6 3 2 1 0 FF RTR DLC 3 DLC 2 DLC 1 DLC 0 RX Identifier 1 Addr 96 RX Frame Information RX Identifier 2 Addr 97 Addr 97 RX Identifier 1 7 6 5 4 3 2 1 0 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 Addr 98 Addr 98 RX Identifier 2 7 6 5 4 3 1 0 7 6 5 4 3 2 1 0 1 20 10 19 1 18 0 0 0 0 1 20 ID 19 ID 18 10 17 10 16 10 15 10 14 10 13 Meaning of the Receive Buffer Bits ID x Identifier bit x F
2. Im M Shift l Loo 1 N NA 1 1n Nn NA 1nh 1 ___ RI TxD Data S J Lo Shift 1 GO n hn n hn hn Stop bit RX Clock fl ff 1n 1 nh NI fl Stop bit MHI027 gt Transmit Receive Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 80C51 INTERNAL BUS write to SBUF SBUF YNI TxD Stop bit Shift Start gen Data TX CONTROL BAUD RATE CLOCK TX Clock TI Send RX Clock RI load SBUF Shift TRANSITION RX CONTROL DETECTOR RxD INPUT SHIFT REGISTER 9 BITS 80C51 INTERNAL BUS i TX Clock write to SBUF Send spit e sit fn Transmit Start Do bt DO X D X D2 0 X D4 X D5 A D6 X D7 X 188 Y Stop bit hec e e e bu _ _ elfe t ru i o S Stop bit gen 16 Reset 5 RX Clock hn i _ f Start RxD bt Do X D1 X D2 X ps X D4 X D5 X D6 X D7 X TB8 f Bit detector sample times M M MM M M ffi MM Receive Shift 1n Nn n f hnh RI MHIO28 Fig 27 Serial Port Mode 2 and 3 2000 Jul 26 70 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 14 5 Enhanced UART The UART operates in all of the usual modes that are described in the Section of S
3. 1 Unsuccessful attempt to send a Start condition 2 SDA line released MHIO44 Start py condition 3 Successful attempt to send a Start condition state D8H is centered Fig 43 Recovering from a bus obstruction caused by a low level on SDA 2000 Jul 26 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 15 3 Software Examples of SIO1 Service Routines This section consists of a software example for e Initialization of SIO1 after a RESET e Entering the SIO1 interrupt routine e The 26 state service routines for the Master transmitter mode Master receiver mode Slave receiver mode Slave transmitter mode 15 3 1 INITIALIZATION In the initialization routine SIO1 is enabled for both master and slave modes For each mode a number of bytes of internal data RAM are allocated to the SIO to act as either a transmission or reception buffer In this example 8 bytes of internal data RAM are reserved for different purposes The data memory map is shown in Figure 44 The initialization routine performs the following functions S1ADR is loaded with the parts own slave address and the general call bit GC P1 6 and P1 7 bit latches are loaded with logic 1s RAM location HADD is loaded with the high order address byte of the service routines The SIC interrupt enable and interrupt priority bits are set The slave mode is enabled by simultaneously setting the ENS1 and
4. _ nominal bit time t ___ seg seg 4 4 MHIO11 De e g 0000106 sample point s TSEG1 0101b TSEG2 010b Fig 12 General structure of a bit period 2000 Jul 26 41 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 12 5 10 RX MESSAGE COUNTER RMC Preliminary Specification P8xC591 The RMC Register CAN Address 9 reflects the number of messages available within the RXFIFO The value is incremented with each receive event and decremented by the Release Receive Buffer command After any reset event this register is cleared Table 22 RX Message Counter RMC CAN address 9 7 6 5 RMC 7 RMC 6 RMC 5 12 5 11 RX BUFFER START ADDRESS RBSA The RBSA register CAN Address 10 reflects the currently valid internal RAM address where the first byte of the received message which is mapped to the Receive Buffer Window is stored With the help of this information it is possible to interpret the internal RAM contents The internal RAM address area begins at CAN address 32 and may be accessed by the CPU for reading and writing writing in Reset Mode only Example If RBSA is set to 24 decimal the current message visible in the Receive Buffer Window CAN Address 96 108 is stored within the internal RAM beginning at RAM address 24 Because the RAM is also mapped directly to the CAN address space beginning at CAN address 128 equal to RAM address 0
5. Addr 18 ACR2 Addr 19 ACR3 7 e s5 4 a 2 1 o z e 5 4 s 2 1 o MSB LSB MSB LSB Filter 1 Filter 2 Acceptance Mask Bit Acceptance Code Bit Acceptance Code Bit Acceptance Mask Bit LI Message Bit 1 LI 1 accepted accepted MHI018 Fig 18 Dual Filter Configuration receiving Extended Frame Messages 54 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 12 5 18 TRANSMIT BUFFER The global layout of the Transmit Buffer is shown in Fig 19 One has to distinguish between the Standard Frame Format SFF and the Extended Frame Format EFF configuration The transmit buffer allows the definition of one transmit message with up to eight data bytes Preliminary Specification P8xC591 12 5 18 1 Transmit Buffer Layout It is subdivided into Descriptor and Data Field where the first byte of the Descriptor Field is the Frame Information Byte Frame Info It describes the Frame Format SFF or EFF Remote or Data Frame and the Data Length Two identifier bytes for SFF and four bytes for EFF messages follow The Data Field contains up to eight data bytes The Transmit Buffer has a length of 13 bytes and is located in the CAN address range from 112 to 124 Standard Frame Format SFF CAN Address 112 TX Frame information 113 TX Identifier 1 114 TX Identifier 2 115 TX Data byte 1 116 TX Data byte 2 117 TX Data by
6. 2000 Jul 26 101 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 15 3 4 MASTER TRANSMITTER AND MASTER RECEIVER MODES The master mode is entered in the main program To enter the master transmitter mode the main program must first load the internal data RAM with the slave address data bytes and the number of data bytes to be transmitted To enter the master receiver mode the main program must first load the internal data RAM with the slave address and the number of data bytes to be received The R W bit determines whether SIO1 operates in the master transmitter or master receiver mode Master mode operation commences when the STA bit in S1CION is set by the SETB instruction and data transfer is controlled by the master state service routines in accordance with Table 61 Table 62 Figure 37 and Figure 38 In the example below 4 bytes are transferred There is no repeated START condition In the event of lost arbitration the transfer is restarted when the bus becomes free If a bus error occurs the I C bus is released and SIO1 enters the not selected slave receiver mode If a slave device returns a not acknowledge a STOP condition is generated A repeated START condition can be included in the serial transfer if the STA flag is set instead of the STO flag in the state service routines vectored to by status codes 28H and 58H Additional software must be written to determine which data is transferre
7. ALE PSEN PORTO PORT 2 A8 A15 A8 A15 MBC483 1 Fig 55 External program memory read cycle 2000 Jul 26 148 Preliminary Specification Philips Semiconductors P8xC591 Single chip 8 bit microcontroller with CAN controller 96 614 1 S8FIAN HOd W04 GLV 8Y 8Y 10 Z ed O cd e AAN ja IMY N Z HH ja XYI TA MT AQT _ gt lt 2 1HOd 0 LHOd N3Sd 149 2000 Jul 26 P8xC591 Preliminary Specification Single chip 8 bit microcontroller with CAN controller Philips Semiconductors e oKo allim Aowsuw eula x3 9 614 1 98 08 HOd W04 GLV 8Y Hda uloli GLY 8Y 10 Z ed O ed 2 1HOd 10 NI HISNI 4 gt 0 LHOd uM N3Sd qv 150 2000 Jul 26 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 MGA175 Fig 58 External clock drive XTAL1 INSTRUCTION o 1 2 ALE CLOCK OUTPUT DATA 0 1 WRITE TO SBUF SET TI INPUT DATA AER LER LER LER LER REA RD INPUT DATA CLEAR RI MBC475 SET RI Fig 59 Shift register mode timing waveforms 2000 Jul 26 151 Philips Semiconductors Single chip 8 bit micr
8. The maximum repetition rate for Timer T2 is twice the maximum repetition rate for Timer 0 and Timer 1 T2 P3 0 is sampled at S2P1 and again at S5P1 i e twice per machine cycle A rising edge is detected when T2 is LOW during one sample and HIGH during the next sample To ensure that a rising edge is detected the input signal must be LOW for at least 1 2 cycle and then HIGH for at least Vo cycle If a rising edge is detected before the end of S2P1 the timer will be incremented during the following cycle otherwise it will be incremented one cycle later The prescaler has a programmable division factor of 1 2 4 or 8 and is cleared if its division factor or input source is changed or if the timer counter is reset Timer T2 may be read on the fly but possesses no extra read latches and software precautions may have to be taken to avoid misinterpretation in the event of an overflow from least to most significant byte while Timer T2 is being read Timer T2 is not loadable and is reset by the RST Preliminary Specification P8xC591 signal or by a rising edge on the input signal RT2 if enabled RT2 is enabled by setting bit T2ER TM2CON 5 When the least significant byte of the timer overflows or when a 16 bit overflow occurs an interrupt request may be generated Either or both of these overflows can be programmed to request an interrupt In both cases the interrupt vector will be the same When the lower byte TML2
9. Table 81 Description of IP1 bits BIT SYMBOL DESCRIPTION 7 PT2 T2 overflow interrupt s priority level 6 PCAN CAN interrupt priority level 5 PCM1 T2 comparator 1 priority interrupt level 4 PCMO T2 comparator 0 priority interrupt level 3 PCT3 T2 capture register 3 priority interrupt level 2 PCT2 T2 capture register 2 priority interrupt level 1 PCT1 T2 capture register 1 priority interrupt level 0 PCTO T2 capture register O priority interrupt level 2000 Jul 26 119 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 17 WATCHDOG TIMER T3 In addition to Timer T2 and the standard timers a Watchdog Timer T3 is also incorporated on the P8xC591 The purpose of a Watchdog Timer is to reset the microcontroller if it enters erroneous processor states possibly caused by electrical noise or RFI within a reasonable period of time An analogy is the dead man s handle in railway locomotives When enabled the watchdog circuitry will generate a system reset if the user program fails to reload the Watchdog Timer within a specified length of time known as the watchdog interval Watchdog Circuit Description The watchdog timer Timer T3 consists of an 8 bit timer with an 11 bit prescaler as shown in Figure 46 The prescaler is fed with a signal whose frequency is s the oscillator frequency 1 MHz with a 6 MHz oscillator The 8 bit timer is incremented every t seconds whe
10. extended C frame messages 1017 1016 1015 1014 1013 1012 1011 1010 1009 IDO8 1006 1005 1004 1003 1002 1001 1000 23 31 bit number 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 arbitration lost ALC 08 example TX RX bit number MHIO13 Fig 13 Arbitration Lost Bit Number Interpretation 2000 Jul 26 43 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 12 5 13 ERROR CODE CAPTURE ECC Preliminary Specification P8xC591 This register contains information about the type and location of errors on the bus The Error Code Capture Register appears to the CPU as a read only memory Table 26 Error Code Capture ECC CAN address 12 2000 Jul 26 7 6 5 4 3 2 1 0 ERRC1 ERRCO DIR SEG4 SEG3 SEG2 SEG1 SEGO Table 27 Description of Error Code Capture ECC Register bits BIT SYMBOL NAME VALUE FUNCTION 7 ERRC1 Error Code 1 ERRC1 ERRCO 6 ERRCO Error Code 0 0 0 Bit Error 0 1 Form Error 1 0 Stuff Error 1 1 Other Error 5 DIR Direction 1 RX Error occurred during reception 0 TX Error occurred during transmission 4 SEG4 Segment 4 Reflects the current Frame Segment to determine between different error events 3 SEG3 Segment 3 00011 Start Of Frame 2 SEG2 Segment 2 00010 1028 1021 1 SEGI Segment1 00110 ID20 ID18 0 SEGO Segment0 00100 SRTR Bit 00101 IDE Bit 00111 1017 1013 01111 1012 105 01110 ID4
11. write to SBUF RxD P3 0 Alt output function TX CONTROL S6 TX Clock Ti TxD P3 1 Alt SHIFT output RX Clock Ri Receive CLOCK function RX CONTROL REN Start Shift RI 1 3 EMO RxD P3 0 Alt input function 80051 INTERNAL BUS 54 st sejsi va sejsi Vv 96 1 ES se s sh sesi Ho sejst es 86 91 se st p Shift l Transmit gt Yo _ TxD Shift Clock M S3P1 sepi n Write to SCON Clear RI RI Receiver e ele Shift 1 Receive RxD Data In DO DI D2 D3 D4 D5 D6 D7 TxD Shift Clock MHI026 Fig 25 Serial Port Mode 0 2000 Jul 26 68 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller with CAN controller P8xC591 80C51 INTERNAL BUS write to SBUF SBUF 1117 Shift Data TX CONTROL BAUD RATE CLOCK TI Send RX Clock R1 load SBUF Shift 1FFH TRANSITION RX CONTROL DETECTOR RxD INPUT SHIFT REGISTER 9 BITS 80C51 INTERNAL BUS TX Clock write to SBUF Send 1 Start 16 Reset Start Fig 26 Serial Port Mode 1 2000 Jul 26 69 bt Do X Di X pz X 68 66 57 TI ee a __ _ RxD pit Do XD Xo X 57 Bit detector sample times IM IM MM
12. 2000 Jul 26 77 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller with CAN controller P8xC591 15 2 5 ARBITRATION AND SYNCHRONIZATION LOGIC The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device If two or more master devices generate clock pulses the mark duration is determined by the device that generates the shortest marks and the space duration is determined by the device that generates the longest spaces Figure 34 shows the synchronization procedure In the master transmitter mode the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C bus If another device on the bus overrules a logic 1 and pulls the SDA line low arbitration is lost and SIO1 immediately changes from master transmitter to slave receiver SIO1 will continue to output clock pulses on SCL until transmission of the current serial byte is complete A slave may stretch the space duration to slow down the bus master The space duration may also be stretched for handshaking purposes This can be done after each bit or after a complete byte transfer SIO1 will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred The serial interrupt flag SI is set and the stretching continues until the serial interrupt flag is cleared Arbitration may also be lost
13. In Idle mode the following functions remain active Timer 0 Timer 1 Timer T3 5100 5101 External interrupts When the P8xC591 enters the Power down mode the oscillator is stopped The Power down mode is entered by Vin setting the PD bit in the PCON register The PD bit can Result 1024 x only be set if the WDE bit is 0 AV cet AVref R 2 B ec R lla pra lt START lt Total resistance SUCCESSIVE SUCCESSIVE 1023R 2 x R DECODER APPROXIMATION APPROXIMATION 10248 REGISTER CONTROL LOGIC Xo Xo READY NE SS R2 V MHIO53 AVss ref Vin COMPARATOR Value 0000 0000 00 is output for voltages 0 V LSB Value 1111 1111 11 is output for voltages Vier Y LSB to Fig 51 ADC Realization 2000 Jul 26 129 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 to comparator 77 MHI054 Rm 0 5 3kQ Cs Cc 15 pF maximum Rs Recommended lt 9 6 kQ for 1 LSB 12 MHz Note Because the analog to digital converter has a sampled data comparator the input looks capacitive to a source When a conversion is initiated switch Sm closes for 8 tcy 4 us 12 MHz crystal frequency during which time capacitance Cs Cc is changed It should be noted that the sampling causes the analog input to prevent a varying load to an analog source Fig 52 A D Input Equivalent Circuit
14. IDO 01100 RTRBit 01101 Reserved Bit 1 01001 Reserved Bit 0 01011 Data Length Code 01010 Data Field 01000 CRC Sequence 11000 CRC Delimiter 11001 Acknowledge Slot 11011 Acknowledge Delimiter 11010 End Of Frame 10010 Intermission 10001 Active Error Flag 10110 Passive Error Flag 10011 Tolerate Dom Bits 10111 Error Delimiter 11100 Overload Flag Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 Always if a bus error occurs the corresponding bus error interrupt is forced if enabled In the same time the current position of the Bit Stream Processor is captured into the Error Code Capture Register The content within this register is fixed until the users software has read out its content once From now on the capture mechanism is activated again The corresponding Interrupt Flag located in the Interrupt Register is cleared during the read access to the Interrupt Register A new Bus Error Interrupt is not possible until the Capture Register is read out once 12 5 14 ERROR WARNING LIMIT REGISTER EWLR The Error Warning Limit could be defined within this register The default value after hardware reset is 96d In Reset Mode this register appears to the CPU as a read write memory Table 28 Error Warning Limit Register EWLR CAN address 13 7 6 5 4 3 2 1 0 EWL 7 EWL 6 EWL 5 EWL 4 EWL 3 EWL 2 EWL 1 EWL O Note that a content change of the EWL Register
15. Table 25 Description of Arbitration Lost Capture ALC Register bits FUNCTION Reserved 4 BITNO4 Bit Number 4 Binary coded Frame Bit Number where arbitration was lost 00 gt arbitration lost in first bit of identifier BITNO3 Bit Number 3 si BITNO2 Bit Number 2 11 arbitration lost in SRTR bit RTR bit for standard frame messages 12 arbitration lost in IDE bit 13 arbitration lost in 12th bit of identifier extended frame only BITNO1 BITNOO Bit Number 1 Bit Number 0 30 gt arbitration lost in last bit of identifier extended frame only 31 gt arbitration lost in RTR bit extended frame only On arbitration lost the corresponding arbitration lost interrupt is forced if enabled In the same time the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register The content within this register is fixed until the users software has read out its contents once From now on the capture mechanism is activated again The corresponding Interrupt Flag located in the Interrupt Register is cleared during the read access to the Interrupt Register A new Arbitration Lost Interrupt is not possible until the Arbitration Lost Capture Register is read out once start of frame fame messages SY 1028 1027 1026 1025 1024 1023 1022 1021 1020 1019 ID18 SRTR IDE 00 01 02 03 04 05 06 07 08 09 10 11 12 bit number
16. pin T2 2000 Jul 26 114 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 16 1 2 TIMER T2 EXTENSION When a 6 MHz oscillator is used a 16 bit overflow on Timer T2 occurs every 65 5 131 262 or 524 ms depending on the prescaler division ratio i e the maximum cycle time is approximately 0 5 seconds In applications where cycle times are greater than 0 5 seconds it is necessary to extend Timer T2 This is achieved by selecting fc 6 as the clock source set 2 50 reset T2MS1 setting the prescaler division ration to Vs set T2PO set T2P1 disabling the byte overflow interrupt reset T2180 and enabling the 16 bit overflow interrupt set T2191 The following software routine is written for a three byte extension which gives a maximum cycle time of approximately 2400 hours OVINT PUSH ACO save accumulator PUSH PSW save status INC TIMEX1 increment first byte low order of extended timer MOV A TIMEX1 JNZ INTEX jump to INTEX if there is no overflow INC TIMEX2 increment second byte MOV A TIMEX2 JNZ INTEX jump to INTEX if there is no overflow INC increment third byte high order INTEX CLR T2OV _ reset interrupt flag POP PSW __ restore status POP ACC restore accumulator RETI return from interrupt 2000 Jul 26 Preliminary Specification P8xC591 16 1 3 TIMER T2 CAPTURE AND COMPARE LOGIC Timer T2 is connected to four 16 bit captu
17. tLow LOW period of the SCL clock gt 4 7 usl tHIGH HIGH period of the SCL clock 27 tok gt 4 0 us tnc rise time of SCL signals 2 tec fall time of SCL signals 0 3 us 3 0 us tSU DAT1 data set up time 10 tci k tap tsu DAT2 SDA set up time before repeated START condition gt 250 ns gt 1 us tsU DAT3 SDA set up time before STOP condition gt 4 tek tHD DAT data hold time gt 4 tok tec tsu STA set up time for a repeated START condition gt 4 7 usl tsu sto set up time for STOP condition gt 4 0 us tBuF bus free time between 27 tok gt 4 7 usl trap rise time of SDA signals 2 trp fall time of SDA signals 0 3 us 0 3 us Notes 1 At 100 kbit s At other bit rates this value is inversely proportional to the bit rate of 100 kbit s 2 Determined by the external bus line capacitance and the external bus line pull resistor this must be lt 1 us 3 Spikes on the SDA and SCL lines with a duration of less than 3 tci will be filtered out Maximum capacitance on bus line s SDA and SCL 400 pF 4 tek 1 fcLk one oscillator clock period at pin XTAL1 For 83 ns lt tek 285 ns 12 MHz fei gt 3 5 MHz the S101 interface meets the I 2C bus specification for bit rates up to 100 kbit s 5 These values are guaranteed but not 100 production tested 2000 Jul 26 147 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591
18. 1 AWake Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending 2 In order to support high priority messages the Receive Interrupt is forced immediately upon a received message which has passed successfully an acceptance filter with high priority see acceptance filter section As long as only messages are received via low priority acceptance filters the receive interrupt is not forced until the FIFO is filled with more bytes than programmed in the Rx Interrupt Level Register The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register Giving the Command Release Receive Buffer will clear RI temporarily If there is another message available within the FIFO after the release command RI is set again Otherwise RI keeps cleared 12 5 6 INTERRUPT ENABLE REGISTER IER The register allows to enable different types of interrupt sources which are signalled to the CPU The Interrupt Enable Register appears to the CPU as a read write memory Table 17 Interrupt Enable Register IER CAN Addr 4 bit interpretation IER 7 Bus Error 1 enabled If a bus error has been detected the CAN controller requests Interrupt Enable the respective interrupt 0 disabled IER 6 Arbitration Lost 1 enabled Ifthe CAN controller has lost arbitration the respective interrupt Interrupt Enable is reque
19. 1018 1019 1020 1021 1022 1023 1024 145 LSB ideal amp 1024 02634 Fig 54 ADC conversion characteristic Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller with CAN controller 25 AC CHARACTERISTICS P8xC591 Vpp 5 V 5 Vss 0 V Tamb 40 C to 85 C C 100 pF for Port 0 ALE and PSEN C 80 pF for all other outputs unless otherwise specified 12 MHz CLOCK VARIABLE CLOCK UNIT SYMBOL PARAMETER MIN MAX MIN MAX External Program Memory see Fig 55 System clock frequency see Note 1 tLHLL ALE pulse width tAVLL address valid to ALE LOW 3 5 tcik 25 0 5 tci 25 address hold after ALE LOVV tiiv ALE LOW to valid instruction in 58 17 17 17 80 tLLPL ALE LOW to PSEN LOW tPLPH PSEN pulse vvidth 0 5 tek 25 1 5 45 tPLIV PSEN LOW to valid instruction in input instruction hold after PSEN MHz ns ns 0 5 tcLk 25 ns ns ns ns ns ns input instruction float after PSEN 17 0 5 tek 25 taviv address to valid instruction in 128 2 80 ns tPLAZ PSEN LOW to address float 10 10 ns External Data Memory see Fig 56 and Fig 57 tRLRH RD pulse width 150 B 3 tek 100 ns tRLDV RD LOW to valid data in 118 2 90 ns tRHDX data hold after RD tRHDZ data float after RD 63 20 4
20. At the 71 8th and 9t counter states of each bit time the bit detector samples the value of R D The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the left most position in the shift register which in Modes 2 and 3 is a 9 bit register it flags the RX Control block to do one last shift load SOBUF and RB8 and set RI The signal to load SOBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0 and 2 Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SOBUF One bit time later whether the above conditions were met or not the unit goes back to looking for a 1 to 0 transition at the RxD input Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 80C51 INTERNAL BUS
21. Bus On the Error Status bit is set 0 ok the Error Counters are reset and an Error Interrupt is generated if enabled Reading the TX Error Counter during this time gives information about the status of the Bus Off recovery Errors detected during reception or transmission will effect the error counters according to the CAN specification The Error Status bit is set when at least one of the error counters has reached or exceeded the CPU warning limit of 96 An Error Interrupt is generated if enabled If both the Receive Status and the Transmit Status bits are 0 idle the CAN Bus is idle The Transmission Complete Status bit is set 0 incomplete whenever the Transmission Request bit or the Self Reception Request bit is set 1 The Transmission Complete Status bit will remain 0 until a message is transmitted successfully If the CPU tries to write to the Transmit Buffer when the Transmit Buffer Status bit is 0 locked the written byte will not be accepted and will be lost without this being signalled When a message that is to be received has passed the acceptance filter successfully the CAN controller needs space in the RXFIFO to store the message descriptor and for each data byte which has been received If there is not enough space to store the massage that message is dropped and the data overrun condition is indicated to the CPU at the moment this message becomes valid If this message is not completed
22. No STDAT action or 0 0 0 No STDAT action or 0 0 0 No STDAT action or 1 0 0 No STDAT action 1 0 0 94 Switched to not addressed SLV mode no recognition of own SLA or General call address Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if S1ADR 0 logic 1 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if S1ADR 0 logic 1 A START condition will be transmitted when the bus becomes free Philips Semiconductors Preliminary Specification 8 591 Single chip 8 bit microcontroller with CAN controller Table 64 Slave Transmitter Mode ene STIS ORME APPLICATION SOFTWARE RESPONSE CODE I2C BUS AND TO SICON RE RE 0 S1STA SIO1 HARDWARE TO FROM S1DAT ASH Own SLA R has been Load data byte or Last data byte will be transmitted and ACK received ACK has been bit will be received returned load data byte Data byte will be transmitted ACK will be received BOH Arbitration lost in Load data byte or Last data byte will be transmitted and ACK SLA R W as master bit will be received Own SLA R has been a Lanna received ACK has been load data byte d be transmitted ACK bit will returned B8H Data byte in S1DAT has Load
23. Single chip 8 bit microcontroller vvith GAN controller P8xC591 SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Outputs VoL LOW level output voltage Ports 1 2 3 lor 1 6 MA 0 4 V except P1 0 P1 6 P1 7 see Note 8 Vout LOW level output voltage Port 0 ALE lor 3 2 see Note 8 PSEN RST PWMO PWM1 Vote LOW level output voltage P1 6 P1 7 lor 3 0 mA see Note 8 Vois LOW level output voltage P1 0 and P1 1 lo 8 0 mA HIGH level output voltage Ports 1 2 3 in loy 60 HA pseudo bidirectional output mode except P1 1 P1 6 and P1 7 1 HIGH level output voltage Port 0 and lon 3 2 mA Port 2 in external bus mode see Note 9 Port 2 in push pull mode ALE PSEN PWMO PWM1 HIGH level output voltage P1 0 and P1 1 lo4 1 6mA HIGH level output voltage Ports 1 2 3in loy 1 6 mA push pull output mode except P1 0 P1 1 P1 6 P1 7 RAST RST pull up resistor Cio I O pin capacitance test frequency 1 MHz 15 Tamb 25 C Analog inputs AVIN analog input voltage AVss 0 2 Vpp 0 2 V Cia analog input capacitance taps sampling time 5 tcy Note 1 8 tcy tADC conversion time including sampling time 24 tcy Note 1 50 tcy DLe differential non linearity see Notes 10 11 12 LSB AV refs reference voltage RREF resistance between AV er and AVss 10 ILeg integral non linearity 8 bit mode 1 Note 1 LSB ILe integral non
24. T3 Timer 3 FFH 00H 2000 Jul 26 18 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 7 4 Dual DPTR The dual DPTR structure see Figure 7 is a way by which the chip will specify the address of an external data memory location There are two 16 bit DPTR registers that address the external memory and a single bit called DPS AUXR1 bit0 that allows the program code to switch between them The DPS bit status should be saved by software when switching between DPTRO and DPTR1 Note that bit 2 is not writable and is always read as a zero This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the other bits DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1 bit 0 register The six instructions that use the DPTR are as follows Preliminary Specification P8xC591 INC DPTRIncrements the data pointer by 1 MCV DPTR data 16 Loads the DPTR with a 16 bit constant MOV A A DPTR Move code byte relative to DPTR to ACC Move external RAM 16 bit address to ACC Move ACC to external RAM 16 bit address Jump indirect relative to DPTR MOVX A DPTR MOVX DPTR A DPTR The data pointer can be accessed on a byte by byte basis by specifying the low or high byte in an instruction which accesses the SFRs See application note AN458 for more det
25. _ 57 6 0 16 1 3 FF3h 19 2 1 0 16 1 3 9 6 1 0 16 1 3 FB2h 24 0 16 1 3 ECSh 0 11 0 01 1 3 71Fh INTERNAL BAUD RATE TIMER KBits s DEVIATION RELOAD VALUE 110 1 FDC8h 110 4 0 0 0 21 2 43h 2000 Jul 26 65 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 14 4 More about UART Modes More About Mode 0 Serial data enters and exits through RxD TxD outputs the shift clock 8 bits are transmitted received 8 data bits LSB first The baud rate is fixed a the oscillator frequency Figure 25 shows a simplified functional diagram of the serial port in Mode 0 and associated timing Transmission is initiated by any instruction that uses SOBUF as a destination register The write to SOBUF signal at S6P2 also loads a 1 into the 9 position of the transmit shift register and tells the TX Control block to commence a transmission The internal timing is such that one full machine cycle will elapse between write to SOBUF and activation of SEND SEND enables the output of the shift register to the alternate output function line of P3 0 and also enable SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK is low during S3 S4 and S5 of every machine cycle and high during S6 51 and S2 At S6P2 of every machine cycle in which SEND is active the contents of the transmit shift are
26. clr SI set AA ISTATE 90 Previously addressed with general call DATA has been received ACK has been returned I ACTION Read DATA After General call only one byte vvill be received vvith ACK the second DATA will be received with NOT DATA will be received and NOT ACK returned sect srs90 base 0x190 mov psw SELRB3 mov r0 S1DAT Read received DATA ajmp LDAT 110 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 LOC 0198 019B 019D 01A0 01A3 0145 01A8 01AB 01 00 8 00 00ED 00 OOFO OBJ 75D8C5 DODO 32 75D8C5 DODO 32 8548DA 75D8C5 01E8 75D018 7948 09 DODO 32 2000 Jul 26 SOURCE STATE 98 Previously addressed with general call DATA has been received NOT ACK has been returned ACTION No save of DATA Enter NOT addressed SLV mode Recognition of own SLA General call recognized if S1ADR 01 sect srs98 base 0 198 S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO clr SI set AA pop psw reti STATE A0 A STOP condition or repeated START has been received while still addressed as SLV REC or SLV TRX I ACTION No save of DATA Enter NOT addressed SLV mode Recognition of own SLA General call recognized if S1ADR 01 srsA0 base 0x1a0 mov S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO clr SI set AA pop psw reti JAKAKKAKKKKKKKKAK
27. e g because of an error no overrun condition is indicated After reading all messages within the RXFIFO and releasing their memory space with the command Release Receive Buffer this bit is cleared 2000 Jul 26 37 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 5 5 INTERRUPT REGISTER IR The Interrupt Register allows the identification of an interrupt source When one or more bits of this register are set a CAN interrupt will be indicated to the CPU After this register is read by the CPU all bits are reset except of the Receive Interrupt bit The Interrupt Register appears to the CPU as a read only memory Table 16 Interrupt Register IR CAN Addr 3 bit interpretation BIT SYMBOL NAME FUNCTION IR 7 BEI Bus Error Interrupt This bit is set when the CAN controller detects an error on the CAN Bus and the BEIE bit is set within the Interrupt Enable Register After a bus error interrupt event this interrupt is locked until the Error Code Capture Register is read out once IR 6 Arbitration Lost This bit is set when the CAN controller has lost arbitration Interrupt and becomes a receiver and the ALIE bit is set within the Interrupt Enable Register After an arbitration lost interrupt event this interrupt is locked until the Arbitration Lost Capture Register is read out once IR 5 Error Passive This bit is set whenever the CAN controller has reached the Inter
28. this message may also be accessed using CAN address 152 and the following bytes 4 3 2 1 0 RMC 4 RMC 3 RMC 2 RMC 1 RMC 0 CAN Address RBSA 128 gt 24 128 152 Always the Release Receive Buffer Command is given while there is at least one more message available within the FIFO RBSA is updated to the beginning of the next message On Hardware Reset this pointer is initialised to 00h Upon a Software Reset setting of Reset Mode this pointer keeps its old value but the FIFO is cleared what means that the RAM contents are not changed but the next received or transmitted message will override the currently visible message within the Receive Buffer Window The RX Buffer Start Address Register appears to the CPU as a read only memory in Operating Mode and as read write memory in Reset Mode Table 23 RX Buffer Start Address RBSA CAN address 10 i ee ee RBSA 7 RBSA 6 RBSA 5 RBSA 4 RBSA 3 RBSA 2 RBSA 1 RBSA 0 2000 Jul 26 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 5 12 ARBITRATION LOST CAPTURE ALC This register contains information about the bit position of losing arbitration The Arbitration Lost Capture Register appears to the CPU as a read only memory Reserved Bits are read as 0 Table 24 Arbitration Lost Capture ALC CAN address 11 7 6 5 4 3 2 1 0 BITNO4 BITNO3 BITNO2 BITNO1 BITNOO
29. 0 absent 2 BS Bus Status Bus On 0 reset ES Error Status ok 0 reset TS Transmit Status wait idle 0 reset RS Receive Status wait idle 0 reset Transmission Complete Status complete O reset Transmit Buffer Status released X no change Data Overrun Status absent 0 reset Receive Buffer Status empty O reset 3 Interrupt Bus Error Interrupt reset X no change 1 Arbitration Lost Interrupt reset O reset Error Passive Interrupt reset O reset Wake Up Interrupt reset O reset Data Overrun Interrupt reset O reset Error Warning Interrupt reset X nochange Transmit Interrupt reset O reset Receive Interrupt reset O reset 4 Interrupt Enable Bus Error Interrupt Enable no change X no change Arbitr Lost Interrupt Enable no change X no change Error Passive Interrupt no change X no change Wake Up Interrupt Enable no change X no change Data Overrun Interrupt Enable no change X nochange Error Warning Interrupt Enable no change X nochange Transmit Interrupt Enable no change X no change Receive Interrupt Enable no change X no change 5 Rx Interrupt Level RIL Rx Interrupt Level 00000000b X no change 6 Bus Timing 0 BTRO 7 SJW 1 Synchronization Jump Width 1 X no change X no change BTRO 6 SJW 0 Synchronization Jump Width 0 X no change X no change BTRO 5 BRP 5 Baud Rate Prescaler 5 X no change X no change BTRO 4 BRP 4 BRP 3 Baud Rate Prescaler 4 X no change X no change BTRO 3 BRP 2 Baud Rate Prescaler 3 X no change X no change BT
30. 00H PWMP1 PWM Register 1 FDH 00H PWMPO PWM Register 0 FCH 00H RTE Reset Enable EFH RP35 RP34 RP33 RP32 xxxx0000B SOADDR Serial 0 Slave Address F9H 00H SOADEN Slave Address Mask B9H 00H SP Stack Pointer 81H 07H SOBUF Serial 0 Data Buffer 99H SOPSL Prescaler Value UART FAH 00H SOPSH Prescaler Value UART FBH SPS Prescaler higher nibble Oxxx0000B 9F 9E 9D 9C 9B 9A 99 98 SOCON Serial 0 Control 98H SMO FE SMI SM2 REN TB8 RB8 TI RI 00H S1CON Serial 1Control D8H CR2 ENS1 STA STO Sl AA CRI CRO 00H S1ADR Serial 1 Address DBH SLAVE ADDRESS GC 00H S1DAT Serial 1 Data DAH 00H S1STA Serial 1 Status D9H SCA SC3 5 2 5 1 Sco 0 0 0 F8H DF DE DD DC DB DA D9 D8 STE Set Enable EEH SP35 SP34 SP33 SP32 xxxx0000B TH1 Timer High 1 8DH 00H THO Timer High 0 8CH 00H TL1 Timer Low 1 8BH 00H TLO Timer Low 0 8AH 00H TMH2 Timer High 2 EDH 00H TML2 Timer Low 2 ECH 00H 2000 Jul 26 17 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 ie SFR BIT FUNCTIONS AND ADDRESSES RESET MSB LSB TMOD Timer Mode 89H GATE MI Mo GATE CIT MI MO 00H 8F 8E 8D 8C 8B 8 89 88 TCON Timer Control 88H TFI TRI TFO TRO IE1 ITI ITO 00H TM2CON Timer 2 Control EAH T2ist T2Iso T2ER T2B0 T2P1 T2Po Tamsi 2 650 00H CF CE cc CB CA C9 C8 TM2IR Timer 2 CAN Int Flag Reg T20V CMI CTH CTIO 00H
31. 101 CODE OUT aos 011 010 001 000 24 3 44 58 Vin QUANTIZATION ERROR q LSB 5mV Vin Vdigital q 2 d e Vin q 2 i MHI055 SYMMETRICAL QUANTIZATION ERROR Fig 53 Effective Conversion Characteristic 2000 Jul 26 130 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 21 INTERRUPTS The 8xC591 has fifteen interrupt sources each of which can be assigned one of four priority levels The five interrupt sources common to the 80C51 are the external interrupts INTO and INT1 the timer 0 and timer 1 interrupts ITO and IT1 and the serial I O interrupt RI or Tl In the 8xC591 the standard serial interrupt is called SIOO The seven Timer T2 interrupts are generated by flags CTIO CTI3 CMIO CMI1 and by the logical OR of flags T2OV and T2BO Flags CTIO to CTI3 are set by input signals CTOI to CT3I The inputs INT2 to INT5 can be regarded as 4 additional external interrupts if the capture facility of Timer T2 is not used details see Timer T2 in Section 16 1 4 1 Flags CMIO to CMI1 are set when a match occurs between Timer T2 and the compare registers CMO and CM1 When an 8 bit or 16 bit overflow occurs flags T2BO and T2OV are set respectively These eight flags are not cleared by hardware and must be reset by software to avoid recurring interrupts The ADC interrupt is generated by the ADCI flag in the ADC control register ADCON This flag is set when an ADC conversion
32. 2 2 60 JC rel Jump if carry flag is set 2 2 40 JB bit rel Jump if direct bit is set 3 2 20 JNB bit rel AI JBC bit rel Jump if direct bit is set and clear bit 3 2 CINE A direct rel Compare direct to A and jump if not equal 3 2 CJNE A data rel Compare immediate to A and jump if not equal 3 2 CJNE Rr data rel Compare immediate to register and jump if not equal 3 2 B DJNZ Rr rel Decrement register and jump if not zero 2 2 D NOP No operation 1 1 00 2000 Jul 26 139 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Preliminary Specification P8xC591 Table 111 Description of the mnemonics in the Instruction set MNEMONIC DESCRIPTION Data addressing modes Rr Working register RO R7 direct 128 internal RAM locations and any special function register SFR Ri Indirect internal RAM location addressed by register RO or R1 of the actual register bank data 8 bit constant included in instruction data 16 16 bit constant included as bytes 2 and 3 of instruction bit Direct addressed bit in internal RAM or SFR addr16 16 bit destination address Used by LCALL and LUMP The branch will be anywhere within the 64 Kbytes Program Memory address space addr1 1 11 bit destination address Used by ACALL and AJMP The branch will be within the same 2 Kbytes page of Program Memory as the first byte of the following instruction rel Signed two s complement 8 bit offset byte Use
33. 5 4 3 2 1 0 7 6 5 4 s8 2 i o 7 6 5 4 3 2 1 0o 7 6 5 4 3 2 1 0 QU Un 9 5 MSB LSB MSB LSB MSB LSB MSB LSB Addr 20 AMRO Addr 21 AMRI Addr 22 AMR2 Addr 23 AMR3 7 6 5 4 3 2 1 0o 7 6 5 4 s 2 i o 7 6 5 4 3 2 1 o 7 6 5 4 3 2 1 0 fe Ego a ojnlololxslolni itololoelr TS E Nea alalalalalalala alalal amp 2515 555 5 5 88 55 a a 2 2 2 2 2 2 e 2 a r alajajalejajalejjajalalajajalala MHI015 Message Bit Acceptance Code Bit Acceptance Mask Bit 1 accepted 0 not accepted DBx y Data Byte x Bit y Fig 15 Single Filter Configuration receiving Standard Frame Messages 2000 Jul 26 51 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 Single Filter Extended Frame least significant bits of AMR3 and AGR3 are not used In order to keep compatible with future products these bits should be programmed to be don t care by setting AMR3 1 and AMR3 0 to 1 If the Extended Frame Format is selected the complete Identifier including the RTR bit is used for acceptance filtering For a successful reception of a message all single bit comparisons have to signal acceptance Note that the 2 MSB LSB MSB LSB MSB LSB MSB LSB Addr 16 ACRO Addr 17 ACRI Addr 18 ACR2 Addr 19 ACR3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2
34. AA bits in S1CON and the serial clock frequency for master modes is defined by loading CRO and CR1 in S1CON The master routines must be started in the main program The SIO1 hardware now begins checking the 12C bus for its own slave address and general call If the general call or the own slave address is detected an interrupt is requested and S1STA is loaded with the appropriate state information The following text describes a fast method of branching to the appropriate service routine 2000 Jul 26 Preliminary Specification P8xC591 15 3 2 SIO1 INTERRUPT ROUTINE When the SIO 1 interrupt is entered the PSW is first pushed on the stack Then S1STA and HADD loaded with the high order address byte of the 26 service routines by the initialization routine are pushed on to the stack S1STA contains a status code which is the lower byte of one of the 26 service routines The next instruction is RET which is the return from subroutine instruction When this instruction is executed the high and low order address bytes are popped from stack and loaded into the program counter The next instruction to be executed is the first instruction of the state service routine Seven bytes of program code which execute in eight machine cycles are required to branch to one of the 26 state service routines SI PUSH PSW Save PSW PUSH S1STA Push status code low order address byte PUSH HADD Push high order address byte RET Jump to state serv
35. E2 E3 MOVX A DPTR Move external RAM 16 bit address to A 1 2 EO MOVX Ri A Move A to external RAM 8 bit address 1 2 F2 F3 MOVX DPTR A Move A to external RAM 16 bit address 1 2 FO PUSH direct Push direct byte onto stack 2 2 direct Pop direct byte from stack 2 2 DO XCH A Rr Exchange register with A 1 1 XCH A direct Exchange direct byte with A 2 1 C5 XCH A Ri Exchange indirect RAM with A 1 1 C6 C7 XCHD A Ri Exchange LOW order digit indirect RAM with A 1 1 D6 D7 Note 1 MOV A ACC is not permitted 2000 Jul 26 138 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Preliminary Specification Table 110 Instruction set description Boolean variable manipulation Program and machine control MNEMONIC DESCRIPTION Boolean variable manipulation BYTES CYCLES P8xC591 OPCODE HEX CLR Clear carry flag 1 1 C3 SETB Set carry flag 1 1 D3 CPL Complement carry flag 1 1 B3 ANL C bit AND direct bit to carry flag 2 2 82 ANL C bit ORL Obi ORL C bit OR complement of direct bit to carry flag 2 2 AO MOV MOV bit C Move carry flag to direct bit 2 2 92 Program and machine control ACALL adarii Absolute subroutine call 2 2 1 LCALL addri6 Long subroutine call 3 2 12 RETI Return from interrupt 1 2 32 AJMP addrit LIMP addr16 Long jump 3 2 02 UMP GADPTR JZ rel Jump if A is zero
36. INITBASE1 sect ibase1 base 0xa0 INITBASE1 mov psw SELRB3 mov r1 MTD mov r0 MRD mov BACKUP NUMBYTMST Save initial value pop psw reti JAKAKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKAKKKKKKKKKKKKKKKKKAKKKAKKKKAKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKK MASTER TRANSMITTER STATE SERVICE ROUTINES JAKAKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKK ISTATE 18 Previous state was STATE 8 or STATE 10 SLA W have been transmitted ACK been received ACTION First DATA is transmitted ACK bit is received letta elica de iene sido dorsi ila e lino li i lio dc sect mts18 base 0 118 mov psw SELRB3 mov S1DAT r1 ajmp CON STATE 20 SLA VV have been transmitted NOT ACK has been received ACTION Transmit STOP condition sect mts20 base 0x120 mov S1CON ENS1_NOTSTA_STO_NOTSI_AA_CRO set STO clr SI pop psw reti 106 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 LOC OBJ 0128 D55285 012B 75D8D5 012E 01B9 00BO 750018 00B3 87DA 00B5 75D8C5 00B8 09 00B9 DODO 00BB 32 0130 750805 0133 DODO 0135 32 0138 75D8E5 013B 855352 013E 01B9 0140 75D8C5 0143 DODO 32 2000 Jul 26 SOURCE STATE 28 DATA of S1DAT have been transmitted ACK received ACTION If Transmitted DATA is last DATA then transmit a STOP condition else trans
37. Mask and Code Registers is possible 4 B3F1EN Bank 3 Filter 1 Enable 1 enabled 0 disabled Filter 1 of Bank 3 is enabled no write access to corresponding Mask and Code Registers is possible Filter 1 of Bank 3 is disabled changing of corresponding Mask and Code Registers is possible ACFEN 3 B2F2EN Bank 2 Filter 2 Enable 1 enabled 0 disabled Filter 2 of Bank 2 is enabled no write access to corresponding Mask and Code Registers is possible Filter 2 of Bank 2 is disabled changing of corresponding Mask and Code Registers is possible ACFEN 2 B2F1EN ACFEN 1 BIF2EN ACFEN 0 B1F1EN Bank 2 Filter 1 Enable Bank 1 Filter 2 Enable Bank 1 Filter 1 Enable 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled Filter 1 of Bank 2 is enabled no write access to corresponding Mask and Code Registers is possible Filter 1 of Bank 2 is disabled changing of corresponding Mask and Code Registers is possible Filter 2 of Bank 1 is enabled no write access to corresponding Mask and Code Registers is possible Filter 2 of Bank 1 is disabled changing of corresponding Mask and Code Registers is possible Filter 1 of Bank 1 is enabled no write access to corresponding Mask and Code Registers is possible Filter 1 of Bank 1 is disabled changing of corresponding Mask and Code Registers is possible Note if the Single Filter Mode is selected f
38. Mode 1 is a 9 bit register it flags the RX Control block to do one last shift load SOBUF and RB8 and set RI The signal to load SOBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0 and 2 Either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SOBUF and RI is activated At this time whether the above conditions are met or not the unit goes back to looking for a 1 to 0 transition in RxD More About Modes 2 and 3 Eleven bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9 data bit and a stop bit 1 On transmit the 9 data bit TB8 can be assigned the values of 0 or 1 On receive the 9the data bit goes into RB8 in SCON The baud rate is programmable to either 4 or 132 the oscillator frequency in Mode 2 Mode 3 may have a variable baud rate generated from Timer 1 Figure 25 show a functional diagram of the serial port in Modes 2 and 3 The receive portion is exactly the same as in Mode 1 The transmit portion differs from Mode 1 only in the 9 bit of the transmit shift register Transmission is initiated by any instruction that uses SOBUF as a destination register The write to SOBUF signal al
39. Port 0 is HIGH Impedance Tri State AD7 to ADO Multiplexed Low order address and Data bus for external memory During these accesses internal pull ups are activated Port 0 can sink source up to 8 LSTTL inputs Analog to Digital Conversion Reference Resistor High end AVss 2000 Jul 26 39 1 Analog ground Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Preliminary Specification P8xC591 PIN SYMBOL DESCRIPTION QFP44 PLCC44 P1 0 to P1 4 40 10 44 2106 Port 1 8 bit VO port vvith a user configurable output type The operation of P1 5 to P1 7 1t03 7t09 Port 1 pins as inputs or outputs depends upon the port configuration selected Each port pin is configured independently Port 1 also provides various special functions as described below P1 0 40 2 RXDC CAN Receiver input line P1 1 41 3 TXDC CAN Transmit output line During reset Port P1 0 and P1 1 will be asynchronously driven resistive HIGH P1 2 to P1 7 is High Impedance Tri state P1 2 to P1 4 42 to 44 4t0 6 CTOI INT2 CT1I INT3 CT2I INT4 T2 Capture timer inputs or External Interrupt inputs ADCO to ADC2 Alternate function Input channels to ADC P1 5 to P1 7 1t03 7t09 ADC3 to ADC5 Input channels to ADC P1 5 1 7 CT3I INT5 T2 Capture timer input or External Interrupt inputs P1 6 2 8 SCL Serial port clock line 1 C Push pull or pseudo bidrectional modes is not implemented at I C P1
40. R W will be logic 0 and we say that a W is transmitted Thus the first byte transmitted is SLA W Serial data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to Modes of Operation indicate the beginning and the end of a serial transfer 2000 Jul 26 74 Preliminary Specification P8xC591 2 Master Receiver Mode The first byte transmitted contains the slave address of the transmitting device 7 bits and the data direction bit In this case the data direction bit R W will be logic 1 and we say that an R is transmitted Thus the first byte transmitted is SLA R Serial data is received via P1 7 SDA while P1 6 SCL outputs the serial clock Serial data is received 8 bits at a time After each byte is received an acknowledge bit is transmitted START and STOP conditions are output to indicate the beginning and end of a serial transfer Slave Receiver Mode Serial data and the serial clock are received through P1 7 SDA and P1 6 SCL After each byte is received an acknowledge bit is transmitted START and STOP conditions are recognized as the beginning and end of a serial transfer Address recognition is performed by hardware after reception of the slave address and direction bit Slave Transmitter Mode The first byte is received and handled as in the slave receiver mode However in this mode the direction bit will indicate that
41. Rate 11 bits are transmitted through TxD or received through RxD start bit 0 8 data bits LSB first a programmable 9 data bit and a stop bit 1 On Transmit the 9 data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On receive the 9 data bit goes into RB8 in Special Function Register SCON while the stop bit ignored The baud rate is programmable to either 146 or the oscillator frequency Mode 1 Mode 2 2000 Jul 26 60 Preliminary Specification P8xC591 Mode 3 9 bit UART Variable Baud Rate 11 bits are transmitted through TxD or received through RxD start bit 0 8 data bits LSB first a programmable 9 data bit and a stop bit 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable In all four modes transmission is initiated by any instruction that uses SOBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 14 1 Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received The 9 one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8
42. X 0 0 Data byte will be received and NOT ACK with General Call DATA will be returned byte has been received AGK has been ret rn d read data byte X 0 0 Data byte will be received and ACK will be returned 2000 Jul 26 93 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Preliminary Specification P8xC591 STATUS CODE SISTA STATUS OF THE I C BUS AND SIO1 HARDWARE APPLICATION SOFTWARE RESPONSE TO S1CON TO FROM S1DAT STA STO SI AA NEXT ACTION TAKEN BY SIO1 HARDWARE 98H Previously addressed with General Call DATA byte has been received NOT ACK has been returned Read data byte or 0 0 0 read data byte or 0 0 0 read data byte or 1 0 0 read data byte 1 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if STADR 0 logic 1 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if S1ADR 0 logic 1 A START condition will be transmitted when the bus becomes free AOH A STOP condition or repeated START condition has been received while still addressed as SLV REC or SLV TRX 2000 Jul 26
43. a certain bit located within the Acceptance Filter Enable Register This allows to change the Acceptance Filter Contents on the fly during normal operation if the corresponding filter is disabled previously A disabled Acceptance Filter does not allow passing of messages to the receive buffer If all Acceptance Filters are disabled default after hardware reset no messages will pass to the receive buffer at all Table 33 Acceptance Filter Enable Register ACF Enable CAN address 30 7 6 5 B4F2EN B4F1EN 2 Table 34 Acceptance Filter Enable Register ACF Enable 4 3 2 1 0 B3F1EN B2F2EN B2F1EN BIF2EN B1F1EN BIT SYMBOL ACFEN 7 B4F2EN ACFEN 6 B4F1EN 5 B3F2EN Bank 4 Filter 2 Enable Bank 4 Filter 1 Enable Bank 3 Filter 2 Enable VALUE 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled FUNCTION Filter 2 of Bank 4 is enabled no write access to corresponding Mask and Code Registers is possible Filter 2 of Bank 4 is disabled changing of corresponding Mask and Code Registers is possible Filter 1 of Bank 4 is enabled no write access to corresponding Mask and Code Registers is possible Filter 1 of Bank 4 is disabled changing of corresponding Mask and Code Registers is possible Filter 2 of Bank 3 is enabled no write access to corresponding Mask and Code Registers is possible Filter 2 of Bank 3 is disabled changing of corresponding
44. able to transmit a START condition The STO flag is cleared by hardware see Figure 42 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 OTHER MST CONTINUES OTHER MASTER SENDS REPEATED RETRY START CONDITION EARLIER MHI042 Fig 41 Simultaneous repeated START conditions from 2 Masters time limit STA FLAG STO FLAG SDA LINE SCL LINE MHI043 start condition Fig 42 Forces access to a busy I C bus 2000 Jul 26 98 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 15 2 15 3 IC bus obstructed by a low level on SCL and SDA An I2C bus hang up occurs if SDA or SCL is pulled LOW by an uncontrolled source If the SCL line is obstructed pulled LOW by a device on the bus no further serial transfer is possible and the SIO1 hardware cannot resolve this type of problem When this occurs the problem must be resolved by the device that is pulling the SCL bus line LOW If the SDA line is obstructed by another device on the bus e g a Slave device out of bit synchronization the problem can be solved by transmitting additional clock pulses on the SCL line see Figure 43 The SIO1 hardware transmits additional clock pulses when the STA flag is set but no START condition can be generated because the SDA line is pulled LOW while the I C bus is considered free Th
45. becoming immediately available within the Receive Buffer If there is no other message available the Receive Interrupt bit is reset The Receive Interrupt is also reset in case there is no high priority message available within the FIFO see acceptance filter description and the available message bytes are equal to or less to the specified value within the Receive Interrupt Level Register If the RRB command is given it will take at least 2 internal clock cycles before a new receive interrupt is generated and Rx Buffer Start Address is updated 4 The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission e g to transmit a more urgent message before A transmission already in progress is not stopped In order to see if the original message had been either transmitted successfully or aborted the Transmission Complete Status bit should be checked This should be done after the Transmit Buffer Status bit has been set 1 or a Transmit Interrupt has been generated 2000 Jul 26 35 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 5 If the Transmission Request or the Self Reception Request bit was set 1 in a previous command it cannot be cancelled by resetting the bits The requested transmission may only be cancelled by setting the Abort Transmission bits 6 Setting the command bits CMR 0 and CMR 1 simultaneously
46. bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Automatic address recognition is shown in Figure 29 The 8 bit mode is called Mode 1 In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address 7 6 5 4 3 2 1 0 SMO FE SM1 SM2 REN TB8 RB8 TI RI Table 50 Description of SOCON bits BIT SYMBOL DESCRIPTION 7 FE Framing Error bit This bit is set by the receiver when an invalid stop bit is detected The FE bit is not cleared by valid frames but should be cleared by software SMO Serial Port Mode Bit 0 SMODO must 0 to access bit SMO see Table 46 6 SMI These bits are used to select the serial port mode see Table 46 5 SM2 Enables the Automatic Address Recognition feature in Modes 2 and 3 If SM2 1 then RI will not be set unless the received 9 data bit RB8 is a logic 1 indicating an address and the received byte is a Given or Broadcast Address In Mode 1 if SM2 1 then RI will not be activated unless a valid stop bit was not received and the received byte is a Given or Broadcast Address In Mode 0 SM2 should be a logic 0 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception 3 TB8 The 9 data bit that will be transmitted in Modes 2 and
47. chip resistor RST RESET CIRCUITRY overflow timer T3 MHI008 Fig 8 On Chip Reset Configuration 8 591 MHI009 Fig 9 Power on Reset Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 11 LOW POWER MODES 11 1 Stop Clock Mode The static design enables the clock speed to be reduced down to 0 MHz stopped When the oscillator is stopped the RAM and Special Function Registers retain their values This mode allows step by step utilization and permits reduced system power consumption by lowering the clock frequency down to any value For lowest power consumption the Power down mode is suggested 11 2 Idle Mode In the Idle mode see Table 7 the CPU puts itself to sleep while all of the on chip peripherals stay active The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the Idle mode is activated The CPU contents the on chip RAM and all of the special function registers remain intact during this mode The Idle mode can be terminated either by any enabled interrupt at which time the process is picked up at the interrupt service routine and continued or by a hardware reset which starts the processor in the same manner as a Power on reset Preliminary Specification P8xC591 11 3 Power down Mode To save even more power a Power down mode see Table 7 can be invoked by software In this
48. difficult for the programmer to ensure that the user program always reloads the watchdog timer within the watchdog interval and thus it becomes more difficult to implement watchdog operation 2000 Jul 26 Preliminary Specification P8xC591 The programmer must now partition the software in such a way that reloading of the watchdog is carried out in accordance with the above requirements The programmer must determine in execution times of all software modules The effect of possible conditional branches subroutines external and internal interrupts must all be taken into account Since it may be very difficult to evaluate the execution times of some sections of code the programmer should use worst case estimations In any event the programmer must make sure that the watchdog is not activated during normal operation The watchdog timer is reloaded in two stages in order to prevent erroneous software from reloading the watchdog First PCON 4 WLE must be set The T3 may be loaded When T3 is loaded PCON 4 WLE is automatically reset T3 cannot be loaded if PCON 4 WLE is reset Reload code may be put in a subroutine as it is called frequently Since Timer T3 is an up counter a reload value of OOH gives the maximum watchdog interval and a reload value of OFFH gives the minimum watchdog interval In the Idle mode the watchdog circuitry remains active When watchdog operation is implemented the Power down mode cannot be used since
49. dual The Single Acceptance Filter option is enabled for filter bank 3 gt one long filter is active The Dual Acceptance Filter option is enabled for filter bank 3 gt two short filters are active Acceptance Filter Bank 2 is used for Extended Frame Messages only Standard Frame Messages are ignored Acceptance Filter Bank 2 is used for Standard Frame Messages only Extended Frame Messages are ignored ACFMOD 2 AMODEB2 Acceptance Filter Mode Bank 2 The Single Acceptance Filter option is enabled for filter bank 2 gt one long filter is active The Dual Acceptance Filter option is enabled for filter bank 2 gt two short filters are active ACFMOD 1 MFORMATB1 Acceptance Filter Format Bank 1 Acceptance Filter Bank 1 is used for Extended Frame Messages only Standard Frame Messages are ignored Acceptance Filter Bank 1 is used for Standard Frame Messages only Extended Frame Messages are ignored ACFMOD O AMODEB1 Acceptance Filter 1 single The Single Acceptance Filter option is enabled for filter Mode Bank 1 bank 1 gt one long filter is active 0 dual The Dual Acceptance Filter option is enabled for filter bank 1 gt two short filters are active 2000 Jul 26 48 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 5 17 2 Acceptance Filter Enable Register Each defined Acceptance Filter is enabled or disabled by
50. in the master receiver mode Loss of arbitration in this mode can only occur while SIO1 is returning a not acknowledge logic 1 to the bus Arbitration is lost when another device on the bus pulls this signal LOW Since this can occur only at the end of a serial byte SIO1 generates no further clock pulses Figure 33 shows the arbitration procedure SCL 1 2 3 4 8 9 1 Another device transmits identical serial data 2 Another device overrules a logic 1 dotted line transmitted by SIO1 master by pulling the SDA line low Arbitration is lost and SIO1 enters the slave receiver mode 3 SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted SIO1 will not generate clock pulses for the next byte Data on SDA originates from the new master once it has won arbitration Fig 33 Arbitration Procedure 2000 Jul 26 78 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller with CAN controller P8xC591 SCL duration the wait state until the SCL line is released 15 2 6 SERIAL CLOCK GENERATOR This programmable clock pulse generator provides the SCL clock pulses when SIO1 is in the master transmitter or master receiver mode It is switched off when SIO1 is in a slave mode The programmable output clock frequencies are fci 120 fc 9600 and the Timer 1 overflow rate divided by eight The output clo
51. individually enabled interrupt will be accepted EAD Enable ADC interrupt ES1 Enable SIO1 12C interrupt ESO Enable SIOO UART interrupt ET1 Enable Timer 1 interrupt ETO Enable Timer 0 interrupt 21 2 2 INTERRUPT ENABLE REGISTER 1 IEN1 Logic 0 interrupt disabled logic 1 interrupt enabled Table 95 Interrupt Enable Register 1 address E8H 7 6 5 4 3 2 1 0 ET2 ECAN ECMI ECMO ECT3 ECT2 ECT1 ECTO Table 96 Description of IEN1 bits BIT SYMBOL DESCRIPTION ET2 Enable T2 overflow interrupt s Enable CAN interrupt Enable T2 comparator 1 interrupt Enable T2 comparator 0 interrupt Enable T2 capture register 3 interrupt Enable T2 capture register 2 interrupt Enable T2 capture register 1 interrupt ojaj jnijcocjkjajojn Enable T2 capture register 0 interrupt 2000 Jul 26 132 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 21 2 3 INTERRUPT PRIORITY REGISTER 0 IPO Logic 0 low priority logic 1 high priority Table 97 Interrupt Priority Register 0 address B8H a aa e a e e e e PAD PS1 Table 98 Description of IPO bits BIT SYMBOL DESCRIPTION 7 Reserved for future use 6 PAD ADC interrupt priority level 5 PS1 SIO1 12C interrupt priority level 4 PSO 100 UART interrupt priority level 3 PT1 Ti
52. is possible only if the Reset Mode was entered previously An Error Status change Status Register and an Error Warning Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again 12 5 15 RX ERROR COUNTER REGISTER RXERR The RX Error Counter Register reflects the current value of the Receive Error Counter After hardware reset this register is initialised to O In Operating Mode this register appears to the CPU as a read only memory A write access to this register is possible only in Reset Mode If a Bus Off event occurs the RX Error counter is initialised to 0 As long as Bus Off is valid writing to this register has no effect Table 29 RX Error Counter Register RXERR CAN address 14 7 6 5 4 3 2 1 0 RXERR 7 RXERR 6 RXERR 5 RXERR 4 RXERR 3 RXERR 2 RXERR 1 RXERR O Note that a CPU forced content change of the RX Error Counter is possible only if the Reset Mode was entered previously An Error Status change Status Register an Error Warning or an Error Passive Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again 2000 Jul 26 45 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 12 5 16 TX ERROR COUNTER REGISTER TXERR The TX Error Counter Register reflects the current value of the Transmit Error Counter In Operating Mode this register appears to the CPU as a read only memory A wr
53. left of the MSB and all positions to the left of that contain zeros The condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI This occurs at the 10th divide by 16 rollover after write to SOBUF Reception is initiated by a detected 1 to 0 transition at RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1 FFH is written into the input shift register Resetting the divide by 16 counter aligns its rollovers with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16th5 At the 71 st and 9 counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 10 0 transition This is to provide rejection of false start bits If the start bit proves valid it shifted into the input shift register and reception of the rest of the frame will proceed Philips Semiconductors Single chip 8 bit microcontroller with CAN controller As data bits come in from the right 1s shift out to the left When the start bit arrives at the left most position in the shift register which in
54. multiple functions The I O s are held HIGH during reset asynchronous before oscillator is running Ports 0 1 2 and 3 perform the following alternative functions Port 0 is the same as in the 80C51 After reset the Port Special Function Register is set to FFh as known from other 80C51 derivatives Port 0 also provides the multiplexed low order address and data bus used for expanding the P8xC591 with standard memories and peripherals Port 1 supports several alternative functionalities For this reason it has different I O stages Note port P1 0 and P1 1 are Driven High and P1 2 to P1 7 are High Impedance Tri state after reset Port 2 is the same as in the 80C51 After reset the Port Special Function Register is set to FFh as known from other 80C51 derivatives Port 2 also provides the high order address bus when the P8xC591 is expanded with external Program Memory and or external Data Memory Port 3 is the same as in the 80C51 During reset the Port 3 Special Function Register is set to FFh as known from other 80C51 derivatives 9 OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respectively of an inverting amplifier The pins can be configured for use as an on chip oscillator as shown in the logic symbol To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected There are no requirements on the duty cycle of the external clock si
55. of SM with at least one of the previously mentioned exceptions valid will result in a wake up interrupt The CAN controller will wake up if SM is set LOW wake up or there is bus activity On wake up a Wake up Interrupt is generated A sleeping CAN controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits Bus Free sequence Note that setting of SM is not possible in Reset Mode After clearing of Reset Mode setting of SM is possible first when Bus Free is detected again 3 This mode of operation forces the CAN controller to be error passive Message Transmission is not possible The Listen Only Mode can be used e g for software driven bit rate detection and hot plugging 2000 Jul 26 34 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 4 During a Hardware reset or when the Bus Status bit is set 1 Bus Off the Reset Mode bit is set 1 present After the Reset Mode bit is set 0 the CAN controller will wait for a one occurrence of Bus Free signal 11 recessive bits if the preceding reset has been caused by Hardware reset or a CPU initiated reset b 128 occurrences of Bus Free if the preceding reset has been caused by a CAN controller initiated Bus Off before re entering the Bus On mode 12 5 3 COMMAND REGISTER CMR The contents of the Command Register are used
56. software or with an external signal Conversion time for one 10 bit analog to digital conversion 25 us 12 MHz Differential non linearity DLe 1 LSB Integral non linearity ILe 2 LSB Offset error OSe 2 LSB Gain error Ge 4 Absolute voltage error Ae 3 LSB Channel to channel matching Mctc 11 LSB Crosstalk between analog inputs C lt 60 dB at 100 kHz Monotonic and no missing codes Separated analog Vssa and digital Vpp Vss supply voltages Reference voltage special pin Vretp A For information on the ADC characteristics refer to Chapter 24 2000 Jul 26 Preliminary Specification P8xC591 20 2 ADC functional description The analog input circuitry consists of an 6 input analog multiplexer and a 10 bit straight binary successive approximation ADC The A D can also be operated in 8 bit mode with faster conversion times by setting bit ADC8 AUXR1 7 The 8 bit result will be contained in the ADCH register The analog reference voltage and analog power supplies are connected via separate input pins For 10 bit accuracy the conversion takes 50 machine cycles i e 25 us at an oscillator frequency of 12 MHz For the 8 bit mode the conversion takes 24 machine cycles Input voltage swing is from 0 V to 5 V Because the internal DAC employs a ratiometric potentiometer there are no discontinouties in the converter characteristic Figure 48 shows a functional diagram of the analog input circ
57. the SDA and SCL lines and switches to the not selected receiver mode The STOP flag is cleared by the hardware 3 SI Serial Interrupt flag This flag is set and an interrupt request is generated after any of the following events occur e A START condition is generated in master mode e The own slave address has been received during AA 1 e The general call address has been received while STADR 0 and AA 1 e A data byte has been received or transmitted in master mode even if arbitration is lost e A data byte has been received or transmitted as selected slave e A STOP or START condition is received as selected slave receiver or transmitter While the SI flag is set SCL remains LOW and the serial transfer is suspended SI must be reset by software 2 AA Assert Acknowledge flag When this bit is set an acknowledge is returned after any one of the following conditions e Own slave address is received e General call address is received S1ADR 0 1 e A data byte is received while the device is programmed to be a master receiver e A data byte is received while the device is a selected slave receiver When the bit is reset no acknowledge is returned Consequently no interrupt is requested when the own address or general call address is received 1 CRI Clock rate bits 1 and 0 see Table 57 0 CRO 2000 Jul 26 81 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 15 2 12 1 ENSI th
58. the number of samples to be taken within a bit time 12 2 8 TRANSMIT MANAGEMENT LOGIC TML The Transmit Management Logic provides the driver signals for the push pull CAN TX transistor stage Depending on the programmable output driver configuration the external transistors are switched on or off Additionally a short circuit protection and the asynchronous float on hardware reset is performed here Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 12 3 Communication between PeliCAN controller and CPU A 80C51 CPU Interface connects the PeliCAN to the internal bus of an 80C51 microcontroller Special Function Registers allows a smart and fast access to the PeliCAN registers and RAM area Because of the big address range to be supported an indirect pointer based addressing is Preliminary Specification P8xC591 included allowing a fast register access with address autoincrement mode This reduces the needed number of Special Function Registers to an amount of 5 e Five Special Function Registers SFRs e Register address generation in auto increment mode e Access to the complete address range of the PeliCAN 12 3 1 SPECIAL FUNCTION REGISTERS Via the five Special Function Registers CANADR CANDAT CANMOD CANSTA and CANCON the CPU has access to the PeliCAN Block Note that CANCON and CANSTA have different registers mapped depending on the direction of the access 2000 Jul 26 INTERFA
59. 0 High impedance 1 1 Open drain Program Store Enable output read strobe to the external Program Memory via Ports 0 and 2 Is activated twice each machine cycle during fetches from external Program Memory When executing out of external Program Memory two activations of PSEN are skipped during each access to external Data Memory PSEN is not activated remains HIGH during no fetches from external Program Memory PSEN can sink source 8 LSTTL inputs It can drive CMOS inputs without external pull ups Address Latch Enable output Latches the low byte of the address during access of external memory in normal operation It is activated every six oscillator periods except during an external Data Memory access ALE can sink source 8 LSTTL inputs It can drive CMOS inputs without an external pull up To prohibit the toggling of ALE pin RFI noise reduction the bit AO SFR AUXR 0 must be set by software see Table 4 PROG the programming pulse input alternative function for the P87C591 External Access input If during reset EA is held at a TTL level HIGH the CPU executes out of the internal Program Memory If during reset EA is held at a TTL level LOW the CPU executes out of external Program Memory via Port 0 and Port 2 EA is not allowed to float EA is latched during reset and don t care after reset Vpp the programming supply voltage alternative function for the P87C591 Port 0 8 bit open drain bidirectional I O port During reset
60. 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first send out an address byte which indentifies the target slave An address byte differs from a data byte in that the 9 bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that weren t being addressed leave their SM2s set and go on about their business ignoring the coming data bytes SM2 has no effect in Mode 0 and in Mode 1 can be used to check the validity of the stop bit In a Mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received 14 2 Serial Port Control Register The serial port control and status register is the Special Function Register SCON shown in Table 38 40 and 41 This register contains not only the mode selection bits but also the 9 data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits TI and RI SOBUF is the receive and transmit buffer of serial interface Writing to SOBUF loads the transmit register and initiates transmis
61. 1 0 7 6 5 4 3 2 1 0 unused MSB LSB MSB LSB MSB LSB MSB LSB Addr 20 AMRO Addr 21 AMR1 Addr 22 AMR2 Addr 23 AMR3 7 6 5 4 312 1 7 6 5 4 312 1 7 6 5 4 312 1 0 7 6 5 4 3 2 1 0 E tr Message Bit Acceptance Code Bit MHIO16 Acceptance Mask Bit ID 28 lt ID 21 o ID 20 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 19 ID 18 ID 17 ID 16 ID 15 ID 14 ee TN 0 12 10 11 10 10 10 9 ID 8 ID 7 ID 6 ID 5 n KON D 4 ID 3 ID 2 ID 1 ID 0 1 accepted 0 not accepted Fig 16 Single Filter Configuration receiving Extended Frame Messages 2000 Jul 26 52 Philips Semiconductors Single chip 8 bit microcontroller vvith GAN controller 12 5 17 5 Dual Filter Configuration In this filter configuration two short filters could be defined A received message is compared with both filters to decide whether this message should be copied into the Receive Buffer or not If at least one of the filters signals an acceptance the received message becomes valid The bit correspondences between the filter bytes and the message bytes depends on the currently received Frame Format Preliminary Specification P8xC591 Dual Filter Standard Frame If the Standard Frame Format is selected the tw
62. 128 occurrences of the Bus Free signal If the Reset Mode is entered again before the end of Bus Off recovery TXERR gt 0 Bus Off keeps active and TXERR is frozen Table 30 TX Error Counter Register TXERR CAN address 15 7 TXERR 7 TXERR 6 TXERR 5 TXERR 4 TXERR 3 TXERR 2 TXERR 1 TXERR O 12 5 17 ACCEPTANCE FILTER With the help of the Acceptance Filter the CAN controller is able to allow passing of received messages to the RXFIFO only when the identifier bits and the Frame Type of the received message are equal to the predefined ones within the Acceptance Filter Registers If at least one filter matches the message is copied to the receive FIFO The Acceptance Filter is defined by the Acceptance Code Registers ACRn and the Acceptance Mask Registers AMRn Within the Acceptance Code Registers the bit patterns of messages to be received are defined The corresponding Acceptance Mask Registers allow defining certain bit positions to be don t care 2000 Jul 26 The PeliCAN is designed to support four of so called Acceptance Filter Banks Each bank has the functionality known from the SJA1000 with the extension that a filter change is possible on the fly Additionally the used Frame Format of each filter bank is programmable now Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 ACCEPTANCE FILTER MODE REGISTER MFORMATB4 AMODEB4 MFORMA
63. 14 3 Slave Receiver Mode In the slave receiver mode a number of data bytes are received from a master transmitter see Figure 39 To initiate the slave receiver mode S1ADR and S1CON must be loaded as in Table 59 2000 Jul 26 bit rate The upper 7 bits are the address to which SIO1 will respond when addressed by a master If the LSB GC is set SIO1 will respond to the general call address 00H otherwise it ignores the general call address CRO CR1 and CR2 do not affect SIO1 in the slave mode ENS1 must be set to logic 1 to enable SIO1 The AA bit must be set to enable SIO1 to acknowledge its own slave address or the general call address STA STO and SI must be reset When S1ADR and S1CON have been initialized SIO1 waits until it is addressed by its own slave address followed by the data direction bit which must be 0 W for SIO1 to operate in the slave receiver mode After its own slave address and the W bit have been received the serial interrupt flag I is set and a valid status code can be read from S1STA This status code is used to vector to an interrupt service routine and the appropriate action to be taken for each of these status codes is detailed in Table 63 The slave receiver mode may also be entered if arbitration is lost while SIO1 is in the master mode see status 68H and 78H If the AA bit is reset during a transfer SIO1 will return a not acknowledge logic 1 to SDA after the next received data
64. 165 ns tAVDV address to valid data in 210 tLLWL ALE LOW to RD or WR LOW 75 175 1 5 tei 50 1 5 terk t 50 ns tavwL address valid to RD or WR LOW 92 2 tok 75 tavwx data valid to WR transition 12 0 5 tci k 30 twHax data hold after WR 6 0 5 tok 25 ns tavwH data valid time WR HIGH 162 3 5 tek 130 ns RD LOW to address float 0 ns 17 6 ns tWHLH RD or WR HIGH to ALE HIGH 7 0 5 tcrgk 25 0 5 tcrg 25 External Clock see Fig 58 high time 37 5 45 8 0 45 0 55 tcHCL fall time S low time 37 5 45 8 0 45 x 0 55 ns rise time 20 20 ns 20 20 5 2000 Jul 26 146 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 MHz CLOCK VARIABLE CLOCK UNIT SYMBOL PARAMETER MIN Max MIN max UART Timing Shift Register Mode see Fig 59 6 tok tavxH output data setup to clock rising edge 284 133 ns input data hold after clock rising edge ns txHDV clock rising edge to input data valid Note 1 Partsa guaranteed to operate down to 0 Hz Table 112 2C bus interface timing AII values referred to Vi min and Vit max levels see Fig 61 SYMBOL PARAMETER OUTPUT tHD STA START condition hold time 4 0 us
65. 2 decimal into CANADR and then moving byte by byte of the message to CANDAT Incrementing CANADR beyond FFh resets CANADR to 00h In case CANADR is below 32 decimal there is no automatic address incrementation performed CANADR keeps its value even if CANDAT is accessed for reading or writing This is to allow polling of registers in the lower address space of the PeliCAN controller 12 3 3 CANDAT REGISTER CANDAT is implemented as a read write register The Special Function Register CANDAT appears as a port to the CAN controller s internal register memory location being selected by CANADR Reading or writing CANDAT is effectively an access to that PeliCAN internal register 2000 Jul 26 PELICAN SFR ACCESS BITS CANADR Read CANA7 CANA6 4 CANA3 CANA2 Write CANDAT Read CAND4 CAND3 CAND2 Write CANMOD SM STM Write CANSTA Read RS TBS Write EIE CANCON Read El Write 28 which is selected by CANADR CANDAT is implemented as a read write register Note that any access to this register automatically increments CANADR if the current address within CANADR is above or equal to 32 decimal 12 3 4 CANMOD With a read or write access to CANMOD the Mode Register of the PeliCAN is accessed directly The Mode register is located at address 00h within the PeliCAN Block 12 3 5 CANSTA The CANSTA SFR provides a direct access to the Status Register of the PeliCAN as well as to
66. 2C bus configuration is shown in Figure 30 and Figure 31 shows how a data transfer is accomplished on the bus Depending on the state of the direction bit R W two types of data transfers are possible on the I C bus 1 Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the I C bus will not be released 15 1 The on chip SIO1 logic may operate in the following four modes 1 Master Transmitter Mode Serial data output through P1 7 SDA while P1 6 SCL outputs the serial clock The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this case the data direction bit
67. 3 Set or clear by software as desired 2 RB8 In modes 2 and 3 the 9 data bit that was received In Mode 1 if SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used 1 TI Transmit Interrupt flag Set by hardware at the end of the 8 bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software 0 RI Receive Interrupt flag Set by hardware at the end of the 8 bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see SM2 Must be cleared by software 2000 Jul 26 71 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 Set FE BIT if STOP BIT is 0 FRAMING ERROR SMO to UART MODE CONTROL suoni 0 SOCON 7 SMO 1 SOCON 7 FE MHIO29 Fig 28 UART Framing Error Detection SK E EO UP RECEIVED ADDRESS DO TO D7 PROGRAMMED ADDRESS COMPARATOR PRETE In UART Mode 2 or Mode 3 and SM2 1 Interrupt if REN 1 RB8 1 and Received Address Programmed Address when own address received clear SM2 to receive data bytes t when all data bytes have been received set SM to wait for next address Fig 29 UART Multiprocessor Communication Automatic Address Recognition 2000 Jul 26 72 Philips Semiconductors Single chip 8 bit m
68. 4 X no change ACFMOD 6 AMODEB4 Accept Filt Mode Bank Message X no change ACFMOD 5 MFORMATB3 Format Bank3 X nochange ACFMOD 4 AMODEB3 Accept Filt Mode Bank3 X no change ACFMOD 3 MFORMATB2 Message Format Bank2 X no change ACFMOD 2 AMODEB2 Accept Filt Mode Banka X no change ACFMOD 1 MFORMATB1 Message Format Bank1 X no change ACFMOD 0 AMODEB1 Accept Filt Mode Bank1 X nochange 30 ACF Enable ACFEN 7 B4F2EN Bank 4 Filter 2 Enable X no change X no change ACFEN 6 B4F1EN Bank 4 Filter 1 Enable X no change X no change ACFEN 5 B3F2EN Bank 3 Filter 2 Enable X no change X no change ACFEN 4 B3F1EN Bank 3 Filter 1 Enable X no change X no change ACFEN 3 B2F2EN Bank 2 Filter 2 Enable X no change X no change ACFEN 2 B2F1EN Bank 2 Filter 1 Enable X no change X no change ACFEN 1 B1F2EN Bank 1 Filter 2 Enable X no change X no change 0 B1F1EN Bank 1 Filter 1 Enable X nochange X nochange 31 ACF Priority ACFPRIO 7 B4F2PRIO Bank 4 Filter 2 Priority X no change X nochange ACFPRIO 6 B4F1PRIO Bank 4 Filter 1 Priority X no change X no change ACFPRIO 5 B3F2PRIO Bank 3 Filter 2 Priority X no change X no change ACFPRIO 4 B3F1PRIO Bank 3 Filter 1 Priority X nochange X no change ACFPRIO 3 B2F2PRIO Bank 2 Filter 2 Priority X nochange X no change ACFPRIO 2 B2F1PRIO Bank 2 Filter 1 Priority X nochange X no change ACFPRIO 1 B1F2PRIO Bank 1 Filter 2 Priority X no change X no change ACFPRIO 0 B1F1PRIO Bank 1 Filter 1 Priority X n
69. 50 0 48 x 256 reload value Timer 1 0 lt 254 0 lt 253 0 lt 251 Reload value Timer 1 in Mode 2 Note 1 These frequencies exceed the upper limit of 100 kHz of the standard I C bus specification 15 2 14 MORE INFORMATION ON SIO1 OPERATING MODES The four operating modes are Master Transmitter Master Receiver e Slave Receiver e Slave Transmitter Data transfers in each mode of operation are shown in Figures 37 to 40 These figures contain the following abbreviations Abbreviation Explanation S Start condition SLA 7 bit slave address R Read bit high level at SDA W Write bit low level at SDA A Acknowledge bit low level at SDA A Not acknowledge bit high level at SDA Data 8 bit data byte P Stop condition 2000 Jul 26 85 In Figures 37 to 40 circles are used to indicate when the serial interrupt flag is set The numbers in the circles show the status code held in the S1STA register At these points a service routine must be executed to continue or complete the serial transfer These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software When a serial interrupt routine is entered the status code in SISTA is used to branch to the appropriate service routine For each status code the required software action and details of the following serial transfer are given in Tables 61 to 65 15 2 14 1 Master Transmitter Mode In t
70. 7 3 9 SDA Serial data clock line I2C Push pull or pseudo bidrectional modes is not implemented at 12C Port 1 has four modes selected on a per bit basis by writing to the P1M1 and P1M2 registers as follows P1M1 x P1M2 x Mode Description 0 0 Pseudo bidirectional standard c51 configuration default 0 1 9 1 0 Push Pull 2 1 1 High impedance Open drain Port 1 is also used to input the lovver order address byte during EPROM programming and verification AO is on P1 0 etc PWMO 6 12 Pulse Width Modulation Output O PWM1 28 34 Pulse Width Modulation Output 1 Notes 1 Toavoid latch up effect as power on the voltage on any pin at any time must not be higher or lower than Vpp 40 5 V or Vss 0 5 2 Not implemented for P1 6 and P1 7 2000 Jul 26 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 7 MEMORY ORGANIZATION The Central Processing Unit CPU manipulates operands in three memory spaces as follows see Fig 5 e 16 Kbytes internal resp 64 Kbytes external Program Memory e 512 bytes internal Data Memory Main and Auxiliary RAM e up to 64 Kbytes external Data Memory with 256 bytes residing in the internal Auxiliary RAM 64K 64K EXTERNAL 16384 fM 16383 OVERLAPPED SPACE b 256 INTERNAL EXTERNAL ER E INDIRECT ONLY SFRs AUXILIARY DIRECT AND EXTRAM 0 INDIRECT 0 MAIN RAM V J V 7 WY v PROGRAM MEMORY INTERNAL DATA MEMORY EXTERNAL MHIO05 DAT
71. A MEMORY Fig 5 Memory map and address space with EXTRAM 0 2000 Jul 26 12 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 7 1 Program Memory The P8xC591 contains 16 Kbytes of on chip Program Memory which can be extended to 64 Kbytes with external memories When EA pin is held HIGH the P8xC591 fetches instructions from internal ROM unless the address exceeds 3FFFh Locations 4000h to FFFFh are fetched from external Program Memory When the EA pin is held LOW all instruction fetches are from external memory The EA pin is latched during reset and is don t care after reset Both for the ROM and EPROM version of the P8xC591 precautions are implemented to protect the device against illegal Program Memory code reading 7 2 Addressing The P8xC591 has five methods for addressing the Program and Data memory e Register e Direct e Register Indirect e Immediate e Base Register plus Index Register Indirect For more details about Addressing modes please refer to Section 22 1 Addressing Modes 7 3 Expanded Data RAM addressing The P8xC591 has internal data memory that is mapped into four separate segments the lower 128 bytes of RAM upper 128 bytes of RAM 128 bytes Special Function Register SFR and 256 bytes Auxiliary RAM AUX RAM as shown in Figure 5 The four segments are 1 The Lower 128 bytes of RAM addresses 00H to 7FH are directly and indirectly addres
72. AM Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 Table 2 AUX RAM Page Register address 8EH 7 6 3 2 1 0 LVADC EXTRAM AO Table 3 Description of AUX RAM bits BIT SYMBOL FUNCTION 7t03 Reserved for future use see Note 1 2 LVADC Enable A D low voltage operation LVADC Operating Mode 0 Turns off A D charge pump 1 Turns on A D charge pump Required for operation below 4 V 1 EXTRAM Internal External RAM 00H FFH access using MOVX RI DPTR EXTRAM Operating Mode 0 Internal AUX RAM 00H FH access using MOVX RI DPTR 1 External data memory access 0 AO Disable Enable ALE AO Operating Mode 0 ALE is permitted at a constant rate of 1 6 the oscillator frequency 1 ALE is active only during a MOVX or MOVC instruction Notes 1 User software should not write 1 s to reserved bits These bits may be used in future 80C51 family products to invoke new features In that case the reset or inactive of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate 2 Reset value is xxxxxx10B 2000 Jul 26 14 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Preliminary Specification P8xC591 7Fh 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1Fh 18h 17h 10h OFh 08h 07h 00h MSB LS
73. AT from right to left Figure 35 shows how data in S1DAT is serially transferred to and from the SDA line 2000 Jul 26 80 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 15 2 12 THE CONTROL REGISTER S1CON The CPU can read from and write to this 8 bit directly addressable SFR Two bits are affected by the SIO1 hardware the SI bit is set when a serial interrupt is requested and the STO bit is cleared when a STOP condition is present on the I2C bus The STO bit is also cleared when ENS1 0 Table 55 Address Register S1CON address D8H 7 6 5 4 3 2 1 0 CR2 ENS1 STA STO Sl AA CRI CRO Table 56 Description of SICON DSH bits BIT SYMBOL DESCRIPTION 7 CR2 Clock rate bit 2 see Table 57 6 ENS1 Enable serial I O ENS1 0 2 I O disabled and reset ENS1 1 serial I O enabled 5 STA START flag When this bit is set in slave mode the hardware checks the 2C bus and generates a START condition if the bus is free or after the bus becomes free If the device operates in master mode it will generate a repeated START condition 4 STO STOP flag If this bit is set in a master mode a STOP condition is generated A STOP condition detected on the I2C bus clears this bit This bit may also be set in slave mode in order to recover from an error condition In this case no STOP condition is generated to the I C bus but the hardware releases
74. B 7F 7E 7D 7 7 7 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6 6 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5 5 5 59 58 57 56 55 54 53 52 51 50 AF 47 4E 46 4D 45 4 44 4 43 4 42 49 41 48 40 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 OF 00 0 0B 0 09 08 07 06 05 04 03 02 01 00 REGISTER BANK 3 REGISTER BANK 2 REGISTER BANK 1 REGISTER BANK 0 1006 127 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 24 23 16 15 Fig 6 Internal Main RAM bit addresses 2000 Jul 26 15 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller with CAN controller P8xC591 7 3 1 SPECIAL FUNCTION REGISTERS Table 4 Special Function Register Bit Address Symbol or Alternate Port Function SFRs are bit addressable SFRs are modified from or added to the 80C51 SFRs NAM
75. CE CAN CONTROLLER CANADR CANDAT SFRs CANCON PeliCAN CANSTA CANMOD MHIO20 Fig 11 CPU to CAN Interfacing The PeliCAN registers may be accessed in two different ways The most important registers which should support software polling or are controlling major CAN functions are accessible directly as separate SFRs Other parts of the PeliCAN Block are accessible using an indirect pointer mechanism In order to achieve a high data throughput even if the indirect access is used an address auto increment feature is included here 27 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Table 10 CAN Special Function Registers Preliminary Specification P8xC591 12 3 2 This read write register defines the address of one of the PeliCAN internal registers to be accessed via CANDAT It could be interpreted as a pointer to the PeliCAN The read and write access to the PeliCAN Block register is performed using the CANDAT register With the implemented auto address increment mode a fast stack like reading and writing of CAN controller internal registers is provided If the currently defined address within CANADR is above or equal to 32 decimal the content of CANADR is incremented automatically after any read or write access to CANDAT For instance loading a message into the Transmit Buffer can be done by writing the first Transmit Buffer Address 11
76. D2 00D4 00D6 0168 016B 016E 0170 0173 0176 0178 017B 017E OBJ 75D8C5 75D018 0100 7840 7908 DODO 32 75D8E5 75D018 0100 7508 5 750018 0100 75D8E5 75D018 0100 2000 Jul 26 JAKAKKAKKKKAKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKAKAKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SLAVE RECEIVER STATE SERVICE ROUTINES JAKAKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKK STATE 60 Own SLA W have been received ACK returned ACTION DATA will be rece MASTER STATE SERVICE ROUTINESeived and ACK returned sect srs60 base 0 160 S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO clr SI set AA mov psw SELRB3 ajmp INITSRD sect insrd base INITSRD mov r0 SRD mov r1 8 pop psw reti STATE 68 Arbitration lost in SLA and R W as MST Own SLA W have been received ACK returned ACTION DATA will be received and ACK returned STA is set to restart MST mode after the bus is free again sect srs68 base Ox168 mov S1CON ZENS1 STA NOTSTO NOTSI AA CRO mov psw SELRB3 ajmp INITSRD STATE 70 General call has been received ACK returned ACTION DATA will be received and ACK returned sect srs70 base 0x170 mov S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO cir SI set AA mov psw SELRB3 Initialize SRD counter ajmp initsrd STATE 78 Arbitration lost in SLA R W as MS
77. Description of SOPSL bits BIT SYMBOL DESCRIPTION 7100 Baud reload low value Lower 8 bits of the baud rate timer reload value Table 40 Internal Baud Rate Generator Prescaler High Register SOPSH address FBH Prescaler higher nibble load value 7 3 2 1 0 6 5 4 SPS __ 2 higher nibble load value Table 41 Description of SOPSH bits SYMBOL DESCRIPTION SPS Baud rate generator enable VVhen set the baud rate of serial interface is derived from the dedicated baud rate generator When cleared default after reset baud rate is derived from the Timer 1 overflow rate Reserved Baud rate generator reload high value Upper four bits of the baud rate timer value 14 3 2 PCON FOR THE INTERNAL BAUD RATE GENERATOR Table 42 PCON address 87H Prescaler load value i ae ee d SMOD1 SMODO POF WLE GF1 GFO IDL Table 43 Description of SMOD1 and SMODO bits BIT SYMBOL DESCRIPTION 7 SMOD1 Double Baud rate When set the baud rate of serial interface is modes 1 2 3 is doubled After reset this bit is cleared 6 SMODO Double Baud rate Selects SMO FE for SCON 7 bit 5100 POF to IDL Description refer to Section 11 3 5 Power Control Register PCON 2000 Jul 26 61 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 14 3 3 BAUD RATE GENERATION OVERVIEW OF OPTIONS Depending on the p
78. E DESCRIPTION BIT FUNCTIONS AND ADDRESSES iun MSB LSB ACC Accumulator EOH E7 E6 E5 E4 E3 E2 E1 00H ADCH A D converter high C6H xxxxxxxxb ADCON A D control C5H ADC 1 ADC 0 ADCI ADCS AADR2 AADR1 AADRO xx000000b AUXR Auxiliary 8EH LVADC EXTRAM xxxxx110B AUXR1 Auxiliary A2H ADC8 AIDL SRST 0 3 DPS 000000x0B B B register FOH F7 F6 F5 F4 F3 F2 F1 FO 00H CTCON Capture control EBH CTN3 CTP3 CTN2 CTP2 CTNI CTP1 CTNO CTPO 00H CTH3 Capture high 3 CFH XXXXXXXXB CTH2 Capture high 2 CEH XXXXXXXXB CTH1 Capture high 1 CDH XXXXXXXXB CTHO Capture high 0 CCH XXXXXXXXB CMH2 Compare high 2 CBH 00H CMH1 Compare high 1 CAH 00H Compare high 0 C9H 00H CTL3 Capture low 3 AFH XXXXXXXXB CTL2 Capture low 2 AEH XXXXXXXXB CTL1 Capture low 1 ADh XXXXXXXXB CTLO Capture low 0 ACH XXXXXXXXB CML2 Compare low 2 ABH 00H CML1 Compare low 1 AAH 00H CMLO Compare low 0 ASH 00H DPTR Data Pointer 2 bytes DPH Data Pointer High 83h 00H DPL Data Pointer Low 82h 00H AF AE AD AC AB AA A9 A8 IENO Interrupt Enable 0 ASH EA EAD ES1 ESO ETI 1 00H EF EE ED EC EB EA E9 E8 IEN1 Interrupt Enable 1 ESH 2 1 2 1 00H BF BE BD BC BB BA B9 B8 IPO Interrupt Priority 0 B8H PAD PS1 PSO PT1 1 x0000000B FF FE FD FC FB FA F9 F8 IPOH Interrupt Priority 0 high B7H PADH PS1H PX1H PTOH 0000000 IP1 Interrupt Pri
79. EFINED STATE OF THE I2C BUS MHIO40 SEE TABLE 63 Fig 39 Format and States in the Slave Receiver Mode 2000 Jul 26 89 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 RECEPTION OF THE OWN SLAVE ADDRESS AND TRANSMISSION OF ONE OR MORE DATA BYTES ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE LAST DATA BYTE TRANSMITTED SWITCHED TO NOT ADDRESSED All 1 s FROM MASTER TO SLAVE SLAVE AA BIT IN S1CON 0 DATA i A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS FROM SLAVE TO MASTER MHI041 THIS NUMBER CONTAINED IN S1STA CORRESPONDS TO A DEFINED STATE OF THE I C BUS SEE TABLE 64 Fig 40 Format and States of the Slave Transmitter Mode 2000 Jul 26 90 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 Table 61 Master Transmitter Mode eras STATUS OE ThE APPLICATION SOFTWARE RESPONSE CODE I2C BUS AND TO SICON S POM 515 SIO1 HARDWARE TO FROM S1DAT STA STO SI AA 08H A START condition has Load SLA W x 0 0 X SLA W will be transmitted been transmitted ACK bit will received 10H A repeated START Load SLA W or X X As above Conran RESA Load SLA R X X SLA W will be transmitted SIO1 will be transmitie switched to MST REC mode 18H SLA W has been Load data byte or 0 0 0 X Data byte will be transmitted ACK bit wil
80. ERENT APPLICATIONS The following software example shows the typical structure of the interrupt routine including the 26 state service routines and may be used as a base for user applications If one or more of the four modes are not used the associated state service routines may be removed but care should be taken that a deleted routine can never be invoked This example does not include any time out routines In the slave modes time out routines are not very useful since in these modes SIO1 behaves essentially as a passive device In the master modes an internal timer may be used to cause a time out if a serial transfer is not complete after a defined period of time This time period is defined by the system connected to the I2C bus 102 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 101 EQUATE LIST LOC OBJ SOURCE JAKAKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK LOCATIONS OF THE SI01 SPECIAL FUNCTION REGISTERS JAKAKKAKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKK 00D8 S1CON Oxd8 00D9 SISTA Oxd9 00DA S1DAT 0xda 00DB S1ADR 00A8 IENO Oxa8 00B8 IPO 0268 JAKAKKAKKKKKKKKKKKAKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKAKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK BIT L
81. Enable Rx Interrupt Level Bus Timing 0 Bus Timing 1 Bus Timing 1 Bus Timing 1 See Note 2 Rx Message Counter Rx Message Counter Rx Buffer Start Address Rx Buffer Start Address Arbitration Lost Capture Error Warning Limit Arbitration Lost Capture Error Warning Limit Error Warning Limit Rx Error Counter Rx Error Counter Rx Error Counter TX Error Counter 16 to 28 reserved 00 TX Error Counter reserved 00 TX Error Counter 29 ACF Mode ACF Mode ACF Mode 30 ACF Enable ACF Priority Acceptance Code 0 ACF Enable ACF Enable ACF Enable ACF Priority ACF Priority ACF Priority Acceptance Code 0 Acceptance Code 0 Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Code 1 Acceptance Code 1 Acceptance Code 1 Acceptance Code 2 Acceptance Code 2 Acceptance Code 2 Acceptance Code 3 Acceptance Code 3 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 0 Acceptance Mask 0 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 Acceptance Mask 1 Acceptance Mask 1 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 2 Acceptance Mask 2 Acceptance Mask 3 Acceptance Mask 3 Acceptance Mask 3 Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 0 Acceptance Code 0 Acceptance Code 0 Acceptance Code 1 Acceptance Code 1 Accepta
82. Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9 data bit RB8 is 0 In Mode 1 if SM2 1 then RI will not be activated if a valid stop bit was not received In Mode 0 SM2 should be 0 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception 3 TB8 The 9 data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired 2 RB8 In Modes 2 and 3 is the 9 data bit that was received In Mode 1 if SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used 1 TI Transmit interrupt flag Set by hardware at the end of the 8 bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software 0 RI Receive interrupt flag Set by hardware at the end of the 8 bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see SM2 Must be cleared by software 64 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 Table 46 Serial port mode select SMO SM1 DESCRIPTION BAUD RATE 0 0 Shift register Ve x folk 0 1 8 bit UART variable 1 0 9 bit UART Yao or Ve X folk 1 1 9 bit UART variable KBits s DEVIATION MODE 750 0 1 3 FFFh 250 0 1 3 FFFh
83. F Frame Format RTR Remote Transmission Request DLC x Data Length Code bit x Note The received Data Length Code located in the Frame Information Byte represents the real sent Data Length Code which may be greater than 8 depends on transmitting CAN node Nevertheless the maximum number of received data bytes is 8 This should be taken into account by reading a message from the Receive Buffer 2000 Jul 26 Fig 22 Bit Layout Receive Buffer Addr 99 RX Identifier 3 3 ID 8 2 ID 7 Addr 100 RX Identifier 4 It depends on the data length how many CAN messages can fit in the RXFIFO at one time If there is not enough space for a new message within the RXFIFO the CAN controller generates a Data Overrun condition the moment this message becomes valid and the acceptance test was positive A message that is partly written into the RXFIFO when the Data Overrun situation occurs is deleted This situation is signalled to the CPU via the Status Register and the Data Overrun Interrupt if enabled 59 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 13 SERIAL I O The P8xC591 is equipped with three independent serial ports CAN SIOO and SIO1 SIOO is a Standard Serial Interface UART with enhanced functionality In following there will be one Section describing the Standard UART functionality and an extra Section for Enhanced UART SIO1 accommodates
84. INTEGRATED CIRCUITS DATA SHEET P8xC591 Single chip 8 bit microcontroller with CAN controller Preliminary Specification 2000 Jul 26 File under Integrated Circuits 1C28 Philips PHILIPS Semiconductors E DH L Philips Semiconductors X Single chip 8 bit microcontroller with CAN controller Preliminary Specification P8xC591 CONTENTS 1 FEATURES 1 1 80C51 Related Features of the 8xC591 1 2 CAN Related Features of the 8xC591 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 FUNCTIONAL DIAGRAM 6 PINNING INFORMATION 6 1 Pinning diagram 6 2 Pin description 7 MEMORY ORGANIZATION 7 1 Program Memory 7 2 Addressing 7 3 Expanded Data RAM addressing 7 4 Dual DPTR 8 FACILITIES 9 OSCILLATOR CHARACTERISTICS 10 RESET 11 LOW POWER MODES 11 1 Stop Clock Mode 11 2 Idle Mode 11 3 Power down Mode 12 CAN CONTROLLER AREA NETWORK 12 1 Features of the PeliCAN controller 12 2 PeliCAN structure 12 3 Communication between PeliCAN controller and CPU 12 4 Register and Message Buffer description 12 5 CAN Registers 13 SERIAL I O 14 SIO0 STANDARD SERIAL INTERFACE UART 14 1 Multiprocessor Communications 14 2 Serial Port Control Register 14 3 Baud Rate Generation 14 4 More about UART Modes 14 5 Enhanced UART 15 SIO1 1 C SERIAL IO 15 1 Modes of Operation 15 2 SIO1 Imple
85. KAKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKK SLAVE TRANSMITTER STATE SERVICE ROUTINES JAKAKKAKKKKAKKKAKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKK STATE A8 Own SLA R received ACK returned ACTION DATA will be transmitted A bit received sect stsa8 base 0x1a8 mov S1DAT STD load DATA in S1DAT mov S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO clr SI set AA ajmp INITBASE2 ibase2 base Oxe8 INITBASE2 mov psw SELRB3 mov ri STD inc ri pop psw reti 111 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller LOC 01B0 01B3 01B6 01B8 01BB 01BD 00F8 00FB 00FC OOFE 01C0 0103 0165 0168 01 01CD OBJ 8548DA 75D8E5 01E8 75D018 87DA 01F8 75D8C5 09 DODO 32 75D8C5 DODO 32 75D8C5 DODO 32 2000 Jul 26 SOURCE Preliminary Specification P8xC591 STATE BO Arbitration lost in SLA and R W as MST Own SLA R received ACK returned ACTION DATA will be transmitted A bit received STA is set to restart MST mode after the bus is free again sect sstsb0 base 0x1b0 S1DALSTD load DATA in SIDAT S1CON ENS1_STA_NOTSTO_NOTSI_AA_CRO INITBASE2 I STATE B8 DATA has been transmitted ACK received ACTION DATA will be transmitted ACK bit is received sect stsb8 base Ox1
86. KAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKK INITIALIZATION ROUTINE Example to initialize IIC Interface as slave receiver or slave transmitter and start a MASTER TRANSMIT or a MASTER RECEIVE function 4 bytes will be transmitted or received JAKAKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKAKKAKKKAKKKAKKKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKK sect strt base 0x00 ajmp INIT RESET sect initial base 0x200 INIT mov S1ADR OWNSLA Load own SLA enable general call recognition setb P1 6 P1 6 High level setb P1 7 P1 7 High level mov HADD PAG1 orl IENO ENSIO1 Enable SIO1 interrupt cir SIO1HP SIO1 interrupt low priority mov S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO Initialize SLV funct JAKAKKAKKKKKKKKKKKAKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKAKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKK START MASTER TRANSMIT FUNCTION JAKAKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKAKKKAKKKKKAKKKKKKKKKKKKKKKAKKKAKAKKKKKKKKKKKKKKKAKKKAKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKK mov NUMBYTMST 0x4 Transmit 4 bytes mov SLA SLAW SLA W Transmit funct setb STA set STA in S1CON JAKAKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKAKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKK START MASTER RECEIVE FUNCTION e e e ke He He he e e e He He e e e e ke ke He e e e e ke He He e e e ke ke He e he e e ke He e e e e ke ke ke He e e e ke ke He He e ee ke ke h
87. Mode is invoked by 1 Pull ALE low while the device is in reset an PSEN is high 2 Hold ALE low as RST is deactivated While the device is in ONCE Mode the Port 0 pins go into a float state and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the device is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored when a normal reset is applied 11 3 4 REDUCED EMI MODE The ALE Off bit AO AUXR 0 can be set to 0 disable the ALE output It will automatically become active when required for external memory accesses and resume to the OFF state after completing the external memory access SMOD1 SMODO Table 9 Description of PCON bits If logic 1s are written to PD and IDL at the same time PD takes precedence The reset value of PCON is 0XX00000 BIT SYMBOL DESCRIPTION 7 SMOD1 Double Baud rate When set to logic 1 the baud rate is doubled when the serial port SIOO is being used in Modes 1 2 and 3 6 SMODO Double Baud rate Selects SMO FE for SCON 7 bit 5 POF Power Off flag WLE Watchdog Load Enable This flag must be set by software prior to loading T3 Watchdog Timer It is cleared when T3 is loaded 3 GF1 General purpose flag bits 2 GFO 1 PD Power down mode select Setting this bit activates Power down mode It can only be set if the Watchdog timer enable bit WDE is set to logic 0 0 IDL I
88. NO 0001 PAG1 0x01 select PAG1 as HADD 00 0 SLAW 0xc0 SLA W to be transmitted 00C1 SLAR 0xc1 SLA R to be transmitted 0018 SELRB3 0x18 Select Register Bank 3 2000 Jul 26 103 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 LOC OBJ 0030 0038 0040 0048 0053 0052 0051 0050 0000 4100 0200 75DB31 0203 D296 0205 D297 0207 755001 020A 43A8A0 020D C2BD 020F 75D8C5 0212 755204 0215 7551C0 0218 D2DD 021A 755204 021D 7551C1 0220 D2DD 2000 Jul 26 ke He e e e e ke ke He He e e e ke ke He e he e e ke k h e de e ke ke ke e e e ke ke ke He e ee ke keke He eee ke ke ke ke e e ke ke ke ke kekeke kekok kekke kk kkk LOCATIONS IN DATA RAM JAKAKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKAKKKKKKAKKKAKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKK MID 0 30 MST TRX DATA base address MRD 0x38 MST REC DATA base address SRD 0x40 SLV REC DATA base address STD 0x48 SLV TRX DATA base address BACKUP 0x53 Backup from NUMBYTMST To restore NUMBYTMST in case of an Arbitration Loss NUMBYTMST 0x52 I Number of bytes to transmit or receive as MST SLA 0x51 Contains SLA R W to be transmitted HADD 0x50 High Address byte for STATE Of till STATE 25 JAKAKKAKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKKKKKKK
89. O Prescaler division factor The Prescaler division factor PWMP 1 18 2 Pulse Width Register 0 PWMO Table 84 Pulse width register address FCH Reset Value 00H 7 6 5 4 3 2 1 0 PWMO 7 PWMO 6 PWMO 5 PWMO 4 PWMO 3 PWMO 2 PWMO 1 0 0 Table 85 Description of PWMO bits BIT SYMBOL DESCRIPTION 7100 PVVMO 7 to PVVMO O Pulse vvidth ratio LOW HIGH ratio of PVVMO signals PWMO 255 PWMO 18 3 Pulse Width Register 1 PWM1 Table 86 Pulse width register address FDH PWM1 7 PWM1 6 PWM1 5 PWM1 4 PWM1 3 PWM1 2 PWM1 1 PWM1 0 Table 87 Description of PWM1 bits BIT SYMBOL DESCRIPTION 7t00 PWM1 7 to PWM1 0 Pulse width ratio a _ PWM1 LOW HIGH ratio of PWM1 signals 355_ PWMI 2000 Jul 26 123 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 19 PORT1 OPERATION Port 1 may be used to input up to 6 analog signals ADC Unused ADC inputs may be used to input digital inputs These inputs have an inherent hysteresis to prevent the input logic from drawing excessive current from the power lines when driven by analog signals Channel to channel crosstalk Ct should be taken into consideration when both analog and digital signals are simultaneously input to Port 3 see Chapter 24 DC Characteristics 20 ANALOG TO DIGITAL CONVERTER ADC 20 1 ADC features e 10 bit resolution e 6 multiplexed analog inputs Start of a conversion by
90. O exceeds the level specified in this register Note that receive interrupts are only generated if complete messages have been received If RIL is set to 00 the PeliCAN functions like the receive interrupt behaviour of the SJA1000 Table 18 Bit interpretation of the Rx Interrupt Level RIL CAN ADDR 5 RX INTERRUPT LEVEL RIL RIL 5 RIL 4 RIL 3 RIL 2 RIL 1 12 5 8 BUS TIMING REGISTER 0 BTRO The contents of the Bus Timing Register 0 defines the values of the Baud Rate Prescaler BRP and the Synchronization Jump Width SJW This register can be accessed read write if the Reset Mode is active In Operating Mode this register is read only Table 19 Bus Timing Register 0 BTRO CAN address 6 7 6 5 4 3 2 1 0 SJW 1 SJW 0 BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 12 5 8 1 Baud Rate Prescaler BRP The period of the CAN system clock tsc is programmable and determines the individual bit timing The CAN system clock is calculated using the following equation 32 x BRP 5 16 x BRP 4 8 x BRP 3 4 x BRP 2 2 x BRP 1 BRP O 1 teLk time period of the uC s system clock dA 12 5 8 2 Synchronization Jump Width SJW To compensate for phase shifts between clock oscillators of different bus controllers any bus controller must resynchronize on any relevant signal edge of the current transmission The synchronization jump width defines the maximum number of clock cycles a bit pe
91. OCATIONS JAKAKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKK 00DD STA Oxdd STA bit in S1CON 00BD SIO1HP Oxbd IPO SI01 Priority bit e e ke He He He e e e He ke He e de e ke ke He he e e e ke He He e e e ke AIA IAA III AIA IAA AIA III AIA IAA AAA IATA IMMEDIATE DATA TO WRITE INTO REGISTER S1CON T e e ke e he e e ke He He he e e e ke ke He e e e e e He He e e e e He He He e e e ke ke He h e e e ke He He he e e ke ke He e e e ke ke ke e e e e ke ke ke He e e e ke ke He e e eke ke ke h e e e ke ke ke e e e keke k He kede eke kek He eee keke kekeke ekek ke kekeeke kekk kkk kk kkk 00D5 ENS1 NOTSTA STO NOTSI AA CRO 0xd5 Generates STOP CRO 100kHz fosc 6 MHz 00C5 ENS1 NOTSTA NOTSTO NOTSI AA CRO 0 5 I Releases BUS and ACK 00C1 ENS1 NOTSTA NOTSTO NOTSI NOTAA CRO 0xc1 Releases BUS and NOT ACK 00E5 ENS1 STA NOTSTO NOTSI AA CRO 0xe5 Releases BUS and set STA GENERAL IMMEDIATE DATA JAKAKKAKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKK 0031 OWNSLA 0x31 Own SLA General Call must be written into S1ADR 00A0 ENSIO1 0xa0 EA ES1 enable SIO1 interrupt must be written into IE
92. OUTPUTS The P8xC591 contains two Pulse Width Modulated PWM output channels see Fig 47 These channels generate pulses of programmable length and interval The repetition frequency is defined by an 8 bit prescaler PWMP which supplies the clock for the counter The prescaler and counter are common to both PWM channels The 8 bit counter counts modulo 255 i e from 0 to 254 inclusive The value of the 8 bit counter is compared to the contents of two registers PWMO and PWM1 Provided the contents of either of these registers is greater than the counter value the corresponding PWMO or PWM output is set LOW If the contents of these registers are equal to or less than the counter value the output will be HIGH The pulse width ratio is therefore defined by the contents of the registers PWMO and PWM1 The pulse width ratio is in the range of 9555 to 295255 and may be programmed in increments of Yass Buffered PWM outputs may be used to drive DC motors The rotation speed of the motor would be proportional to the contents of PWMn The PWM outputs may also be configured as a dual DAC PRESCALER INTERNAL BUS PWMP 2000 Jul 26 8 BIT COMPARATOR Preliminary Specification P8xC591 In this application the PWM outputs must be integrated using conventional operational amplifier circuitry If the resulting output voltages have to be accurate external buffers with their own analog supply should be used to
93. RO 2 BRP 1 BRPO Baud Rate Prescaler 2 X no change X no change BTRO 1 Baud Rate Prescaler 1 X no change X no change 0 0 Baud Rate Prescaler 0 X no change X no change T Bus Timing 1 BTR1 7 SAM Sampling X no change no change BTR1 6 TSEG2 2 Time Segment 2 2 X no change X no change BTR1 5 TSEG2 1 Time Segment 2 1 X no change X no change BTR1 4 TSEG2 0 Time Segment 2 0 X no change X no change BTR1 3 TSEG1 3 Time Segment 1 3 X no change X no change BTR1 2 TSEG1 2 Time Segment 1 2 X no change X no change BTR1 1 TSEG1 1 Time Segment 1 1 X nochange X no change BTR1 0 TSEG1 0 Time Segment 1 0 X no change X no change 2000 Jul 26 32 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 RESET BY SETTING MOD 0 BY ADDR REGISTER BIT SYMBOL NAME HARDWARE SOFTWARE OR DUE TO BUS OFF 9 Rx Message Counter RMC Rx Message Counter 0 0 10 Rx Buffer Start Address RBSA Rx Buffer Start Address 00000000 X no change 11 Arbitr Lost Capture r Arbitration Lost Capture 0 X no change 12 Error Code Capture ECC Error Code Capture 0 X no change 13 Error Warning Limit EWLR Error Warning Limit Register 96d X no change 14 Rx Error Counter gt RXERR Receive Error Counter 0 reset X no change 2 15 Tx Error Counter TXERR Transmit Error Counter X no change 2 29 ACF Mode ACFMOD 7 MFORMATB4 Message Format Bank
94. STATE SERVICE ROUTINES JAKAKKAKKKKKKKKAKKAKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK J E E E e e State 08 and State 10 are both for MST TRX and MST REC The R W bit decides whether the next state is within MST TRX mode or within MST REC mode e e e Ae k e e k e e e k e Ae k e e Re e e Ae k e e k e e Re k e Ae k e e Re e e He k e e k e e Re k e Ae Sk e e Re e e e k e He Sk e e Re k e He Sk e e k e e Re k e He Re e e Re e e He k e e k e e Re k e He k e e Re e e Hek e He k 08 A START condition has been transmitted ACTION SLA R W are transmitted ACK bit is received sect mts8 base 0x108 mov S1DAT SLA Load SLA R W mov S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO l clr SI ajmp INITBASE1 105 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 SOURCE LOC OBJ 0110 8551DA 0113 75D8C5 010E 01A0 00A0 75D018 00A3 7930 00A5 7838 00A7 855253 00 DODO 00AC 32 0118 75D018 011B 87DA 011D 01B5 0120 750805 0123 DODO 0125 32 2000 Jul 26 STATE STATE 10 A repeated START condition has been transmitted ACTION SLA R W are transmitted ACK bit is received 510 base 0x110 mov S1DAT SLA Load SLA R W mov S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO l clr SI ajmp
95. SYMBOL FUNCTION 7 ET2 Enable Timer T2 overflow interrupt s 6 ECAN Enable CAN interrupt 5 ECM1 Enable T2 Comparator 1 interrupt 4 ECMO Enable T2 Comparator 0 interrupt 3 ECT3 Enable T2 Capture register 3 interrupt 2 ECT2 Enable T2 Capture register 2 interrupt 1 ECT1 Enable T2 Capture register 1 interrupt 0 ECTO Enable T2 Capture register 0 interrupt 113 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 16 1 1 T2 CONTROL REGISTER TM2CON Table 68 T2 Control Register address EAH 7 6 5 4 3 2 1 0 2151 2150 2 T2BO T2P1 T2P0 T2MS1 2 50 Table 69 Description of TM2CON bits BIT SYMBOL DESCRIPTION 7 2151 2 16 bit overflovv interrupt select 6 2150 Timer T2 byte overflow interrupt select 5 T2ER Timer T2 external reset enable When this bit is set Timer T2 may be reset by a rising edge on RT2 P3 1 4 T2BO Timer T2 byte overflow interrupt flag 3 T2P1 Timer T2 prescaler select see Table 70 2 T2PO 1 T2MS1 Timer T2 mode select see Table 71 0 2 50 Table 70 Timer 2 prescaler select T2P1 T2P0 TIMER T2 CLOCK 0 0 clock source Vy x clock source Y x clock source O A 1 x clock source Table 71 Timer 2 mode select T2MS1 T2MSO MODE SELECTED 0 0 Timer T2 halted off 0 1 Ve x fek T2 clock source 1 0 Test mode do not use 1 1 T2 clock source
96. T General call has been received ACK returned ACTION DATA will be received and ACK returned STA is set to restart MST mode after the bus is free again sect srs78 base 0x178 mov S1CON ENS1_STA_NOTSTO_NOTSI_AA_CRO mov psw SELRB3 Initialize SRD counter ajmp INITSRD 109 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 LOC OBJ 0180 75D018 0183 A6DA 0185 01D8 00D8 D906 00DA 75D8C1 00DD DODO OODF 32 00 0 75D8C5 00E3 08 00E4 DODO 00E6 32 0188 75D8C5 018B 01 4 0190 760018 0193 A6DA 0195 01DA 2000 Jul 26 SOURCE STATE 80 Previously addressed with own SLA DATA received ACK returned ACTION Read DATA IF received DATA was the last THEN superfluous DATA will be received and NOT ACK returned ELSE next DATA will be received and ACK returned sect srs80 base Ox180 mov psw SELRB3 mov r0 S1DAT I Read received DATA ajmp REC2 sect srs80s base Oxd8 REC2 djnz r1 NOTLDAT3 LDAT mov S1CON ENS1_NOTSTA_NOTSTO_NOTSI_NOTAA_CRO l clr SI AA pop psw reti NOTLDAT3 mov S1CON ENS1_NOTSTA_NOTSTO_NOTSI_AA_CRO l clr SI set AA inc ro RETsr pop psw reti STATE 88 Previously addressed with own SLA DATA received NOT ACK returned I ACTION No save of DATA Enter NOT addressed SLV mode Recognition of own SLA General call recognized if S1ADR 01 sect srs88 base 0x188 mov S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO
97. T action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 38H Arbitration lost in No S1DAT action or 0 0 X I2C bus will be released not addressed SLA R W or Data bytes slave will be entered No S1DAT action 0 0 X ASTART condition will be transmitted when the bus becomes free 2000 Jul 26 91 Philips Semiconductors Preliminary Specification 8 591 Single chip 8 bit microcontroller with CAN controller Table 62 Master Receiver Mode SATUS Eois BEB APPLICATION SOFTWARE RESPONSE CODE I2C BUS AND TO SICON E eM S1STA SIO1 HARDWARE TO FROM S1DAT 08H A START condition has Load SLA WR SLA R will be transmitted ACK bit will be been transmitted received 10H A repeated START Load SLA R or As above condition been Load SLA W SLA W will be transmitted SIO1 will be switched to MST TRX mode 38H Arbitration lostin NOT no S1DAT action or 2 bus will be released SIO1 will enter a ACK bit slave mode no S1DAT action A START condition will be transmitted when the bus becomes free 40H SLA R has been no S1DAT action or Data byte will be received NOT ACK bit transmitted ACK has will be returned been received no S1DAT action Data byte will be received ACK bit will be returned 48H SLA R has been no S1DAT action or Repeated START condition will be transmitted NOT ACK transmitted has beeniraceiyed no S1DAT action or S
98. TB3 AMODEB3 MFORMATB2 AMODEB2 MFORMATB1 AMODEBI standard standard standard standard dual single extended Ut extended dual single extended extended ACCEPTANCE FILTER ACCEPTANCE FILTER ACCEPTANCE FILTER ACCEPTANCE FILTER BANK 4 BANK 3 BANK 2 BANK 1 ACRO ACRO ACRO ACRO ACR 1 ACR 1 ACR 1 ACR 1 ACR 2 ACR 2 ACR 2 ACR 2 ACR3 AMRO AMRO AMRO AMRO AMR 1 AMR 1 AMR 1 AMR 1 AMR 2 AMR 2 AMR 2 AMR 2 AMR 3 AMR 3 AMR 3 AMR 3 ai 2 1 ni 2 al 1 2 five 1 ali 2 sl 1 enable enable enable enable enable enable enable enable disable disable disable disable Hele e BAF2EN B4F1EN B3F2EN B3F1EN B2F2EN B2F1EN B1F2EN B1F1EN ACCEPTANCE FILTER ENABLE REGISTER 4 t 4 t t filter 2 filter 1 filter 2 filter 1 filter 2 filter 1 filter 2 filter 1 priority priority priority priority priority priority priority priority low high low high low high low high low high low high low high low high B4F2PRIO B4F1PRIO B3F2PRIO B3F1PRIO B2F2PRIO B2F1PRIO B1F2PRIO B1F1PRIO ACCEPTANCE FILTER PRIORITY REGISTER MHI014 Fig 14 Acceptance Filter Banks 2000 Jul 26 47 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 12 5 17 1 Acceptance Filter Mode Register Preliminary Specification P8xC591 The current operating mode is def
99. TERFACE addressidata MANAGEMENT i LOGIC MESSAGE BUFFER PeliCAN Core Block TRANSMIT ERROR gt BUFFER MANAGEMENT LOGIC TXDC IA RECEIVE BIT TRANSMIT FIFO TIMING MANAGEMENT LOGIC LOGIC RXDC BIT STREAM ACCEPTANCE PROCESSOR gt FILTER MHI010 Fig 10 Block Diagram of the PeliCAN 2000 Jul 26 25 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 12 2 1 INTERFACE MANAGEMENT LOGIC IML The Interface Management Logic interprets commands from the CPU controls addressing of the CAN Registers and provides interrupts and status information to the CPU Additionally it drives the universal interface of the PeliCAN 12 2 2 TRANSMIT BUFFER TXB The Transmit Buffer is an interface between the CPU and the Bit Stream Processor BSP and is able to store a complete CAN message which should be transmitted over the CAN network The buffer is 13 bytes long written by the CPU and read out by the BSP or the CPU itself 12 2 3 RECEIVE BUFFER RXB RXFIFO The Receive Buffer is an interface between the Acceptance Filter and the CPU and stores the received and accepted messages from the CAN Bus line The Receive Buffer RXB represents a CPU accessible 13 byte window of the Receive FIFO RXFIFO which has a total length of 64 bytes With the help of this FIFO the CPU is able to process one message while other messages are being received 12 2 4 ACCEPTANCE FILTER ACF The Acce
100. TOP condition will be transmitted STO flag will be reset no S1DAT action STOP condition followed by a START condition will be transmitted STO flag will be reset 50H Data byte has been Read data byte or Data byte will be received NOT ACK bit received NOT ACK has will be returned been returned read data byte Data byte will be received ACK bit will be returned 58H Data byte has been Read data byte or 1 0 0 Repeated START condition vvill be received ACK has been transmitted returned read data byte or 0 1 0 STOP condition vvill be transmitted STO flag vvill be reset read data byte 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset 2000 Jul 26 92 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Table 63 Slave Receiver Mode APPLICATION SOFTWARE RESPONSE Preliminary Specification P8xC591 STATUS STATUS OF THE CODE I2C BUS AND TO SICON E ORE S1STA SIO1 HARDWARE TO FROM S1DAT 60H Own SLA W has been No S1DAT action or Data byte will be received and NOT ACK received ACK has been will be returned returned no S1DAT action Data byte will be received and ACK will be returned 68H Arbitration lost in No S1DAT action or Data byte will be received and NOT ACK SLA R W as master will be returned Own SLA W has been no SIDAT action Data byte will be received and ACK will be received ACK returned returned 70H General call addres
101. Timing 2000 Jul 26 83 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 15 2 12 4 SI the Serial Interrupt Flag SI 1 When the SI flag is set then if the EA and ES1 interrupt enable register bits are also set a serial interrupt is requested SI is set by hardware when one of 25 of the 26 possible SIO1 states is entered The only state that does not cause SI to be set is state F8H which indicates that no relevant state information is available While SI is set the low period of the serial clock on the SCL line is stretched and the serial transfer is suspended A high level on the SCL line is unaffected by the serial interrupt flag SI must be reset by software SI 0 When the SI flag is reset no serial interrupt is requested and there is no stretching of the serial clock on the SCL line 15 2 12 5 AA the Assert Acknowledge flag AA 1 If the AA flag is set an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line when e The own slave address has been received e The general call address has been received while the general call bit GC in S1ADR is set e A data byte has been received while SIO1 is in the master receiver mode e A data byte has been received while SIO1 is in the addressed slave receiver mode AA 0 if the AA flag is reset a not acknowledge high level to SDA will be returned during t
102. UART drivers which do not make use of this feature 15 5101 I2C SERIAL IO The I2C bus uses two wires SDA and SCL to transfer information between devices connected to the bus The main features of the bus are e Bidirectional data transfer between masters and slaves Multimaster bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The 12C bus may be used for test and diagnostic purposes The I O pins P1 6 and P1 7 must be set to Open Drain SCL and SDA The 8xC591 on chip I C logic provides a serial interface that meets the I C bus specification The SIO1 logic handles bytes transfer autonomously It also keeps track of serial transfers and a status register S1STA reflects the status of SIO1 and the I C bus Philips Semiconductors Single chip 8 bit microcontroller with CAN controller The CPU interfaces to the I2C logic via the following four special function registers S1CON SIO1 control register S1STA SIO1 status register S1DAT SIO1 data register and S1ADR SIO1 slave address register The SIO1 logic interfaces to the external I2C bus via two port 1 pins P1 6 SCL serial clock line and P1 7 SDA serial data line A typical 1
103. WMO PWM1 80C51 CONFIGURABLE CORE TWO 16 BIT TIMER EVENT COUNTERS TO T1 16 KBYTES 512 BYTES PROGRAM MEMORY DATA MEMORY P8xC591 VDD Vss CPU INTERFACE 16 BIT TIMER EVENT PC SERIAL SFRs XTAL1 OSCILLATOR WATCHDOG PARALLEL COUNTER WITH CAPTURE INTERFACE TIMER T3 YO PORTS XTAL2 CAN 2 0 B INTERFACE RST PO P1 P2 P3 fan NE cd apr SDA SCL TXDC RXDC CTOXINTx CMSRO to 5 CMTO to 1 MHIOO1 Fig 1 Block diagram P8xC591 2000 Jul 26 5 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 5 FUNCTIONAL DIAGRAM Vss alternative functions oa XTAL1 gt ADO gt ADI lt gt AD3 and data bus XTAL2 gt PORT 0 AD4 low order address gt AD5 NN lt gt RST 4 07 __ RXDC PSEN a gt CAN ADCO CTOI INT2 ADC1 CTII INT3 PORTA 4 ADC2 CT2I INT4 AVret 4 ADC3 CT3I INT5 P8xC591 lt ADC4 SCL p Avss J 4 5 4 lt PWM1 4 T2 RXD gt 0 RT2 TXD 1 gt CSMRO 4 INTO gt 2 gt CSMR1 INT1 3 E CSMR2 4 To gt PORT 3 4 PORT 2 Ed address bus CSMR3 T1 5 gt WR 6 gt RD 4 7 4 MHI002 Fig 2 Functional diagram 2000 Jul 26 6 Philips Semiconductors Prel
104. aborted when the Idle or Power down mode is entered The result of a completed conversion ADCI logic 1 remains unaffected when entering the Idle mode VDAC VDAC full scale 1 Vin SUCCESSIVE APPROXIMATION REGISTER START 15 16 SUCCESSIVE APPROXIMATION CONTROL LOGIC STOP 59164 4 5 titau 6 MHI051 Fig 49 Successive Approximation ADC 2000 Jul 26 126 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Start of conversion 1052 Fig 50 A D Conversion Flowchart 2000 Jul 26 127 Preliminary Specification P8xC591 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 20 3 1 ADC CONTROL REGISTER ADCON Table 88 ADC Control Register address C5H Reset value xx00 0000B 7 6 5 4 3 2 1 0 ADC 1 ADC 0 ADEX ADCI ADCS AADR2 AADR1 AADRO Table 89 Description of ADCON bits BIT SYMBOL DESCRIPTION ADC 1 Bit 1 of ADC result ADC 0 Bit 0 of ADC result Reserved for future use ADCI ADC interrupt flag This flag is set when an A D conversion result is ready to be read An interrupt is invoked if its is enabled The flag may be cleared by the interrupt service routine While this flag is set the ADC cannot start a new conversion ADCI cannot be Set by software 3 ADCS ADC start and status Setting this bit starts an A D conversi
105. addressed SLV mode Own SLA will be recognized General call address will be recognized if S1ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 2000 Jul 26 95 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 Table 65 Miscellaneous States APPLICATION SOFTWARE RESPONSE STATUS STATUS OF THE NEXT ACTION TAKEN BY SIO1 CODE I C BUS AND TO S1CON SISTA J SIO1 HARDWARE TO FROM S1DAT HARDWARE STA STO SI AA F8H No relevant state No S1DAT action No S1CON action Wait or proceed current transfer information available SI 0 00H Bus error during MST or No S1DAT action 0 1 0 X Only the internal hardware is affected in selected slave modes the MST or addressed SLV modes In all due to an illegal START cases the bus is released and SIO1 is or STOP condition switched to the not addressed SLV mode State 00H can also STO is reset occur when interference causes SIO1 to enter an undefined state 2000 Jul 26 96 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 15 2 14 4 Slave Transmitter Mode In the slave transmitter mode a number of data bytes are transmitted to a master receiver see Figure 40 Data transfer is initialized as in the slave receiver mode When S1ADR and S1CON have been initialized SIO1 waits until it is addressed by its own slave address followed by the da
106. ails 2000 Jul 26 DPS BTO E AUXRI DPTRI DPTRO DPH DPL EXTERNAL 83H 82H DATA MEMORY MHI007 Fig 7 Dual DPTR Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 7 4 1 AUXR1 PAGE REGISTER Table 5 AUXHR1 Page Register address A2H 7 6 5 4 3 2 1 0 ADC8 AIDL SRST WDE WUPD 0 DSP Table 6 Description of AUXR1 of bits User software should not write 1s to reserved bits Theses bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be logic 0 and its active value will be logic 1 The value read from a reserved bit is indeterminate The reset value of AUXR1 is 000000xB BIT SYMBOL DESCRIPTION 7 ADC8 ADC Mode Switch Switches between 10 bit conversion and 8 bit conversion ADC8 Operating Mode 0 10 bit conversion 50 machine cycles 1 8 bit conversion 24 machine cycles 6 AIDL Enables the ADC during Idle mode 5 SRST Software Reset 4 WDE Watchdog Timer Enable Flag 3 WUPD Enable Wake up from Power down 2 1 Reserved 0 Data Pointer Switch Switches between DPRTO and DPTR1 ADC8 Operating Mode 0 DPTRO 1 DPTR1 2000 Jul 26 20 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 8 I O FACILITIES The P8xC591 consists of 32 I O Port lines with partly
107. at interface to the I2C bus via standard I O port lines which are software driven and slow 100kHz is usually the maximum bit rate and can be derived from a 16 MHz 12 MHz ora 6 MHz oscillator A variable bit rate 0 5 kHz to 62 5 kHz may also be used if Timer 1 is not required for any other purpose while SIO1 is in a master mode The frequencies shown in Table 57 are unimportant when SIO1 is in a slave mode In the slave modes SIO1 will automatically synchronize with any clock frequency up to 100 kHz Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 15 2 13 THE STATUS REGISTER S1STA S1STA is an 8 bit read only special function register The three least significant bits are always zero The five most significant bits contain the status code There are 26 possible status codes When S1STA contains F8H no relevant state information is available and no serial Table 57 Serial clock rate Preliminary Specification P8xC591 interrupt is requested All other S1STA values correspond to defined SIO1 states When each of these states is entered a serial interrupt is requested SI 1 A valid status code is present in S1STA one machine cycle after Slis set by hardware and is still present one machine cycle after SI has been reset by software BIT FREQUENCY kHz at fci CR2 CR1 CRO DIVIDED BY 0 0 0 0 1 1 1 1 1 1 0 49 62 5 0 65 55 6 0 98
108. ator for the serial port To enable this feature bit SPS bit 7 of Special Function Register SOPSH must be set Bit SMOD1 PCON 7 controls a divide by 2 circuit which affect the input and output clock signal of the baud rate generator After reset the divide by 2 circuit is active and the resulting overflow output clock will be divided by 2 The input clock of the baud rate generator is fck The baud rate generator consists of its own free running upward counting 12 bit timer On overflow of this timer next count step after counter value FFFH there is an automatic 12 bit reload from the registers SOPSL and SOPSH The lovver 8 bits of the timer are reloaded from SOPSL while the upper four bits are reloaded from bit 0 to 3 of register SOPSH The baud rate timer is reloaded by writing to SOPSH foLK Note The switch configuration shows the reset state 2000 Jul 26 overflow 12 BIT TIMER 1025 Fig 24 Serial Port Input Clock when using the Baud Rate Generator 63 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller with CAN controller P8xC591 With the baud rate generator as clock source for the serial SMOD1 port in Mode 1 and Mode 3 the baud rate of can be Mode 1 3 baud rate x timer 1 overflow rate determined as follows Mode 1 3 baud rate 2 SMOD1 32 The Timer 1 interrupt is usually disabled in this application Timer 1 itself can be configured for eith
109. b8 sect scn base Oxf8 SCON mov mov ajmp mov psw SELRB3 S1DAT r1 SCON S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO clr SI set AA ri psw STATE CO DATA has been transmitted NOT ACK received ACTION Enter not addressed SLV mode sect stsc0 base Ox1c0 mov S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO l clr SI set AA psw I STATE C8 Last DATA has been transmitted AA 0 ACK received ACTION Enter not addressed SLV mode stsc8 base Ox1c8 mov pop reti S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO l clr SI set AA psw JAKAKKAKKKKKKKKAKKAKKKAKKKKKAKKKKKKKKAKKKKKKAKKKAKAKKKKKKKKKKKKKKKAKKKAKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKK END OF SI01 INTERRUPT ROUTINE JAKAKKAKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKK 112 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 16 TIMER 2 16 1 Features of Timer 2 Timer T2 is a 16 bit timer consisting of two registers TMH2 HIGH byte and TML2 LOW byte The 16 bit timer counter can be switched off or clocked via a prescaler from one of two sources fcLk 6 or an external signal When Timer T2 is configured as a counter the prescaler is clocked by an external signal on T2 P3 0 A rising edge on T2 increments the prescaler and the maximum repetition rate is one count per machine cycle 1 MHz with a 6 MHz oscillator
110. bility no Data Length Code gt 8 should be used If a value greater than 8 is selected 8 bytes are transmitted in the data frame with the Data Length Code specified in DLC 12 5 18 4 Identifier ID In Standard Frame Format SFF the Identifier consists of 11 bits ID 28 to ID 18 and in Extended Frame Format EFF messages the identifier consists of 29 bits ID 28 to ID 0 ID 28 is the most significant bit which is transmitted first on the bus during the arbitration process The Identifier acts as the message s name used in a receiver for acceptance filtering and also determines the bus access priority during the arbitration process The lower the binary value of the Identifier the higher the priority This is due to the larger number of leading dominant bits during arbitration 12 5 18 5 Data Field The number of transferred data bytes is defined by the Data Length Code The first bit transmitted is the most significant bit of data byte 1 at address 115 SFF or address 117 EFF 2000 Jul 26 57 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 5 19 RECEIVE BUFFER The global layout of the Receive Buffer is very similar to the Transmit Buffer described in the previous chapter The Receive Buffer is the accessible part of the RXFIFO and is located in the range between CAN Address 96 and 108 Each message is subdivided into a Descriptor and a Data Field
111. both states are contradictory Thus when watchdog operation is enabled by setting WDE bit in AUXR1 4 it is not possible to enter the Power down mode and an attempt to set the Power down bit PCON 1 will have no effect PCON 1 will remain at logic 0 Watchdog Software Example The following example shows how watchdog operation might be handled in a user program at the program start T3 EQU OFFH address of watchdog timer T3 PCON EQU 087H address of PCON SFR WATCH INTV EQU 156 waichdog interval e g 2 x 100 ms sto be inserted at each watchdog location within ihe user program LCALL WATCHDOG watchdog service routine WATCHDOG ORL PCON 10H set condition flag PCON 4 jload T3 with watchdog interval MOV T3 WATCH INV RET If its possible for this subroutine to be called in an erroneous state then the condition flag WLE should be set at different parts of the main program 120 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 INTERNAL BUS PRESCALER 11 BIT 1 6 folk to reset circuitry TIMER T3 8 BIT LOAD LOADEN CLEAR LOADEN vvrite T3 AUXR1 4 PCON 4 PCON 1 WDE INTERNAL BUS MHI047 1 See Fig 8 Fig 46 Functional diagram of T3 VVatchdog Timer 2000 Jul 26 121 Philips Semiconductors Single chip 8 bit microcontroller vvith GAN controller 18 PULSE VVIDTH MODULATED
112. buffer the PWM outputs before they are integrated The repetition frequency fpwy at the PWMn outputs is fpwm PWMP 1 x255 This gives a repetition frequency range of 184 Hz to 47 kHz at fci 12 MHz By loading the PWM registers with either 00H or FFH the PWM channels will output a constant HIGH or LOW level respectively Since the 8 bit counter counts modulo 255 it can never actually reach the value of the PWM registers when they are loaded with FFH When a compare register PWMO or PWM1 is loaded with a new value the associated output is updated immediately It does not have to wait until the end of the current counter period Both PWMn output pins are driven by push pull drivers These pins are not used for any other purpose PWMO 8 BIT COMPARATOR 8 BIT COUNTER PWMO OUTPUT BUFFER OUTPUT WIKIA BUFFER 1048 Fig 47 Functional diagram of Pulse Width Modulated outputs 122 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 18 1 Prescaler Frequency Control Register PWMP Reading PWMP gives the current reload value The actual count of the prescaler cannot be read Table 82 Prescaler Frequency Control Register address FEH Reset Value 00H PWMP 7 PWMP 6 PWMP 5 PWMP 4 PWMP 3 PWMP 2 PWMP 1 PWMP 0 Table 83 Description of PWMP bits BIT SYMBOL DESCRIPTION 7t00 PWMP7 to PWMP
113. byte While AA is reset SIO1 does not respond to its own slave address or a general call address However the 12 bus is still monitored and address recognition may be resumed at any time by setting AA This means that the AA bit may be used to temporarily isolate SIO1 from the 22 bus Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 Table 59 Address Register STADR DBH address 00H own slave address Table 60 Address Register S1CON D8H address 00H SUCCESSFUL TRANSMISSION TO A SLAVE RECEIVER NEXT TRANSFER STARTED WITH A REPEATED START CONDITION NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS TO MST REC MODE ENTRY MR NOT ACKNOWLEDGE RECEIVED AFTER A DATA BYTE ARBITRATION LOST IN SLAVE ADDRESS Agr A OTHER MST OR DATA BYTE AOT CONTINUES OTHER MST CONTINUES Aor A OTHER MST ARBITRATION LOST AND ADDRESSED AS SLAVE CONTINUES TO CORRESPONDING STATES IN SLAVE MODE m FROM MASTER TO SLAVE FROM SLAVE TO MASTER DATA i A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS THIS NUMBER CONTAINED S1STA CORRESPONDS TO A DEFINED STATE OF THE 12C BUS MHIO38 SEE TABLE 61 Fig 37 Format and States in the Master Transmitter Mode 2000 Jul 26 87 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller wit
114. ch has bit 0 0 for Slave 0 and bit 1 0 for Slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following could be used to select Slaves 1 and 2 while excluding Slave 0 Slave0 SADDR 1100 0000 SADEN 11111001 Given 1100 0XX0 Slave1 SADDR 1110 0000 SADEN 11111010 Given 1110 0X0X Slave2 SADDR 11100000 SADEN 11111100 Given 1110 00XX 2000 Jul 26 73 Preliminary Specification P8xC591 In the above example the differentiation among the 3 Slaves is in the lower 3 address bits Slave 0 requires that bit 0 O and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude Slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are trended as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon reset SADDR SFR address 0A9H and SADEN SFR address 0B9H are leaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type
115. cification P8xC591 15 2 12 3 STO the STOP Flag STO 1 When the STO bit is set while SIO1 is ina master mode a STOP condition is transmitted to the I2C bus When the STOP condition is detected on the bus the SIO1 hardware clears the STO flag In a slave mode the STO flag may be set to recover from an error condition In this case no STOP condition is transmitted to the 12C bus However the SIO1 hardware behaves as if a STOP condition has been received and switches to the defined not addressed slave receiver mode The STO flag is automatically cleared by hardware Ifthe STA and STO bits are both set the a STOP condition is transmitted to the I2C bus if SIO1 is in a master mode in a slave mode SIO1 generates an internal STOP condition which is not transmitted SIO1 then transmits a START condition STO 0 When the STO bit is reset no STOP condition will be generated Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 gt INTERNAL BUS ie SCL gt SHIFT PULSES MHI036 SDA Fig 35 Serial Input Output Configuration a Te Te Tee 5 555 0 SHIFT ACK 8 SIDAT TI TI SHIFT IN ACK A A 2 HIFT BSD7 5 5 OUT so 55 loaded by the CPU MHI037 1 Valid data in SIDAT 2 Shifting data in SIDAT and ACK 3 High level on SDA Fig 36 Shift in and Shift out
116. ck pulses have a 50 duty cycle unless the clock generator is synchronized with other SCL clock sources as described above 15 2 7 TIMING AND CONTROL The timing and control logic generates the timing and control signals for serial byte handling This logic block provides the shift pulses for SIDAT enables the comparator generates and detects start and stop conditions receives and transmits acknowledge bits controls the master and slave modes contains interrupt request logic and monitors the I2C bus status 15 2 8 CONTROL REGISTER SICON This 7 bit special function register is used by the microcontroller to control the follovving SIO1 functions start and restart of a serial transfer termination of a serial transfer bit rate address recognition and acknovvledgment 2000 Jul 26 mark 1 space duration 1 Another service pulls the SCL line low before the SIO mask duration is complete The serial clock generator is immediately reset and commences with the space duration by pulling SCL low 2 Another device still pulls the SCL line low after SIO1 releases SCL The serial clock generator is forced into 3 The SCL line is released and the serial clock generator commences with the mark duration Fig 34 Serial Clock Synchronization 1035 lt 2 15 2 9 STATUS DECODER AND STATUS REGISTER The status decoder takes all of the internal status bits and comp
117. d after a repeated START condition 15 3 5 SLAVE TRANSMITTER AND SLAVE RECEIVER MODES After initialization SIO1 continually tests the I C bus and branches to one of the slave state service routines if it detects its own slave address or the general call address see Table 63 Table 64 Figure 39 and Figure 40 If arbitration was lost while in the master mode the master mode is restarted after the current transfer If a bus error occurs the I C bus is released and SIO1 enters the not selected slave receiver mode 2000 Jul 26 Preliminary Specification P8xC591 In the slave receiver mode a maximum of 8 received data bytes can be stored in the internal data RAM A maximum of 8 bytes ensures that other RAM locations are not overwritten if a master sends more bytes If more than 8 bytes are transmitted a not acknowledge is returned and SIO1 enters the not addressed slave receiver mode A maximum of one received data byte can be stored in the internal data RAM after a general call address is detected If more than one byte is transmitted a not acknowledge is returned and SIO1 enters the not addressed slave receiver mode In the slave transmitter mode data to be transmitted is obtained from the same locations in the internal data RAM that were previously loaded by the main program After a not acknowledge has been returned by a master receiver device SIO1 enters the not addressed slave mode 15 3 6 ADAPTING THE SOFTWARE FOR DIFF
118. d by SJMP and all conditional jumps Range is 128 to 127 bytes relative to first byte of the following instruction x Hexadecimal opcode cross reference 8 9 A B D E F 1 3 5 7 9 22 1 Addressing Modes 0 2 4 6 8 A C E e Immediate Addressing Most instructions have a destination source field that specifies the data type addressing modes and operands involved For all these instructions except for MOVs the destination operand is also the source operand e g ADD A R7 There are five kinds of addressing modes Register Addressing RO R7 4 banks A B C bit AB 2 bytes DPTR double byte e Direct Addressing lower 128 bytes of internal Main RAM including the 4 RO R7 register banks Special Function Registers 128 bits in a subset of the internal Main RAM 128 bits in a subset of the Special Function Registers Register Indirect Addressing internal Main RAM RO R1 SP PUSH POP internal Auxiliary RAM RO R1 DPTR external Data Memory RO R1 DPTR 2000 Jul 26 Program Memory in code 8 bit or 16 bit constant e Base Register plus Index Register Indirect Addressing Program Memory look up table DPTR A PC A The first three addressing modes are usable for destination operands 140 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controll
119. d to Vin again If the input voltage is greater than VDAC then the bit being tested remains set 125 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller otherwise the bit being tested is cleared This process is repeated until all ten bits have been tested at which stage the result of the conversion is held in the successive approximation register Figure 48 shows a conversion flow chart The bit pointer identifies the bit under test The conversion takes four machine cycles per bit The end of the 10 bit conversion is flagged by control bit ADCON 4 ADCI The upper 8 bits of the result are held in Special Function Register ADCH and the two remaining bits are held in ADCON 7 ADC 1 and ADCON 6 ADC 0 The user may ignore the two least significant bits in ADCON and use the ADC as an 8 bit converter 8 upper bits in ADCH In any event the total actual conversion Vin Preliminary Specification P8xC591 time is 50 machine cycles for the P8xC591 ADCI will be set and the ADCS status flag will be reset 50 or 24 cycles after the command flip flop ADCS is set Control bits ADCON 0 ADCON 1 and ADCON 2 are used to control an analog multiplexer which selects one of six analog channels see Section 20 3 1 An ADC conversion in progress is unaffected by a new software ADC start The result of a completed conversion remains unaffected provided ADCI logic 1 a new ADC conversion already in progress is
120. d when combined with the IPx SFR determines the priority of each interrupt The priority of each interrupt is determined as shown in the following table Table 92 Interrupt Priority Register PRIORITY BITS INTERRUPT PRIORITY LEVEL Level 0 lowest priority Level 1 Level 2 Level 3 highest priority The priority scheme for servicing the interrupts is the same as that for the 80C51 except there are four interrupt levels rather than two as on the 80C51 An interrupt will be Serviced as long as an interrupt of equal or higher priority is not already being serviced If an interrupt of equal or higher level priority is being serviced the new interrupt will wait until it is finished before being serviced If a lower priority level interrupt is being serviced it will be stopped and the new interrupt serviced When the new interrupt is finished the lower priority level interrupt that was stopped will be completed Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 21 2 Interrupt Enable and Priority Registers 21 2 1 INTERRUPT ENABLE REGISTER 0 IENO Logic 0 interrupt disabled logic 1 interrupt enabled Table 93 Interrupt Enable Register 0 address A8H 7 EA EAD ES1 ESO ET1 EX1 ETO EXO Table 94 Description of IENO bits BIT SYMBOL DESCRIPTION 7 EA Global enable disable control If bit EA is LOW then no interrupt is enabled HIGH then any
121. data byte or Last data byte will be transmitted and ACK been transmitted ACK bit will be received has been received load data byte Data byte will be transmitted ACK bit will be received COH Data byte in S1DAT has No S1DAT action or 0 0 0 Switched to not addressed SLV mode no been transmitted NOT recognition of own SLA or General call ACK has been received address no S1DAT action or 0 0 0 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if STADR 0 logic 1 no S1DAT action or 1 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no S1DAT action 1 0 0 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if S1ADR 0 logic 1 A START condition will be transmitted when the bus becomes free C8H Last data byte in S1DAT No S1DAT action or 0 0 0 Switched to not addressed SLV mode no has been transmitted recognition of own SLA or General call AA 0 ACK has been address received no S1DAT action or 0 0 0 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if STADR 0 logic 1 no S1DAT action or 1 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no S1DAT action 1 0 0 Switched to not
122. direct byte 2 1 05 INC Ri Increment indirect RAM 06 07 DEC A Decrement A 1 1 14 DEC Rr Decrement register DEC direct Decrement direct byte 2 1 15 DEC Ri Decrement indirect RAM 1 1 16 17 INC DPTR Increment data pointer 1 2 A3 MUL AB Multiply A and B 1 4 A4 DIV AB Divide A by B 84 DA A Decimal adjust A 1 1 D4 2000 Jul 26 136 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Table 108 Instruction set description Logic operations MNEMONIC Logic operations DESCRIPTION Preliminary Specification P8xC591 OPCODE BYTES CYCLES HEX ANL A Rr AND register to A 1 1 5 ANL A direct AND direct byte to A ANL A Ri AND indirect RAM to A 1 1 56 57 ANL A data AND immediate data to A ANL direct A AND A to direct byte 2 1 52 ANL direct data AND immediate data to direct byte ORL A Rr OR register to A 1 1 4 ORL A direct OR direct byte to A 45 ORL OR indirect RAM to A ORL A data OR immediate data to A 2 1 44 ORL direct A OR A to direct byte 42 ORL direct data OR immediate data to direct byte 3 2 43 XRL A Rr Exclusive OR register to A 6 XRL A direct Exclusive OR direct byte to A 2 1 65 XRL A Ri Exclusive OR indirect RAM to A 66 67 XRL A data Exclusive OR immediate data to A 2 1 64 XRL direct A Exclusive OR A to direct byte 62 XRL direct data Exclusive OR immediate data to direct byte 3 2 63 CLR A Clear A 1 1 E4 CPL A Comp
123. dle mode select Setting this bit activates the Idle mode 2000 Jul 26 23 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 12 CAN CONTROLLER AREA NETWORK Controller Area Network is the definition of a high performance communication protocol for serial data communication The CAN controller circuitry is designed to provide a full implementation of the CAN Protocol according to the CAN Specification Version 2 0 B Microcontroller including this on chip CAN controller are used to build powerful local networks both for general industrial and automotive environments The result is a strongly reduced wiring harness and enhanced diagnostic and supervisory capabilities The P8xC591 includes the same functions known from the SJA1000 stand alone CAN controller from Philips Semiconductors with the following improvements e Enhanced receive interrupt e Enhanced acceptance filter 8 filter for standard frame formats 4 filter for extended formats change on the fly feature 12 1 12 1 1 Features of the PeliCAN controller GENERAL CAN FEATURES CAN 2 0B protocol compatibility e Multi master architecture Bus access priority determined by the message identifier 11 bit or 29 bit e Non destructive bit wise arbitration Guaranteed latency time for high priority messages Programmable transfer rate up to 1Mbit s Multicast and broadcast message facility Data length from 0
124. e SIO1 enable bit ENS1 0 When ENSI is 0 the SDA and SCL input signals are ignored SIO1 is in the not addressed slave state and the STO bit in S1CON is forced to 0 No other bits are affected ENS1 1 When ENSI is 1 12C is enabled Note that P1 6 and P1 7 have to set to Open Drain by writing the Port mode registers P1M1 x and P1M2 x bits 6 and 7 with a 1 see Section 6 2 Pin description ENS1 should not be used to temporarily release SIO1 from the I C bus since when ENS is reset the I C bus status is lost The AA flag should be used instead see description of the AA flag in the following text In the following text it is assumed that ENS1 1 15 2 12 2 STA the START flag STA 1 When the STA bit is set to enter a master mode 5101 hardware checks the status of the I C bus and generates a START condition if the bus is free If the bus is not free then SIO1 waits for a STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal serial clock generator If STA is set while SIO1 is already in a master mode and one or more bytes are transmitted or received SIO1 transmits a repeated START condition STA may be set at any time STA may also be set when SIO1 is an addressed slave STA 0 When the STA bit is reset no START condition or repeated START condition will be generated 2000 Jul 26 82 Preliminary Spe
125. e SIO1 hardware attempts to generate a START condition after every two additional clock pulses on the SCL line When the SDA line is eventually released a normal START condition is transmitted state 08H is entered and the serial transfer continues Preliminary Specification P8xC591 If a forced bus access occurs or a repeated START condition is transmitted while SDA is obstructed pulled LOW the SIO1 hardware performs the same action as described above In each case state 08H is entered after a successful START condition is transmitted and normal serial transfer continues Note that the CPU is not involved in solving these bus hang up problems 15 2 15 4 Bus error A bus error occurs when a START or STOP condition is present at an illegal position in the format frame Examples of illegal positions are during the serial transfer of an address byte a data or an acknowledge bit The SIO1 hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave When a bus error is detected SIO1 immediately switches to the not addressed slave mode releases the SDA and SCL lines sets the interrupt flag and loads the status register with OOH This status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 65 STA FLAG 1 1 SDA LINE SCL LINE
126. e actual and the ideal transfer curve after appropriate adjustment of gain and offset error see Fig 54 The offset error OS is the absolute difference between the straight line which fits the actual transfer curve after removing gain error and a straight line which fits the ideal transfer curve see Fig 54 The gain error Ge is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error and the straight line which fits the ideal transfer curve Gain error is constant at every point on the transfer curve see Fig 54 The absolute voltage error Ae is the maximum difference between the centre of the steps of the actual transfer curve of the non calibrated ADC and the ideal transfer curve This should be considered when both analog and digital signals are simultaneously input to Port 1 The parameter is guaranteed by design and characterized but is not production tested 2000 Jul 26 144 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 1023 Preliminary Specification P8xC591 offset error OSe de gain error Ge 1022 1021 1020 1019 1018 code out 7 offset error 1 Example of an actual transfer curve 2 The ideal transfer curve 3 Differential non linearity DLe 4 Integral non linearity IL 5 Centre of a step of the actual transfer curve 2000 Jul 26
127. e e e ke ke ke eke e ke ke ke He he e e ke keke He ee e ke ke ke ke e e ke ke ke kekeeke kekok kekeke k kkk mov NUMBYTMST 0x4 Receive 4 bytes mov SLA SLAR SLA R Receive funct setb STA set STA in S1CON 104 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 LOC 002B 002D 002F 0031 0100 0103 0105 0108 010B 010E OBJ CODO COD9 C050 22 75D8D5 DODO 32 8551DA 75D8C5 01A0 2000 Jul 26 JAKAKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKAKKKKKKAKKKAKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKK S101 INTERRUPT ROUTINE JAKAKKAKKKKKKKKAKKAKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKK S101 interrupt vector base 0x00 S1STA and HADD are pushed onto the stack They serve as return address for the RET instruction The RET instruction sets the Program Counter to address HADD S1STA and jumps to the right subroutine push psw save psw push S1STA push HADD ret JMP to address HADD S1STA STATE 00 Bus error ACTION Enter not addressed SLV mode and release bus STO reset sect sto base 0x100 mov S1CON ENS1_NOTSTA_STO_NOTSI_AA_CRO cir SI set STO AA pop psw reti JAKAKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKAKAKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKK MASTER
128. e received 7 bit slave address with its own slave address 7 most significant bits in S1ADR It also compares the first received 8 bit byte with the general call address 00H If an equality is found the appropriate status bits are set and an interrupt is requested 2000 Jul 26 76 Preliminary Specification P8xC591 15 2 4 SHIFT REGISTER S1DAT This 8 bit special function register contains a byte of serial data to be transmitted or a byte which has just been received Data in S1DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of S1DAT While data is being shifted out data on the bus is simultaneously being shifted in S1DAT always contains the last byte present on the bus Thus in the event of lost arbitration the transition from master transmitter to slave receiver is made with the correct data in S1DAT Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 FILTER P1 7 SDA ET OUTPUT STAGE ARBITRATION amp INPUT SYNC LOGIC FILTER TIMING amp 1 4 fosc vastik PA CONTROL LOGIC OUTPUT SERIAL CLOCK INTERRUPT STAGE GENERATOR INTERNAL BUS TIMER 1 OVERFLOW I S1CON STATUS STATUS BITS DECODER SISTA STATUS REGISTER MHI033 Fig 32 I2C Bus Interface Block Diagram
129. en CM2 and T2 0 RP32 If HIGH then P3 2 is reset on a match between CM2 and T2 16 1 6 2 Set Enable Register STE Table 76 Set enable register address EEH SP35 SP34 SP33 SP32 Table 77 Description of STE bits BIT SYMBOL DESCRIPTION Reserved SP35 If HIGH then P3 5 is set on a match between CM2 and T2 SP34 If HIGH then P3 4 is set on a match between CM2 and T2 SP33 If HIGH then P3 3 is set on a match between CM2 and T2 SP32 If HIGH then P3 2 is set on a match between CM2 and T2 2000 Jul 26 118 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 16 1 7 TIMER T2 INTERRUPT FLAG REGISTER TM2IR Seven of the eight Timer T2 interrupt flags are located in special function register TM2IR see Section 16 1 7 1 The eights flag is TM2CON 4 The CTOI and CT1I flags are set during S4 of the cycle in which the contents of Timer T2 are captured CTOI is scanned by the interrupt logic during S2 and CT11 is scanned during S3 2 CT3l are set during S6 and are scanned during S4 and S5 The associated interrupt requests are recognized during the following cycle If these flags are polled a transition at CTOI or CT11 will be recognized one cycle before a transition on CT2l or since registers are read during S5 The CMIO CMI1 and CMI2 flags are set during S6 of the cycle following a match 16 1 7 1 Interrupt Flag Register TM2IR Table 78 Interr
130. eptance Mask 1 Acceptance Mask 1 Acceptance Mask 1 62 Acceptance Mask 2 Acceptance Mask 2 Acceptance Mask 2 Acceptance Mask 2 63 Acceptance Mask 3 Acceptance Mask 3 Acceptance Mask 3 Acceptance Mask 3 64 95 reserved 00 reserved 00 SFF EFF SFF EFF SFF EFF 96 Rx Frame Info Rx Frame Info Rx Frame Info Rx Frame Info Rx Frame Info Rx Frame Info 97 Rx Identifier 1 Rx Identifier 1 Rx Identifier 1 Rx Identifier 1 Rx Identifier 1 Rx Identifier 1 98 99 Rx Data 1 Rx Identifier 3 Rx Data 1 Rx Identifier 3 Rx Data 1 Rx Identifier 3 100 Rx Data 2 Rx Identifier 4 Rx Data 2 Rx Identifier 4 Rx Data 2 Rx Identifier 4 101 Rx Data 3 Rx Data 1 Rx Data 3 Rx Data 1 Rx Data 3 Rx Data 1 103 Rx Data 5 Rx Data 3 Rx Data 5 Rx Data 3 Rx Data 5 Rx Data 3 106 Rx Data 8 Rx Data 6 Rx Data 8 Rx Data 6 Rx Data 8 Rx Data 6 107 0 _ 7 1 Rx Data 7 FIFO RAM 1 Rx Data 7 108 0 RxData8 FIFO RAM 1 Rx Data 8 FIFO RAM 1 Rx Data 8 109 to 111 reserved 00 reserved 00 SFF SFF EFF SFF EFF 112 Tx Frame Info Tx Frame Info Tx Frame Info Tx Frame Info Tx Frame Info Tx Frame Info Tx Frame Info Tx Frame Info 114 Tx Identifier 2 Tx Identifier 2 Tx Identifier 2 Tx Identifier 2 Tx Identifier 2 Tx Identifier 2 Tx Identifier 2 Tx Identifier 2 2000 Jul 26 30 Philips Semiconductors Preliminary Specification Single chi
131. er timer or counter operation and in any of its operating modes In x osciillator frequency most typical applications it is configured for timer 32x baud rate generator overflow rate operation in the auto reload high nibble of TMOD Baud rate generator overflow rate 212 SOPS with SOPS SOPSH 3 0 SOPSL 7 0 0010B In this case the baud rate is given by the formula MODI 2 x oscillator frequency Mode1 3 baud rate 32x6x 255 THD SOPS Baud Rate Generator Prescaler load value Very low baud rates can be achieved with Timer 1 if Table 47 lists baud rates and how they can be obtained leaving the Timer 1 interrupt enabled configuring the timer from the Internal Baud Rate Generator to run as 16 bit timer high nibble of TMOD 0001B and using the Timer 1 interrupt for a 16 bit software reload 14 3 8 USING TIMER 1 TO GENERATE BAUD RATES Table 49 lists lower baud rates and how they can be In Mode 1 and 3 of the serial port also timer 1 canbe used obtained from Timer 1 for generating baud rates Then the baud rate is determined by the timer 1 overflow rate and the value of SMODI as follows Table 44 Serial Port Control Register SCON address 7 6 5 4 3 2 1 0 SMO SMI SM2 REN TB8 RB8 TI RI Table 45 Description of SOPSH and SOPSL bits 2000 Jul 26 BIT SYMBOL DESCRIPTION 7 SMO See Table 46 6 SM1 See Table 46 5 SM2
132. er P8xC591 23 LIMITING VALUES In accordance with the Absolute Maximum Rating System IEC 134 Note 1 SYMBOL PARAMETER MIN Voltage on Vpp to Vss and SCL SDA to Vss 0 5 VI Input voltage on any other pin to Vss 0 5 li lo Input output current on any I O pin Prot Total power dissipation Note 2 Tstg Storage temperature range 65 Tamb Operating ambient temperature range P8xC591VFx 40 Vpp Voltage on EA Vpp to Vss 0 5 Notes 1 The following applies to the Absolute Maximum Ratings a Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Chapters 24 and 25 of this specification is not implied g This product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge However its suggested that conventional precautions be taken to avoid applying greater than the rated maxima c Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted 2 This value is based on the maximum allowable die temperature and the thermal resistance of the package not on device power consumption 2000 Jul 26 141 Philips Semiconductors Preliminary Specification S
133. erviced I I I P l a SCL I 1 2 2247 8 9 1 2 3 8 9 i S 7 P S repeated if more bytes LE C are transferred MHIO32 Fig 31 Data Transfer on the I C Bus 2000 Jul 26 75 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 15 2 SIO1 Implementation and Operation Figure 32 shows how the on chip I C bus interface is implemented and the following text describes the individual blocks 15 2 1 INPUT FILTERS AND OUTPUT STAGES The input filters have 1 C compatible input levels If the input voltage is less than 1 5 V the input logic level is interpreted as 0 if the input voltage is greater than 3 0 V the input logic level is interpreted as 1 Input signals are synchronized with the internal clock fc 4 and spikes shorter than three oscillator periods are filtered out The output stages consist of open drain transistors that can sink 3 mA at Vout lt 0 4 V These open drain outputs do have clamping diodes to Vpp Thus precautions have to be considered if a powered down 8xC591 on one board clamps the 12C bus externally 15 2 2 ADDRESS REGISTER S1ADR This 8 bit special function register may be loaded with the 7 bit slave address 7 most significant bits to which SIO1 will respond when programmed as a slave transmitter or receiver The LSB GC is used to enable general call address 00H recognition 15 2 3 COMPARATOR The comparator compares th
134. es Filter 1 within Acceptance Filter Bank 1 0 low A receive interrupt is generated if the FIFO level exceeds the Receive Interrupt Level Register 2000 Jul 26 50 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 12 5 17 4 Single Filter Configuration In this filter configuration one long filter 4 byte could be defined The bit correspondences between the filter bytes and the Message bytes depends on the programmed Frame Format see ACF Mode Register Single Filter Standard Frame If the Standard Frame Format is selected the complete Identifier including the RTR bit and the first two data bytes are used for acceptance filtering Messages may also be Preliminary Specification P8xC591 accepted if there are no data bytes existing due to a set RTR bit or if there is no or only one data byte because of the corresponding data length code For a successful reception of a message all single bit comparisons have to signal acceptance Note that the 4 least significant bits of AMR1 and ACRI are not used In order to keep compatible with future products these bits should be programmed to be don t care by setting AMR1 3 AMR1 2 AMR1 1 and AMR1 0 to 1 MSB LSB MSB LSB MSB LSB MSB LSB Addr 16 ACRO Addr 17 ACRI Addr 18 ACR2 Adar 19 ACR3 7 6
135. es the first 256 bytes of external data memory With EXTRAM 0 the AUX RAM is indirectly addressed using the MOVX instruction in combination with any of the registers RO R1 ofthe selected bank or DPTR An access to AUX RAM will not affect ports PO P3 6 WR and P3 7 RD P2 SFR is output during external addressing For example with EXTRAM 0 MOV RO data where RO contains 0AOh access the AUX RAM at address OAOH rather than external memory An access to external data memory locations higher than FFH i e 0100H to FFFFH will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51 so with PO and P2 as data address bus and P3 6 and P3 7 as write and read timing signals Refer to Table 4 With EXTRAM 1 MOVX Ri and MOVX DPTR will be similar to the standard 80C51 MOVX Ri will provide an 8 bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits This is to provide the external paging capability MOVX DPTR will generate a 16 bit address Port 2 outputs the high order eight address bits the contents of DPH while Port 0 multiplexes the low order eight address bits DPL with data MOVX Ri and MOVX DPTR will generate either read or write signals on P3 6 WR and P3 7 RD The stack pointer SP may be located anywhere in the 256 bytes RAM lower and upper RAM internal data memory The stack cannot be located in the AUX R
136. gnal However minimum and maximum high and low times specified in the data sheet must be observed 10 RESET A reset is accomplished by holding the RST pin LOW for at least two machine cycles 12 oscillator periods while the oscillator is running To insure a good power on reset the RST pin must be low long enough to allow the oscillator time to start up normally a few milliseconds plus two machine cycles The RST line can also be pulled LOW internally by a pull down transistor activated by the watchdog timer T3 The length of the output pulse from T3 is 3 machine cycles 2000 Jul 26 Preliminary Specification P8xC591 A pulse of such short duration is necessary in order to recover from a processor or system fault as fast as possible Note that the short reset pulse from Timer T3 cannot discharge the power on reset capacitor see Figure 8 Consequently when the watchdog timer is also used to set external devices this capacitor arrangement should not be connected to the RST pin and a different circuit should be used to perform the power on reset operation A timer T3 overflow if enabled will force a reset condition to the P8xC591 by an internal connection whether the output RST is pulled up HIGH or not A reset may be performed in software by setting the software reset bit SRST AUXR1 5 This device also has a Power on Detect Reset circuit as Voc transitions from Vec past VRST VDD SCHMITT TRIGGER on
137. h CAN controller P8xC591 SUCCESSFUL RECEPTION FROM A SLAVE TRANSMITTER NEXT TRANSFER STARTED WITH A REPEATED START CONDITION NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS ARBITRATION LOST IN SLAVE ADDRESS OR ACKNOWLEDGE BIT ARBITRATION LOST AND ADDRESSED AS SLAVE FROM MASTER TO SLAVE EN FROM SLAVE TO MASTER SEE TABLE 62 MR Aor OTHER MST CONTINUES A OTHER MST CONTINUES OTHER MST CONTINUES TO CORRESPONDING STATES IN SLAVE MODE DATA i A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS THIS NUMBER CONTAINED IN S1STA CORRESPONDS TO A DEFINED STATE OF THE I2C BUS Fig 38 Format and States in the Master Receiver Mode TO MST TRX MODE ENTRY MT MHI039 2000 Jul 26 88 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 RECEPTION OF THE OWN SLAVE ADDRESS AND ONE OR MORE DATA BYTES ALL ARE ACKNOWLEDGED S LAST DATA BYTE RECEIVED IS NOT ACKNOVVLEDGED ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE RECEPTION OF THE GENERAL CALL ADDRESS AND ONE OR MORE DATA BYTES LAST DATA BYTE IS NOT ACKNOVVLEDGED ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE BY GENERAL CALL d FROM MASTER TO SLAVE FROM SLAVE TO MASTER DATA i A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS THIS NUMBER CONTAINED IN S1STA CORRESPONDS TO A D
138. he SJA1000 stand alone CAN2 0B controller PELICAN FEATURES Four independently configurable Screeners Acceptance Filters Each Screener has two 32 bit specifies 32 bit Match and 32 bit Mask 32 bits of Mask per Screener allows unique Group addressing per Screener Higher layer protocols especially supported in Standard CAN format with Upto four 11 bit ID Screeners that also Screen the two 2 Data Bytes i e Data Frames are Screened by the CAN ID and by Data Byte content Up to eight 11 bit ID Screeners half of which also Screen the first Data Byte All Screeners are changeable on the fly Listen Only Mode Self Test Mode Error Code Capture Arbitration Lost Capture readable Error Counters Philips Semiconductors Single chip 8 bit microcontroller vvith GAN controller 2 GENERAL DESCRIPTION P8xC591 is a single chip 8 bit high performance microcontroller with on chip CAN controller derived from the 80C51 microcontroller family It uses the powerful 80C51 instruction set and includes the successful PeliCAN functionality of the SJA1000 CAN controller from Philips Semiconductors The fully static core provides extended power save provisions as the oscillator can be stopped and easily restarted without loss of data The improved internal clock prescaler of 1 1 achieves a 500 ns instruction cycle time at 12 MHz external clock rate Preliminary Specification P8xC591 The temperat
139. he acknowledge clock pulse on SCL when e A data has been received while SIO1 is in the master receiver mode e A data byte has been received while SIO1 is in the addressed slave receiver mode When SIO1 is in the addressed slave transmitter mode state C8H will be entered after the last serial is transmitted see Figure 40 When SI is cleared SIO1 leaves state C8H enters the not addressed slave receiver mode and the SDA line remains at a high level In state C8H the AA flag can be set again for future address recognition 2000 Jul 26 84 Preliminary Specification P8xC591 When SIO 1 is in the not addressed slave mode its own slave address and the general call address are ignored Consequently no acknowledge is returned and a serial interrupt is not requested Thus SIO1 can be temporarily released from the I C bus while the bus status is monitored While SIO1 is released from the bus START and STOP conditions are detected and serial data is shifted in Address recognition can be resumed at any time by setting the AA flag If the AA flag is set when the parts own slave address or the general call address has been partly received the address will be recognized at the end of the byte transmission 15 2 12 6 CRO CR1 and CR2 the Clock Rate Bits These three bits determine the serial clock frequency when SIO1 is in a master mode The various serial rates are shown in Table 57 A 12 5 kHz bit rate may be used by devices th
140. he master transmitter mode a number of data bytes are transmitted to a slave receiver see Figure 37 Before the master transmitter mode can be entered S1CON must be initialized as in Table 58 CRO CR1 and CR2 define the serial bit rate ENS1 must be set to logic 1 to enable SIO1 If the AA bit is reset SIO1 will not acknowledge its own slave address or the general call address in the event of another device becoming Philips Semiconductors Single chip 8 bit microcontroller with CAN controller master of the bus In other words if AA is reset SIOO cannot enter a slave mode STA STO and SI must be reset The master transmitter mode may now be entered by setting the STA bit using the SETB instruction The SIO1 logic will now test the I2C bus and generate a start condition as soon as the bus becomes free When a START condition is transmitted the serial interrupt flag SI is set and the status code in the status register S1STA will be 08H This status code must be used to vector to an interrupt service routine that loads S1DAT with the slave address and the data direction bit SLA W The Table 58 Address Register S1CON address D8H Preliminary Specification P8xC591 SI bit in S1CON must then be reset before the serial transfer can continue When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received the serial interrupt flag SI is set again and a number of statu
141. he write to SCON that cleared RI RECEIVE is cleared as RI is set 2000 Jul 26 Preliminary Specification P8xC591 More About Mode 1 Ten bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first anda stop bit 1 On receive the stop bit goes into RB8 in SCON In the 80C51 the baud rate is determined by the Timer 1 overflow rate Figure 25 shows a simplified functional diagram of the serial port in Mode1 and associated timings for transmit receive Transmission is initiated by any instruction that uses SOBUF as a destination register The write to SOBUF signal also loads a1 into the 9 bit position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the vvrite to SOBUF signal The transmission begins with activation of SEND which puts the start bit at TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to TxD The first shift pulse occurs one bit time after that As data bits shift out to the right zeros are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the
142. ial transfer S1STA 00H This status code indicates that a bus error has occurred during an SIO1 serial transfer A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge bit A bus error may also be caused when external interference disturbs the internal SIO1 signals When a bus error occurs SI is Set To recover from a bus error the STO flag must be set and SI must be cleared This causes SIO1 to enter the not addressed slave mode a defined state and to clear the STO flag no other bits in S1CON are affected The SDA and SCL lines are released a STOP condition is not transmitted 2000 Jul 26 97 Preliminary Specification P8xC591 15 2 15 SOME SPECIAL CASES The SIO1 hardware has facilities to handle the following special cases that may occur during a serial transfer Simultaneous Repeated START Conditions from Two Masters A repeated START condition may be generated in the master transmitter or master receiver modes A special case occurs if another master simultaneously generates a repeated START condition see Figure 41 Until this occurs arbitration is not lost by either master since they were both transmitting the same data If the SIO1 hardware detects a repeated START condition on the I2C bus before generating a repeated START condition itself it
143. ice routine The state service routines are located in a 256 byte page of program memory The location of this page is defined in the initialization routine The page can be located anywhere in program memory by loading data RAM register HADD with the page number Page 01 is chosen in this example and the service routines are located between addresses 0100H and 01FFH 15 3 3 THE STATE SERVICE ROUTINE The state service routines are located 8 bytes from each other Eight bytes of code are sufficient for most of the service routines A few of the routines require more than 8 bytes and have to jump to other locations to obtain more bytes of code Each state routine is part of the SIO1 interrupt routine and handles one of the 26 states It ends with a RETI instruction which causes a return to the main program 100 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 SPECIAL FUNCTION REGISTERS IENO EA ESI AB INTERNAL DATA RAM 7F BACKUP ORIGINAL VALUE OF NUMBYTMST 53 NUMBYTMST NUMBER OF BYTES AS MASTER 52 SLA SLA R W TO BE TRANSMITTED TO SLA 51 HADD HIGHER ADDRESS BYTE INTERRUPT ROUTINE 50 SLAVE TRANSMITTER DATA RAM t STD FH 48 SLAVE RECEIVER DATA RAM SRD i T 40 5 MASTER RECEIVER DATA RAM 42 MRD 1 T MASTER TRANSMITTER DATA RAM MTD 1 T so RI 19 RO 18 MHI045 Fig 44 SIO1 Data Memory Map
144. icrocontroller with CAN controller Mode 0 is the Shift Register mode and SM2 is ignored Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address All of the slaves may be contacted by using the Broadcast address Two Special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Slave0 SADDR 1100 0000 SADEN 11111101 Given 1100 00X0 Slave 1 SADDR 1100 0000 SADEN 11111110 Given 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two salves Slave 0 requires as 0 in bit 0 and itignores bit 1 Slave 1 requires a0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a O in bit 1 A unique address for Slave 1 would be 1100 0001 since a 1 in bit O will exclude slave 0 Both slaves can be selected at the same time by an address whi
145. iginal inch dimensions A1 Aa min max UNITI A bp by D E e ep ee Hp He 16 66 16 66 16 51 16 51 0 656 0 656 0 650 0 650 0 51 3 05 inches 0 12 1 Plastic or metal protrusions of 0 01 inches maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAJ PROJECTION SOT187 2 112E10 MO 047AC 21 245 ISSUE DATE 2000 Jul 26 158 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 QFP44 plastic quad flat package 44 leads lead length 1 3 mm body 10 x 10 x 1 75 mm SOT307 2 22 calla 1 N detail X DIMENSIONS mm are the original dimensions A max UNIT A4 As bp 2 10 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION SOT307 2 Ec Q 95 02 04 ISSUE DATE 2000 Jul 26 159 Philips Semiconductors Single chip 8 bit microc
146. iminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 6 PINNING INFORMATION 6 1 Pinning diagram P1 3 ADC1 INT3 CT11I P1 2 ADCO INT2 CTOI ZI 3 P1 1 TXDC 2 P1 0 RXDC 44 66 P1 4 ADC2 INT4 CT2I P0 2 AD2 40 P0 3 AD3 43 P0 0 ADO 42 P0 1 ADI1 CT3I INT5 ADC3 P1 5 P0 4 AD4 SCL ADC4 P1 6 8 P0 5 AD5 SDA ADC5 P1 7 9 P0 6 AD6 RST P0 7 AD7 T2 P3 0 RXD EAVpp PWMO P8xC591 PWM1 RT2 P3 1 TXD ALE PROG CMSRO P3 2 INTO PSEN CMSR1 P3 3 INT1 P2 7 A15 CMSR2 P3 4 TO P2 6 A14 CMSR3 P3 5 T1 P2 5 A13 N N N N MHI003 P3 6 WR P3 7 RD XTAL2 XTAL1 P2 2 A10 2 3 11 2 4 12 Fig 3 Pinning Diagram for 44 lead LCC Package 2000 Jul 26 7 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 lt lt c P1 5 ADCS INTS CTSI P0 4 AD4 P1 6 ADC4 SCL P0 5 AD5 P1 7 ADC5 SDA P0 6 AD6 RST P0 7 AD7 P3 0 T2 RXD EANpp PWMO P8xC591 PWM1 RT2 P3 1 TXD ALE PROG CMSRO P3 2 INTO PSEN CMSR1 P3 3 INT1 P2 7 A15 CMSR2 P3 4 T0 P2 6 A14 CMSR3 P3 5 T1 P2 5 A13 e em N N N N MHI004 P3 6 WR P3 7 RD XTAL2 XTAL1 Vss VDD P2 0 A8 P2 1 A9 P2 2 A10 P2 3 A11 P2 4 A12 Fig 4 Pinning Diagram for 44 lead Plastic Quad Flat Package QFP 2000 Jul 26 8 Philips Semiconductors Preliminary Specification Single ch
147. ined within the Acceptance Filter Mode Register located at CAN Address 29 A write access to this register is possible only within Reset Mode Mode Register Table 31 Acceptance Filter Mode Register ACF Mode CAN address 29 7 6 5 4 3 2 1 0 MFORMATB4 AMODEB4 MFORMATB3 AMODEB3 MFORMATB2 AMODEB2 MFORMATBI AMODEB1 Table 32 Acceptance Filter Mode Register ACF Mode 1 bits BIT SYMBOL NAME VALUE FUNCTION ACFMOD 6 AMODEB4 ACFMOD 7 MFORMATBA Acceptance Filter Format Bank 4 Acceptance Filter Mode Bank 4 1 EFF 0 SFF 1 single 0 dual Acceptance Filter Bank 4 is used for Extended Frame Messages only Standard Frame Messages are ignored Acceptance Filter Bank 4 is used for Standard Frame Messages only Extended Frame Messages are ignored The Single Acceptance Filter option is enabled for filter bank 4 gt one long filter is active The Dual Acceptance Filter option is enabled for filter bank 4 gt two short filters are active ACFMOD 5 MFORMATB3 Acceptance Filter Format Bank 3 1 EFF 0 SFF Acceptance Filter Bank 3 is used for Extended Frame Messages only Standard Frame Messages are ignored Acceptance Filter Bank 3 is used for Standard Frame Messages only Extended Frame Messages are ignored ACFMOD 4 ACFMOD 3 AMODEB3 MFORMATB2 Acceptance Filter Mode Bank 3 Acceptance Filter Format Bank 2 1 single 0
148. ingle chip 8 bit microcontroller vvith GAN controller P8xC591 24 DC CHARACTERISTICS Vpp 5 V 5 Vsg 0 V all voltages with respect to Vss unless otherwise specified Tamb 40 to 85 C for the P8xC591VFx Vpp 5 V 5 Vsg 0 0 SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Supply Ipp operating supply current toLk 12 MHz 45 mA see Notes 2 and 3 lip supply current Idle mode tek 12 MHz 25 mA see Notes 2 and 4 lpp supply current Power down mode 2 V Vpp Vpp 100 uA see Notes 2 and 5 LOW level input voltage except P1 0 P1 1 P1 6 P1 7 0 5 0 2 Vpp 0 1 liii Ports 1 2 3 in pseudo bidirectional output mode except P1 6 P1 7 input leakage current Ports 0 2 3 and P1 0 P1 1 in high impedance 0 45 V lt VIN lt LOW level input voltage EA 0 5 0 2 Vpp 0 3 V Vit LOW level input voltage P1 0 and P1 1 0 2 Vpp V Vin HIGH level input voltage except P1 0 V P1 1 P1 6 P1 7 XTAL1 RST ViHi HIGH level input voltage XTAL1 RST 0 7 Vpp Vpp 0 5 V Vins HIGH level input voltage P1 0 and P1 1 Vpp V mi LOW level input current Ports 1 2 and 3 Viy 2 0 45 V LA in pseudo bidirectional output mode except P1 6 P1 7 lr input current HIGH to LOW transition LA configurations 12 input leakage current Port 1 0 45 V lt Vin lt 1 LA except P1 0 P1 1 2000 Jul 26 142 Philips Semiconductors Preliminary Specification
149. ion ADS External interrupt 0 0003H 19 Timer 0 overflovv TO 000BH e Serial I O 0 UART 50 0023H T2 capture 1 CT1 5101 26 2 1 CHI T2 capture 0 CTO 0033H T2 capture 2 2 2 CT2 0043H MART i ADC completion ADC 0053H Timer T2 overtiow 12 CAN interrupt CAN 006BH 2000 Jul 26 135 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 22 INSTRUCTION SET For the description of the Data Addressing Modes and Hexadecimal opcode cross reference see Table 111 Table 107 Instruction set description Arithmetic operations MNEMONIC DESCRIPTION BYTES CYCLES ea Arithmetic operations ADD A Rr Add register to A 1 1 2 ADD A direct Add direct byte to A 2 1 25 ADD A Ri Add indirect RAM to A 1 1 26 27 ADD A data Add immediate data to A 2 1 24 ADDC A Rr Add register to A with carry flag 3 ADDC A direct Add direct byte to A with carry flag 2 1 35 ADDC A Ri Add indirect RAM to A with carry flag 36 37 ADDC A data Add immediate data to A with carry flag 2 1 34 SUBB A Rr Subtract register from A with borrow 9 SUBB A direct Subtract direct byte from A with borrow 2 1 95 SUBB A Ri Subtract indirect RAM from A with borrow 1 1 96 97 SUBB A data Subtract immediate data from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rr Increment register 0 direct Increment
150. ip 8 bit microcontroller vvith GAN controller P8xC591 6 2 Pin description Table 1 Pin description for QFP44 PLCC44 see Note 1 PIN SYMBOL DESCRIPTION QFP44 PLCC44 ST 4 10 Reset A Input to reset the P8xC591 It also provides a reset pulse as output when Timer T3 overflows P3 0to P3 7 Port 3 P3 0 to P3 7 8 bit programmable port lines Port 3 can sink source 4 LSTTL inputs Port 3 pins serve alternate functions as follows P3 0 RXD 5 RXD Serial input port for UART T2 T2 event input P3 1 TXD 7 TXD Serial output port for UART RT2 T2 timer reset signal Rising edge triggered P3 2 INTO CMSRO 8 INTO External interrupt input 0 CMSRO Compare and Set Reset output for Timer T2 P3 3 INT1 9 INT1 External interrupt input 1 CMSR1 CMSR1 Compare and Set Reset output for Timer T2 P3 4 TO CMSR2 10 TO Timer 0 external interrupt input CMSR2 Compare and Set Reset output for Timer T2 P3 5 T1 CMSR3 11 T1 Timer 1 external interrupt input CMSR3 Compare and Set Reset output for Timer T2 P3 6 WR 12 WR External Data Memory Write strobe P3 7 RD 13 RD External Data Memory Read strobe During reset Port 3 will be asynchronously driven resistive HIGH Port 3 has four modes selected on a per bit basis by writing to the PSM1 and P3M2 registers as follows P3M1 x P3M2 x Mode Description 0 0 Pseudo bidirectional standard c51 configuration default 0 1 Push Pull 1 0 High impedance 1 1 Open drain XTAL2 14 Cry
151. is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power down 2000 Jul 26 22 Philips Semiconductors Single chip 8 bit microcontroller vvith GAN controller 11 3 1 The Power Off Flag POF is set by on chip circuitry when the Vcc level on the P8xC591 rises from 0 to 5 V The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power on or warm after Power down The Vcc level must remain above 3 V for the POF to remain unaffected by the Vcc level POWER OFF FLAG 11 3 2 DESIGN CONSIDERATION When the Idle mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control On chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external Memory 11 3 5 POWER CONTROL REGISTER PCON Table 8 Power Control Register address 87H Preliminary Specification P8xC591 11 3 3 The ONCETM On Circuit Emulation Mode facilities testing and debugging of systems vvithout the device having to be removed from the circuit The ONCE
152. ite access to this register is possible only in Reset Mode After hardware reset this register is initialised to 0 If a bus off event occurs the TX Error Counter is initialised to 127 to count the minimum protocol defined time 128 occurrences of the Bus Free signal Reading the TX Error Counter during this time gives information about the status of the Bus Off recovery If Bus Off is active a write access to TXERR in the range of 0 to 254 clears the Bus Off Flag and the controller will wait for one occurrence of 11 consecutive recessive bits bus free after clearing of Reset Mode Writing 255 to TXERR allows to initiate a CPU driven Bus Off event Note that a CPU forced content change of the Preliminary Specification P8xC591 TX Error Counter is possible only if the Reset Mode was entered previously An Error or Bus Status change Status Register an Error Warning or an Error Passive Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again After leaving the Reset Mode the new TX Counter content is interpreted and the Bus Off event is performed in the same way as if it was forced by a bus error event That means that the Reset Mode is entered again the TX Error Counter is initialised to 127 the RX Counter is cleared and all concerned Status and Interrupt Register Bits are set Clearing of Reset Mode now will perform the protocol defined Bus Off recovery sequence waiting for
153. l transmitted ACK has be received been received beenijeceiveng no S1DAT action or 1 0 X Repeated START will be transmitted no S1DAT action or 0 1 0 X STOP condition will be transmitted STO flag will be reset no S1DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 20H SLA W has been Load data byte or 0 0 0 X Data byte will be transmitted ACK will be transmitted NOT ACK received has been received no S1DAT action or 1 0 X Repeated START will be transmitted no S1DAT action or 0 1 0 X STOP condition will be transmitted STO flag will be reset no S1DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 28H Data byte in SIDAT has Load data byte or 0 0 0 X_ Data byte will be transmitted ACK bit will been transmitted ACK be received has been received no S1DAT action or 1 0 Repeated START will be transmitted no S1DAT action or 0 1 0 X STOP condition will be transmitted STO flag will be reset no S1DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 30H Data byte in SIDAT has Load data byte or 0 0 0 X Data byte will be transmitted ACK bit will been transmitted NOT be received ACK has been received no S1DAT action or 1 0 Repeated START will be transmitted no S1DAT action or 0 X STOP condition will be transmitted STO flag will be reset no S1DA
154. lave address and if the least Table 51 Address Register S1ADR address DBH Preliminary Specification P8xC591 significant bit is set the general call address 00H is recognized otherwise it is ignored The most significant bit corresponds to the first bit received from the I2C bus after a start condition A logic 1 in STADR corresponds to a high level on the I C bus and a logic 0 corresponds to a low level on the bus 7 6 5 4 3 2 1 0 X X X X X X X GC Table 52 Description of S1ADR DBH bits BIT SYMBOL DESCRIPTION 7t01 Own slave address 0 GC 0 general call address is not recognized 1 general call address is recognized 15 2 11 THE DATA REGISTER S1DAT SIDAT contains a byte of serial data to be transmitted or a byte which has just been received The CPU can read from and write to this 8 bit directly addressable SFR while it is not in the process of shifting a byte This occurs when SIO1 is in a defined state and the serial interrupt flag is set Data in S1DAT remains stable as long as Sl is set Data in S1DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of S1DAT While data is being shifted out data on the bus is simultaneously being shifted in S1DAT always contains the last data byte present on the bus Thus in the event of lost arbitratio
155. lement A F4 RL A Rotate A left 1 1 23 RLC A Rotate A left through the carry flag RR A Rotate A right 1 1 03 RRC A Rotate A right through the carry flag SWAP A Swap nibbles within A 1 1 C4 2000 Jul 26 137 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Table 109 Instruction set description Data transfer MNEMONIC Data transfer DESCRIPTION BYTES Preliminary Specification CYCLES P8xC591 OPCODE HEX MOV A Rr Move register to A 1 1 E MOV A direct Note 1 Move direct byte to A 2 MOV A Ri Move indirect RAM to A 1 1 E6 E7 MOV A data Move immediate data to A 2 1 74 MOV Rr A Move A to register 1 1 Fe MOV Rr direct Move direct byte to register 2 MOV Rr data Move immediate data to register 2 1 i MOV direct A Move A to direct byte 2 MOV direct Rr Move register to direct byte 2 MOV direct direct Move direct byte to direct 3 2 85 MOV direct Ri Move indirect RAM to direct byte 2 MOV direct data Move immediate data to direct byte 3 2 75 MOV Ri A Move A to indirect RAM 1 MOV Ri direct Move direct byte to indirect RAM 2 2 A6 A7 MOV Ri data Move immediate data to indirect RAM 2 1 76 77 MOV DPTR data 16 Load data pointer with a 16 bit constant 3 2 90 MOVC A A DPTR Move code byte relative to DPTR to A 1 2 93 MOVC A A PC Move code byte relative to PC to A 1 2 83 MOVX A Ri Move external RAM 8 bit address to A 1 2
156. linearity see Notes 10 13 LSB Ge gain error 40 4 Ae absolute voltage error see Notes 10 16 LSB channel to channel matching t 1 2 OSeg offset error 8 bit mode 1 Note 1 LSB OSe offset error see Notes 10 15 2 LSB 3 1 Ci crosstalk between analog inputs of Port 1 j 0 to 100 kHz see Notes 60 dB 17 18 2000 Jul 26 143 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 Notes to the DC characteristics 1 2 3 8 bit mode See Figures 62 through 64 for Ipp test conditions The operating supply current is measured with all output pins disconnected XTAL1 driven with tr t 10 ns ViL Vss 0 5 V j Vit Vbp 0 5 V XTAL2 not connected EA Port 0 Vpp RST Vss The Idle mode supply current is measured with all output pins disconnected XTAL1 driven with t t 2 10 ns Vit Vsg 0 5 V Vin 0 5 V XTAL2 not connected Port 0 RST Vpp EA Vgs The Power down current is measured with all output pins disconnected XTAL2 not connected RST Port 0 Vpp EA XTAL1 Vss The input threshold voltage of P1 6 and P1 7 SIO1 meets the I2C specification so an input voltage below 1 5 V will be recognized as a logic 0 while an input voltage above 3 0 V will be recognized as a logic 1 Pins of Port 1 except P1 6 P1 7 2 and 3 source a transition current when they are being e
157. lity Application information Where application information is given it is advisory and does not form part of the specification 30 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale 2000 Jul 26 160
158. ll other pins are disconnected 1 The following pins must be forced to Vpp EA and Port 0 2 The following pins must be forced to Vss AVss and RST 3 Port 1 6 and 1 7 should be connected to Vpp through resistors of sufficiently high value such that the sink current into these pins cannot exceed the loj 4 spec of the pins 4 The following pins must be disconnected XTAL2 and all pins not specified above 5 Note during reset active the power consumption will be reduced by an internal clock divider by two Fig 63 Ipp Test Conditions Active Mode 2000 Jul 26 154 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 VDD VDD P8xC591 n c XTAL2 CLOCK SIGNAL XTAL1 Vss MHI057 All other pins are disconnected 1 The following pins must be forced to Vpp Port 0 and RST 2 The following pins must be forced to Vss AVss and EA 3 Port 1 6 and 1 7 should be connected to Vpp through resistors of sufficiently high value such that the sink current into these pins cannot exceed 1 spec of the pins These pins must not have logic O written to them prior to this measurement 4 The following pins must be disconnected XTAL2 and all pins not specified above Fig 64 Ipp Test Condition Idle Mode 0 2 Vpp 0 1 0 5 V tCHCL 1058 Fig 65 Clock Signal Waveform for Ipp Te
159. mentation and Operation 15 3 Software Examples of SIO1 Service Routines 16 TIMER 2 Features of Timer 2 2000 Jul 26 17 18 18 1 18 2 18 3 19 20 1 20 2 21 1 WATCHDOG TIMER T3 PULSE WIDTH MODULATED OUTPUTS Prescaler Frequency Control Register PWMP Pulse Width Register 0 PWMO Pulse Width Register 1 PWM1 PORT 1 OPERATION ANALOG TO DIGITAL CONVERTER ADC ADC features ADC functional description 10 Bit Analog to Digital Conversion 10 Bit ADC Resolution and Analog Supply Power Reduction Modes INTERRUPTS Interrupt Enable Registers Interrupt Enable and Priority Registers Interrupt priority Interrupt Vectors INSTRUCTION SET Addressing Modes LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS Timing symbol definitions EPROM CHARACTERISTICS Program verification Security bits PACKAGE OUTLINES SOLDERING Plastic leaded chip carriers quad flat packs DEFINITIONS LIFE SUPPORT APPLICATIONS Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 1 FEATURES 1 1 80C51 Related Features of the 8xC591 Full static 80C51 Central Processing Unit available as OTP ROM and ROMless 16 Kbytes internal Program Memory expandable externally to 64 Kbytes 512 bytes on chip Data RAM expandable externally to 64 Kbytes Three 16 bit timers counters TO T1 standard 80C51 and additional T2 capture amp compare 10 bit ADC with 6 multiplexed analog inputs with fast 8 bi
160. mer 1 interrupt priority level 2 PX1 External interrupt 1 Seconds priority level 1 PTO Timer 0 interrupt priority level 0 PXO External interrupt 0 priority level 21 2 4 INTERRUPT PRIORITY HIGH REGISTER O IPOH Logic 0 low priority logic 1 high priority Table 99 Interrupt Priority High Register 0 address B7H 7 6 5 4 3 2 1 0 PADH PS1H PSOH PTIH PXIH PTOH PXOH Table 100Description of IPOH bits BIT SYMBOL DESCRIPTION Reserved for future use PADH ADC interrupt priority level PS1H 5101 I2C interrupt priority level PSOH 100 UART interrupt priority level PT1H Timer 1 interrupt priority level PX1H External interrupt 1 Seconds priority level PTOH Timer O interrupt priority level PXOH External interrupt 0 priority level 2000 Jul 26 133 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 21 2 5 INTERRUPT PRIORITY REGISTER 1 IP1 Logic 0 low priority logic 1 high priority Table 101 Interrupt Priority Register 1 address F8H a I ee PT2 PCAN PCM1 PCMO PCT3 PCT2 PCT1 PCTO Table 102Description of IP1 bits BIT SYMBOL DESCRIPTION 7 PT2 T2 overflow interrupt s priority level 6 PCAN CAN interrupt priority level 5 PCM1 T2 comparator 1 interrupt priority level 4 PCMO T2 comparator 0 interrupt priority level 3 PCT3 T2 capture register 3 in
161. mit next DATA 528 base 0x128 djnz NUMBYTMST NOTLDAT 1 JMP if NOT last DATA mov S1CON ENS1_NOTSTA_STO_NOTSI_AA_CRO clr SI set AA ajmp RETmt mts28sb base 0 000 NOTLDAT1 mov psw SELRB3 mov S1DAT r1 CON mov S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO clr SI set AA inc ri RETmt pop psw reti sect mts30 base 0x130 mov S1CON ZENS1 NOTSTA STO NOTSI AA CRO set STO cir SI pop psw reti STATE 38 Arbitration lost in SLA W or DATA ACTION Bus is released not addressed SLV mode is entered A new START condition is transmitted when the IIC bus is free again sect mts38 base 0x138 mov S1CON ZENS1 STA NOTSTO NOTSI AA CRO mov NUMBYTMST BACKUP ajmp RETmt JAKAKKAKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKK MASTER RECEIVER STATE SERVICE ROUTINES JAKAKKAKKKKKKKKAKKKKKKAKKKKKAKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKAKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKKKKKKKKAKKKKKKKKKKKKKKK I STATE 40 Previous state was STATE 08 or STATE 10 SLA R have been transmitted ACK received ACTION DATA will be received ACK returned sect mts40 base 0x140 mov S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO l clr STA STO SI set AA pop psw reti 107 Philips Semiconductors Single chip 8 bit microcontroller vvith GAN controller P8xC591 LOC OBJ SOURCE STATE 48 SLA R have been transmitted NOT ACK received ACTION STOP co
162. mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on chip RAM and Special Function Registers retain their values down to 2 0 V and care must be taken to return Voc to the minimum specified operating voltages before the Power down Mode is terminated A hardware reset or external interrupt can be used to exit from Power down The Wake up from Power down bit WUPD AUXR1 3 must be set in order for an interrupt to cause a Wake up from Power down Reset redefines all the SFRs but does not change the on chip RAM A Wake up allows both the SFRs and the on chip RAM to retain their values To properly terminate Power down the reset or external interrupt should not be executed before Vcc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize normally less than 10 ms Table 7 Status of external pins during Idle and Power down modes MODE MEMORY ALE PSEN PORTO PORT 1 PORT 2 PORT 3 Su Idle internal 1 1 port data port data port data port data high external 1 1 high Power down _ internal 0 port data port data port data port data high external 0 float port data port data port data high With an external interrupt INTO and INT1 must be enabled and configured as level sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes the exit Once the interrupt
163. n the transition from master transmitter to slave receiver is made with the correct data in S1DAT S1DAT and the ACK flag form a 9 bit shift register which shifts in or shifts out an 8 bit byte followed by an Table 53 Address Register S1DAT address DAH acknowledge bit The ACK flag is controlled by the SIO1 hardware and cannot be accessed by the CPU Serial data is shifted through the ACK flag into S1DAT on the rising edges of serial clock pulses on the SCL line When a byte has been shifted into S1DAT the serial data is available in S1DAT and the acknowledge bit is returned by the control logic during the ninth clock pulse Serial data is shifted out from S1DAT via a buffer BSD7 on the falling edges of clock pulses on the SCL line When the CPU writes to S1DAT BSD7 is loaded with the content of S1DAT 7 which is the first bit to be transmitted to the SDA line see Figure 36 After nine serial clock pulses the eight bits in S1DAT will have been transmitted to the SDA line and the acknowledge bit will be present in ACK Note that the eight transmitted bits are shifted back into S1DAT 7 6 5 4 3 2 1 0 SD7 SD6 SD5 Table 54 Description of S1DAT DAH bits BIT SYMBOL DESCRIPTION 7100 507 500 Eight bits to be transmitted or just received A logic 1 in SIDAT corresponds to a high level on the I2C bus and a logic 0 corresponds to a low level on the bus Serial data shifts through S1D
164. nal program memory are disabled from fetching code bytes from the internal memory EA is latched on Reset and all further programming of the EPROM is disabled When security bits 1 and 2 are programmed in addition to the above verify mode is disabled When all three security bits are programmed all of the conditions above apply and all external program memory execution is disabled LENS 581 SB2 SB3 PROTECTION DESCRIPTION 1 U U U No Program Security features enabled Code verify will still be encrypted by the Encryption Array if programmed 2 MOVC instructions executed from external Program Memory are disabled from 3 U fetching code bytes from internal memory EA is sampled and latched on reset and further programming of the EPROM is disabled Same as 2 also verify is disabled Same as 3 and external memory execution is disabled Note 1 Any other combination of the security bits is not defined 2000 Jul 26 157 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 27 PACKAGE OUTLINES PLCC44 plastic leaded chip carrier 44 leads SOT187 2 c rl SIA CUMULO E i 3 detail X 5 scale DIMENSIONS millimetre dimensions are derived from the or
165. nalog ground AVss and a positive analog reference pin Vref connected to each end of the DAC s resistance ladder The ladder has 1023 equally spaced taps separated by a resistance of R The first tap is located 0 5 x R above AVss and the last tap is located 1 5 x R below Vier This gives a total ladder resistance of 1024 x R This structure ensures that the DAC is monotonic and results in a symmetrical quantization error is shown in Figure 48 For input voltages between 0 V and 1 2 LSB the 10 bit result of an A D conversion will be 00 0000 0000B OOOOH For input voltages between Vier 3 2 LSB and Vjet the result of a conversion will be 11 1111 1111B SFFFH AV er may be between Vpp 0 2 V and AVss 0 2 V AVrer should be positive 0 V and AV ep If the analog input voltage range is from 2 V to 4 V the 10 bit resolution can be obtained over this range if 4 The result can always can always be calculated from the following formula Preliminary Specification P8xC591 20 5 Power Reduction Modes The P8xC591 has two reduced power modes of operation the Idle mode and the Power down mode These modes are entered by setting bits in the PCON Special Function Register When the P8xC591 enters the Idle mode the following functions are disabled CPU halted Timer T2 halted and reset PWMO PWM1 reset outputs are high ADC may be enabled for operation in Idle mode by setting bit AIDC AUXR1 6
166. nce Code 1 Acceptance Code 2 Acceptance Code 2 Acceptance Code 2 Acceptance Code 3 Acceptance Code 3 Acceptance Code 3 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 0 Acceptance Mask 0 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 1 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 2 Acceptance Mask 3 2000 Jul 26 Acceptance Mask 3 29 Acceptance Mask 3 Acceptance Mask 2 Acceptance Mask 3 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Preliminary Specification P8xC591 49 Acceptance Code 1 Acceptance Code 1 Acceptance Code 1 Acceptance Code 1 50 Acceptance Code 2 Acceptance Code 2 Acceptance Code 2 Acceptance Code 2 52 Acceptance Mask 0 Acceptance Mask 0 Acceptance Mask 0 Acceptance Mask 0 53 Acceptance Mask 1 Acceptance Mask 1 Acceptance Mask 1 Acceptance Mask 1 54 Acceptance Mask 2 Acceptance Mask 2 Acceptance Mask 2 Acceptance Mask 2 55 Acceptance Mask 3 Acceptance Mask 3 Acceptance Mask 3 Acceptance Mask 3 56 Acceptance Code 0 Acceptance Code 0 Acceptance Code 0 Acceptance Code 0 57 Acceptance Code 1 Acceptance Code 1 Acceptance Code 1 Acceptance Code 1 59 Acceptance Code 3 Acceptance Code 3 Acceptance Code 3 Acceptance Code 3 60 Acceptance Mask 0 Acceptance Mask 0 Acceptance Mask 0 Acceptance Mask 0 61 Acceptance Mask 1 Acc
167. ndition will be generated fe eee BS ee Se Sie eee ee tS Soe Stee Soe pe ae eo ee sa ss Sh S sect mts48 base 0x148 0148 75D8D5 STOP mov S1CON ZENS1 NOTSTA STO NOTSI AA CRO set STO clr SI 014B DODO pop psw 014D 32 reti EA Shere tte ere Giese irene alienare STATE 50 DATA have been received ACK returned ACTION Read DATA of S1DAT DATA will be received if it is last DATA then NOT ACK will be returned else ACK will be returned e e epee Se be BSS ato sect mrs50 base 0x150 0150 75D018 mov psw SELRB3 0153 A6DA mov r0 S1 DAT Read received DATA 0155 01C0 ajmp RECI sect mrs50s base 0 0 00 0 D55205 djnz NUMBYTMST NOTLDAT2 00C3 75D8C1 mov S1CON ZENS1 NOTSTA NOTSTO NOTSI NOTAA CRO clr SLAA 00C6 8003 sjmp RETmr 00C8 75D8C5 NOTLDAT2 mov S1CON ZENS1 NOTSTA NOTSTO NOTSI AA CRO clr SI set AA 00CB 08 RETmr inc ro 00CC DODO pop psw 32 reti e EN ISTATE 58 DATA have been received NOT ACK returned ACTION Read DATA of MASTER STATE SERVICE ROUTINESS1DAT and generate a STOP condition Ja t n end ph S So Sete et dere ey epee sect mrs58 base 0x158 0158 75D018 mov psw SELRB3 015B A6DA mov RO S1DAT 015D 80 9 sjmp STOP 2000 Jul 26 108 Preliminary Specification Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 LOC 0160 0163 0166 00DO 00
168. nected to are CTO CT1 CT2 and CT3 These registers are loaded with the contents of Timer T2 and an interrupt is requested upon receipt of the input signals CTOI CT11 CT2I or CTSI These input signals are shared with port 1 The four interrupt flags are in the Timer T2 interrupt register TM2IR special function register If the Preliminary Specification P8xC591 capture facility is not required these inputs can be regarded as additional external interrupt inputs INT2 to INTS Using the capture control register CTCON see Section 16 1 4 1 these inputs may capture on a rising edge a falling edge or on either a rising or falling edge The inputs are sampled during S1P1 of each cycle When a selected edge is detected the contents of Timer T2 are captured at the end of the cycle 16 1 4 1 Capture Control Register CTCON Table 72 Capture Control Register address EBH 7 6 5 4 3 2 1 0 CTN3 CTP3 CTN2 CTP2 CTNI CTP1 CTNO CTPO Table 73 Description of CTCON bits BIT SYMBOL DESCRIPTION 7 CTN3 Capture Register 3 triggered by a falling edge on CTSI 6 CTP3 Capture Register 3 triggered by a rising edge on CT3lI 5 CTN2 Capture Register 2 triggered by a falling edge on CT2l 4 CTP2 Capture Register 2 triggered by a rising edge on CT2l 3 CTN1 Capture Register 1 triggered by a falling edge on CT1I 2 CTP1 Capture Register 1 triggered by a rising edge on CT1I 1 CTNO Capture Register 0 triggered b
169. ning of the next message that is received after the current one If no further message is received parts of old messages may occur here 2 Register at address 8 performs NO system function reserved for future use 2000 Jul 26 31 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 12 5 CAN Registers 12 5 1 RESET VALUES Preliminary Specification P8xC591 Detection of a set Reset Mode bit results in aborting the current transmission reception of a message and entering the Reset Mode On the 1 to 0 transition of the Reset Mode bit the CAN controller returns to the mode defined within the Mode Register Table 12 Reset mode configuration X means that the values of these registers or bits are not influenced SETTING MOD 0 BY ADDR REGISTER SYMBOL SOFTWARE OR DUE TO BUS OFF 0 Mode TM Test Mode disabled 0 disabled reserved X reserved RPM Receive Polarity Mode active lovv 0 active high SM Sleep Mode vvake up 0 reserved 0 reserved STM Self Test Mode normal X no change LOM Listen Only Mode normal X no change RM Reset Mode present 1 present 1 Command reserved 0 reserved SRR Self Reception Request absent 0 absent CDO Clear Data Overrun no action 0 no action RRB Release Receive Buffer no action 0 no action AT Abort Transmission absent 0 absent TR Transmission Request absent
170. ns of at least one complete filter have to signal acceptance In case of a set RTR bit or a data length code of 0 no data byte is existing Nevertheless a message may pass Filter 1 if the first part up to the RTR bit signals acceptance If no data byte filtering is required for Filter 1 the four least significant bits of AMR1 and AMR3 have to be set 1 don t care Then both filters are working identically using the standard identifier range including the RTR bit Preliminary Specification P8xC591 Dual Filter Extended Frame If the Extended Frame Format is selected the two defined filters are looking identically Both filters are comparing the first two bytes of the Extended Identifier range only For a successful reception of a message all single bit comparisons of at least one complete filter have to signal acceptance 2000 Jul 26 MSB LSB MSB LSB Adar 16 ACRO Adar 17 ACRI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Filter 1 V MSB LSB MSB LSB Addr 20 AMRO Addr 21 AMRI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SEIFIEIEIEIEIENEEIEIEIEIPIEIE Message dld ala a a a a Na aia id G ala G Addr 22 AMR2 Addr 23 AMR3 7 6 5 4 3 2 1 0 7 6 5 4 8 2 1 0 MSB LSB MSB LSB Filter 2
171. ntents L Logic level LOW or ALE P PSEN Q output data R RD signal t time V valid W WR signal X no longer a valid logic level Z float Examples tavit time for address valid to ALE LOW tp time for ALE LOW to PSEN LOW Table 113 Program security bits for EPROM devices P programmed U unprogrammed Preliminary Specification P8xC591 26 EPROM CHARACTERISTICS The P8xC591 contains three signature bytes that can be read and used by an EPROM programming system to identify the device The signature bytes identify the device as an P8xC591 manufactured by Philips e 030H 15H indicates manufactured by Philips e 0031H 98H indicates Hamburg e 60H 01H indicates P87C591 26 1 If security bits 2 or 3 have not been programmed the on chip program memory can be read out for program verification Program verification If the encryption table has been programmed the data presented at port 0 will be exclusive NOR of the program byte with one of the encryption bytes The user will have to know the encryption table contents in order to correctly decode the verification data The encryption table itself cannot be read out 26 2 Security bits With none of the security bits programmed the code in the program memory can be verified If the encryption table is programmed the code will be encrypted when verified When only security bit 1 see Table 113 is programmed MOVC instructions executed from exter
172. o defined filters are different The first filler compares the complete Standard Identifier including the RTR bit and the first Data Byte of the message The second filter just compares the complete Standard Identifier including the RTR bit MSB LSB MSB LSB LSB Addr 16 ACRO Addr 17 ACRI ACR3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 3 2 1 o nu 1 i 5 MSB LSB MSB LSB LSB Addr 20 AMRO Addr 21 AMRI AMR3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 3 2 1 o injeelsjalnia Sese Message INININININI NIN 9 ain Addr 22 AMR2 Addr 23 AMR3 7 6 5 4 3 2 1 0 7 6 5 4 MSB LSB MSB Filter 2 Addr 18 ACR2 Addr 19 ACR3 7 6 5 4 312 1 0 7 6 5 4 MSB LSB MSB Filter 1 Acceptance Mask Bit Acceptance Code Bit Tp Message Bit Acceptance Code Bit Acceptance Mask Bit Filter 2 Fig 17 Dual Filter Configuration receiving Standard Frame Messages 1 accepted accepted MHI017 2000 Jul 26 53 Philips Semiconductors Single chip 8 bit microcontroller vvith GAN controller For a successful reception of a message all single bit compariso
173. ochange X no change 32 to 35 ACROto3 ACRO to ACR3 Acceptance Code Register X no change X no change 36 to 39 AMR 0 to 3 AMRO to AMR3 Acceptance Mask Register X no change X no change 40 to 43 ACR 0 to 3 ACRO to ACR3 Acceptance Code Register X no change X no change 44 to 47 AMR 0 to 3 AMRO to AMR3 Acceptance Mask Register X no change X nochange 48 to 51 ACR 0 to 3 ACRO to ACR3 Acceptance Code Register X no change X no change 52 to 55 AMR 0 to 3 Lo aj AMRO to AMR3 Acceptance Mask Register X no change X no change 56 to 59 Bank4 ACR 0 to 3 ACRO to ACR3 Acceptance Code Register X no change X no change 60 to 63 AMR 0 to 3 AMRO to AMR3 Acceptance Mask Register X nochange X nochange 96 to 108 Rx Buffer RXB Receive Buffer X empty 8 X empty 3 112 to 124 Tx Buffer me Transmit Buffer X nochange X no change 125 to 127 General Purpose RAM General Purpose RAM X no change X change Notes 1 On Bus Off the Error Warning Interrupt is set if enabled 2 fthe Reset Mode was entered due to a Bus off condition the Receive Error Counter is cleared and the Transmit Error Counter is initialized to 127 to count down the CAN defined Bus off recovery time consisting of 128 occurrences of 11 consecutive recessive bits 3 Internal read write pointers of the RXFIFO are reset to their initial values A subsequent read access to the RXB would show undefined data values parts of old messages If a message is transmi
174. ocontroller with CAN controller Preliminary Specification P8xC591 2 4V test points 0 45 V a float 24V 2 0V 2 0V 0 8V 0 8V 0 45 V b AC testing inputs are driven at 2 4 V for a HIGH and 0 45 V for a LOW Timing measurements are taken at 2 0 V for a HIGH and 0 8 V for a LOW see Fig 60 a 2 0 V 0 8 V 2 4V 0 45 V MGA174 The float state is defined as the point at which a Port 0 pin sinks 3 2 mA or sources 400 the voltage test levels see Fig 60 b Fig 60 AC testing input output waveform a and float waveform b 2000 Jul 26 152 Preliminary Specification Philips Semiconductors Single chip 8 bit microcontroller vvith CAN controller P8xC591 221 19 10 15 ELVG NS aai g o VISINS 4015 UONIPUOO LUVIS Uonipuoo Hv LS pereedo Liva ns MOT 15 uonipuoo 15 10 LUVIS indino indu 105 vas 153 2000 Jul 26 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 Ipp mA 50 maximum active Ipp 20 gt 3 6 9 12 MHz frequency at XTAL1 Fig 62 Ipp as a function of frequency P1 6 P1 7 RST P8xC591 n c XTAL2 CLOCK SIGNAL XTAL1 Vss MHI056 A
175. ods 0 low active RXD inputs are active low dominant 0 MOD 4 SM Sleep Mode 1 high active The CAN controller enters Sleep Mode if no CAN interrupt is Note 2 pending and there is no bus activity 0 low active woos resevwa MOD 2 STM Self Test Mode 1 self test In this mode a full node test is possible without any other Note 1 active node on the bus using the Self Reception Request command The CAN controller will perform a successful transmission even if there is no acknowledge received 0 normal An acknowledge is required for successful transmission MOD 1 LOM Listen Only 1 reset In this mode the CAN would give no acknowledge to the Mode Notes 1 CAN bus even if a message is received successfully No and 3 active error flags are driven to the bus The error counters are stopped at the current value 0 normal Normal communication MOD 0 RM Reset Mode 1 reset Setting the Reset Mode bit results in aborting the current Note 4 transmission reception of a message and entering the Reset Mode 0 normal On the 1 to 0 transition of the Reset Mode bit the CAN controller returns to the Operating Mode Notes 1 Awrite access to the bits MOD 1 MOD 2 MOD 5 MOD 6 and MOD 7 is possible only if the Reset Mode is entered previously 2 The PeliCAN Block will enter Sleep Mode if the Sleep Mode bit is set 1 sleep there is no bus activity and no interrupt is pending Setting
176. on It is set by software The ADC logic ensures that this signal is HIGH while the ADC is busy On completion of the conversion ADCS is reset immediately after the interrupt flag has been set ADCS cannot be reset by software A new conversion may not be started while either ADCS or ADCI is high see Table 90 If ADDCI is cleared by software while ADCS is set at the same time a new A D conversion with the same channel number may be started But it is recommended to reset ADCI before ADCS is set 2100 AADR2 to Analogue input select This binary coded address selects one of the six analogue port AADRO bits of P1 to be input to the converter It can only be changed when ADCI and ADCS are both LOW Table 90 ADC status ADCI ADCS ADC STATUS 0 0 ADC not busy a conversion can be started 0 1 ADC busy start of a new conversion is blocked 1 0 Conversion completed start of a new conversion requires ADCI 0 1 1 Conversion completed start of a new conversion requires ADCI 0 Table 91 Selected analog channel AADR2 AADR1 AADRO SELECTED ANALOG CHANNEL ADCO P1 2 ADC1 P1 3 P1 3 ADC2 P1 4 iP i 0 0 1 0 1 0 0 1 1 ADC3 P1 5 1 0 1 ADCS P1 7 2000 Jul 26 128 Philips Semiconductors Single chip 8 bit microcontroller vvith GAN controller 20 4 10 Bit ADC Resolution and Analog Supply Figure 48 shows how the ADC is realized The ADC has its own a
177. ontroller with CAN controller 28 SOLDERING 28 1 Plastic leaded chip carriers quad flat packs 28 1 1 BY WAVE During placement and before soldering the component must be fixed with a droplet of adhesive After curing the adhesive the component can be soldered The adhesive can be applied by screen printing pin transfer or syringe dispensing Maximum permissible solder temperature is 260 C and maximum duration of package immersion in solder bath is 10 s if allowed to cool to less than 150 C within 6 s Typical dwell time is 4 s at 250 C A modified wave soldering technique is recommended using two solder waves dual wave in which a turbulent wave with high upward pressure is followed by a smooth laminar wave Using a mildly activated flux eliminates the need for removal of corrosive residues in most applications 28 1 2 BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste a suspension of fine solder particles flux and binding agent to be applied to the substrate by screen printing stencilling or pressure syringe dispensing before device placement 29 DEFINITIONS Data sheet status Objective specification Preliminary Specification P8xC591 Several techniques exist for reflowing for example thermal conduction by heated belt infrared and vapour phase reflow Dwell times vary between 50 and 300 s according to method Typical reflow temperatures range from 215 to 250 C Preheating is necessa
178. or an Acceptance Filter Bank this single filter is related to the corresponding Filter 1 Enable Bit The Filter 2 Enable Bits have no influence within Single Filter Mode 2000 Jul 26 49 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 5 17 3 Acceptance Filter Priority Register For each available Acceptance Filter it could be defined whether a receive interrupt is forced immediately if a message passes a certain Acceptance Filter or whether the programmed Receive Interrupt Level should be used for interruption This allows to use certain Acceptance Filters for alarm message recognition interrupting the host CPU immediately Table 35 Acceptance Filter Priority Register ACF Priority CAN address 31 B4F2PRIO B4FiPRIO B3F2PRIO B3F1PRIO B2F2PRIO B2F1PRIO B1F2PRIO B1F1PRIO Table 36 Acceptance Filter Priority Register ACF Priority BIT SYMBOL NAME VALUE FUNCTION ACFPRIO 7 B4F2PRIO Bank 4 Filter 2 1 high JA receive interrupt is generated immediately if a message Priority passes Filter 2 vvithin Acceptance Filter Bank 4 0 low A receive interrupt is generated if the FIFO level exceeds the Receive Interrupt Level Register ACFPRIO 6 B4F1PRIO Bank 4 Filter 1 1 hi A receive interrupt is generated immediately if a message Priority passes Filter 1 within Acceptance Filter Bank 4 A receive interrupt is generated if the FIFO level exceeds
179. ority 1 F8h PT2 PCAN PCMI PCMO PCT3 PCT2 PCT1 PCTO 00H IP1H Interrupt Priority 1 high F7H PT2H 2 00H CANMOD CAN Mode Register C4H 00H CANCON CAN Command vv and C3H 00H Interrupt r CANDAT CAN Data C2H 00H CANADR CAN Address C1H 00H C7 C6 C5 C4 2 1 CANSTA CAN Status r COH BS ES TS RS TCS TBS DOS RBS 00H CAN Interrupt Enable w BEIE 2000 Jul 26 16 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller with CAN controller P8xC591 NAME B SEHIEHON Sm BIT FUNCTIONS AND ADDRESSES RESET MSB LSB P1M1 Port 1 output mode 1 92H FCH P1M2 Port 1 output mode 2 93H 00H P2M1 Port 2 output mode 1 94H 00H P2M2 Port 2 output mode 2 95H 00H P3M1 Port 3 output mode 1 9AH 00H P3M2 Port 3 output mode 2 9BH 00H B7 B6 B5 B4 B3 B2 B1 BO CSMR3 CSMR2 CSMR1 CSMRO RT2 T2 par Port 3 BOH RD WR TI INTO TXD RXD 7 A6 A5 A4 A3 A2 A1 2 Port 2 A15 A14 m3 ato A9 AB FFH 97 96 95 94 93 92 91 90 ADC5 ADC4 ADC3 ADC2 ADCI ADCO PI Port 1 90H SDA SCL cTal CTII CTOI TXDC RXDC FFH 87 86 85 84 83 82 81 80 Po Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 ADI ADO FFH PCON Power Control 87H SMOD1 SMODO POF WLE 1 GFO PD IDL 00x00000B PSW Program Status Word DOH CY AC FO RSI RSO OV 1 00H PWMP PWM Prescaler FEH
180. overflows flag T2B0 TM2CON is set and flag T20V TM2IR is set when TMH2 overflows These flags are set one cycle after an overflow occurs Note that when T20V is set T2BO will also be set To enable the byte overflow interrupt bits ET2 IEN1 7 enable overflow interrupt see Table 67 and T2180 TM2CON 6 byte overflow interrupt select must be set Bit TWBO TM2CON 4 is the Timer T2 byte overflow flag To enable the 16 bit overflow interrupt bits ET2 IE1 7 enable overflow interrupt and T2131 TM2CON 7 16 bit overflow interrupt select must be set Bit T2OV TM2IR 7 is the Timer T2 16 bit overflow flag All interrupt flags must be reset by software To enable both byte and 16 bit overflow T21S0 and T2181 must be set and two interrupt service routines are required A test on the overflow flags indicates which routine must be executed For each routine only the corresponding overflow flag must be cleared Timer T2 may be reset by a rising edge on RT2 P3 1 if the Timer T2 external reset enable bit T2ER in TM2CON is set This reset also clears the prescaler In the Idle mode the timer counter and prescaler are reset and halted Timer T2 is controlled by the TM2CON special function register see Section 16 1 1 Table 66 Timer T2 Interrupt Enable Register IEN1 address E8H 2000 Jul 26 e e ie i ET2 ECAN ECMI ECMO ECT3 ECT2 ECTI ECTO Table 67 Description of interrupt Enable Register IEN1 bits BIT
181. p 8 bit microcontroller with CAN controller P8xC591 CAN OPERATING MODE RESET MODE ADDR READ WRITE READ WRITE 115 Tx Data 1 Tx Identifier 3 Tx Data 1 Tx Identifier 3 Tx Data 1 Tx Identifier 3 Tx Data 1 Tx Identifier 3 116 Tx Data 2 Tx Identifier 4 Tx Data 2 Tx Identifier 4 Tx Data 2 Tx Identifier 4 Tx Data 2 Tx Identifier 4 117 Tx Data 3 Tx Data 1 Tx Data 3 Tx Data 1 Tx Data 3 Tx Data 1 Tx Data 3 Tx Data 1 118 Tx Data 4 Tx Data 2 Tx Data 4 Tx Data 2 Tx Data 4 Tx Data 2 Tx Data 4 Tx Data 2 119 Tx Data 5 Tx Data 3 Tx Data 5 Tx Data 3 Tx Data 5 Tx Data 3 Tx Data 5 Tx Data 3 120 Tx Data 6 Tx Data 4 Tx Data 6 Tx Data 4 Tx Data 6 Tx Data 4 Tx Data 6 Tx Data 4 121 Tx Data 7 Tx Data 5 Tx Data 7 Tx Data 5 Tx Data 7 Tx Data 5 Tx Data 7 Tx Data 5 122 Tx Data 8 Tx Data 6 Tx Data 8 Tx Data 6 Tx Data 8 Tx Data 6 Tx Data 8 Tx Data 6 123 TXB Memory Tx Data 7 TXB Memory Tx Data 7 TXB Memory Tx Data 7 TXB Memory Tx Data 7 124 TXB Memory Tx Data 8 TXB Memory Tx Data 8 TXB Memory Tx Data 8 TXB Memory Tx Data 8 125 to 127 General purpose RAM General purpose RAM General purpose RAM General purpose RAM 128 Internal RAM Address 0 FIFO Internal RAM Address 0 FIFO Internal RAM Address 0 FIFO 191 Internal RAM Address 63 FIFO Internal RAM Address 63 FIFO Internal RAM Address 63 FIFO Notes 1 These address locations reflect the FIFO RAM space behind the current message The contents are randomly after power up and contain the begin
182. ptance Filter compares the received identifier with the Acceptance Filter Table contents and decides whether this message should be accepted or not In case of a positive acceptance test the complete message is stored in the RXFIFO The ACF contains 4 independent Acceptance Filter banks supporting extended and standard CAN frames with change on the fly feature 12 2 5 BIT STREAM PROCESSOR BSP The Bit Stream Processor is a sequencer controlling the data stream between the Transmit Buffer RXFIFO and the CAN Bus It also performs the error detection arbitration stuffing and error handling on the CAN bus 12 2 6 ERROR MANAGEMENT LOGIC EML The EML is responsible for the error confinement of the transfer layer modules lt gets error announcements from the BSP and then informs the BSP and IML about error statistics 2000 Jul 26 Preliminary Specification P8xC591 12 2 7 Bit TIMING Loaic BTL The Bit Timing Logic monitors the serial CAN bus line and handles the Bus line related bit timing It synchronizes to the bit stream on the CAN Bus on a recessive to dominant Bus line transition at the beginning of a message hard synchronization and resynchronizes on further transitions during the reception of a message soft synchronization The BTL also provides programmable time segments to compensate for the propagation delay times and phase shifts e g due to oscillator drifts and to define the sampling time and
183. ration is chosen to be compatible with the Receive Buffer Layout see Section 12 5 19 1 The values marked with in the Transmit Buffer should be set to the values expected in the Receive Buffer for an easy comparison only when using the Self Reception facility otherwise they are don t care Table 37 Frame Format FF and Remote Transmission Request RTR bits BIT VALUE FUNCTION FF 1 EFF Extended Frame Format will be transmitted by the CAN controller 0 SFF Standard Frame Format will be transmitted by the CAN controller RTR 1 remote Remote Frame will be transmitted by the CAN controller 0 data Data Frame will be transmitted by the CAN controller 2000 Jul 26 56 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 5 18 3 Data Length Code DLC The number of bytes in the Data Field of a message is coded by the Data Length Code At the start of a Remote Frame transmission the Data Length Code is not considered due to the RTR bit being 1 remote This forces the number of transmitted received data bytes to be 0 Nevertheless the Data Length Code must be specified correctly to avoid bus errors if two CAN controllers start a Remote Frame transmission with the same identifier simultaneously The range of the Data Byte Count is 0 to 8 bytes and is coded as follows DataByteCount 8x DLC 3 4x DLC 2 2x DLC 1 DLC O For reasons of compati
184. re T3 is incremented every 1024 us derived from the oscillator frequency of 12 MHz by the following formula t 6 x 2048 x 1 fcLk 1024 us at fork 12 MHz If the 8 bit timer overflows a short internal reset pulse is generated which will reset the P8xC591 A short output reset pulse is also generated at the RST pin This short output pulse 3 machine cycles may be destroyed if the RST pin is connected to a capacitor This would not however affect the internal reset operation Watchdog operation is activated by setting the WDE bit in Special Function Register AUXR1 Once WDE is set it can only be disabled by applying a reset How to Operate the Watchdog Timer The watchdog timer has to be reloaded within periods that are shorter than the programmed watchdog interval otherwise the watchdog timer will overflow and a system reset will be generated The user program must therefore continually execute sections of code which reload the watchdog timer The period of time elapsed between execution of these sections of code must never exceed the watchdog interval When using a 12 MHz oscillator the watchdog interval is programmable between 1024 us and 261 ms In order to prepare software for watchdog operation a programmer should first determine how long his system can sustain an erroneous processor state The result will be the maximum watchdog interval As the maximum watchdog interval becomes shorter it becomes more
185. re registers and three 16 bit compare registers A capture register may be used to capture the contents of Timer T2 when a transition occurs on its corresponding input pin A compare register may be used to set or reset port 3 output pins at certain pre programmable time intervals The combination of Timer T2 and the capture and compare logic is very powerful in applications involving rotating machinery automotive injection systems etc Timer T2 and the capture and compare logic are shown in Figure 45 115 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 INT CTIIINT3 INTO CT2I INT4 INT CT3I INTS INT CT3 off 8 bit overflovv interrupt T2 COUNTER folk 1 6 PRESCALER 16 bit overflow interrupt T2 RT2 O T2ER 23552 external reset enable INT INTO COMP 3 2 5 R S R P3 3 5 R P34 VO port 3 CMO S CM2 S R P3 5 MHI046 STE RTE S set T2 SFR address TML2 lower 8 bits R reset TMH2 higher 8 bits reserved 1 to internal logic Fig 45 Block diagram of Timer 2 2000 Jul 26 116 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 16 1 4 CAPTURE LOGIC The four 16 bit capture registers that Timer T2 is con
186. resses them into a 5 bit code This code is unique for each 12C bus status The 5 bit code may be used to generate vector addresses for fast processing of the various service routines Each service routine processes a particular bus status There are 26 possible bus states if all four modes of SIO1 are used The 5 bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set by hardware and remains stable until the interrupt flag is cleared by software The three least significant bits of the status register are always zero If the status code is used as a vector to service routines then the routines are displaced by eight address locations Eight bytes of code is sufficient for most of the service routines see the software example in this section 15 2 10 THE FoUR SIO1 SPECIAL FUNCTION REGISTERS The microcontroller interfaces to SIO1 via four special function registers These four SFRs S1ADR S1DAT S1CON and S1STA are described individually in the following sections Philips Semiconductors Single chip 8 bit microcontroller with CAN controller 15 2 10 1 The Address Register SIADR The CPU can read from and write to this 8 bit directly addressable SFR S1ADR is not affected by the SIO1 hardware The contents of this register are irrelevant when SIO1 is in a master mode In the slave modes the seven most significant bits must be loaded with the microcontrollers own s
187. result is ready to be read ADCI is not cleared by hardware and must be reset by software to avoid recurring interrupts The SIO1 12C interrupt is generated by the SI flag in the SIO1 control register S1CON This flag is set when S1STA is loaded with a valid status code The ADCI flag may be reset by software It cannot be set by software All other flags that generate interrupts may be set or cleared by software and the effect is the same as setting or resetting the flags by hardware Thus interrupts may be generated by software and pending interrupts can be cancelled by software A CAN interrupt is generated vector address 006BH when one or more bits of CANCON register are set refer to CAN Section 12 5 5 Interrupt Register IR for details 2000 Jul 26 131 Preliminary Specification P8xC591 21 1 Interrupt Enable Registers Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable Special Function Registers IENO and IEN1 All interrupt sources can also be globally enabled or disabled by setting or clearing bit EA in IENO The interrupt enable registers are described in Section 21 2 1 and 21 2 2 There are 3 SFRs associated with each of the four level interrupts They are the IENx IPx and IPxH see Section 21 2 3 to 21 2 6 The IPxH Interrupt Priority High register makes the four level interrupt structure possible The function of the IPXH SFR is simple an
188. results in transmitting a message once No re transmission will be performed in case of an error or arbitration lost single shot transmission Setting the command bits CMR 4 and CMR 1 simultaneously results in sending the transmit message once using the self reception feature No re transmission will be performed in case of an error or arbitration lost Setting the command bits CMR 0 CMR 1 and CMR 4 simultaneously results in transmitting a message once as described for CMR 0 and CMR 1 The moment the Transmit Status bit is set within the Status Register the internal Transmission Request Bit is cleared automatically Setting CMR 0 and CMR 4 simultaneously will ignore the set CMR 4 bit 12 5 4 STATUS REGISTER SR The content of the Status Register reflects the status of the CAN controller The Status Register appears to the CPU as a read only memory Table 15 Status Register SR CAN Addr 2 bit interpretation BIT SYMBOL FUNCTION SR 7 Bus Status Note 1 1 Bus Off The CAN controller is not involved in bus activities The CAN controller is involved in bus activities SR 6 Error Status Note 2 1 error At least one of the error counters has reached or exceeded the CPU vvarning limit Both error counters are below the warning limit SR 5 Transmit Status The CAN controller is transmitting a message Note 3 SR 4 Receive Status The CAN controller is receiving a message Note 3 idle SR 3 Transmission complete Last requested
189. riod may be shortened or lengthened by one resynchronization tsJw tgci X 2x SJW 1 SJW 0 1 2000 Jul 26 40 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 5 9 Bus TIMING REGISTER 1 BTR1 The contents of Bus Timing Register 1 defines the length of the bit period the location of the sample point and the number of samples to be taken at each bit time This register can be accessed read write if the Reset Mode is active In Operating Mode this register is read only Table 20 Bus Timing Register 1 BTR1 CAN address 7 UE ee a eae SAM TSEG2 2 TSEG2 1 TSEG2 0 TSEG1 3 TSEG1 2 TSEG1 1 TSEG1 0 12 5 9 1 Sampling SAM Table 21 Sampling SAM BIT VALUE FUNCTION SAM 1 triple The bus is sampled three times recommended for lovvimedium speed buses class A and B vvhere filtering spikes on the bus line is beneficial 0 once The bus is sampled once gt recommended for high speed buses SAE class C 12 5 9 2 Time Segment 1 TSEG1 and Time Segment 2 TSEG2 TSEG1 and TSEG2 determine the number of clock cycles per bit period and the location of the sample point isvNcsEG tTsEG1 sci 8 x TSEG1 3 4 x TSEG1 2 2 x TSEG1 1 TSEG1 0 1 tTsEG2 tscl 4 x TSEG2 2 2 x TSEG2 1 TSEG2 0 1 uc l baud rate prescaler tSYNCSEG 5 1 gt lt ITSEG2
190. rogrammed operating mode different paths are selected for the baud rate clock generation Figure 23 shows the dependencies of the serial port baud rate clock generation on the two control bits and from the mode which is selected in the Special Function Register SCON TIMER 1 overflow SOPSH 7 SCON 7 5 5 SCON 6 BAUD SMO FE RATE GENERATOR 50 5 SOPSL MHI024 only one mode can be selected Note The switch configuration shows the reset state Fig 23 Baud Rate Generation for the Serial Port 2000 Jul 26 62 Philips Semiconductors Single chip 8 bit microcontroller vvith GAN controller 14 3 4 BAUD RATE IN MODE 0 The baud rate in Mode 0 is fixed to Mode 0 baud rate oscillator frequency 14 3 5 BAUD RATE IN MODE 2 The baud rate in Mode 2 depends on the value of bit SMODI in Special Function Register PCON If SMOD1 0 which is the value after reset the baud rate is 1 55 of oscillator frequency If SMOD1 1 the baud rate is 1 6 of the oscillator frequency SMODI Mode 2 baud rate 32 x oscillator frequency 14 3 6 BAUD RATE IN MODE 1 AND 3 In these modes the baud rate is variable and can be generated alternatively by a baud rate generator or by Timer 1 BAUD RATE SOPSH SOPSL Preliminary Specification P8xC591 14 3 7 USING THE INTERNAL BAUD RATE GENERATOR In Modes 1 and 3 the P8xC591 can use an internal baud rate gener
191. rupt Error Passive Status at least one error counter exceeds the CAN protocol defined level of 127 or if the CAN controller is in Error Passive Status and enters the Error Active Status again and the EPIE bit is set within the Interrupt Enable Register IR 4 Wake Up Interrupt This bit is set when the CAN controller is sleeping and bus Note 1 activity is detected and the WUIE bit is set within the Interrupt Enable Register IR 3 Data Overrun This bit is set on a 0 to 1 change of the Data Overrun Status Interrupt bit when the Data Overrun Interrupt Enable is set to 1 enabled IR 2 Error Interrupt This bit is set on every change set and clear of either the Error Status or Bus Status bits if the Error Interrupt Enable is set to 1 enabled IR 1 TI Transmit Interrupt 1 set This bit is set whenever the Transmit Buffer Status changes Note 2 from 0 to 1 released and Transmit Interrupt Enable is set to 1 enabled 0 reset IR 0 RI Receive Interrupt 1 set This bit is set whenever the RXFIFO is filled with more bytes Note 2 than specified in the Rx Interrupt Level register or a message has passed an acceptance filter which is set to high priority and the RIE bit is set within the Interrupt Enable Register 0 reset 2000 Jul 26 38 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Notes to Table 16 Preliminary Specification P8xC591
192. ry to dry the paste and evaporate the binding agent Preheating duration 45 min at 45 C 28 1 3 REPAIRING SOLDERED JOINTS BY HAND HELD SOLDERING IRON OR PULSE HEATED SOLDER TOOL Fix the component by first soldering two diagonally opposite end pins Apply the heating tool to the flat part of the pin only Contact time must be limited to 10 s at up to 300 C When using proper tools all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C Pulse heated soldering is not recommended for SO packages For pulse heated solder tool resistance soldering of VSO packages solder is applied to the substrate by dipping or by an extra thick tin lead plating before package placement This data sheet contains target or goal specifications for product development Preliminary specification Product specification This data sheet contains preliminary data supplementary data may be published later This data sheet contains final product specifications Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied Exposure to limiting values for extended periods may affect device reliabi
193. s No S1DAT action or Data byte will be received and NOT ACK OOH has been will be returned received ACK has been no S1DAT action Data byte will be received and ACK will be returned returned 78H Arbitration lost in No S1DAT action or Data byte will be received and NOT ACK SLA R W as master will be returned General call address ng SIDAT action Data byte will be received and ACK will be has been received ACK returned has been returned 80H Previously addressed Read data byte or Data byte will be received and NOT ACK with own SLV address will be returned DATA has been received ACK has been read data byte Data byte will be received and ACK will be returned returned 88H Previously addressed Read data byte or 0 0 0 Switched to not addressed SLV mode no with own SLA DATA recognition of own SLA or General call byte has been received address NOT has been read data byte or 0 0 0 Switched to not addressed SLV mode returne Own SLA will be recognized General call address will be recognized if S1ADR 0 logic 1 read data byte or 1 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free read data byte 1 0 0 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if S1ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 90H Previously addressed Read data byte or
194. s codes in S1STA are possible There are 18H 20H or 38H for the master mode and also 68H 78H or BOH if the slave mode was enabled AA logic 1 The appropriate action to be taken for each of these status codes is detailed in Table 61 After a repeated start condition state 10H SIO1 may switch to the master receiver mode by loading S1DAT with SLA R bit rate 15 2 14 2 Master Receiver Mode In the master receiver mode a number of data bytes are received from a slave transmitter see Figure 38 The transfer is initialized as in the master transmitter mode When the start condition has been transmitted the interrupt service routine must load S1DAT with the 7 bit slave address and the data direction bit SLA R The SI bit in S1CON must then be cleared before the serial transfer can continue When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received the serial interrupt flag SI is set again and a number of status codes in S1STA are possible These are 40H 48H or 38H for the master mode and also 68H 78H or BOH if the slave mode was enabled AA logic 1 The appropriate action to be taken for each of these status codes is detailed in Table 62 ENS1 CR1 and CRO are not affected by the serial transfer and are not referred to in Table 62 After a repeated start condition state 10H SIO1 may switch to the master transmitter mode by loading SIDAT with SLA W 15 2
195. sable see Fig 6 2 The Upper 128 bytes of RAM addresses 80H to FFH are indirectly addressable 3 The Special Function Registers SFRs addresses 80H to FFH are directly addressable only All these SFRs are described in Table 4 4 The 256 bytes AUX RAM 00H FFH are indirectly accessed by move external instruction MOVX and within the EXTRAM bit cleared see Table 3 The Lower 128 bytes can be accessed by either direct or indirect addressing The Upper 128 bytes can be accessed by indirect addressing only The Upper 128 bytes occupy the same address space as the SFR That 2000 Jul 26 Preliminary Specification P8xC591 means they have the same address but are physically separate from SFR space When an instruction accesses an internal location above address 7FH the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction Instructions that use direct addressing access SFR space For example 0A0H data accesses the SFR at location OAOH which is P2 Instructions that use indirect addressing access the Upper 128 bytes of data RAM For example MOV RO data where RO contains OAOH accesses the data byte at address OAOH rather than P2 whose address is OAOH The AUX RAM can be accessed by indirect addressing with EXTRAM bit cleared and MOVX instructions This part of memory is physically located on chip logically occupi
196. shifted to the right one position As data bits shift out to the right zeros come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9 position is just to the left of the MSB and all positions to the left of that contain zeros This condition flags the TX Control block to do one last shift and then deactivate SEND and set T1 Both of these actions occur at S1P1 of the 10 machine cycle after write to SOBUF Reception is initiated by the condition REN 1 and R1 0 At S6P2 of the next machine cycle the RX Control unit writes the bits 11111110 to the receive shift register and in the next clock phase activates RECEIVE RECEIVE enable SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle At S6P2 of every machine cycle At S6P2 of every machine cycle in which RECEIVE is active the contents of the receive shift register are shifted to the left one position The value that comes in from the right is the value that was sampled at the P3 0 pin at S5P2 of the same machine cycle As data bits come in from the right 1s shift out to the left When the 0 that was initially loaded into the weightiness position arrives at the left most position in the shift register it flags the RX Control block to do one last shift and load SOBUF At S1P1 of the 10 machine cycle after t
197. sion Reading out SOBUF accesses a physically separate receive register Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 14 3 Baud Rate Generation divided by 16 results in the actual baud rate However all formulas given in the following section already include the factor and calculate the final baud rate Further the abbreviation fcLk refers to the external clock frequency oscillator or external input clock operation There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating For clarification some terms regarding the difference between baud rate clock and baud rate should be mentioned The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization Therefore the baud rate generators have to provide a baud rate clock to the serial interface which there The baud rate of the serial port is controlled by the two bits SPS and SMOD1 which are located in the Special Function Registers SOPSH and PCON In SFRs SOPSH and SOPSL the prescaler load value of the internal baud rate generator can be programmed see Table 38 to 43 14 3 1 INTERNAL BAUD RATE GENERATOR PRESCALER SOPSH SOPSL Table 38 Internal Baud Rate Generator Prescaler Low Register SOPSL address FAH Prescaler load value 7 6 5 4 3 2 1 0 prescaler load value Table 39
198. so loads TB8 into the 9 bit position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission commences at S1P1 of the machine cycle following the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the write to SUB signal The transmission begins with activation of SEND which puts the start bit at TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to TxD The first shift pulse occurs one bit time after that The first shift clocks a 1 the stop bit into the 9 bit position of the shift register Thereafter only zeros are clocked in Thus as data bit shift out to the right zeros are clocked in from the left When TB8 is at the output position of the shift register then the stop bit is just to the left of TB8 and all positions to the left of that contain zeros This condition flags the TX Control unit to do one last shift 2000 Jul 26 Preliminary Specification P8xC591 and then deactivate SEND and set TI This occurs at the 119 divide by 16 rollover after write to SUBF Reception is initiated by a detected 1 to 0 transition at RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFH is written to the input shift register
199. stal pin 2 output of the inverting amplifier that forms the oscillator Left open circuit when an external oscillator clock is used XTAL1 15 Crystal pin 1 input to the inverting amplifier that forms the oscillator and input to the internal clock generator Receives the external oscillator clock signal when an external oscillator is used Vss 16 Ground circuit ground potential Vpp 17 23 Power supply power supply pin during normal operation and power reduction modes 2000 Jul 26 9 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller Preliminary Specification P8xC591 SYMBOL PIN QFP44 PLCC44 DESCRIPTION P2 0 A08 to P2 7 A15 ALE PROG EA Vpp P0 0 ADO to P0 7 AD7 18 to 25 24 to 31 26 27 29 30 to 37 36 to 43 38 44 Port 2 P2 0 to P2 7 8 bit programmable port lines A08 to A15 High order address byte for external memory Alternate function High order address byte for external memory A08 A15 Port 2 is also used to input the upper order address during EPROM programming and verification A8 is on P2 0 A9 on P2 1 through A12 on P2 4 During reset Port 2 will be asynchronously driven HIGH Port 2 has four output modes selected on a per bit basis by writing to the P2M1 and P2M2 registers as follows P2M1 x P2M2 x Mode Description 0 0 Pseudo bidirectional standard c51 configuration default 0 1 Push Pull 1
200. sted 0 disabled IER 5 Error Passive 1 enabled If the error status of the CAN controller changes from error Interrupt Enable active to error passive or vice versa the respective interrupt is requested 0 disabled IER 4 Wake Up Interrupt 1 enabled If the sleeping CAN controller wakes up the respective interrupt Enable is requested 0 disabled IER 3 Data Overrun 1 enabled If the Data Overrun Status bit is set see Status Register the Interrupt Enable CAN controller requests the respective interrupt 0 disabled IER 2 EIE Error Interrupt 1 enabled If the Error or Bus Status change see Status Register the Enable CAN controller requests the respective interrupt 0 disabled IER 1 TIE Transmit Interrupt 1 enabled When a message has been successfully transmitted or the Enable Transmit Buffer is accessible again e g after an Abort Transmission command the CAN controller requests the respective interrupt 0 disabled IER O RIE Receive Interrupt 1 enabled When the Receive Buffer Status is full the CAN controller Enable requests the respective interrupt 0 disabled 2000 Jul 26 39 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 5 7 RX INTERRUPT LEVEL RIL The RIL register is used to define the receive interrupt level for the RXFIFO A receive interrupt is generated if the number of valid CAN message bytes in the RXFIF
201. sts in Active and Idle Modes tcLcH tcHer 10 ns 2000 Jul 26 155 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 VDD VDD P8xC591 n c XTAL2 CLOCK SIGNAL XTAL1 Vss MHI057 All other pins are disconnected Vpp 2 V to 5 5 V 1 The following pins must be forced to Vpp Port 0 and RST 2 The following pins must be forced to Vss AVss and EA 3 Port 1 6 and 1 7 should be connected to Vpp through resistors of sufficiently high value such that the sink current into these pins cannot exceed the Io_1 spec of the pins These pins must not have logic 0 written to them prior to this measurement 4 The following pins must be disconnected XTAL2 and all pins not specified above Fig 66 Ipp Test Condition Power down Mode 2000 Jul 26 156 Philips Semiconductors Single chip 8 bit microcontroller vvith GAN controller 25 1 Timing symbol definitions Oscillator fox clock frequency telk clock period Timing symbols acronyms Each timing symbol has five characters The first character is always a t time the remaining four characters of the symbol typed in subscript depending on their relative positions indicate the name of a signal or the logical status of that signal the designations are as follows A address C clock D input data H logic level HIGH 1 instruction program memory co
202. t ADC option Two 8 bit resolution Pulse Width Modulated outputs 32 VO port pins in the standard 80C51 pinout I2C bus serial I O port with byte oriented master and slave functions On chip Watchdog Timer T3 Extended temperature range 40 to 85 C Accelerated prescaler 1 1 instruction cycle time 500 ns 12 MHz Operation voltage range 5 V 5 Security bits ROM version has 2 bits OTP EPROM version has 3 bits 32 bytes Encryption array 4 level priority interrupt 15 interrupt sources Full duplex enhanced UART with programmable Baudrate Generator Power Control Modes Clock can be stopped and resumed Idle Mode Power down Mode ADC active in Idle Mode Second DPTR register ALE inhibit for EMI reduction Programmable I O port pins pseudo bi directional push pull high impedance open drain Wake up from Power down by external interrupts Software reset bit AUXR1 5 Low active reset pin Power on detect reset Once mode 2000 Jul 26 Preliminary Specification P8xC591 1 2 CAN Related Features of the 8xC591 1 2 1 CAN 2 0B active controller supporting 11 bit Standard and 29 bit Extended indentifiers 1 Mbit s CAN bus speed with 8 MHz clock achievable 64 byte receive FIFO can capture sequential Data Frames from the same source as required by the Transport Layer of higher protocols such as DeviceNet CANopen and OSEK 13 byte transmit buffer Enhanced PeliCAN core from t
203. ta direction bit which must be 1 R for SIO1 to operate in the slave transmitter mode After its own slave address and the R bit have been received the serial interrupt flag SI is set anda valid status code can be read from S1STA This status code is used to vector to an interrupt service routine and the appropriate action to be taken for each of these status codes is detailed in Table 64 The slave transmitter mode may also be entered if arbitration is lost while SIO1 is in the master mode see state BOH If the AA bit is reset during a transfer SIO1 will transmit the last byte of the transfer and enter state COH or C8H SIO1 is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer Thus the master receiver receives all 1s as serial data While AA is reset SIO1 does not respond to its own slave address or a general call address However the I C bus is still monitored and address recognition may be resumed at any time by setting AA This means that the AA bit may be used to temporarily isolate SIO1 from the I C bus 15 2 14 5 Miscellaneous States There are two S1STA codes that do not correspond to a defined SIO1 hardware state see Table 65 These are discussed below S1STA F8H This status code indicates that no relevant information is available because the serial interrupt flag SI is not yet set This occurs between other states and when SIO1 is not involved in a ser
204. tandard Serial Interface 80C51 Based 8 Bit Microcontrollers In addition the UART can perform framing error detect by looking for missing stop bits and automatic address recognition The UART also fully supports multiprocessor communication as does the standard 80C51 UART When used for framing error detect the UART looks for missing stop bits in the communication A missing bit will set the FE bit in the SOCON register The FE bit shares the SOCON 7 bit with SMO and the function of SOCON 7 is determined by PCON 6 SMODO see Table 50 If SMODO is set then SOCON 7 functions as FE SOCON 7 functions as SMO when SMODO is cleared When as FE SOCON 7 can only be cleared by software Refer to Figure 25 14 5 2 SERIAL PORT CONTROL REGISTER SOCON Table 49 Serial Port Control Register address 98H Preliminary Specification P8xC591 14 5 1 AUTOMATIC ADDRESS RECOGNITION Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SOCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag RI will be automatically set when the received byte contains either the Given address or the Broadcast address The 9
205. te 3 118 TX Data byte 4 119 TX Data byte 5 120 TX Data byte 6 121 TX Data byte 7 122 TX Data byte 8 123 unused 124 unused CAN Address Extended Frame Format EFF MHI023 Fig 19 Transmit Buffer Layout for Standard and Extended Frame Format configurations 2000 Jul 26 55 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 5 18 2 Descriptor Field of the Transmit Buffer Standard Frame Format SFF Extended Frame Format EFF Addr 112 TX Frame Information Addr 112 TX Frame Information 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FF RTR 0 0 DLC 3 DLC 2 DLC 1 DLC O FF RTR 0 0 DLC 3 DLC 2 DLC 1 DLC O Addr 113 TX Identifier 1 Addr 113 TX Identifier 1 Addr 114 TX Identifier 2 Addr 114 TX Identifier 2 7 4 3 2 1 0 7 4 0 ID 20 RTR 0 0 0 0 ID 20 ID 17 ID 13 Meaning of the Transmit Buffer Bits Addr 115 TX Identifier 3 ID x Identifier bit x EE IRAE AE E FF Frame Format ID 12 ID 11 ID 10 ID 9 ID 8 ID 7 ID 6 ID 5 RTR Remote Transmission Request DECOR Data Length Addr 116 TX Identifier 4 X don t care 0 don t care but recommended to be 7 6 5 4 3 2 1 0 compatible to Receive Buffer ID 4 1D 3 ID 2 ID 1 ID 0 0 0 Fig 20 Bit Layout Transmit Buffer This configu
206. terrupt priority level 2 PCT2 T2 capture register 2 interrupt priority level 1 PCT1 T2 capture register 1 interrupt priority level 0 PCTO T2 capture register O interrupt priority level 21 2 6 INTERRUPT PRIORITY REGISTER HIGH 1 IP1H Logic 0 low priority logic 1 high priority Table 103Interrupt Priority Register High 1 address F7H 7 6 5 4 3 2 1 0 PT2 PCANH PCM1H PCMOH PCT3H PCT2H PCT1H PCTOH Table 104Description of IP1H bits BIT SYMBOL DESCRIPTION 7 PT2 T2 overflow interrupt s priority level 6 PCANH CAN interrupt priority level high 5 PCM1H T2 comparator 1 interrupt priority level 4 PCMOH T2 comparator 0 interrupt priority level 3 PCTSH T2 capture register 3 interrupt priority level 2 PCT2H T2 capture register 2 interrupt priority level 1 PCT1H T2 capture register 1 interrupt priority level 0 PCTOH T2 capture register O interrupt priority level 2000 Jul 26 134 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 21 3 Interrupt priority 21 4 Interrupt Vectors Table 105 Interrupt priority structure The vector indicates the Program Memory location where rana a PRIORITY interrupt service routine starts see VVITHIN LEVEL External interrupt 0 highest Table 106 Interrupt vector addresses SIO1 PC 1 T SOURCE SYMBOL VECTOR ADG complet
207. th two flip flops a command flip flop which is affected by Set operations and a status flag which is accessed during read operations 2000 Jul 26 10 BIT A D CONVERTER peo fe Ee pps pe pe p ep e poses E INTERNAL BUS Fig 48 Functional diagram of Analog Input Circuitry Preliminary Specification P8xC591 ANALOG REF ANALOG GROUND 1050 The next two machine cycles are used to initiate the converter At the end of the first cycle the ADCS status flag is set and a value of 1 will be returned if the ADCS flag is read while the conversion is progress Sampling of the analog input commences at the end of the second cycle During the next eight machine cycles the voltage at the previously selected pin of port 1 is sampled and this input voltage should be stable in order to obtain a useful sample In any event the input voltage slew rate must be less than 10 V ms in order to prevent an undefined result The successive approximation control logic first sets the most significant bit and clears all other bits in the successive approximation register 10 0000 0000B The output of the DAC 50 full scale is compared to the input voltage Vin If the input voltage is greater than VDAC then the bit remains set otherwise it is cleared The successive approximation control logic now sets the next most significant bit 11 0000 0000B or 01 0000 0000B depending on the previous result and VDAC is compare
208. the I C bus 14 SIO0 STANDARD SERIAL INTERFACE UART The serial port is full duplex meaning it can transmit and receive simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the register However if the first byte still hasn t been read by the time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both accessed at Special Function Register transmit registers are both accessed at Special Function Register SOBUF Writing to SOBUF loads the transmit register and reading SOBUF accesses a physically separate receive register The serial port can operate in 4 modes one synchronous mode three asynchronous modes The baud rate clock for the serial port is derived from the oscillator frequency mode 0 2 or generated either by timer 1 or by dedicated baud rate generator mode 1 3 Mode 0 Shift Register Synchronous Mode Serial data enters and exits through RxD TxD outputs the shift clock 8 bits are transmitted received LSB first The baud rate is fixed Ve the oscillator frequency 8 bit UART Variable Baud Rate 10 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in Special Function Register SCON The baud rate is variable 9 bit UART Fixed Baud
209. the Interrupt Enable Register depending on the direction of the access Reading CANSTA is an access to the Status Register of the PeliCAN address 2 When writing to CANSTA the Interrupt Enable Register is accessed address 4 12 3 6 CANCON The CANCON SFR provides a direct access to the Interrupt Register of the PeliCAN as well as to the Command register depending on the direction of the access When reading CANCON the Interrupt Register of the PeliCAN is accessed address 3 while writing to CANCON means an access to the Command Register address 1 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 4 Register and Message Buffer description 12 4 1 ADDRESS LAYOUT The PeliCAN internal registers appear to the host CPU as on chip memory mapped peripheral registers Because the PeliCAN can operate in different modes Operating Reset see also Mode Register one have to distinguish between different internal address definitions Starting from CAN Address 128 the complete internal FIFO RAM is mapped to the CPU Interface Table 11 Address allocation CAN OPERATING MODE RESET MODE ADDR Mode Mode Mode Interrupt 00 Command 00 Interrupt Command E em E LL Interrupt Enable Bus Timing 0 Interrupt Enable Rx Interrupt Level Rx Interrupt Level Interrupt Enable Rx Interrupt Level Bus Timing 0 Interrupt
210. the Receive Interrupt Level Register ACFPRIO 5 B3F2PRIO Bank 3 Filter 2 1 hi A receive interrupt is generated immediately if a message Priority passes Filter 2 within Acceptance Filter Bank 3 A receive interrupt is generated if the FIFO level exceeds the Receive Interrupt Level Register ACFPRIO 4 BSF1PRIO Bank 3 Filter 1 1 hi A receive interrupt is generated immediately if a message Priority passes Filter 1 within Acceptance Filter Bank 3 A receive interrupt is generated if the FIFO level exceeds the Receive Interrupt Level Register ACFPRIO 3 B2F2PRIO Bank 2Filter 2 1 hi A receive interrupt is generated immediately if a message Priority passes Filter 2 within Acceptance Filter Bank 2 A receive interrupt is generated if the FIFO level exceeds the Receive Interrupt Level Register ACFPRIO 2 B2F1PRIO Bank 2 Filter 1 1 hi A receive interrupt is generated immediately if a message Priority passes Filter 1 within Acceptance Filter Bank 2 A receive interrupt is generated if the FIFO level exceeds the Receive Interrupt Level Register ACFPRIO 1 B1F2PRIO Bank 1 Filter 2 1 hi A receive interrupt is generated immediately if a message Priority passes Filter 2 within Acceptance Filter Bank 1 A receive interrupt is generated if the FIFO level exceeds the Receive Interrupt Level Register ACFPRIO 0 B1F1PRIO Bank 1 Filter 1 1 high A receive interrupt is generated immediately if a message Priority pass
211. the transfer direction is reversed Serial data is transmitted via P1 7 SDA while the serial clock is input through P1 6 SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application SIO1 may operate as a master and as a slave In the slave mode the SIO1 hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontroller wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode SIO1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 VDD Rp 5 SCL P1 7ISDA P1 61SCL OTHER DEVICE VVITH OTHER DEVICE VVITH 8xC591 12C INTERFACE 12C INTERFACE MHI031 Fig 30 Typical I C Bus configuration m 1 x I STOP 7 4 condition gt L repeated M x START I I Le slave address R W condition I I direction acknowledgment I bit Signal from receiver Ce A I I acknowledgment I I signal from receiver clock line held low while I i i interrupts are s
212. to change the behaviour of the CAN controller Control bits may be set or reset by the CPU which uses the Command Register as a write only memory Table 14 Command Register CMR CAN Addr 1 bit interpretation BIT SYMBOL NAME VALUE FUNCTION CMR 7 reserved to CMR 5 CMR 4 SRR Self Reception Request 1 present A message shall be transmitted and received Notes 1 and 6 simultaneously CMR 3 CMR 2 RRB Release Receive Buffer The Receive Buffer representing the message Note 3 memory space in the RXFIFO is released 0 no action CMR 1 Abort Transmission 1 present If not already in progress a pending Transmission Notes 4 and 6 Request is cancelled 0 absent CMR 0 TR Transmission Request 1 present A message shall be transmitted Notes 5 and 6 0 absent Notes 1 Upon Self Reception Request a message is transmitted and simultaneously received if the acceptance filter is set to the corresponding identifier A receive and a transmit interrupt will indicate correct self reception see also Self Test Mode in Mode Register 2 This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit As long as the Data Overrun Status bit is set no further Data Overrun Interrupt is generated 3 After reading the contents of the Receive Buffer the CPU can release this memory space of the RXFIFO by setting the Release Receive Buffer bit 1 This may result in another message
213. transmission has been successfully Complete Status completed Note 4 0 incomplete Previously requested transmission is not yet completed SR 2 Transmit Buffer 1 released The CPU may write a message into the Transmit Status Note 5 Buffer 0 locked The CPU cannot access the Transmit Buffer A message is either waiting for transmission or is in transmitting process SR 1 Data Overrun Status 1 overrun A message was lost because there was not enough Note 6 space for that message in the RXFIFO 0 absent No data overrun has occurred since the last Clear Data Overrun command was given SR 0 Receive Buffer One or more complete messages are available in the Status Note 7 RXFIFO No message is available 2000 Jul 26 36 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 Notes to Table 15 1 When the Transmit Error Counter exceeds the limit of 255 the Bus Status bit is set 1 Bus Off the CAN controller will set the Reset Mode bit 1 present an Error Warning and a Bus Error Interrupt is generated if enabled The Transmit Error Counter is set to 127 It will stay in this mode until the CPU clears the Reset Request bit Once this is completed the CAN controller will wait the minimum protocol defined time 128 occurrences of the Bus Free signal counting down the Transmit Error Counter After that the Bus Status bit is cleared
214. ts of the reset enable register RTE are at logic 1 see Section 16 1 6 1 If RTE is 0 then P3 n is not affected by a match between CM1 or CM2 and Timer 2 Thus if the current operation is set the next operation will be reset even if the port latch is reset by software before the reset operation occurs CMO CM1 and CM2 are reset by the RST signal The modified port latch information appears at the port pin during S5P1 of the cycle following the cycle in which a match occurred If the port is modified by software the outputs change during S1P1 of the following cycle Each port 3 bit 0 3 can be set or reset by software at any time A hardware modification resulting from a comparator match takes precedence over a software modification in the same cycle When the comparator results require a set and a reset at the same time the port latch will be reset 117 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 16 1 6 1 Reset Toggle Enable Register RTE Table 74 Reset Toggle enable register address EFH 7 6 5 4 3 2 1 0 RP35 RP34 RP33 RP32 Table 75 Description of RTE bits BIT SYMBOL DESCRIPTION 7104 Reserved 3 RP35 If HIGH then P3 5 is reset on a match between CM2 and T2 2 RP34 If HIGH then P3 4 is reset on a match between CM2 and T2 1 RP33 If HIGH then P3 3 is reset on a match betwe
215. tted this message is written in parallel to the Receive Buffer A Receive Interrupt is generated only if this transmission was forced by the Self Reception Request So even if the Receive Buffer is empty the last transmitted message may be read from the Receive Buffer until it is overridden by the next received or transmitted message Upon a Hardware Reset the RXFIFO pointers are reset to the physical RAM address 0 Setting MOD 0 by software or due to the Bus Off event will reset the RXFIFO pointers to the currently valid FIFO Start Address RBSA Register which is different from the RAM address 0 after the first Release Receive Buffer command 2000 Jul 26 33 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 5 2 MODE REGISTER MOD The contents of the Mode Register are used to change the behaviour of the CAN controller Bits may be set or reset by the CPU that uses the Mode Register as a read write memory Reserved Bits are read as 0 Table 13 Mode Register MOD CAN Addr 0 bit interpretation BIT SYMBOL NAME VALUE FUNCTION MOD 7 TM Test Mode 1 activated The TXDC pin will reflect the bit detected on RXDC pin with Note 1 the next positive edge of the system clock The RPM bit has no influence within this mode 0 disabled MOD 6 RIPM Reserved MOD 5 RPM Receive Polarity 1 high active RXD inputs are active high dominant 1 M
216. uitry The ADC has the option of either being powered off in Idle mode for reduced power consumption or being active in the Idle mode for reducing internal noise during the conversion This option is selected by the AIDL bit of AUXR1 register AUXR1 6 With the AIDL bit set the ADC is active in the Idle mode and with the AIDL bit cleared the ADC is powered off in Idle mode 124 Philips Semiconductors Single chip 8 bit microcontroller with CAN controller ADCO ADCI ADC2 ADC3 ANALOG INPUT ADC4 MULTIPLEXER ADC5 n c n c 20 3 10 Bit Analog to Digital Conversion Figure 48 shows the elements of a successive approximation SA ADC The ADC contains a DAC which converts of a successive approximation register to a voltage VDAC which is compared to the analog input voltage Vin The output of the comparator is fed to the successive approximation control logic which controls the successive approximation register A conversion is initiated by setting ADCS in ADCON register ADCS can bet set by software only The software start mode is selected when control bit ADCON 5 ADEX 0 A conversion is then started by setting control bit ADCON 3 ADCS The software start mode is selected when ADCON 5 1 and a conversion may be started by setting ADCON 3 When a conversion is initiated the conversion starts at the beginning of the machine cycle which follows the instruction that sets ADCS ADCS is actually implemented wi
217. up to 8 bytes Powerful error handling capability Non return to zero NRZ coding decoding with bit stuffing Suitable for use in a wide range of networks including SAE s network classes A B 2000 Jul 26 24 Preliminary Specification P8xC591 12 1 2 P8xC591 PELICAN FEATURES ADDITIONAL CAN 2 0B Supports 11 bit identifier as well as 29 bit identifier Bit rates up to 1 Mbit s Error Counters with read write access Programmable Error Warning Limit Error Code Capture with detailed bit position Arbitration Lost Interrupt with detailed bit position Single Shot Transmission no re transmission Listen Only Mode no acknowledge no active error flags Hot Plugging support software driven bit rate detection Extended receive buffer FIFO 64 byte Receive Buffer level sensitive Receive Interrupt High Priority Acceptance Filters for Receive Interrupt Acceptance Filters with change on the fly feature Reception of own messages Self Reception Request Programmable CAN output driver configuration Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 12 2 PeliCAN structure A 80C51 CPU Interface connects the PeliCAN to the internal bus of the P8xC591 microcontroller Via five Special Function Registers CANADR CANDAT CANMOD CANSTA and CANCON the CPU has access to the PeliCAN The SFR will described later on control IN
218. upt flag register address C8H Preliminary Specification P8xC591 CMIO is scanned by the interrupt logic during S2 CMI1 and CMI2 are scanned during S3 and S4 A match of CMIO and CMI1 will be recognized by the interrupt logic or by polling the flags two cycles after the match takes place A match of CMI2 will cause no interrupt this flag can be polled only The 16 bit overflow flag T2OV and the byte overflow flag T2BO are set during S6 of the cycle in which the overflow occurs These flags are recognized by the interrupt logic during the next cycle Special function register IP1 see Section 16 1 7 2 is used to determine the Timer T2 interrupt priority Setting a bit high gives that function a high priority and setting a bit low gives the function a low priority The functions controlled by the various bits of the IP1 register are shown in Section 16 1 6 2 7 6 5 4 3 2 1 0 T20V Table 79 Description of TM2IR bits BIT SYMBOL DESCRIPTION 7 2 T2 16 bit overflow interrupt flag 6 CMI2 CAN CM2 flag for polling only CAN CAN interrupt flag polling only 5 CMI1 CM1 interrupt flag 4 CMIO CMO interrupt flag 3 CTI3 CT3 interrupt flag 2 CTI2 CT2 interrupt flag 1 CT1 interrupt flag 0 CTO interrupt flag 16 1 7 2 Interrupt Priority Register 1 IP1 Table 80 Interrupt Priority Register 1 address F8H 7 6 5 4 3 2 1 0 PT2 PCAN PCM1 PCMO PCT3 PCT2 1
219. ure range includes max fci 12 MHz e 40 to 85 C version for general applications The P8xC591 combines the functions of the P87C554 microcontroller and the SJA1000 stand alone CAN controller with the following enhanced features e Enhanced CAN receive interrupt level sensitive e Extended acceptance filter Acceptance filter changeable on the fly The main differences between P8xC591 and P87C554 are e CAN controller on chip Figure 1 shows a Block Diagram of the P8xC591 The e 6 input ADC microcontroller is manufactured in an advanced CMOS e Low active Reset process and is designed for use in automotive and e 44 leads general industrial applications In addition to the 80C51 standard features the device provides a number of dedicated hardyvare functions for these applications Two versions of the P8xC591 will be offered e P83C591 with ROM e P87C591 with OTP Hereafter these versions will be referred to as P8xC591 3 ORDERING INFORMATION PACKAGE TYPE NUMBER IE E NAME DESCRIPTION VERSION GE P83C591VFA PLCC44 plastic leaded chip carrier 44 leads SOT187 2 P87C591VFA P83C591VFB i 8985 QEP44 plastic quad flat package 44 leads lead length 1 3 mm SOT307 2 P87C591VFB body 10 x 10 x 1 75 mm 2000 Jul 26 Philips Semiconductors Preliminary Specification Single chip 8 bit microcontroller vvith GAN controller P8xC591 4 BLOCK DIAGRAM INTO INTI EA AVret AVgg ANOto5 P
220. will release the bus and no interrupt request is generated If another master frees the bus by generating a STOP condition SIO1 will transmit a normal START condition state 08H and a retry of the total serial data transfer can commence 15 2 15 1 Data Transfer after loss of Arbitration Arbitration may be lost in the master transmitter and master receiver modes see Figure 33 Loss of arbitration is indicated by the following states in S1STA 38H 68H 78H and BOH see Figures 37 and 38 If the STA flag in S1CON is set by the routines which service these states then if the bus is free again a START condition state 08H is transmitted without intervention by the CPU and a retry of the total serial transfer can commence 15 2 15 2 Forced Access to the bus In some applications it may be possible for an uncontrolled source to cause a bus hang up In such situations the problem may be caused by interference temporary interruption of the bus or a temporary short circuit between SDA and SCL If an uncontrolled source generates a superfluous START or masks a STOP condition then the I C bus stays busy indefinitely If the STA flag is set and bus access is not obtained within a reasonable amount of time then a forced access to the 12C bus is possible This is achieved by setting the STO flag while the STA flag is still set No STOP condition is transmitted The SIO1 hardware behaves as if a STOP condition was received and is
221. xternally driven from HIGH to LOW The transition current reaches its maximum value when Vin is approximately 2 V Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the Vo of ALE and Ports 1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make HIGH to LOW transitions during bus operations In the worst cases capacitive loading 100pF the noise pulse on the ALE pin may exceed 0 8 V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt Trigger STROBE input lo can exceed these conditions provided that no single outputs sinks more than 5 mA and no more than two outputs exceed in the test conditions Capacitive loading on Ports 0 and 2 may cause the Vou on ALE and PSEN to momentarily fall below the 0 9 Vpp specification when the address bits are stabilizing Conditions AVss 0 V Vpp 5 0 V Measurement by continuous conversion of AViy 20 mV to 5 12 V in steps of 0 5 mV derivating parameters from collected conversion results of ADC AVggr P8xC591 4 977 V ADC is monotonic with not missing codes The differential non linearity D amp is the difference between the actual step width and the ideal step width see Fig 54 The ADC is monotonic there are no missing codes The integral non linearity lI amp is the peak difference between the centre of the steps of th
222. y a falling edge on CTOI 0 CTPO Capture Register 0 triggered by a rising edge on CTOI 16 1 5 MEASURING TIME INTERVALS USING REGISTERS When a recurring external event is represented in the form of rising or falling edges on one of the four capture pins the time between two events can be measured using Timer T2 and a capture register When an event occurs the contents of Timer T2 are copied into the relevant capture register and an interrupt request is generated The interrupt service routine may then compute the interval time if it Knows the previous contents of Timer T2 when the last event occurred With a 6 MHz oscillator Timer T2 can be programmed to overflow every 524 ms When event interval times are shorter than this computing the interval time is simple and the interrupt service routine is short For longer interval times the Timer T2 extension routine may be used 16 1 6 COMPARE LOGIC Each time Timer T2 is incremented the contents of the three 16 bit compare registers CMO CM1 and CM2 are compared with the new counter value of Timer T2 When a match is found the corresponding interrupt flag in TM2IR is set at the end of the following cycle When a match with 2000 Jul 26 CMO occurs the controller sets bits 0 3 of port 3 if the corresponding bits of the set enable register STE are at logic 1 see Section 16 1 6 2 When a match with CM1 occurs the controller resets bits 0 3 of port 3 if the corresponding bi

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